A printed circuit board and processor board card

Abstract

The embodiment of the present application provides a printed circuit board and a processor board card, which comprises a substrate, a signal layer arranged in the substrate and close to a first side of the substrate, a power supply layer arranged in the substrate and close to a second side of the substrate, a power supply via penetrating the substrate along a first direction, a signal via arranged in the substrate and extending along the first direction, wherein the length of the signal via in the first direction is smaller than that of the power supply via, a processor interface arranged on the first side of the substrate, in communication with the signal layer and the power supply layer, and a memory particle interface arranged on both sides of the substrate, the number of the memory particle interfaces is greater than 12 groups, the memory particle interfaces are in communication with the signal layer and the power supply layer. The embodiment of the present application changes the design of the printed circuit board layer and uses a blind hole, so that the signal interference in the printed circuit board can be reduced, and the number of particle chips that can be arranged on the printed circuit board is increased.

Description

Technical Field

[0001] This application relates to the field of computer boards, specifically to a printed circuit board and a processor board. Background Technology

[0002] With the development of artificial intelligence applications, algorithms and big data are becoming increasingly important, and computing power is the technical support for algorithms and big data. As a result, heterogeneous computing chips can provide stronger computing power, making them the cornerstone of the development of computing-intensive application industries such as artificial intelligence.

[0003] The existing processor board design uses vias that connect to the signal layer through the power layer, causing interference from the power layer to the signals within those vias. Furthermore, these vias are mostly through-holes, resulting in redundant structures outside the signal layer that can negatively impact signal quality. Therefore, to ensure signal quality, this processor board can only accommodate a maximum of 24 GDDR6 (Graphics Double Data Rate version 6) memory chips, a relatively small number.

[0004] Therefore, how to reduce signal interference within printed circuit boards and increase the number of chips that can be placed on printed circuit boards has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, embodiments of this application provide a printed circuit board and a processor board to reduce signal interference within the printed circuit board and increase the number of chips that can be placed on the printed circuit board.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] This application provides a printed circuit board, including:

[0008] substrate;

[0009] A signal layer is disposed within the substrate and close to a first side of the substrate;

[0010] A power layer is disposed within the substrate and close to a second side of the substrate, wherein the first side and the second side are opposite sides of the substrate;

[0011] A power via penetrates the substrate along a first direction;

[0012] A signal via is disposed within the substrate and extends along the first direction, wherein the length of the signal via in the first direction is less than the length of the power via in the first direction;

[0013] The processor interface is disposed on the first side of the substrate, and is connected to the signal layer through a signal via and to the power layer through a power via;

[0014] The memory chip interface is disposed on the first side and the second side of the substrate. The number of memory chip interfaces is greater than 12. The memory chip interface is connected to the signal layer through signal vias and to the power layer through power vias.

[0015] Optionally, the memory chip interface includes a GDDR6 interface.

[0016] Optionally, the processor interface is adapted to connect to a first processor, wherein the printed circuit board further includes:

[0017] A high-speed peripheral component interconnection interface is connected to the processor interface through the signal layer and is adapted to connect to a second processor;

[0018] A miscellaneous signal control signal interface is connected to the processor interface through the signal layer and is adapted to connect to the second processor.

[0019] Optionally, it also includes: a voltage conversion module interface, which is connected to the processor interface through the power layer and is adapted to connect to a power supply.

[0020] Optionally, it also includes: a complex programmable logic device interface, which connects to the voltage conversion module interface and the miscellaneous signal control signal interface through the signal layer.

[0021] Optionally, it may also include: a clock signal interface, adapted to connect to the processor interface through the signal layer.

[0022] This application embodiment also provides a processor board, including:

[0023] The printed circuit board as described above;

[0024] The first processor is electrically connected to the printed circuit board via the processor interface.

[0025] Optionally, it also includes: memory chips, which are electrically connected to the printed circuit board via the memory chip interface.

[0026] Optionally, the printed circuit board includes a high-speed peripheral component interconnect interface and a miscellaneous signal control signal interface, and the processor board further includes:

[0027] A first connector is connected between the high-speed peripheral component interconnect interface and the miscellaneous signal control signal interface of the second processor and the printed circuit board to communicate between the second processor and the printed circuit board.

[0028] Optionally, the first connector may include a PCIe gold finger or a high-density horizontal connector.

[0029] Optionally, the printed circuit board includes a voltage conversion module interface, and the processor board further includes:

[0030] A voltage conversion module is connected to the interface of the voltage conversion module and to the power supply, for converting the first voltage of the power supply into the second voltage required by the processor board.

[0031] Optionally, when the first connector includes PCIe gold fingers, the processor board further includes:

[0032] An additional power source, connected to the voltage conversion module, is used to provide power that meets a predetermined voltage.

[0033] Optionally, the printed circuit board includes a complex programmable logic device interface, and the processor board further includes:

[0034] A complex programmable logic device, with an interface connected to the complex programmable logic device, is used to control the voltage input of the processor board.

[0035] Optionally, the printed circuit board includes a serial peripheral interface, and the processor board further includes:

[0036] The flash memory chip is connected to the serial peripheral interface.

[0037] Optionally, the printed circuit board includes a clock signal interface, and the processor board further includes:

[0038] The clock module is connected to the clock signal interface.

[0039] This application provides a printed circuit board comprising: a substrate; a signal layer disposed within the substrate and near a first side of the substrate; a power layer disposed within the substrate and near a second side of the substrate, wherein the first side and the second side are opposite sides of the substrate; a power via penetrating the substrate along a first direction; a signal via disposed within the substrate and extending along the first direction, wherein the length of the signal via in the first direction is less than the length of the power via in the first direction; a processor interface disposed on the first side of the substrate, communicating with the signal layer through the signal via and with the power layer through the power via; and memory chip interfaces disposed on the first and second sides of the substrate, wherein the number of memory chip interfaces is greater than 12 groups, and the memory chip interfaces communicate with the signal layer through the signal via and with the power layer through the power via. By disposing each signal layer on the first side of the substrate and each power layer on the second side of the substrate opposite to the first side, and using signal vias with a length less than that of the power vias to connect the signal layers, the processor interface, and the memory chip interfaces, signal vias penetrating through the power layer are avoided, thereby reducing signal interference. Furthermore, by using signal vias with a length shorter than power vias, redundant structures of signal vias can be eliminated, signal leakage can be reduced, and signal quality can be improved. This allows for an increase in the number of memory chip interfaces that can be set on the printed circuit board, thereby increasing the number of chips on the processor board. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a single-ended signal circuit.

[0042] Figure 2 This is a schematic diagram of the layer design of a printed circuit board;

[0043] Figure 3 A schematic diagram of the layer design of a printed circuit board provided in an embodiment of this application;

[0044] Figure 4 A top view of the printed circuit board provided in an embodiment of this application;

[0045] Figure 5 This is a first circuit topology diagram of the processor board provided in an embodiment of this application;

[0046] Figure 6This is a second circuit topology diagram of the processor board provided in the embodiments of this application;

[0047] Figure 7 A third circuit topology diagram of the processor board provided in the embodiments of this application;

[0048] Figure 8 A schematic diagram of a power supply design for a processor board connected to an external motherboard using PCIe gold fingers, provided in an embodiment of this application.

[0049] Figure 9 A schematic diagram of a power supply design for a processor board provided in this application embodiment, which uses a high-density horizontal connector to connect to an external motherboard;

[0050] Figure 10 Another power supply design schematic diagram for the processor board provided in this application embodiment, which uses a high-density horizontal connector to connect to an external motherboard;

[0051] Figure 11 This is another power supply design diagram for a processor board provided in this application embodiment, which uses a high-density horizontal connector to connect to an external motherboard;

[0052] Figure 12 A schematic diagram of another power supply design for a processor board provided in this application embodiment, which uses a high-density horizontal connector to connect to an external motherboard;

[0053] Figure 13 A schematic diagram of the power supply design when the processor board is integrated into an external motherboard, as provided in an embodiment of this application;

[0054] Figure 14 This is a schematic diagram of the heat sink structure of the processor board provided in an embodiment of this application. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] With the development of artificial intelligence applications, algorithms and big data are becoming increasingly important, and computing power is the technical support for algorithms and big data. As a result, heterogeneous computing chips can provide stronger computing power, making them the cornerstone of the development of computing-intensive application industries such as artificial intelligence.

[0057] One type of heterogeneous computing chip for implementing heterogeneous computing is a deep learning processor chip, which is a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) EP (Endpoint) device. It needs to be connected to a PCIe Host, such as a CPU. Its storage system design uses external GDDR6 chips.

[0058] GDDR technology is a type of DDR (Double Data Rate) memory optimized for graphics displays, suitable for high-speed data exchange. GDDR6 interconnects with deep learning processor chips on a PCB (Printed Circuit Board) to form a processor board. This method is low-cost, allows for the integration of more channel chips, offers design flexibility, and reduces system cost. GDDR6 data signals are single-ended signals, such as... Figure 1 As shown, a set of signal lines is used in conjunction with a set of address signal lines to transmit signals. The signal transmitted on a single-ended signal line is the potential difference between the signal line and the ground line, which has relatively poor anti-interference capability. Therefore, high-speed single-ended signals place extremely high demands on board-level design.

[0059] A printed circuit board design for a processor board, such as Figure 2 The cross-sectional view of the printed circuit board 10 shown shows that... ， The first via 181 to the fifth via 185 connect the signal layers 12 and 13 to the processor 14, the top GDDR6 chip 15, or the bottom GDDR6 chip 16, and also pass through the power layer 11 connected to the power supply 17, causing the power layer 11 to interfere with the signals of the first via 181 to the fifth via 185. Furthermore, as... Figure 2 The second via 182 and the fourth via 184, in addition to connecting the signal layer 13, also have some redundant structures 180 that can affect signal quality. Therefore, to ensure signal quality, the distance between the signal layer 12 and the power layer 11 needs to be larger, and the distance between the first via 181 to the fifth via 185 needs to be larger, thereby reducing crosstalk and ensuring the quality of single-ended high-speed signals. Therefore, the processor board with the processor 14 can be configured with a maximum of 12 channels (that is, a maximum of 24 GDDR6 chips, including 12 GDDR6 chips on the top surface and 12 GDDR6 chips on the bottom surface), and the number of memory chips is relatively small.

[0060] To address the aforementioned problems, this application provides a printed circuit board that can increase the number of memory chips that can be configured on a processor board while ensuring signal quality. The specific structure of this printed circuit board is as follows: Figure 3 As shown, it includes:

[0061] substrate 20;

[0062] A signal layer 21 is disposed within the substrate 20 and close to a first side of the substrate 20;

[0063] A power layer 22 is disposed within the substrate 20 and close to a second side of the substrate 20, wherein the first side and the second side are opposite sides of the substrate 20;

[0064] A power via 27 extends through the substrate 20 along a first direction;

[0065] A signal via 26 is disposed within the substrate 20 and extends along the first direction, wherein the length of the signal via 26 in the first direction is less than the length of the power via 27 in the first direction;

[0066] The processor interface 23 is disposed on the first side of the substrate 20, and is connected to the signal layer 21 through the signal via 26 and to the power layer 22 through the power via 27.

[0067] The memory chip interface 25 is disposed on the first side and the second side of the substrate 20. The number of memory chip interfaces 25 is greater than 12. The memory chip interface 25 is connected to the signal layer 21 through the signal via 26 and to the power layer 22 through the power via 27.

[0068] It should be noted that the substrate 20 of the printed circuit board 10 mentioned herein refers to a plate-like structure that serves as a support, carrying various signal layers 21, power layers 22, and interfaces, etc. The substrate 20 of the printed circuit board 10 may include multiple signal layers 21, which are used to arrange signal lines within the substrate 20, as shown below. Figure 3 The diagram shows a first signal layer 211 to a third signal layer 213, and each signal layer 21 has a corresponding ground layer (not shown in the diagram). By setting ground layers to separate different signal layers 21, crosstalk between two directly adjacent signal layers can be avoided, which could lead to circuit malfunction.

[0069] like Figure 3 As shown, the substrate 20 of the printed circuit board 10 may include multiple power layers 22. The first power layer 221 and the second power layer 222 serve as power layers and ground layers, respectively, and appear in pairs. Multiple pairs of first power layers 221 and second power layers 222 may be provided in the substrate 20 of a printed circuit board 10.

[0070] It is easy to understand, such as Figure 2As shown, the memory chip interfaces 25 are arranged in pairs on the first and second sides of the substrate 20 of the printed circuit board 10. Each pair of memory chip interfaces 25 is a group, and the number of groups is greater than 12, that is, the number of memory chip interfaces 25 is greater than 24.

[0071] Thus, the printed circuit board provided in this application embodiment, by placing each signal layer 21 on the first side of the substrate 20 and each power layer 22 on the second side of the substrate opposite to the first side, and using signal vias 26 with a length shorter than the power vias 27 to connect the signal layers 21, the processor interface 23, and the memory chip interface 25, avoids the signal vias 26 passing through the power layers 22, thereby reducing signal interference. Furthermore, by using signal vias 26 with a length shorter than the power vias 27, redundant structures of the signal vias 26 can be eliminated, reducing signal leakage and improving signal quality. This increases the number of memory chip interfaces 25 that can be disposed on the printed circuit board 10, thereby increasing the number of memory chips on the processor board.

[0072] Furthermore, to make the printed circuit board suitable for processor boards equipped with GDDR6 memory chips, in one embodiment, the memory chip interface includes a GDDR6 interface. Specifically, the GDDR6 interface supports four interface modes: X16 mode for connecting 16 external GDDR6 chips, X8 mode for connecting 32 external GDDR6 chips, X8 mode for connecting 16 external GDDR6 chips (using only 8 GDDR6 interfaces), and X16 mode for connecting 8 external GDDR6 chips (using only 8 GDDR6 interfaces). Thus, by using higher-speed GDDR6 memory chips, the performance of the processor board using this printed circuit board 10 can be improved.

[0073] Furthermore, to facilitate power supply to the devices on the printed circuit board, in one embodiment, please refer to... Figure 4 , Figure 4 This is a top view of the printed circuit board provided in an embodiment of this application. Figure 4 As shown, the printed circuit board 10 further includes a voltage conversion module interface 25, which is disposed on the substrate 20 and connected to the processor interface through the power layer, and is suitable for connecting to a power supply.

[0074] Furthermore, to facilitate the connection between electronic devices on the printed circuit board 10 and electronic devices outside the printed circuit board 10, in one embodiment, such as... Figure 4 As shown, the processor interface is adapted to connect to a first processor, wherein the printed circuit board further includes:

[0075] The high-speed peripheral component interconnection interface 41 is connected to the processor interface 23 through the signal layer 21 and is adapted to connect to a second processor;

[0076] Miscellaneous signal control signal interface 42 is connected to the processor interface 23 through the signal layer 21 and is adapted to connect to the second processor.

[0077] It should be noted that in actual use, the printed circuit board 10 is usually installed on an external motherboard as part of a processor board. This makes it easy to connect the processor board to a second processor on the external motherboard.

[0078] It is easy to understand that the high-speed peripheral component interconnection interface 41 is used to transmit data signals; the miscellaneous signal control signal interface 42 is used to transmit miscellaneous signals.

[0079] In one embodiment, the high-speed peripheral component interconnection interface 41 is a PCIe X16 interface, used to transmit PCIe X16 signals, connect PCIe uplink devices such as CPUs, and support PCIe Gen4 16G speed.

[0080] The miscellaneous signals mainly include reset signals, general input / output signals, system management bus signals, and other sideband signals, which are used for the setting and management of the peripheral circuits of the first processor 31.

[0081] It should be noted that the second processor 43 may also include its peripheral systems, such as chip devices 431 that support the operation of the second processor 43.

[0082] In one embodiment, the second processor 43 may be a CPU, and the chip device 431 may include a flash memory chip storing a BIOS that supports CPU operation, and a dual in-line memory module.

[0083] In this way, the processor board can connect to the second processor 43 on the external motherboard at a faster speed, and the first processor 31 and the second processor 43 can work together better, improving the performance of the processor board.

[0084] Furthermore, in order to reduce the power consumption of the processor board 10, electronic devices for controlling the voltage input are provided. In one embodiment, such as... Figure 4 As shown, the printed circuit board 10 further includes:

[0085] The complex programmable logic device interface is connected to the voltage conversion module interface and the miscellaneous signal control signal interface through the signal layer 21.

[0086] Specifically, the complex programmable logic device interface is the interface for connecting to a CPLD (Complex Programmable Logic Device).

[0087] Through the complex programmable logic device (CPL) interface, the printed circuit board 10 can be connected to a complex programmable logic device (CPL), realizing the connection between the first processor 31 and the complex programmable logic device 462. Thus, the complex programmable logic device 462 can be used to manage the power-on and power-off timing of all power supplies in the voltage conversion module 451.

[0088] Furthermore, to facilitate the placement of the first processor-related electronic devices on the printed circuit board 10, in one embodiment, such as... Figure 4 As shown, the printed circuit board 10 further includes:

[0089] Serial peripheral interface 471 is adapted to be connected to processor interface 23 via signal layer 21.

[0090] Specifically, the serial peripheral interface is SPI (Serial Peripheral Interface).

[0091] The serial peripheral interface allows the printed circuit board 10 to connect to the flash memory chip 472, enabling the connection between the first processor 31 and the flash memory chip 472. This facilitates the configuration of VBIOS (VIDEOBIOS, graphics card BIOS module) for the first processor 31 via the flash memory chip.

[0092] Furthermore, in order to enable the printed circuit board 10 to provide a uniform clock signal for the electronic devices thereon, in one embodiment, such as Figure 4 As shown, the printed circuit board 10 further includes:

[0093] A clock signal interface, adapted to be connected to the processor interface 23 via the signal layer 21.

[0094] The clock signal interface enables the printed circuit board 10 to connect the first processor 31 and the clock module 482 via the clock module 482, thereby providing a clock signal to the first processor 31.

[0095] To address the aforementioned problems, this application also provides a processor board including the printed circuit board described in any of the above embodiments, which can increase the number of memory chips that can be configured on the processor board while ensuring signal quality. Figure 5-7 As shown, Figure 5 This is a first circuit topology diagram of the processor board provided in an embodiment of this application. Figure 6 This is a second circuit topology diagram of the processor board provided in the embodiments of this application. Figure 7 This is a third circuit topology diagram of the processor board provided in the embodiments of this application. In addition to the printed circuit board 10, the processor board also includes:

[0096] The first processor 31 is electrically connected to the printed circuit board 10 through the processor interface 23.

[0097] Thus, in the processor board provided in this application embodiment, the signal layers 21 and power layers 22 of the printed circuit board 10 are located on opposite sides of the substrate 20, and signal vias 26 with a length shorter than the power vias 27 are used to connect the signal layers 21, the processor interface 23, and the memory chip interface 25, avoiding the signal vias 26 from passing through the power layer 22, thereby reducing signal interference. Furthermore, the signal vias 26 are blind vias rather than through-holes, which eliminates redundant via structures, reduces signal leakage, and improves signal quality, thereby increasing the number of chip interfaces that can be set on the printed circuit board 10, and consequently increasing the number of chips on the processor board.

[0098] In one embodiment, to enable the processor board to have higher performance, the first processor 31 is a depth computing processor chip.

[0099] In another specific embodiment, the processor board provided in this application embodiment also includes a memory chip 33, which is electrically connected to the printed circuit board 10 through the memory chip interface 25.

[0100] In one embodiment, to enable the processor board to have higher performance, the memory chip 33 is a GDDR6 chip.

[0101] In this way, by using the printed circuit board 10 as described above, the number of memory chips configured for the first processor on the processor board can be increased, thereby improving the performance of the processor board.

[0102] Of course, to power the processor board, an external power supply 44 is required. Furthermore, to protect the processor board from excessive voltage and ensure a stable voltage supply, please refer to [further details needed]. Figure 5 In one embodiment, the printed circuit board 10 includes a voltage conversion module interface 25, and the processor board further includes:

[0103] Voltage conversion module 451 is connected to the voltage conversion module interface and to the power supply, and is used to convert the first voltage supplied to the processor board into the voltage required by the processor board.

[0104] It should be noted that the voltage conversion module 451 can be a single module or multiple modules, and the number can be set according to the working needs of the first processor.

[0105] It is easy to understand that in order to power the second processor 43, which is connected to the processor board through the aforementioned peripheral component interconnection interface 41 and miscellaneous signal control signal interface 42l, the second processor 43 also needs to be connected to an external power supply 44. In order to protect the second processor 43 from excessive voltage and ensure a stable voltage supply, the second processor 43 can also be connected to a voltage conversion module 452. That is, the voltage conversion module 452 connects the power supply and the second processor 43, and is used to convert the second voltage supplied to the second processor 43 into the voltage required by the second processor 43.

[0106] In this way, the voltage conversion modules 451 and 452 can provide the processor board and the second processor 43 with the stable voltage they require.

[0107] Furthermore, to control power supply according to the needs of the first and second processors, in one embodiment, the printed circuit board 10 includes a complex programmable logic device interface 461, and the processor board further includes:

[0108] Complex programmable logic device 462, with an interface connected to the complex programmable logic device, is used to control the voltage input of the processor board.

[0109] It should be noted that the complex programmable logic device 462 uses the power timing control signal 463 to manage the power-on and power-off sequence of all power supplies in the voltage conversion module 451, and controls the operation and enable of each voltage conversion module 451 according to the power-on sequence required by the DCU chip.

[0110] In addition, the complex programmable logic device 462 also needs to handle some abnormal situations during the operation of the first processor 31. For example, if the first processor 31 detects an abnormal phenomenon and needs to shut down the power urgently, the first processor 31 notifies the complex programmable logic device 462 through the miscellaneous signal control signal interface 41. After receiving the abnormal alarm signal, the complex programmable logic device 462 sends a power timing control signal 463 to shut down the voltage conversion module 451 in sequence and power down the first processor 31.

[0111] In addition, the complex programmable logic device 462 is also responsible for some logic signal processing and expands the peripheral circuits of the first processor 31, such as management and indication functions. The connection and control relationship between the complex programmable logic device 462 and the power conversion module 452 of the second processor is the same as that between the complex programmable logic device 462 and the voltage conversion module 451, and will not be described again here.

[0112] Furthermore, to ensure the normal startup of the first processor, in one embodiment, the printed circuit board 10 includes a serial peripheral interface 471, and the processor board further includes:

[0113] Flash memory chip 472 is connected to the Serial Peripheral Interface (SPI) interface.

[0114] It should be noted that the serial peripheral interface 471 is used to connect an external flash memory chip 472. The flash memory chip 472 stores the VBIOS (VIDEO BIOS, graphics card BIOS module) of the first processor 31. The first processor 31 reads the VBIOS through the serial peripheral interface 471.

[0115] In another implementation, the VBIOS can also be configured via a second processor, that is, the VBIOS is stored in a flash memory chip connected to the second processor 43, and the VBIOS is configured into the system of the first processor 31 during the boot phase of the second processor 43.

[0116] Furthermore, to ensure the normal and orderly operation of each hardware component, in one embodiment, the printed circuit board 10 includes a clock signal interface 481, and the processor board further includes:

[0117] Clock module 482 is connected to the clock signal interface.

[0118] It is readily understood that the clock module 482 provides a clock signal through the clock signal interface 481. The clock module 482 includes, for example, the core clock of the first processor chip, the clock of the PCIe interface module, and the clock of the GDDR6 interface module.

[0119] The PCIe interface module clock is derived from the clock output of the second processor 43. The GDDR6 interface clock can be selected from the PCIe 100MHz output clock of the second processor 43, or a local clock can be selected via a clock switching module. Furthermore, if the processor board is directly mounted on an external motherboard, replacing the processor board or other components would be labor-intensive and costly. However, when the processor board is independent of the external motherboard, its connection to the second processor 43 causes system interference.

[0120] Therefore, in order to reduce system interference when the processor board is connected to the second processor independently of the external motherboard, in one embodiment, when the printed circuit board 10 of the processor board includes a high-speed peripheral component interconnect interface 41 and a miscellaneous signal control signal interface 42, the processor board further includes:

[0121] The first connector 50 is used to connect the high-speed peripheral component interconnect interface and the miscellaneous signal control signal interface to the second processor.

[0122] In this way, by connecting the processor board and the external motherboard with the second processor through the first connector 50, system interference can be reduced while facilitating the upgrading and maintenance of the processor board.

[0123] In one embodiment, the first connector 50 includes a PCIe gold finger 51 or a high-density horizontal connector 52.

[0124] Please refer to Figure 6 , Figure 6 This is a circuit topology diagram of the processor board when the first connector 50 is a PCIe gold finger 51.

[0125] like Figure 6 As shown, when the first connector 50 is a PCIe gold finger 51, i.e., a PCIe standard card design, the processor board is made into a PCIe standard card form according to the standard PCIe signal definition. It is connected through a PCIe slot on the external motherboard. When the first processor 31 is a deep learning processor chip, because the deep learning processor chip is relatively large, the PCIe standard card is designed as a full-height, full-length PCIe standard card. However, its height is too high, making it difficult to meet the needs of some large data centers with limited overall machine height and high integration requirements. In this design, a gold finger card is usually used as the connection method to the external motherboard, which is commonly used in general consumer products.

[0126] Please refer to Figure 7 , Figure 7 This is a circuit topology diagram of the processor board when the first connector 50 is a high-density horizontal connector 52.

[0127] like Figure 7 As shown, when the first connector 50 is a high-density horizontal connector 52, i.e. a horizontal card, the processor board is parallel to the motherboard and interconnected with the motherboard through a high-density, low-height connector. This method not only facilitates the upgrade of the first processor, but also solves the system height problem.

[0128] Horizontal cards, due to their greater number of signal interconnections and higher reliability compared to standard PCIe cards, are often used in large data centers.

[0129] It should be noted that when the processor board is connected to the external motherboard through the first connector 50, the external board is no longer directly powered by the external power supply 44, but is powered by the external motherboard through the first connector 50.

[0130] Therefore, the voltage conversion module 451 requires different power supply schemes for different connection methods between different processor boards and external motherboards:

[0131] 1. Please continue to refer to Figure 6When the first connector 50 is a PCIe gold finger 51, connecting the processor board and the external motherboard with the second processor, the power supplied by the PCIe gold finger 51 is connected to the complex programmable logic device 462. Power is always available when the system is in sleep or operating state, meaning the complex programmable logic device 462 is always operational, performing management functions. Part of the power supply is converted to the required power voltage by the voltage conversion module 451, providing it to the power domain of the first processor 31 with lower current consumption. Conversely, part of the power supply is converted to the required power voltage by the voltage conversion module 451, providing it to the power domain of the first processor 31 with higher current consumption.

[0132] However, due to the high power consumption of the processor board chip, the power provided by the PCIe gold fingers cannot meet the power requirements of the first processor 31. Therefore, in one embodiment, the processor board further includes an additional power supply connected to the voltage conversion module to provide power at a predetermined voltage. Please refer to [reference needed] for details. Figure 8 This ensures that the processor board meets its power requirements.

[0133] At this time, the first connector 50 is the power supply scheme for the processor board of the PCIe gold finger 51. It is similar to the power supply scheme when the processor board is integrated on the external motherboard as described above. Only the input of the voltage conversion modules 4511 and 4512 is changed to the PCIe gold finger 51, and the input of the voltage conversion modules 4513, 4514 and 4515 is changed from the power supply 44 to the additional power supply 54. This will not be described in detail here.

[0134] Please continue to refer to this. Figure 7 When the first connector 50 is a high-density horizontal connector 52, connecting the processor board and the external motherboard with the second processor, the processor board is powered by the high-density horizontal connector 52 and connected to the complex programmable logic device 462. The system is always powered when it is in sleep or working state, that is, the complex programmable logic device 462 is always in working state to realize management functions.

[0135] Meanwhile, the high-density horizontal connector 52 can supply power to the first processor 31 using multiple different voltages simultaneously, or only one voltage. In this case, multiple power supply schemes are possible; details can be found in [reference needed]. Figure 9 and Figure 10 .

[0136] like Figure 9As shown, a power supply scheme when the first connector 50 is a high-density horizontal connector 52 is as follows: the input voltages to the first voltage conversion module 4511 to the fifth voltage conversion module 4515 via the high-density horizontal connector 52 are all the same; however, the voltages converted and output to the first processor 31 by each of the voltage conversion modules 4511 to 4515 can be different. Under normal circumstances, the voltages converted and output by each of the voltage conversion modules 4511 to 4515 can be lower than the voltage input via the high-density horizontal connector 52.

[0137] like Figure 10 As shown, another power supply scheme when the first connector 50 is a high-density horizontal connector 52 is as follows: the input voltage to the first voltage conversion module 4511 and the second voltage conversion module 4512 via the high-density horizontal connector 52 is the same, but the voltages converted and output to the first processor 31 by each voltage conversion module in the first voltage conversion module 4511 and the second voltage conversion module 4512 can be different. The input voltage to the third voltage conversion module 4513, the fourth voltage conversion module 4514 and the fifth voltage conversion module 4515 via the high-density horizontal connector 52 is the same, but the voltages converted and output to the first processor 31 by each voltage conversion module in the third voltage conversion module 4513, the fourth voltage conversion module 4514 and the fifth voltage conversion module 4515 can be different. Under normal circumstances, the voltage converted and output by each voltage conversion module in the first voltage conversion module 4511 to the fifth voltage conversion module 4515 can be less than the voltage input via the high-density horizontal connector 52.

[0138] like Figure 11As shown, another power supply scheme when the first connector 50 is a high-density horizontal connector 52 is as follows: the input voltages to the first voltage conversion module 4511, the second voltage conversion module 4512, and the voltage conversion module 4516 via the high-density horizontal connector 52 are all the same; the voltages converted and output to the first processor 31 by each voltage conversion module in the first voltage conversion module 4511 and the second voltage conversion module 4512 can be different; the input voltages converted and output to the third voltage conversion module 4513, the fourth voltage conversion module 4514, and the fifth voltage conversion module 4515 via each voltage conversion module in the voltage conversion module 4516 are all the same; the voltages converted and output to, for example, the first processor 31 by each voltage conversion module in the third voltage conversion module 4513, the fourth voltage conversion module 4514, and the fifth voltage conversion module 4515 can be different. Under normal circumstances, the voltage converted and output by each voltage conversion module in the first voltage conversion module 4511 to the fifth voltage conversion module 4515 can be less than the voltage input via the high-density horizontal connector 52.

[0139] like Figure 12 As shown, another power supply scheme when the first connector 50 is a high-density horizontal connector 52 is as follows: After being input to the sixth voltage conversion module 4516 via the high-density horizontal connector 52, the input voltages converted and output by each voltage conversion module in the voltage conversion module 4516 to the first voltage conversion module 4511 and the second voltage conversion module 4512 are the same. The voltages converted and output by each voltage conversion module in the first voltage conversion module 4511 and the second voltage conversion module 4512 to, for example, the first processor 31 can be different. Under normal circumstances, the voltage converted and output by each voltage conversion module in the first voltage conversion module 4511 to the fifth voltage conversion module 4515 can be less than the voltage input via the high-density horizontal connector 52. When the processor board is integrated on an external motherboard, please refer to the power supply scheme design of the voltage conversion module 451. Figure 13 , Figure 13 This is a schematic diagram of the power supply design when the processor board provided in this application is set on an external motherboard.

[0140] like Figure 13As shown, the power supplied by the external power source is connected to the complex programmable logic device 462. Power is always available when the system is in sleep or operating state, meaning the complex programmable logic device 462 is always operational, enabling management functions. The external power supply to the first processor 31 typically involves voltage conversion by the voltage conversion module 451, which dynamically adjusts the supply voltage according to the operating status of the first processor 31. This adjustment is achieved through a serial power voltage regulation control interface connected to the voltage conversion module 451 controller via the first processor 31. The first processor 31 dynamically adjusts the output voltage of the voltage conversion module 451 in real time. The first processor 31 has multiple sets of serial power voltage regulation control interfaces 53, connected to voltage conversion modules 4511 and 4512 respectively. Each voltage conversion module 4511 or 4512 outputs two power supplies to the first processor 31, dynamically adjusting to optimize power consumption. Additionally, three voltage conversion modules 4513, 4514, and 4515 output fixed power voltages to the first processor 31 to ensure stable system operation.

[0141] By pre-setting multiple power supply schemes, a more suitable power supply scheme can be selected according to actual usage needs during the processor board design, thereby protecting the safety of the first processor 31 and saving energy.

[0142] Furthermore, after the processor board is independent of the external motherboard, in order to ensure good heat dissipation, in one embodiment, the processor board also includes a heat sink 60, which covers the processor board and is used to dissipate heat for the processor board.

[0143] The heatsink 60 is generally designed in two forms: one is an overall air-cooled heatsink, in which the entire processor board is covered by the heatsink 60, thereby increasing the heat dissipation area and accelerating the heat dissipation speed.

[0144] Another type of radiator, 60, uses water cooling, such as... Figure 14 As shown, the heat sink 60 is a sealed chamber covering the processor board. Through the inlet 61 and outlet 61 on the sealed chamber, the cooling liquid circulates and carries away the heat generated by the processor board. Optionally, the water-cooled heat sink 60 may further include an external heat sink 63 for dissipating heat from the coolant, thereby assisting the heat sink 60 in heat dissipation.

[0145] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A printed circuit board, characterized in that, include: substrate; A signal layer is disposed within the substrate and close to a first side of the substrate; A power layer is disposed within the substrate and close to a second side of the substrate, wherein the first side and the second side are opposite sides of the substrate; A power via penetrates the substrate along a first direction; A signal via is disposed within the substrate and extends along a first direction, wherein the length of the signal via in the first direction is less than the length of the power via in the first direction; The processor interface is disposed on the first side of the substrate, and is connected to the signal layer through a signal via and to the power layer through a power via, thereby preventing the signal via from passing through the power layer; The memory chip interface is disposed on the first side and the second side of the substrate. The number of memory chip interfaces is greater than 12. The memory chip interface is connected to the signal layer through signal vias and to the power layer through power vias.

2. A printed circuit board as described in claim 1, characterized in that, The memory chip interface includes a GDDR6 interface.

3. The printed circuit board as described in claim 1, characterized in that, The processor interface is adapted to connect to a first processor, wherein the printed circuit board further includes: A high-speed peripheral component interconnection interface is connected to the processor interface through the signal layer and is adapted to connect to a second processor; A miscellaneous signal control signal interface is connected to the processor interface through the signal layer and is adapted to connect to the second processor.

4. The printed circuit board as described in claim 3, characterized in that, Also includes: The voltage conversion module interface is connected to the processor interface through the power layer and is suitable for connecting to a power supply.

5. The printed circuit board as described in claim 4, characterized in that, Also includes: The complex programmable logic device interface connects to the voltage conversion module interface and the miscellaneous signal control signal interface through the signal layer.

6. The printed circuit board as described in claim 4, characterized in that, Also includes: A serial peripheral interface, adapted to connect to the processor interface via the signal layer.

7. A printed circuit board as described in claim 4, characterized in that, Also includes: A clock signal interface, adapted to connect to the processor interface via the signal layer.

8. A processor board, characterized in that, include: Printed circuit board as described in any one of claims 1-7; The first processor is electrically connected to the printed circuit board via the processor interface.

9. The processor board as described in claim 8, characterized in that, Also includes: The memory chip is electrically connected to the printed circuit board through the memory chip interface.

10. The processor board as described in claim 9, characterized in that, The printed circuit board includes a high-speed peripheral component interconnect interface and a miscellaneous signal control signal interface. The processor board also includes: A first connector is connected between the high-speed peripheral component interconnect interface and the miscellaneous signal control signal interface of the second processor and the printed circuit board to communicate between the second processor and the printed circuit board.

11. The processor board as described in claim 10, characterized in that, The first connector includes a PCIe gold finger or a high-density horizontal connector.

12. The processor board as described in claim 11, characterized in that, The printed circuit board includes a voltage conversion module interface, and the processor board also includes: A voltage conversion module is connected to the interface of the voltage conversion module and to the power supply, for converting the first voltage of the power supply into the second voltage required by the processor board.

13. The processor board as described in claim 12, characterized in that, When the first connector includes PCIe gold fingers, the processor board also includes: An additional power source, connected to the voltage conversion module, is used to provide power that meets a predetermined voltage.

14. The processor board as described in claim 8, characterized in that, The printed circuit board includes a complex programmable logic device interface, and the processor board further includes: A complex programmable logic device, with an interface connected to the complex programmable logic device, is used to control the voltage input of the processor board.

15. The processor board as described in claim 8, characterized in that, The printed circuit board includes a serial peripheral interface, and the processor board further includes: The flash memory chip is connected to the serial peripheral interface.

16. A processor board as described in claim 8, characterized in that, The printed circuit board includes a clock signal interface, and the processor board also includes: The clock module is connected to the clock signal interface.

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