Low-power LVDS transmitter

Abstract

The present application discloses a low-power LVDS transmitter, which provides a switching circuit and a mirror current source, so that the switching circuit is connected to at least one transistor in the mirror current source, and can selectively control multiple transistors in the mirror current source to be turned on or off, thereby turning on or off the mirror current source. When the mirror current source is turned on, the mirror current source can output current to the main drive circuit, so that the main drive circuit can generate a differential signal, thereby realizing data transmission. When the mirror current source is turned off, the main drive circuit is also turned off due to the lack of input current. This realizes that when data transmission does not need to be performed through the LVDS transmitter, the mirror current source and the main drive circuit are turned off, thereby reducing the power consumption of the LVDS transmitter, and at the same time, it will not affect the normal operation of other functional modules in the circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a low-power LVDS transmitter. Background Art

[0002] LVDS (Low Voltage Differential Signaling) uses extremely low voltage swings to transmit data differentially at high speed, enabling point-to-point or point-to-multipoint connections. It features low power consumption, low bit error rate, low crosstalk, and low radiation.

[0003] In the prior art, regardless of whether a main driving circuit of an LVDS transmitter needs to output a differential signal to realize data transmission, the main driving circuit remains in an operating state, resulting in high power consumption of the LVDS transmitter. Summary of the Invention

[0004] In order to solve the above problems, the present application provides a low-power LVDS transmitter capable of selectively shutting down a main driving circuit.

[0005] According to one aspect of an embodiment of the present application, a low-power LVDS transmitter is disclosed, which includes a mirror current source, a main driving circuit, and a switching circuit. The mirror current source is configured to convert an input first current into a second current output, and the mirror current source includes multiple transistors; the main driving circuit is connected to the mirror current source, and the main driving circuit is configured to generate a differential signal based on the second current; the switching circuit is connected to at least one of the transistors in the mirror current source and is configured to selectively control at least one of the transistors to be turned on or off, so as to control the multiple transistors in the mirror current source to be turned on or off; wherein, when the multiple transistors are turned off, the mirror current source is turned off.

[0006] In an exemplary embodiment, the mirror current source includes a first current mirror circuit and a second current mirror circuit, wherein the first current mirror circuit is configured to receive the input first current, and the first current mirror circuit is a common source and common gate current mirror circuit; the second current mirror circuit connects the first current mirror circuit and the main driving circuit, and the second current mirror circuit is configured to output the second current to the main driving circuit.

[0007] In an exemplary embodiment, the first current mirror circuit includes a first resistor, a first front-end transistor, a plurality of first back-end transistors, a second front-end transistor, and a plurality of second back-end transistors, wherein the first end of the first resistor is connected to the control end of the first front-end transistor and the control end of the plurality of first back-end transistors, the second end of the first resistor is connected to the first end of the first front-end transistor, the first current is input through the first end of the first resistor, the second end of the first front-end transistor is connected to the first end of the second front-end transistor; the control end of the second front-end transistor is connected to the control end of the plurality of second back-end transistors; the first end of one of the plurality of first back-end transistors is connected to the main driving circuit, and the plurality of first back-end transistors except for the one are connected to the first end of the first back-end transistor. The first end of the first back-end transistor is connected to the second current mirror circuit, the second end of each of the first back-end transistors is connected to the first end of a second back-end transistor, and the second ends of the multiple second back-end transistors are connected to the ground end; the switching circuit includes a first switching transistor and a second switching transistor, the control end of the first switching transistor is configured to receive a first signal, the first end of the first switching transistor is connected to the first end of the first front-end transistor, the second end of the first switching transistor is connected to the control end of the second front-end transistor, the control end of the second switching transistor is configured to receive a second signal, the second signal is opposite in level to the first signal, the first end of the second switching transistor is connected to the control end of the second front-end transistor, and the second end of the second switching transistor is connected to the ground end.

[0008] In an exemplary embodiment, the multiple first back-end transistors include three first back-end transistors, and the multiple second back-end transistors include three second back-end transistors; the second current mirror circuit includes three third back-end transistors, and the control ends of the three third back-end transistors are connected together, wherein the first ends of two third back-end transistors are respectively connected to the first end of one of the first back-end transistors, and the first end of one third back-end transistor is connected to the current input end of the main driving circuit, wherein the first end of one of the two third back-end transistors is connected to its control end, and the second ends of the three third back-end transistors are connected to a voltage source.

[0009] In an exemplary embodiment, the first front-end transistor, the first back-end transistor, the second front-end transistor, the second back-end transistor, the first switch transistor and the second switch transistor are P-type field-effect transistors, and the second current mirror circuit includes multiple N-type field-effect transistors.

[0010] In an exemplary embodiment, the low power LVDS transmitter further includes a voltage source capable of providing a 1.8V voltage output to turn on each transistor.

[0011] In an exemplary embodiment, the low-power LVDS transmitter also includes a common-mode feedback circuit, which includes a first feedback amplifier circuit and a second feedback amplifier circuit. The first feedback amplifier circuit is connected to the output end of the main driving circuit, and is used to detect the common-mode voltage of the differential signal output by the main driving circuit, and amplify the voltage difference between the common-mode voltage and the reference voltage and output it. The input end of the second feedback amplifier circuit is connected to the output end of the first feedback amplifier circuit to receive and amplify the voltage difference amplified by the first feedback amplifier circuit. The output end of the second feedback amplifier circuit is connected to the current input end of the main driving circuit to adjust the common-mode voltage of the differential signal output by the main driving circuit.

[0012] In an exemplary embodiment, the second feedback amplifier circuit includes an amplifier transistor having a control end, a first end, and a second end. The control end of the amplifier transistor serves as the input end of the second feedback amplifier circuit, the first end of the amplifier transistor serves as the output end of the second feedback amplifier circuit, and the second end of the amplifier transistor is connected to a voltage source.

[0013] In an exemplary embodiment, the common-mode feedback circuit also includes a Miller compensation circuit, which includes a Miller compensation capacitor and a zero-adjustment resistor. One end of the Miller compensation capacitor is connected to the output end of the first feedback amplifier circuit, the other end of the Miller compensation capacitor is connected to one end of the zero-adjustment resistor, and the other end of the zero-adjustment resistor is connected to the current input end of the main drive circuit.

[0014] In an exemplary embodiment, the low-power LVDS transmitter further includes a single-ended to differential circuit and a pre-driver circuit, wherein the single-ended to differential circuit is configured to convert an input signal into a differential signal output; the input end of the pre-driver circuit is connected to the output end of the single-ended to differential circuit, and the output end of the pre-driver circuit is connected to the main driver circuit.

[0015] The technical solutions provided by the embodiments of the present application include at least the following beneficial effects:

[0016] The low-power LVDS transmitter disclosed in the present application is provided with a switching circuit and a mirror current source, so that the switching circuit is connected to at least one transistor in the mirror current source, and can selectively control multiple transistors in the mirror current source to be turned on or off, thereby turning on or off the mirror current source. When the mirror current source is turned on, the mirror current source can output current to the main drive circuit, so that the main drive circuit can generate a differential signal, thereby realizing data transmission. When the mirror current source is turned off, the main drive circuit is also turned off due to the lack of input current. This realizes that when data transmission does not need to be performed through the LVDS transmitter, the mirror current source and the main drive circuit are turned off, thereby reducing the power consumption of the LVDS transmitter. At the same time, it will not affect the normal operation of other functional modules in the circuit.

[0017] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 The figure shows a block diagram of the low-power LVDS transmitter provided in the first embodiment of the present application.

[0020] Figure 2 A partial circuit schematic diagram of a low-power LVDS transmitter provided in Example 1 of the present application is shown.

[0021] Figure 3 A schematic diagram of a partial circuit of a low-power LVDS transmitter and a receiving end provided in Example 1 of the present application is shown.

[0022] Figure 4 The schematic diagram of the circuit of the comparison amplifier provided in the first embodiment of the present application is shown.

[0023] Figure 5 The output eye diagram of the low-power LVDS transmitter provided in the first embodiment of the present application is shown.

[0024] The following are the descriptions of the reference numerals:

[0025] 100, low-power LVDS transmitter; 101, single-ended to differential conversion circuit; 102, pre-driver circuit; 103, transmitter circuit; 1031, mirror current source; 10311, first current mirror circuit; R1, first resistor; M3, first front-end transistor; M5 / M7 / M9, first back-end transistor; M4, second front-end transistor; M6 / M8 / M10, second back-end transistor; 10312, second current mirror circuit; M11 / M12 / M13, third back-end transistor; 1032, main driver circuit; M14, first transistor; M15, second transistor; M16, third transistor; M17, fourth transistor; I1, tail current source; R load , load resistance; 1033, switching circuit; M1, first switching transistor; M2, second switching transistor; 104, common-mode feedback circuit; 1041, first feedback amplifier circuit; 10411, voltage detection circuit; R2, first voltage-dividing resistor; R3, second voltage-dividing resistor; 10412, comparison amplifier; M19, fifth transistor; M20, sixth transistor; M21, seventh transistor; M22, eighth transistor; M23, ninth transistor; 1042, second feedback amplifier circuit; M18, amplifier transistor; 1043, Miller compensation circuit; Cc, Miller compensation capacitor; Rc, zero adjustment resistor. DETAILED DESCRIPTION

[0026] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0027] In the description of this application, the terms "first," "second," "third," and other ordinal numbers are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features specified with ordinal numbers such as "first," "second," and "third" may explicitly or implicitly include one or more features.

[0028] In the related art, an LVDS transmitter generally includes a current source and a main drive circuit. The current source provides input current to the main drive circuit, and the main drive circuit generates a differential signal based on the input current, thereby achieving data transmission. However, in the prior art, regardless of whether the main drive circuit needs to output a differential signal to achieve data transmission, the main drive circuit and the current source remain in an operating state, resulting in high power consumption of the LVDS transmitter. To this end, the present application provides a low-power LVDS transmitter that can shut down the current source and the main drive circuit when data transmission is not required through the LVDS transmitter, thereby reducing the power consumption of the LVDS transmitter.

[0029] Figure 1 The following is a block diagram of a low-power LVDS transmitter according to the first embodiment of the present invention. Figure 2 A partial circuit schematic diagram of a low-power LVDS transmitter provided in Example 1 of the present application is shown.

[0030] See Figure 1 As shown, the low-power LVDS transmitter 100 mainly includes a single-ended to differential circuit 101, a pre-driving circuit 102, a transmitting end circuit 103 and a common-mode feedback circuit 104.

[0031] Among them, the input end of the single-ended to differential circuit 101 receives the single-ended input signal TX_Datain, the output end of the single-ended to differential circuit 101 is connected to the input end of the pre-driver circuit 102, and the single-ended to differential circuit 101 is configured to convert the single-ended input signal TX_Datain into a differential signal and output the differential signal to the pre-driver circuit 102.

[0032] It should be noted that the single-ended to differential circuit 101 can be any existing single-ended to differential circuit as long as it can convert a single-ended input signal into a differential signal output, so it will not be described in detail here.

[0033] As previously described, the input end of the pre-driver circuit 102 is connected to the output end of the single-ended to differential conversion circuit 101, and the output end of the pre-driver circuit 102 is connected to the transmitter circuit 103. The pre-driver circuit 102 is configured to drive and convert the differential signal input by the single-ended to differential conversion circuit 101 and then output the differential signal to the transmitter circuit 103, thereby increasing the signal transmission rate to ensure high-speed signal transmission.

[0034] It should be noted that the pre-driver circuit 102 can be any existing pre-driver circuit as long as it can improve the signal transmission rate of the LVDS transmitter 100, and therefore will not be described in detail here. In one embodiment of the present application, the LVDS transmitter 100 can transmit data signals at 1 Gbps, which is a significant improvement in signal transmission rate compared to traditional LVDS technology.

[0035] Of course, in some embodiments, the pre-driving circuit 102 and / or the single-ended to differential circuit 101 may not be provided.

[0036] See Figure 2 As shown, the transmitting end circuit 103 mainly includes a mirror current source 1031, a main driving circuit 1032 and a switch circuit 1033.

[0037] The current input terminal of the mirror current source 1031 is connected to a current output circuit (not shown) to receive a first current. The current output circuit may include a bandgap circuit and a current calibration circuit. The bandgap circuit outputs a bandgap reference, which is calibrated by the current calibration circuit. The current calibration circuit then outputs a precise current Ibias_drv (first current) that is independent of temperature and voltage to the mirror current source 1031. The current output terminal of the mirror current source 1031 is connected to the current input terminal of the main drive circuit 1032. The mirror current source 1031 is configured to convert the input first current Ibias_drv into a second current Iload and output it to the current input terminal of the main drive circuit 1032.

[0038] In one embodiment of the present application, the mirror current source 1031 includes a first current mirror circuit 10311 and a second current mirror circuit 10312 .

[0039] The first current mirror circuit 10311 is configured to receive an input first current Ibias_drv, and the first current mirror circuit 10311 is a cascode current mirror circuit. In this embodiment, the first current mirror circuit 10311 is configured as a cascode current mirror circuit. The cascode current mirror circuit has a large output impedance and a more accurate mirror current, so that the mirror current source 1031 can accurately convert the first current Ibias_drv into the desired second current Iload.

[0040] In one embodiment of the present application, Figure 2 As shown, the first current mirror circuit 10311 includes a first resistor R1, a first front-end transistor M3, three first back-end transistors (labeled as M5, M7, and M9 respectively), a second front-end transistor M4, and three second back-end transistors (labeled as M6, M8, and M10 respectively).

[0041] The first end of the first resistor R1 is connected to the control end of the first front-end transistor M3 and the control ends of the first back-end transistors M5, M7, and M9. The second end of the first resistor R1 is connected to the first end of the first front-end transistor M3. The first end of the first resistor R1 serves as the current input end of the mirror current source 1031, which is connected to the aforementioned current output circuit. That is, the first current Ibias_drv is input through the first end of the first resistor R1. The second end of the first front-end transistor M3 is connected to the first end of the second front-end transistor M4. The control end of the second front-end transistor M4 is connected to the control ends of the second back-end transistors M6, M8, and M10. The second end of the second front-end transistor M4 is connected to the ground end. The first ends of the first back-end transistor M5 and the first back-end transistor M7 are connected to the second current mirror circuit 10312, the first end of the first back-end transistor M9 is connected to the main driving circuit 1032, the second end of the first back-end transistor M5 is connected to the first end of the second back-end transistor M6, the second end of the first back-end transistor M7 is connected to the first end of the second back-end transistor M8, the second end of the first back-end transistor M9 is connected to the first end of the second back-end transistor M10, and the second ends of the second back-end transistors M6, M8, and M10 are connected to the ground.

[0042] exist Figure 2 In the illustrated embodiment, the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, the first back-end transistor M9, the second front-end transistor M4, the second back-end transistor M6, the second front-end transistor M8, and the second front-end transistor M10 are all P-type field-effect transistors, wherein the control terminal of the transistor is the gate of the transistor, the first terminal of the transistor is the drain of the transistor, and the second terminal of the transistor is the source of the transistor. Of course, the transistors may also be replaced by transistors other than field-effect transistors.

[0043] The second current mirror circuit 10312 is connected to the first current mirror circuit 10311 and the current input terminal of the main driving circuit 1032 . The second current mirror circuit 10312 is configured to output a second current Iload to the current input terminal of the main driving circuit 1032 .

[0044] In one embodiment of the present application, the second current mirror circuit 10312 includes three third back-end transistors (labeled as M11, M12, and M13, respectively). The control terminals of the three third back-end transistors M11, M12, and M13 are connected together, wherein the first terminal of the third back-end transistor M11 is connected to the first terminal of the first back-end transistor M5, the first terminal of the third back-end transistor M12 is connected to the first terminal of the first back-end transistor M7, and the first terminal of the third back-end transistor M13 is connected to the current input terminal of the main driving circuit 1032. That is, the first terminal of the third back-end transistor M13 serves as the current output terminal of the mirror current source 1031 to output the second current Iload to the main driving circuit 1032. The control terminal of the third back-end transistor M11 is connected to its first terminal so that the control terminal of the third back-end transistor M11 is connected to the first terminal of the first back-end transistor M5. The second terminals of the third back-end transistors M11, M12, and M13 are connected to the voltage source VDD.

[0045] exist Figure 2 In the illustrated embodiment, the third back-end transistor M11, the third back-end transistor M12, and the third back-end transistor M13 are all N-type field-effect transistors, wherein the control terminal of the transistor is the gate of the transistor, the first terminal of the transistor is the drain of the transistor, and the second terminal of the transistor is the source of the transistor. Of course, the transistors may also be replaced by transistors other than field-effect transistors.

[0046] When the first front-end transistor M3 is turned on, the first current Ibias_drv reaches the first front-end transistor M3 through the first resistor R1, and the control end of the first front-end transistor M3 generates a voltage vbn1. Since the control ends of the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are connected together, the control ends of the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 generate the same voltage vbn1 as the control end of the first front-end transistor M3, and the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are all turned on. If the second front-end transistor M4 is also turned on at this time, a voltage vbn2 is generated at the control terminal of the second front-end transistor M4. Since the control terminals of the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 are connected together, the control terminals of the second back-end transistors M6, the second back-end transistor M8, and the second back-end transistor M10 generate the same voltage vbn2 as the control terminal of the second front-end transistor M4, and the second back-end transistors M6, the second back-end transistor M8, and the second back-end transistor M10 are turned on. Since the first terminal of the third back-end transistor M11 is connected to the first terminal of the first back-end transistor M5, and the control terminal of the third back-end transistor M11 is connected to the first terminal of the first back-end transistor M5, a voltage vbp is generated at the control terminal of the third back-end transistor M11. Since the control terminals of the third back-end transistors M11, the third back-end transistors M12, and the third back-end transistors M13 are connected together, the control terminals of the third back-end transistors M12 and the third back-end transistors M13 generate the same voltage vbp as the control terminal of the third back-end transistor M11, and the third back-end transistors M11, M12, and M13 are all turned on. At this time, the mirror current source 1031 can convert the first current Ibias_drv into the second current Iload for output.

[0047] The second current Iload is determined based on the first current Ibias_drv and the parameters of the transistors M3-M13 in the mirror current source 1031. In one embodiment of the present application, the mirror current source 1031 amplifies the first current Ibias_drv by a factor of 14 to obtain and output the second current Iload. For example, the first current Ibias_drv is 17.5uA to 35uA, and accordingly, the second current Iload is 2.45mA to 4.90mA.

[0048] Conversely, when the first front-end transistor M3 is turned off, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are all turned off. If the voltage at the control terminal of the second front-end transistor M4 is at a low level at this time, the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 are turned off. Since the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are turned off at this time, the third back-end transistor M11, the third back-end transistor M12, and the third back-end transistor M13 are also turned off. At this time, the mirror current source 1031 is turned off and no current is output by the mirror current source 1031.

[0049] See again Figure 2 As shown, the switch circuit 1033 is connected to at least one transistor in the mirror current source 1031 and is configured to selectively control the at least one transistor in the mirror current source 1031 to be turned on or off, thereby controlling all transistors in the mirror current source 1031 to be turned on or off.

[0050] In one embodiment of the present application, the switching circuit 1033 includes a first switching transistor M1 and a second switching transistor M2. The control end of the first switching transistor M1 is configured to receive a first signal pwd_b. The first end of the first switching transistor M1 is connected to the first end of the first front-end transistor M3. The second end of the first switching transistor M1 is connected to the control end of the second front-end transistor M4. The control end of the second switching transistor M2 is configured to receive a second signal pwd. The second signal pwd has a level opposite to that of the first signal pwd_b. The first end of the second switching transistor M2 is connected to the control end of the second front-end transistor M4. The second end of the second switching transistor M2 is connected to the ground end.

[0051] When the second signal pwd is at a low level, the first signal pwd_b is at a high level. At this time, the first switching transistor M1 is turned on and the second switching transistor M2 is turned off. The first current Ibias_drv can be input through the first resistor R1, causing the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 to generate a gate voltage and turn on. Similarly, the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 generate a gate voltage and turn on, and the third back-end transistors M11, the third back-end transistor M12, and the third back-end transistor M13 generate a gate voltage and turn on. At this time, the entire mirror current source 1031 is turned on, and the mirror current source 1031 can convert the first current Ibias_drv into the second current Iload for output.

[0052] Conversely, when the second signal pwd is at a high level, the first signal pwd_b is at a low level. At this time, the first switching transistor M1 is turned off, the first current Ibias_drv cannot be input through the first resistor R1, and the first front-end transistor M3, the first back-end transistor M5, the first back-end transistor M7, and the first back-end transistor M9 are turned off. At the same time, the second switching transistor M2 is turned on, and its gate voltage is equal to the ground voltage, causing the second front-end transistor M4, the second back-end transistor M6, the second back-end transistor M8, and the second back-end transistor M10 to be turned off, and the third back-end transistors M11, M12, and M13 to be turned off as well. At this time, the entire mirror current source 1031 is turned off, and the mirror current source 1031 has no current output.

[0053] exist Figure 2 In the illustrated embodiment, the first switching transistor M1 and the second switching transistor M2 are both P-type field-effect transistors, wherein the control terminal of the transistor is the gate of the transistor, the first terminal of the transistor is the drain of the transistor, and the second terminal of the transistor is the source of the transistor. Of course, the transistors may also be replaced by transistors other than field-effect transistors.

[0054] exist Figure 2 In the illustrated embodiment, the switching circuit 1033 is configured to include a first switching transistor M1 and a second switching transistor M2. The first signal pwd_b received by the control terminal of the first switching transistor M1 is configured to have opposite levels to the second signal pwd received by the control terminal of the second switching transistor M2, thereby reliably controlling the mirror current source 1031 to be turned on or off.

[0055] The main driving circuit 1032 is connected to the mirror current source 1031, specifically to the current output terminal of the second current mirror circuit 1031, that is, the drain of the third back-end transistor M13. The main driving circuit 1032 is configured to generate a differential signal based on the second current Iload output by the mirror current source 1031.

[0056] In one embodiment of the present application, Figure 3 As shown, the main driving circuit 1032 includes a first transistor M14, a second transistor M15, a third transistor M16, a fourth transistor M17 and a tail current source I1.

[0057] Among them, the control ends of the first transistor M14 and the third transistor M16 are connected to the positive signal input terminal Vin+, and the control ends of the second transistor M15 and the fourth transistor M17 are connected to the negative signal input terminal Vin-. The first transistor M14, the second transistor M15, the third transistor M16, and the fourth transistor M17 are controlled to be turned on or off by the control signals input to the signal input terminal Vin+ and the signal input terminal Vin-.

[0058] The first transistor M14, the second transistor M15, the third transistor M16, and the fourth transistor M17 are all linear switching transistors. The first end of the first transistor M14 is connected to the first end of the third transistor M16, and the first end of the second transistor M15 is connected to the first end of the fourth transistor M17. The second end of the first transistor M14 and the second end of the second transistor M15 serve as current input ends of the main driving circuit 1032 and are connected to the mirror current source 1031. A constant second current Iload is input through the mirror current source 1031. The second end of the third transistor M16 and the second end of the fourth transistor M17 are connected to the tail current source I1 and are connected to the ground end through the tail current source I1.

[0059] At the same time, the current input terminal of the main driving circuit 1032, that is, the second terminal of the first transistor M14 and the second terminal of the second transistor M15 are also connected to the output terminal of the common mode feedback circuit 104 to receive the adjustment current I output by the common mode feedback circuit 104. CM , the second current Iload input by the mirror current source 1031 and the adjustment current I CM The superposition is used as the power supply current of the main driving circuit 1032. When the power supply current changes, the common mode voltage V out,cm Change accordingly.

[0060] A connection node between the first end of the first transistor M14 and the first end of the third transistor M16 is connected to a load resistor R load One end of the load resistor R load The other end is connected to the connection node of the first end of the second transistor M15 and the first end of the fourth transistor M17, and the load resistor R load The two ends of the resistor R load The voltage across the two ends of is the differential signal voltage swing output by the main driving circuit 1032. load As the matching impedance of the main driving circuit 1032, the load resistor R load Connect in parallel to the differential signal receiving end.

[0061] When the second transistor M15 and the third transistor M16 are turned on and the first transistor M14 and the fourth transistor M17 are turned off, the supply current flows through the second transistor M15 to the load resistor R load , and through the load resistor R load Then it returns to the third transistor M16, and finally reaches the ground through the third transistor M16. The supply current flows through the load resistor R loadWhen the second transistor M15 and the third transistor M16 are turned off and the first transistor M14 and the fourth transistor M17 are turned on, the supply current flows through the first transistor M14 to the load resistor R load , and through the load resistor R load Then it returns to the fourth transistor M17, and finally reaches the ground through the fourth transistor M17. The supply current flows through the load resistor R load The corresponding voltage drop also occurs on the load resistor R load The voltage drop across the main drive circuit 1032 is opposite in direction to that when the second and third transistors M15 and M16 are on and the first and fourth transistors M14 and M17 are off. That is, if the output of the main drive circuit 1032 is high at this time, then the output of the main drive circuit 1032 is low when the second and third transistors M15 and M16 are on and the first and fourth transistors M14 and M17 are off. If the output of the main drive circuit 1032 is low at this time, then the output of the main drive circuit 1032 is high when the second and third transistors M15 and M16 are on and the first and fourth transistors M14 and M17 are off. The main drive circuit 1032 utilizes voltage swings for high-speed differential data transmission.

[0062] In one embodiment of the present application, the load resistor R load The resistance is 100Ω, the supply current is in the load resistance R load The voltage drop generated on the load is the product of the supply current and 100Ω. For example, the first current Ibias_drv is 17.5uA ~ 35uA, and the mirror current source 1031 amplifies the first current Ibias_drv by 14 times. Correspondingly, the second current Iload is 2.45mA ~ 4.90mA. It can be seen that the voltage swing range of the main driving circuit 1032 is V OD =490mV~980mV.

[0063] It should be noted that the tail current source I1 may be any existing current source structure. For example, the tail current source I1 is composed of two field effect transistors.

[0064] It should be noted that the main driving circuit 1032 is not limited to Figure 3 The structure shown is as shown. In other embodiments, the main driving circuit 1032 can be of any structural form as long as it can achieve the generation and output of differential signals.

[0065] exist Figure 3In the illustrated embodiment, the first transistor M14, the second transistor M15, the third transistor M16, and the fourth transistor M17 are all field-effect transistors (FETs), with the control terminal being the gate of the transistor, the first terminal being the drain of the transistor, and the second terminal being the source of the transistor. The first transistor M14 and the second transistor M15 are N-type FETs, while the third transistor M16 and the fourth transistor M17 are P-type FETs. Of course, the transistors may also be replaced by transistors other than FETs.

[0066] See Figure 3 As shown, the common-mode feedback circuit 104 includes a first feedback amplifier circuit 1041 and a second feedback amplifier circuit 1042. The first feedback amplifier circuit 1041 is connected to the output end of the main driving circuit 1032 and is used to detect the common-mode voltage V of the differential signal output by the main driving circuit 1032. out,cm , and amplify the common mode voltage V out,cm With the reference voltage V cm，ref The voltage difference is then output. Among them, the reference voltage V cm，ref It can be generated by a bandgap circuit (not shown in the figure).

[0067] The first feedback amplifier circuit 1041 includes a voltage detection circuit 10411 and a comparison amplifier 10412 .

[0068] The voltage detection circuit 10411 is connected between the two differential output terminals of the main driving circuit 1032, that is, the voltage detection circuit 10411 is connected in parallel with the load resistor R load The voltage detection circuit 10411 is used to detect the common mode voltage V of the differential signal output by the main driving circuit 1032. out,cm .

[0069] In one embodiment of the present application, the voltage detection circuit 10411 includes a first voltage divider resistor R2 and a second voltage divider resistor R3. One end of the first voltage divider resistor R2 is connected to one of the differential output terminals of the main driving circuit 1032. That is, one end of the first voltage divider resistor R2 is connected to the load resistor R load The other end of the first voltage-dividing resistor R2 is connected to one end of the second voltage-dividing resistor R3, and the other end of the second voltage-dividing resistor R3 is connected to the other differential output end of the main driving circuit 1032. That is, the other end of the second voltage-dividing resistor R3 is connected to the load resistor R load the other end.

[0070] In this embodiment, the voltage detection circuit 10411 is configured to include a first voltage-dividing resistor R2 and a second voltage-dividing resistor R3 , and the circuit structure of the voltage detection circuit 10411 is simple.

[0071] It should be noted that the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3 are large-value resistors so that the power supply current flows entirely through the load resistor R load .

[0072] The comparison amplifier 10412 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparison amplifier 10412 is connected to the voltage detection circuit 10411 to receive the common mode voltage V detected by the voltage detection circuit 10411. out,cm The second input terminal of the comparison amplifier 10412 is used to receive the reference voltage V cm,ref The output of the comparison amplifier 10412 is connected to the input of the second feedback amplifier circuit 1042. The comparison amplifier 10412 compares the common mode voltage V out,cm With the reference voltage V cm,ref The voltage difference is amplified and the common mode voltage V out,cm With the reference voltage V cm,ref The voltage difference is then output to the second feedback amplifier circuit 1042.

[0073] In an embodiment where the voltage detection circuit 10411 includes a first voltage-dividing resistor R2 and a second voltage-dividing resistor R3, the first input terminal of the comparison amplifier 10412 is connected to the junction node of the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3, and the common-mode voltage V of the differential signal output by the main driving circuit 1032 is obtained by detecting the resistor voltage divider. out,cm .

[0074] In this embodiment, the first feedback amplifier circuit 1041 includes a voltage detection circuit 10411 and a comparison amplifier 10412. The voltage detection circuit 10411 is used to detect the common mode voltage V of the differential signal output by the main driving circuit 1032. out,cm , and then compare the common mode voltage V out,cm With the reference voltage V cm,ref The voltage difference is amplified and the common mode voltage V out,cm With the reference voltage V cm,ref The voltage difference is then output to the second feedback amplifier circuit 1042. The circuit structure of the first feedback amplifier circuit 1041 is simple and the cost is low.

[0075] Figure 4 The schematic diagram of the circuit of the comparison amplifier provided in the first embodiment of the present application is shown.

[0076] See Figure 4 As shown, in one embodiment of the present application, the comparison amplifier 10412 includes a fifth transistor M19, a sixth transistor M20, a seventh transistor M21, an eighth transistor M22 and a ninth transistor M23.

[0077] The control terminal of the fifth transistor M19 serves as the first input terminal of the comparison amplifier 10412, which receives the common mode voltage V obtained by the voltage detection circuit 10411. out,cm , a first end of the fifth transistor M19 is connected to the second end of the seventh transistor M21 , and a second end of the fifth transistor M19 is connected to the first end of the ninth transistor M23 .

[0078] The control terminal of the sixth transistor M20 serves as the second input terminal of the comparison amplifier 10412, receiving the reference voltage B cm, The first end of the sixth transistor M20 is connected to the second end of the eighth transistor M22, and the connection node between the first end of the sixth transistor M20 and the second end of the eighth transistor M22 serves as the output end of the comparison amplifier 10412, outputting the amplified voltage difference V fb , the second end of the sixth transistor M20 is connected to the first end of the ninth transistor M23.

[0079] The control end of the seventh transistor M21 is connected to the control end of the eighth transistor M22, and a connection node between the control end of the seventh transistor M21 and the control end of the eighth transistor M22 and a connection node between the first end of the fifth transistor M19 and the second end of the seventh transistor M21 are connected. The first end of the seventh transistor M21 and the first end of the eighth transistor M22 are connected to a voltage source VDD. The voltage source VDD provides a voltage to each transistor in the comparison amplifier 10412, thereby enabling each transistor in the comparison amplifier 10412 to be turned on and operate.

[0080] The ninth transistor M23 serves as a tail current source. A first terminal of the ninth transistor M23 is connected to the second terminals of the fifth transistor M19 and the sixth transistor M20. A second terminal of the ninth transistor M23 is connected to the ground. A control terminal of the ninth transistor M23 receives the input voltage Vb.

[0081] exist Figure 4 In the illustrated embodiment, the comparison amplifier 10412 is a simple five-transistor operational amplifier with a simple structure and a high output swing, which facilitates the introduction of the output voltage into the main driving circuit 1032 .

[0082] exist Figure 4 In the illustrated embodiment, the fifth transistor M19, the sixth transistor M20, the seventh transistor M21, the eighth transistor M22, and the ninth transistor M23 are all field-effect transistors (FETs), wherein the control terminal is the gate of the transistor, the first terminal is the drain of the transistor, and the second terminal is the source of the transistor. Specifically, the seventh transistor M21 and the eighth transistor M22 are P-type FETs, while the fifth transistor M19, the sixth transistor M20, and the ninth transistor M23 are N-type FETs. Of course, the transistors may also be replaced by transistors other than FETs.

[0083] See also Figure 3 The input end of the second feedback amplifier circuit 1042 is connected to the output end of the first feedback amplifier circuit 1041 to receive and amplify the voltage difference amplified by the first feedback amplifier circuit 1041, and the output end of the second feedback amplifier circuit 1042 is connected to the current input end of the main driving circuit 1032 to adjust the common-mode voltage of the differential signal output by the main driving circuit 1032.

[0084] In one embodiment of the present application, the second feedback amplifier circuit 1042 includes an amplifier transistor M18, which has a control terminal, a first terminal, and a second terminal. The control terminal of the amplifier transistor M18 serves as an input terminal of the second feedback amplifier circuit 1042 for receiving the voltage difference V fb ; The first end of the amplifier transistor M18 serves as the output end of the second feedback amplifier circuit 1042 and is connected to the current input end of the main driving circuit 1032; the second end of the amplifier transistor M18 is connected to the voltage source VDD, and the voltage source VDD provides voltage to the amplifier transistor M18, so that the amplifier transistor M18 can be turned on and work.

[0085] In this embodiment, the amplifying transistor M18 is used as the second feedback amplifying circuit 1042. The second feedback amplifying circuit 1042 has a simple structure. Of course, in other embodiments, the second feedback amplifying circuit 1042 may also have other components.

[0086] In detail, the amplifier transistor M18 is an N-type field effect transistor, the control end of the amplifier transistor M18 is the gate of the amplifier transistor M18, the first end of the amplifier transistor M18 is the drain of the amplifier transistor M18, and the second end of the amplifier transistor M18 is the source of the amplifier transistor M18.

[0087] When the common-mode voltage V out,cm Higher than the reference voltage V cm，ref , the voltage difference V output by the first feedback amplifier circuit 1041 fb Increase, the gate voltage V of the amplifying transistor M18 G Increases, and the source of the amplifier transistor M18 is connected to the voltage source VDD, that is, the source voltage of the amplifier transistor M18 is VDD. Since the amplifier transistor M18 satisfies the relationship V Gs =VDD(V S )-V G (V fb ), when the gate voltage V G Increase, V Gs So the output current of the amplifier transistor M18 decreases (the output current of the transistor is related to V Gs The relationship between V GsThe smaller the value, the smaller the output current. GS The larger the output current is, the larger the output current is). CM decreases, so the supply current of the main driving circuit 1032 decreases, thereby making the common mode level V out,cm Similarly, when the common mode voltage V out,cm Lower than the reference voltage V cm，ref , the voltage difference V output by the first feedback amplifier circuit 1041 fb Reduce, amplify the gate voltage V of transistor M18 G Lower, V GS Increases, so the output current of the amplifier transistor M18 increases, that is, the adjustment current I CM increases, so the supply current of the main driving circuit 1032 increases, thereby making the common mode level V out,cm That is, by adjusting the output current I of the amplifying transistor M18 CM , to adjust the common mode level V out,cm .

[0088] In one embodiment of the present application, the common-mode feedback circuit 104 further includes a Miller compensation circuit 1043 connected between the output terminal of the first feedback amplifier circuit 1041 and the current input terminal of the main driving circuit 1032. The Miller compensation circuit 1043 improves the phase margin of the common-mode feedback circuit 104.

[0089] In one embodiment of the present application, the Miller compensation circuit 1043 includes a Miller compensation capacitor Cc and a zero-adjustment resistor Rc, one end of the Miller compensation capacitor Cc is connected to the output end of the first feedback amplifier circuit 1041, the other end of the Miller compensation capacitor Cc is connected to one end of the zero-adjustment resistor Rc, and the other end of the zero-adjustment resistor Rc is connected to the current input end of the main driving circuit 1032.

[0090] Of course, the Miller compensation circuit 1043 may also adopt other component structures. For example, in some embodiments, the Miller compensation circuit 1043 only includes a Miller compensation capacitor Cc, and the two ends of the Miller compensation capacitor Cc are respectively connected to the output end of the first feedback amplifier circuit 1041 and the current input end of the main driving circuit 1032; for another example, in some embodiments, the Miller compensation circuit 1043 includes two Miller compensation capacitors and a zero adjustment resistor, and the zero adjustment resistor is connected in series between the two Miller compensation capacitors.

[0091] In one embodiment, the Miller compensation capacitor Cc is implemented by a MOM capacitor and a MOS transistor, that is, the MOM capacitor and the MOS transistor are stacked together, and the MOS transistor is used to provide a metal layer structure, thereby providing partial capacitance, which can reduce the occupied area of ​​the Miller compensation capacitor Cc.

[0092] In the aforementioned embodiment, the common mode voltage V of the differential signal output by the main driving circuit 1032 is detected by the first feedback amplifier circuit 1041. out,cm and the common mode voltage V out,cm With the reference voltage V cm,ref Compare and obtain the common mode voltage V out,cm With the reference voltage V cm,ref The voltage difference is amplified and outputted, and then the voltage difference amplified by the first feedback amplifier circuit 1041 is amplified by the second feedback amplifier circuit 1042 and fed back to the main driving circuit 1032, specifically to adjust the current I CM , thereby adjusting the current input to the main driving circuit 1032, and further adjusting the common mode voltage V of the differential signal output by the main driving circuit 1032 out,cm , which can stabilize the common-mode voltage and thus reduce signal jitter. The two-stage feedback amplifier circuit provides a high loop gain for the entire common-mode feedback circuit 104. Miller compensation circuit 1043 also improves the phase margin and stability of the common-mode feedback circuit 104. This prevents significant output waveform deviation when the entire low-power LVDS transmitter 100 transmits high-rate signals, thereby improving the accuracy of the output signal.

[0093] In one embodiment of the present application, the voltage source VDD provides a 1.8V voltage output to turn on each transistor in the LVDS transmitter 100 so that each transistor can operate normally. Compared with the existing method of using a 3.3V voltage source, the power consumption of the entire circuit can be reduced.

[0094] It should be noted that, in this embodiment, each transistor used can be turned on and operate normally at a voltage of 1.8V.

[0095] The applicant also conducted simulation verification based on the specific embodiment of the present application. During the simulation, a pseudo-random code generator was used to generate a random signal. Considering the series of parasitic effects and transmission loss of the entire LVDS transmitter 100, the 1Gbps differential signal amplitude will be attenuated to a certain extent during the transmission process. Therefore, assuming that the output load capacitance is 2.5pF, the output eye diagram obtained is as follows: Figure 5 As shown. Among them, Figure 5 (a) is the output eye diagram corresponding to the first current Ibias_drv being at its minimum value (i.e., 17.5uA). Figure 5 (b) is the output eye diagram corresponding to the first current Ibias_drv being at its maximum value (ie, 35 uA).

[0096] Depend on Figure 5As shown in (a), when the first current Ibias_drv is 17.5uA, the output eye height of the LVDS transmitter 100 is 463.8mV and the peak-to-peak jitter is 21ps. Figure 5 As shown in (b), when the first current Ibias_drv is 35uA, the output eye height of the LVDS transmitter 100 is 813.8mV and the peak-to-peak jitter is 23ps. Ultimately, the overall power consumption of the LVDS transmitter is less than 12mW. That is, after actual simulation verification, the LVDS transmitter 100 of the present application, under different process angles, power supply voltages and temperature conditions, when the output load capacitance is 2.5pF, can achieve a data transmission rate of up to 1Gbps, which is suitable for signal transmission under high transmission rate requirements. The output differential signal eye height is 490mV-980mV, the output swing is high, the peak-to-peak jitter is less than 23ps, and the maximum static power consumption is 12mW, which can effectively achieve high-speed and low-power data transmission.

[0097] The comparison of parameters between the technical solution of this application and the existing technical solution is shown in Table 1 below:

[0098] Table 1

[0099]

[0100] In summary, the low-power LVDS transmitter 100 disclosed in the present application is provided with a switch circuit 1033 and a mirror current source 1031. The switch circuit 1033 is connected to at least one transistor in the mirror current source 1031, and can selectively control the on or off of multiple transistors in the mirror current source 1031, thereby turning on or off the mirror current source 1031. When the mirror current source 1031 is on, it can output current to the main driving circuit 1032 through the mirror current source 1031, so that the main driving circuit 1032 can generate a differential signal, thereby realizing data transmission. When the mirror current source 1031 is off, due to the lack of input current, the main driving circuit 1032 is also turned off. This achieves the goal of turning off the mirror current source 1031 and the main driving circuit 1032 when data transmission is not required through the LVDS transmitter 100, thereby reducing the power consumption of the LVDS transmitter 100. Ultimately, the maximum static power consumption can be reduced to below 12 mW, and at the same time, it will not affect the normal operation of other functional modules in the circuit.

[0101] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the appended claims.

Claims

1. A low-power LVDS transmitter, characterized in that: include: a mirror current source configured to convert an input first current into a second current output, the mirror current source comprising a first current mirror circuit and a second current mirror circuit having a plurality of transistors, the first current mirror circuit being configured to receive the input first current, the first current mirror circuit being a cascode current mirror circuit comprising a first resistor, a first front-end transistor, a plurality of first back-end transistors, a second front-end transistor, and a plurality of second back-end transistors, wherein a first end of the first resistor is connected to a control end of the first front-end transistor and a control end of the plurality of first back-end transistors, a second end of the first resistor is connected to a first end of the first front-end transistor, the first current is input via the first end of the first resistor, a second end of the first front-end transistor is connected to a first end of the second front-end transistor; a control end of the second front-end transistor is connected to a control end of the plurality of second back-end transistors; a first end of one of the plurality of first back-end transistors is connected to a main body driving circuit, a first end of all first back-end transistors other than the first one of the plurality of first back-end transistors is connected to the second current mirror circuit, a second end of each of the first back-end transistors is connected to a first end of a second back-end transistor, and a second end of the plurality of second back-end transistors is connected to a ground terminal; a second current mirror circuit is connected to the first current mirror circuit and the main body driving circuit, and the second current mirror circuit is configured to output the second current to the main body driving circuit; a main body driving circuit configured to generate a differential signal based on the second current; a switch circuit connected to at least one of the transistors in the mirror current source and configured to selectively control at least one of the transistors to be turned on or off, thereby controlling the multiple transistors in the mirror current source to be turned on or off, the switch circuit comprising a first switch transistor and a second switch transistor, the control terminal of the first switch transistor being configured to receive a first signal, the first terminal of the first switch transistor being connected to the first terminal of the first front-end transistor, the second terminal of the first switch transistor being connected to the control terminal of the second front-end transistor, the control terminal of the second switch transistor being configured to receive a second signal, the second signal being of an opposite level to the first signal, the first terminal of the second switch transistor being connected to the control terminal of the second front-end transistor, and the second terminal of the second switch transistor being connected to a ground terminal; When the multiple transistors are turned off, the mirror current source is turned off.

2. The low-power LVDS transmitter according to claim 1, wherein: The multiple first back-end transistors include three first back-end transistors, and the multiple second back-end transistors include three second back-end transistors; the second current mirror circuit includes three third back-end transistors, and the control ends of the three third back-end transistors are connected together, wherein the first ends of two third back-end transistors are respectively connected to the first end of one of the first back-end transistors, and the first end of one third back-end transistor is connected to the current input end of the main driving circuit, wherein the first end of one of the two third back-end transistors is connected to its control end, and the second ends of the three third back-end transistors are connected to a voltage source.

3. The low-power LVDS transmitter according to claim 1, wherein: The first front-end transistor, the first back-end transistor, the second front-end transistor, the second back-end transistor, the first switch transistor and the second switch transistor are P-type field effect transistors, and the second current mirror circuit includes multiple N-type field effect transistors.

4. The low-power LVDS transmitter according to any one of claims 1 to 3, characterized in that: Also includes: A voltage source is provided, wherein the voltage source can provide a 1.8V voltage output to turn on each transistor.

5. The low-power LVDS transmitter according to any one of claims 1 to 3, characterized in that: Also includes: The common-mode feedback circuit includes a first feedback amplifier circuit and a second feedback amplifier circuit. The first feedback amplifier circuit is connected to the output end of the main driving circuit, and is used to detect the common-mode voltage of the differential signal output by the main driving circuit, and amplify the voltage difference between the common-mode voltage and the reference voltage and output it. The input end of the second feedback amplifier circuit is connected to the output end of the first feedback amplifier circuit to receive and amplify the voltage difference amplified by the first feedback amplifier circuit. The output end of the second feedback amplifier circuit is connected to the current input end of the main driving circuit to adjust the common-mode voltage of the differential signal output by the main driving circuit.

6. The low-power LVDS transmitter according to claim 5, characterized in that: The second feedback amplifier circuit includes an amplifier transistor having a control end, a first end, and a second end. The control end of the amplifier transistor serves as the input end of the second feedback amplifier circuit, the first end of the amplifier transistor serves as the output end of the second feedback amplifier circuit, and the second end of the amplifier transistor is connected to a voltage source.

7. The low-power LVDS transmitter according to claim 5, characterized in that: The common-mode feedback circuit also includes a Miller compensation circuit, which includes a Miller compensation capacitor and a zero-adjustment resistor. One end of the Miller compensation capacitor is connected to the output end of the first feedback amplifier circuit, the other end of the Miller compensation capacitor is connected to one end of the zero-adjustment resistor, and the other end of the zero-adjustment resistor is connected to the current input end of the main drive circuit.

8. The low-power LVDS transmitter according to any one of claims 1 to 3, characterized in that: Also includes: a single-ended to differential conversion circuit configured to convert an input signal into a differential signal output; A pre-driving circuit, wherein the input end of the pre-driving circuit is connected to the output end of the single-ended to differential circuit, and the output end of the pre-driving circuit is connected to the main driving circuit.

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