A double feedback control circuit for TVS reliable triggering

Abstract

The application relates to a double feedback control circuit for reliable triggering of a TVS, and belongs to the field of electronic circuits.The double feedback control circuit comprises a main circuit, a triggering circuit, a field programmable logic gate array (FPGA1), a vacuum relay (2), a display control module (3), a pulse trigger (4), a fiber optic transmitter (5), a fiber optic receiver (6), an AD conversion module two (7), a DA conversion module (8), an AD conversion module one (9) and a fiber (10); the main circuit comprises a main circuit feedback circuit (111); in the main circuit feedback circuit (111), a resistor (R11) and a resistor (R12) are connected in series, one end of the series connection is grounded, and the other end is connected with a vacuum trigger switch (TVS). The triggering circuit is provided with a high-voltage direct-current voltage regulating module, the voltage of a high-voltage output end is regulated by regulating the voltage of a Vadj port, and then the amplitude of a triggering signal is regulated.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of electronic circuits and relates to a double feedback control circuit for reliable triggering of a TVS. BACKGROUND

[0002] A triggered vacuum switch (TVS) is a kind of vacuum switch developed on the basis of a vacuum gap and a triggered spark gap technology, and is used in a capacitor energy storage discharge system, a closed switch in a pulsed power field, an electromagnetic emission field and the like. Such working conditions are usually high voltage and large current, and the TVS is required to be capable of fast conduction and shutdown and high current passing capacity. The basic structure of the TVS includes a ceramic shell, an anode, a cathode and a trigger electrode. The anode and the cathode are referred to as main electrodes and function to conduct large current. The trigger electrode functions to provide initial plasma for a discharge channel between the main electrodes. The plasma rapidly spreads throughout the vacuum gap under the action of an electric field between the main electrodes, so as to realize conduction of the TVS. According to different triggering principles, the trigger of the TVS mainly has several modes such as passive freewheeling, active freewheeling and capacitor direct discharge, and the ultimate goal is to generate a high-voltage trigger pulse.

[0003] Due to manufacturing errors of the vacuum tube or after experiencing multiple conduction, the trigger voltages experienced by vacuum tubes of the same model and the same batch will also differ. The use of a multi-channel synchronous triggering mode can improve the conduction probability of the vacuum tube, but causes complex hardware circuit design. In a high-voltage and large-current working environment, the complex circuit design will cause unpredictable risks and increase design costs.

[0004] Therefore, it is urgent to design an adjustable trigger pulse voltage control circuit. The conduction state of the TVS is detected in real time through a feedback circuit, a state signal is fed back to a field programmable logic gate array (FPGA) for logical operation processing, a voltage regulating port of a high-voltage direct-current voltage regulating module is controlled, so as to realize adjustment of the trigger pulse voltage. Meanwhile, the conduction state of a silicon carbide MOSFET is detected in real time through a feedback signal of a trigger circuit. The FPGA reads the feedback signal of the trigger circuit and the TVS conduction signal in real time, and judges whether the pulse signal is repeatedly sent according to a pre-set logical state. SUMMARY

[0005] In view of this, the purpose of the application is to provide a double feedback control circuit for reliable triggering of a TVS.

[0006] To achieve the above purpose, the application provides the following technical scheme.

[0007] A kind of double feedback control circuit for TVS reliable triggering, including main circuit, trigger circuit, field programmable logic gate array FPGA1, vacuum relay 2, display control module 3, pulse trigger 4, optical fiber transmitter 5 optical fiber receiver 6, AD conversion module two 7, DA conversion module 8, AD conversion module one 9 and optical fiber 10;

[0008] The main circuit includes main circuit feedback circuit 111;In the main circuit feedback circuit 111, resistance R11 and resistance R12 are connected in series, and one end is grounded, and the other end is connected with vacuum trigger switch TVS;Feedback signal Vfb1 is connected between the resistance R11 and the resistance R12;

[0009] The TVS is connected in series with resistance r, coil and capacitor C1 in turn;Capacitor C1 is connected with power supply U1 at one end, and is connected in series with resistance R1, the output end of diode D1, the input end of diode D1 and switch S1 at the other end;Switch S1 is connected to power supply U1;

[0010] The trigger circuit includes high-voltage DC voltage regulating module 221, MOS tube driving chip 222, trigger circuit feedback circuit 223 and MOS tube 224;

[0011] The high-voltage DC voltage regulating module 221 has 6 pins, pin 1-pin 6, pin 1 is connected with resistance R2, and is connected with capacitor C2 and the primary winding of pulse transformer in turn, and is connected to pin 2;Pin 3 is grounded;Pin 4 is connected to output voltage regulating signal Vadj;Pin 5 is connected to the negative electrode of battery;Pin 6 is connected to the positive electrode of battery;The secondary winding of the pulse transformer is connected with TVS;The pin 2 is also connected with the input end of diode D2, and the output end of diode D2 is connected with resistance R2;

[0012] In the trigger circuit feedback circuit 223, one end of resistance R21 is connected between resistance R2 and capacitor C2, and the other end is connected to resistance R22, and then grounded;Feedback signal Vfb2 is connected between the resistance R21 and the resistance R22;

[0013] The D pole of the MOS tube 224 is connected between capacitor C2 and resistance R2;The S pole of the MOS tube 224 is connected between the input end of diode D2 and the primary winding of pulse transformer;The G pole of the MOS tube 224 is connected with MOS tube driving chip 222, and the MOS tube driving chip 222 is also connected with trigger signal;

[0014] The FPGA1 is electrically connected with vacuum relay 2, pulse trigger 4, AD conversion module two 7, DA conversion module 8, AD conversion module one 9 respectively;

[0015] The pulse trigger 4 is connected with the optical fiber transmitter 5 and the optical fiber receiver 6 in turn; the optical fiber transmitter 5 and the optical fiber receiver 6 are connected through the optical fiber 10; the optical fiber receiver 6 is connected with the trigger signal;

[0016] The DA conversion module 8 comprises the DA chip AD970881, the low-pass filter 82, the amplitude modulation circuit 83 and the analog DC power supply 84 connected in turn; the analog DC power supply 84 is connected with the output voltage adjusting signal Vadj;

[0017] The AD conversion module one 9 comprises the AD chip AD9280-one 91 and the attenuation circuit one 92 connected in turn; the attenuation circuit one 92 is connected with the feedback signal Vfb1;

[0018] The AD conversion module two 7 comprises the AD chip AD9280-two 71 and the attenuation circuit two 72 connected in turn; the attenuation circuit two 72 is connected with the feedback signal Vfb2.

[0019] The beneficial effects of the present application are that:

[0020] 1. The main circuit feedback circuit is designed, and the feedback signal can reflect the working state of the TVS;

[0021] 2. The trigger circuit feedback circuit is designed, and the working state of the trigger circuit can be known from the feedback signal;

[0022] 3. The high-voltage DC voltage regulating module is arranged in the trigger circuit, the voltage (0-5V) of the Vadj port is adjusted to realize the adjustment of the voltage of the high-voltage output end, and then the amplitude of the trigger signal is adjusted;

[0023] 4. The FPGA is used as the controller, the input information of the display control module is combined with the feedback signal to control the main circuit capacitor charging and the TVS switch conduction, and finally the main capacitor C1 realizes the instantaneous discharge of the coil.

[0024] Other advantages, objects and features of the present application will be in part apparent and in part pointed out hereinafter in the specification, and in part will be observed by persons skilled in the art upon examination of the following specification, or can be learned by practice of the present application. The objects and other advantages of the present application can be realized and attained by the means and combinations pointed out in the following specification. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to make the purposes, technical solutions and advantages of the present application more clear, the preferred detailed description of the present application will be combined with the drawings to make the preferred detailed description of the present application, and the drawings are as follows:

[0026] Figure 1 It is the main circuit schematic diagram;

[0027] Figure 2 It is the trigger circuit schematic diagram;

[0028] Figure 3 For double feedback control principle diagram;

[0029] Figure 4 For Vfb1 signal waveform;

[0030] Figure 5 For Vfb2 signal waveform.

[0031] The figure mark: FPGA 1, vacuum relay 2, display control module 3, pulse trigger 4, optical fiber transmitter 5, optical fiber receiver 6, AD conversion module two 7, DA conversion module 8, AD conversion module one 9, optical fiber 10, DA chip AD9708 81, low pass filter 82, amplitude modulation circuit 83, analog DC power supply 84, AD chip AD9280 one 91, attenuation circuit one 92, AD chip AD9280 two 71, attenuation circuit two 72, main circuit feedback circuit 111, high voltage DC voltage regulation module 221, MOS tube drive chip 222, trigger circuit feedback circuit 223, MOS tube 224. DETAILED DESCRIPTION

[0032] The present application will be described in more detail by the following specific examples, and other advantages and effects of the present application will be easily understood by those skilled in the art from this disclosure. The present application can also be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details in this specification based on different views and applications without departing from the spirit of the present application. It should be noted that the drawings provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and the following examples and features in the examples can be combined with each other without conflict.

[0033] Wherein, the drawings are only used for exemplary illustration, and the representation is only a schematic diagram, not a physical diagram, and cannot be understood as a limitation of the present application; in order to better illustrate the embodiments of the present application, some components of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some known structures and their descriptions in the drawings may be omitted.

[0034] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0035] like Figure 1 As shown, this is the main circuit schematic. Figure 2 The diagram shown is a schematic of the trigger circuit.

[0036] like Figure 3 As shown, optimizations and improvements are made to the trigger circuit: (1) a feedback circuit is added to detect the conduction state of the MOSFET; (2) a high-voltage DC voltage regulation module is added, and the amplitude of the trigger pulse voltage is adjusted or multiple trigger pulses are sent through the above two feedback signals to ensure reliable conduction of the TVS. Optimizations and improvements are made to the main circuit: the main circuit feedback is added to detect the conduction state of the TVS.

[0037] The purpose of the trigger circuit is to turn on the TVS in the main circuit. The added feedback circuit and control circuit are to ensure that the TVS can be turned on more reliably.

[0038] The present invention provides a dual feedback control circuit, comprising a main circuit, a trigger circuit, a field-programmable gate array (FPGA) 1, a vacuum relay 2, a display control module 3, a pulse trigger 4, an optical fiber transmitter 5, an optical fiber receiver 6, an AD conversion module 2 7, a DA conversion module 8, an AD conversion module 1 9, and an optical fiber 10.

[0039] The main circuit includes a main circuit feedback circuit 111; in the main circuit feedback circuit 111, resistors R11 and R12 are connected in series, one end of which is grounded and the other end is connected to a vacuum trigger switch TVS; a feedback signal Vfb1 is connected between resistors R11 and R12.

[0040] The TVS is connected in series with resistor R, coil and capacitor C1 in sequence; one end of capacitor C1 is connected to power supply U1, and the other end is connected in series with resistor R1, output terminal of diode D1, input terminal of diode D1 and switch S1 in sequence; switch S1 is connected to power supply U1.

[0041] The trigger circuit includes a high-voltage DC voltage regulation module 221, a MOSFET driver chip 222, a trigger circuit feedback circuit 223, and a MOSFET 224;

[0042] The high-voltage direct-current voltage regulating module 221 has six pins, pin 1-pin 6, pin 1 is connected with the resistor R2, then connected with the capacitor C2 and the primary winding of the pulse transformer in turn, and then connected to pin 2; pin 3 is grounded; pin 4 is connected to the output voltage regulating signal Vadj; pin 5 is connected to the negative electrode of the battery; pin 6 is connected to the positive electrode of the battery; the secondary winding of the pulse transformer is connected with the TVS; the pin 2 is also connected with the input end of the diode D2, and the output end of the diode D2 is connected with the resistor R2;

[0043] In the trigger circuit feedback circuit 223, one end of the resistor R21 is connected between the resistor R2 and the capacitor C2, and the other end is connected to the resistor R22, and then grounded; the resistor R21 and the resistor R22 are connected with the feedback signal Vfb2;

[0044] The D pole of the MOS tube 224 is connected between the capacitor C2 and the resistor R2; the S pole of the MOS tube 224 is connected between the input end of the diode D2 and the primary winding of the pulse transformer; the G pole of the MOS tube 224 is connected with the MOS tube driving chip 222, and the MOS tube driving chip 222 is also connected with the feedback signal;

[0045] The FPGA1 is electrically connected with the vacuum relay 2, the pulse trigger 4, the AD conversion module two 7, the DA conversion module 8, and the AD conversion module one 9 respectively;

[0046] The pulse trigger 4 is connected with the optical fiber transmitter 5 and the optical fiber receiver 6 in turn; the optical fiber transmitter 5 and the optical fiber receiver 6 are connected through the optical fiber 10; the optical fiber receiver 6 is connected with the trigger signal;

[0047] The DA conversion module 8 includes the DA chip AD970881, the low-pass filter 82, the amplitude modulation circuit 83 and the analog DC power supply 84 connected in turn; the analog DC power supply 84 is connected with the output voltage regulating signal Vadj;

[0048] The AD conversion module one 9 includes the AD chip AD9280 one 91 and the attenuation circuit one 92 connected in turn; the attenuation circuit one 92 is connected with the feedback signal Vfb1;

[0049] The AD conversion module two 7 includes the AD chip AD9280 two 71 and the attenuation circuit two 72 connected in turn; the attenuation circuit two 72 is connected with the feedback signal Vfb2.

[0050] The attenuation circuit one 92 and the attenuation circuit two 72 are both attenuated to 0-2V.

[0051] 1. Design the main circuit feedback circuit, the feedback signal can reflect the working state of the TVS: such as Figure 4As shown in the Vfb1 signal waveform, when the signal waveform appears a falling edge and the amplitude oscillation decreases, it indicates that the TVS is successfully turned on, and there is no need to change the pulse parameters or send the pulse again.

[0052] 2. A feedback circuit is designed for the trigger circuit, and the working state of the trigger circuit can be known from the feedback signal, such as Figure 5 As shown in the Vfb2 signal waveform, when the signal waveform appears a falling edge, it indicates that the MOSFET is successfully turned on, and the trigger signal is sent by the pulse transformer.

[0053] 3. A high-voltage DC voltage regulating module is arranged in the trigger circuit, the voltage of the Vadj port (0-5V) is adjusted to realize the adjustment of the voltage of the high-voltage output end, and then the amplitude of the trigger signal is adjusted.

[0054] 4. The FPGA is used as a controller, the input information of the display control module is combined with the feedback signal to control the capacitor charging of the main circuit and the conduction of the TVS switch, and finally the main capacitor C1 realizes the instantaneous discharge of the coil.

[0055] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the purpose and scope of the present application, and all of them should be covered in the scope of the claims of the present application.

Claims

1. A dual feedback control circuit for TVS reliable triggering, characterized in that: The double feedback control control circuit comprises a main circuit, a trigger circuit, a field programmable logic gate array (FPGA) (1), a vacuum relay (2), a display control module (3), a pulse trigger (4), a fiber transmitter (5), a fiber receiver (6), an AD conversion module two (7), a DA conversion module (8), an AD conversion module one (9) and a fiber (10); The main circuit comprises a main circuit feedback circuit (111); in the main circuit feedback circuit (111), the resistance R11 and the resistance R12 are connected in series, one end of which is grounded, and the other end is connected with a vacuum trigger switch TVS; a feedback signal Vfb1 is connected between the resistance R11 and the resistance R12; The TVS is connected in series with a resistance r, a coil and a capacitor C1 in sequence; one end of the capacitor C1 is connected with a power supply U1, and the other end is connected to the cathode of a diode D1 through a resistance R1; one end of a switch S1 is connected with the anode of the diode D1, and the other end is connected with the power supply U1; The trigger circuit comprises a high-voltage direct-current voltage regulating module (221), a MOS tube driving chip (222), a trigger circuit feedback circuit (223) and a MOS tube (224); The high-voltage direct-current voltage regulating module (221) has six pins, pin 1-pin 6, pin 1 is connected with a resistance R2, then connected with a capacitor C2 and a primary winding of a pulse transformer in sequence, and connected to pin 2; pin 3 is grounded; pin 4 is connected to an output voltage adjusting signal Vadj; pin 5 is connected to the negative electrode of a battery; pin 6 is connected to the positive electrode of the battery; the secondary winding of the pulse transformer is connected with the TVS; pin 2 is also connected with the input end of a diode D2, and the output end of the diode D2 is connected with the resistance R2; In the trigger circuit feedback circuit (223), one end of a resistance R21 is connected between the resistance R2 and the capacitor C2, and the other end is connected to a resistance R22, and then grounded; a feedback signal Vfb2 is connected between the resistance R21 and the resistance R22; The D pole of the MOS tube (224) is connected between the capacitor C2 and the resistance R2; the S pole of the MOS tube (224) is connected between the input end of the diode D2 and the primary winding of the pulse transformer; the G pole of the MOS tube (224) is connected with the MOS tube driving chip (222), and the MOS tube driving chip (222) is also connected with a trigger signal; The FPGA (1) is electrically connected with the vacuum relay (2), the pulse trigger (4), the AD conversion module two (7), the DA conversion module (8) and the AD conversion module one (9) respectively; The pulse trigger (4) is connected with the fiber transmitter (5) and the fiber receiver (6) in sequence; the fiber transmitter (5) and the fiber receiver (6) are connected through the fiber (10); the fiber receiver (6) is connected with a trigger signal; The DA conversion module (8) comprises a DA chip AD9708 (81), a low-pass filter (82), an amplitude modulation circuit (83) and an analog DC power supply (84) connected in sequence; the analog DC power supply (84) is connected with an output voltage adjusting signal Vadj; The AD conversion module one (9) comprises AD chip AD9280 one (91) and attenuation circuit one (92) connected in sequence; the attenuation circuit one (92) is connected with feedback signal Vfb1; The AD conversion module two (7) comprises AD chip AD9280 two (71) and attenuation circuit two (72) connected in sequence; the attenuation circuit two (72) is connected with feedback signal Vfb2.

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