Error frame injection device, method and system

Abstract

The invention provides an error frame injection device, method and system, and the device comprises a control register module, an error frame memory module and a medium access control module which are respectively constructed in a field programmable gate array. The control register module is used for receiving an Ethernet data frame and an error frame injection strategy, generating an Ethernet error frame, and generating an injection control signal of the Ethernet error frame according to an error injection frequency if an injection trigger condition is monitored to be established; the error frame memory module is used for receiving and storing Ethernet error frames; and the medium access control module is used for responding to the injection control signal, reading the Ethernet error frame from the error frame memory module, and injecting the Ethernet error frame into the equipment to be tested for testing. By integrating the control register module, the error frame memory module and the medium access control module in the field programmable gate array, Ethernet error frame injection is realized, and an efficient, comprehensive and economical test means is provided for high-speed Ethernet equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication testing, and in particular to an error frame injection device, method and system. BACKGROUND

[0002] With the rapid development of information technology, network infrastructure has become the core pillar supporting key fields such as digital economy, industrial automation, intelligent transportation, cloud computing and Internet of Things. Ethernet, with its high bandwidth, low delay, good compatibility and scalability, is a widely used local area network communication technology. However, in actual operation, various error frames may occur due to electromagnetic interference, hardware failure, driver abnormality or malicious attack. In the research and development, testing and verification stage of Ethernet devices, the generation and injection of error frames are the key means to verify the fault tolerance capability, protocol robustness and fault recovery mechanism of the devices.

[0003] In related technologies, the generation and injection of Ethernet error frames mainly rely on two methods: one is a software simulation method, which constructs Ethernet frames that do not conform to the standard by running a test program on a general-purpose computer, and then sends them to the device under test via a network card; the other is a method using special test instruments, such as network protocol analyzers or consistency test platforms, which have built-in special hardware and test firmware and can generate Ethernet frames containing various error types, and then send them to the device under test. However, both methods have obvious limitations and cannot provide efficient, comprehensive and economical testing means for high-speed Ethernet devices. SUMMARY

[0004] The present application discloses an error frame injection device, method and system to solve the technical problems of poor real-time performance, inflexible configuration and poor expandability in Ethernet error frame injection.

[0005] The application provides an error frame injection device, which comprises a control register module, an error frame memory module and a medium access control module constructed in a field programmable gate array respectively; the control register module is used for receiving an Ethernet data frame and a corresponding error frame injection strategy, wherein the error frame injection strategy comprises an error injection type, an injection trigger condition and an error injection frequency, and an Ethernet error frame is generated according to the Ethernet data frame and the error injection type, and if the injection trigger condition is monitored to be established, an injection control signal of the Ethernet error frame is generated according to the error injection frequency; the error frame memory module is connected with the control register module, and the error frame memory module receives and stores the Ethernet error frame from the control register module; the medium access control module is connected with the control register module and the error frame memory module respectively, the error frame memory module reads the Ethernet error frame from the error frame memory module in response to the injection control signal, and the Ethernet error frame is injected into a device under test for testing.

[0006] In an embodiment of the application, a user interface module is further constructed in the field programmable gate array; a bus protocol of the user interface module is adapted to a bus protocol of a processing system; the control register module is connected with the processing system through the user interface module, and is used for receiving the Ethernet data frame and the error frame injection strategy from the processing system through the user interface module.

[0007] In an embodiment of the application, the error frame memory module is connected with the processing system through the user interface module, and is further used for receiving a first reading request from the processing system through the user interface module, and returning a storage result of the Ethernet error frame to the processing system through the user interface module in response to the first reading request.

[0008] In an embodiment of the application, a multiplexer module is further constructed in the field programmable gate array; the medium access control module is used for analyzing the error injection frequency carried in the injection control signal after receiving the injection control signal, and controlling the multiplexer module to switch an input source based on the error injection frequency, wherein the input source comprises a normal frame input source and the error frame memory module; the multiplexer module is used for reading the Ethernet error frame from the error frame memory module and transmitting the Ethernet error frame to the medium access control module under the condition that the input source is the error frame memory module.

[0009] In an embodiment of the present application, the media access control module is configured with a cyclic redundancy check code generation function; the media access control module is further configured to, before reading the Ethernet error frame, turn off the cyclic redundancy check code generation function, and after completing the injection of the Ethernet error frame, re-enable the cyclic redundancy check code generation function.

[0010] In an embodiment of the present application, the media access control module is connected to the processing system through the user interface module, and is further configured to, after injecting the Ethernet error frame, monitor and record network state information and bus state information; and receive a second read request from the processing system through the user interface module, and in response to the second read request, return the network state information and the bus state information to the processing system through the user interface module; wherein the network state information includes link state between the device under test, the number of error frames sent by the device under test, and the number of pause frames.

[0011] In an embodiment of the present application, the field programmable gate array is configured with a plurality of control register modules, a plurality of error frame memory modules, and a plurality of media access control modules, forming a plurality of error frame injection channels; the plurality of error frame injection channels are configured with different error frame injection strategies, and are used to inject Ethernet error frames to different devices under test or different network ports of the same device under test.

[0012] In an embodiment of the present application, the error injection type includes cyclic redundancy check code error, length error, interframe gap anomaly, and preamble error; the injection trigger condition includes time trigger condition, count trigger condition, and external signal trigger condition.

[0013] The present application also provides an error frame injection method, the method comprising: respectively constructing a control register module, an error frame memory module, and a media access control module in a field programmable gate array; receiving an Ethernet data frame and a corresponding error frame injection strategy through the control register module, wherein the error frame injection strategy includes an error injection type, an injection trigger condition, and an error injection frequency; generating an Ethernet error frame according to the Ethernet data frame and the error injection type by the control register module, and writing the Ethernet error frame into the error frame memory module to store the Ethernet error frame by the error frame memory module; if the injection trigger condition is detected, generating an injection control signal of the Ethernet error frame according to the error injection frequency by the control register module, and sending the injection control signal to the media access control module; reading the Ethernet error frame from the error frame memory module by the media access control module in response to the injection control signal, and injecting the Ethernet error frame into a device under test for testing.

[0014] The application also provides an error frame injection system comprising the error frame injection device as described above, or using the error frame injection method as described above.

[0015] The application has the following beneficial effects: the error frame injection device, method and system provided by the application, the device comprises a control register module, an error frame memory module and a medium access control module which are respectively constructed in a field programmable gate array, wherein the control register module is configured to receive an Ethernet data frame and a corresponding error frame injection strategy, the error frame injection strategy comprises an error injection type, an injection trigger condition and an error injection frequency, and generate an Ethernet error frame according to the Ethernet data frame and the error injection type, and if the injection trigger condition is detected, generate an injection control signal of the Ethernet error frame according to the error injection frequency, the error frame memory module is configured to receive and store the Ethernet error frame from the control register module, and the medium access control module is configured to read the Ethernet error frame from the error frame memory module in response to the injection control signal, and inject the Ethernet error frame into a device under test for testing, by integrating the control register module, the error frame memory module and the medium access control module in the field programmable gate array, the Ethernet error frame can be injected in real time at the physical layer, the error injection process can be accurately controlled, and by the configurable error injection type, injection trigger condition and error injection frequency, high real-time and high flexibility injection of the Ethernet error frame is realized, complex test scenarios are supported, and the device can be integrated in an existing network interface card or test board card to realize low-cost Ethernet error frame injection, has high scalability, and provides an efficient, comprehensive and economical test means for high-speed Ethernet devices. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and serve to explain the principles of the application. It is readily apparent to one of ordinary skill in the art that the drawings described below are merely some embodiments of the application, and other drawings can be obtained from these drawings without creative labor.

[0017] In the drawings: Figure 1 is a schematic diagram of an implementation environment of an error frame injection device according to an exemplary embodiment of the application; Figure 2 is a block diagram of an error frame injection device according to an exemplary embodiment of the application; Figure 3 is a block diagram of another error frame injection device according to an exemplary embodiment of the application; Figure 4is a block diagram of yet another error frame injection device according to an example embodiment of the present application; Figure 5 is a block diagram of a specific error frame injection device according to an example embodiment of the present application; Figure 6 is a block diagram of still another error frame injection device according to an example embodiment of the present application; Figure 7 is a flowchart of an error frame injection method according to an example embodiment of the present application; Figure 8 is a flowchart of a specific error frame injection method according to an example embodiment of the present application. DETAILED DESCRIPTION

[0018] The present application is herein described, by way of example only, with reference to the accompanying drawings, with the following being detailed description in connection with these drawings, wherein:

[0019] It is to be understood that the drawings are to be used as your reference in potentially interpreting the application. Other embodiments upon which the application can be practiced and potentially realized will be apparent to one skilled in the art upon reading the present description.

[0020] In the following description, numerous specific details are discussed to provide a thorough understanding of embodiments of the application. However, one having ordinary skill in the relevant art will recognize that the application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, devices, and so forth are not shown or described in detail to avoid obscuring aspects of the application.

[0021] In the research, test and verification phase of Ethernet device, the generation and injection of error frame is a key means to verify the fault tolerance capability, protocol robustness and fault recovery mechanism of the device. The generation and injection of Ethernet error frame mainly depends on two ways, one is based on software simulation method, and the other is using special test instrument method. But the inventors of the present application found that both of the two ways have obvious limitations. First, the real-time performance of the software simulation method is poor, which is difficult to meet the test requirements of high-speed network (such as Gigabit / 10 Gigabit Ethernet). Second, the error frame type and trigger condition configuration is not flexible, which is difficult to realize complex error scene simulation. Third, the cost of special test equipment is high, and the expansibility is poor, which is difficult to integrate into the automatic test system. It is unable to provide efficient, comprehensive and economic test means for high-speed Ethernet device.

[0022] Therefore, referring to Figure 1 , Figure 1 is a schematic diagram of an implementation environment of an error frame injection device according to an example embodiment of the present application. As Figure 1 shown, the implementation environment can include an error frame injection device 110 and a device under test 120, wherein the error frame injection device 110 is used to actively send Ethernet frames containing specific error types to the device under test 120 to simulate abnormal communication scenarios that may occur in the actual network. The device under test 120 can be a switch, a router, a network interface card or other network devices supporting Ethernet protocol, which should have corresponding error detection, processing or discarding mechanism after receiving the error frame. The error frame injection device 110 integrates control register module, error frame memory module and medium access control module in field programmable gate array, so that the Ethernet error frame can be injected in real time at the physical layer, and the error injection process can be accurately controlled. Through the configurable error injection type, injection trigger condition and error injection frequency, high real-time and high flexibility of Ethernet error frame injection is realized, complex test scenarios are supported, and the error frame injection device can be integrated into existing network interface card or test board card to realize low-cost Ethernet error frame injection with high scalability, which provides efficient, comprehensive and economic test means for high-speed Ethernet device.

[0023] Therefore, referring to Figure 2 , Figure 2 is a block diagram of an error frame injection device according to an example embodiment of the present application. The device can be applied to Figure 1 shown implementation environment, it should be understood that the device can also be applied to other example implementation environments, and the present embodiment does not limit the implementation environment to which the device is applied.

[0024] As Figure 2As shown, in an exemplary embodiment, the error frame injection device comprises at least a control register module 210, an error frame memory module 220 and a media access control module 230, which are respectively built in a field programmable gate array (FPGA), as described in detail below. The control register module 210 is configured to receive an Ethernet data frame and a corresponding error frame injection strategy, wherein the error frame injection strategy comprises an error injection type, an injection trigger condition and an error injection frequency, and generate an Ethernet error frame according to the Ethernet data frame and the error injection type, and generate an injection control signal of the Ethernet error frame according to the error injection frequency if the injection trigger condition is detected.

[0025] The error frame memory module 220 is connected with the control register module 210, and the error frame memory module 220 receives and stores the Ethernet error frame from the control register module 210.

[0026] The media access control module 230 is connected with the control register module 210 and the error frame memory module 220, respectively, and the media access control module 230 reads the Ethernet error frame from the error frame memory module 220 in response to the injection control signal, and injects the Ethernet error frame into the device under test for testing.

[0027] Wherein, the FPGA (Field Programmable Gate Array) is a programmable logic device, which contains configurable logic blocks, programmable interconnection resources and input / output units inside. The hardware structure of the FPGA is configured by programming to realize specific digital circuit functions, which is used as a hardware platform for building the error frame injection device, and the control register module 210, the error frame memory module 220 and the media access control module 230 are integrated in the programmable logic; the Ethernet data frame is a data unit conforming to the Ethernet protocol format; the error frame injection strategy is a set of rules for defining how to generate and inject Ethernet error frames, the error injection type in the strategy is used to specify the type of error to be introduced, the injection trigger condition is used to define when to start injecting error frames, and the error injection frequency is used to control the density or rate of error frame injection; the Ethernet error frame is a data frame that is specially modified to make it not conform to the Ethernet protocol specification, which is used to test the processing ability of the device under test for abnormal conditions; the injection control signal is used to instruct the media access control module 230 to read the Ethernet error frame from the error frame memory module 220 and inject it into the device under test; the device under test refers to the target device that needs to be tested by the Ethernet error frame injection.

[0028] For the control register module 210, it is a logic function unit implemented internally in the FPGA, which mainly functions to receive and process the error frame injection strategy to generate Ethernet error frames and generate injection control signals, including a series of registers for storing user-set parameters, such as error frame injection strategies, and through read-write operations on these registers, the behavior of the injection device is dynamically controlled.

[0029] For the error frame storage module 220, it is a hardware resource for storing Ethernet error frames, which can be a RAM (Random Access Memory) internally in the FPGA, and its function is to provide a buffer for temporarily storing Ethernet error frames generated by the control register module 210, so as to be read by the media access control module 230 when needed.

[0030] For the media access control module 230, i.e., the MAC (Media Access Control) module, it is responsible for frame encapsulation and decapsulation, controls the sending and receiving of data, and ensures orderly, efficient and reliable communication, and is configured to inject Ethernet error frames stored in the error frame storage module 220 into the device under test based on the injection control signals of the control register module 210.

[0031] In this embodiment, by integrating the control register module 210, the error frame storage module 220 and the media access control module 230 in the field programmable gate array, Ethernet error frames can be injected in real time at the physical layer, and the error injection process can be accurately controlled, and through the configurable error injection type, injection trigger condition and error injection frequency, high real-time and high flexibility of Ethernet error frame injection is achieved, complex test scenarios are supported, and the Ethernet error frame injection can be integrated in the existing network interface card or test board card, realizing low-cost Ethernet error frame injection with high scalability, providing an efficient, comprehensive and economical testing means for high-speed Ethernet devices.

[0032] Exemplarily, the error injection type in the error frame injection strategy can be represented by a group of binary codes, and different binary codes represent different error injection types.

[0033] Exemplarily, the error injection frequency in the error frame injection strategy can be a preset fixed value, for example, one error frame is injected every 100 normal frames, and the error injection frequency can be realized by a counter.

[0034] Exemplarily, the interface signal definition between the error frame storage module 220 and the media access control module 230 is shown in Table 1: Table 1

[0035] In an embodiment, the error injection types include cyclic redundancy check error, length error, inter-frame gap anomaly and preamble error; the injection trigger conditions include time trigger condition, count trigger condition and external signal trigger condition.

[0036] The cyclic redundancy check error refers to the cyclic redundancy check code field of the Ethernet frame being intentionally tampered with to test the response capability of the device under test to data integrity check failure. In implementation, the control register module 210 can modify the cyclic redundancy check code field of the frame when generating the Ethernet error frame. The length error refers to the length field of the Ethernet frame being inconsistent with the actual frame data length to test the processing capability of the device under test to abnormal frame length. In implementation, the control register module 210 can make the length of the Ethernet error frame not match the actual data payload when generating the Ethernet error frame. The inter-frame gap anomaly refers to the inter-frame gap between two consecutive Ethernet frames not meeting the minimum interval specified in the Ethernet standard to test the receiving and processing capability of the device under test under the condition of non-standard frame interval. In implementation, the control register module 210 can set the transmission interval of the frame to not meet the minimum interval specified in the Ethernet standard when generating the Ethernet error frame. The preamble error refers to the preamble or frame start delimiter part of the Ethernet frame being tampered with to test the behavior of the device under test when the physical layer synchronization or frame start identification problem occurs. In implementation, the control register module 210 can modify the specific bit pattern of the preamble or frame start delimiter when generating the Ethernet error frame.

[0037] In addition, the injection trigger conditions include at least one of the following modes, which can be selected and parameterized by the user. The timing trigger mode is triggered based on the internal clock count reaching a preset time threshold. The count trigger mode is triggered based on the number of normal data frames reaching a preset value. The external signal trigger mode is triggered based on the logic state of one or more specified trigger signals input from the outside of the FPGA.

[0038] In this embodiment, considering that the device under test may have different robustness requirements for a plurality of specific types of errors, and the timing and frequency of error injection also need to be highly precise and flexible control. If the error injection type and injection trigger condition are too single or fixed, it is difficult to comprehensively and effectively evaluate the performance and stability of the device under test in various complex network environments. Therefore, a plurality of specific error injection types such as cyclic redundancy check error, length error, inter-frame gap anomaly and preamble error are introduced, and a plurality of injection trigger conditions such as time trigger condition, count trigger condition and external signal trigger condition are provided, which greatly enhances the flexibility and accuracy of error injection, thereby more comprehensively and accurately evaluating the performance of the device under test in various complex network conditions.

[0039] In an embodiment, please refer to Figure 3 ,Figure 3 is a block diagram of another error frame injection device shown in an example embodiment of the present application. As shown, a user interface module 240 is also built in the field programmable gate array; the bus protocol of the user interface module 240 is adapted to the bus protocol of the processing system; the control register module 210 is connected with the processing system through the user interface module 240, and is used to receive the Ethernet data frames and the error frame injection strategy from the processing system through the user interface module 240. Figure 3

[0040] Among them, the user interface module 210 is a logical unit built in the field programmable gate array, which serves as an interactive bridge between the entire error frame injection device and the external processing system, and is responsible for data exchange and protocol conversion between the external processing system and the internal modules of the device; in addition, the user interface module 210 supports multi-protocol extension and adapts to the bus protocol of the processing system, such as AXI4-Lite (a throughput address mapping communication bus) protocol.

[0041] In this embodiment, by integrating the user interface module 210 adapted to the bus protocol of the processing system in the field programmable gate array, the control register module 210 can efficiently and seamlessly receive the Ethernet data frames and the error frame injection strategy from the processing system, which simplifies the design of the software and hardware interactive interface, and improves the configuration flexibility and system integration.

[0042] For example, the user can write data into the control register module 210 through the user interface module 240 based on the AXI4-Lite write bus, and the access timing is consistent with the AXI4 bus protocol standard, as shown in Table 2: Table 2

[0043] For example, the user can read data in the control register module 210 through the user interface module 240 based on the AXI4-Lite read bus, and the access timing is consistent with the AXI4 bus protocol standard, as shown in Table 3: Table 3

[0044] In an embodiment, please continue to refer to Figure 3 the error frame storage module 220 is connected with the processing system through the user interface module 240, and is also used to receive the first read request from the processing system through the user interface module 240, and in response to the first read request, returns the storage result of the Ethernet error frame to the processing system through the user interface module 240.

[0045] ​In this embodiment, considering that writing the Ethernet error frame into the error frame memory module 220 alone cannot guarantee the correctness and integrity of its storage, if the Ethernet error frame fails to be stored correctly, it will affect the reliability of subsequent tests. Therefore, by connecting the user interface module 240 with the error frame memory module 220, the processing system monitors and reads back the error frame storage result, thereby improving the reliability of error frame injection.

[0046] For example, if the storage result is a storage failure, the processing system can take corresponding error handling measures, including re-writing, issuing a warning, or terminating the test, etc.

[0047] In an embodiment, referring to Figure 4 , Figure 4 is a block diagram of another error frame injection device according to an exemplary embodiment of the present application. As shown in Figure 4 , a multiplexer module 250 is also constructed in the field programmable gate array; the media access control module 230 is configured to parse the error injection frequency carried in the injection control signal after receiving the injection control signal, and control the multiplexer module 250 to switch the input source based on the error injection frequency, wherein the input source includes a normal frame input source and the error frame memory module 220; the multiplexer module 250 is configured to read the Ethernet error frame from the error frame memory module 220 under the condition that the input source is the error frame memory module 220, and transmit the Ethernet error frame to the media access control module 230.

[0048] Among them, the multiplexer module 250, i.e. MUX (Multiplexer) module, is a kind of digital logic circuit, which can select one from multiple input signals as output; the normal frame input source refers to the channel that provides conventional, error-free Ethernet data frames, ensuring that the device under test can receive normal Ethernet frames during non-error injection; the error frame memory module 220 serves as an abnormal frame input source, which is used to provide Ethernet error frames.

[0049] In this embodiment, considering that in a real network environment, error frames usually do not occur alone, but are mixed in normal Ethernet data streams, therefore, it is necessary to flexibly switch between normal Ethernet frames and Ethernet error frames and inject as needed, in order to accurately simulate network abnormal scenarios.

[0050] Specifically, after receiving the injection control signal generated by the control register module 210, the media access control module 230 parses the injection control signal, extracts the error injection frequency contained therein, and generates a corresponding selection control signal based on the error injection frequency. The media access control module 230 sends the selection control signal to the multiplexer module 250. When it is necessary to inject Ethernet error frames according to the error injection frequency, the media access control module 230 controls the multiplexer module 250 to select the error frame memory module 220 as the input source thereof, and when it is not necessary to inject Ethernet error frames, the media access control module 230 controls the multiplexer module 250 to select a normal frame input source.

[0051] In this way, by introducing the multiplexer module 250 and precisely controlling the input source thereof by the media access control module 230 based on the error injection frequency, flexible switching and injection between normal Ethernet frames and Ethernet error frames are achieved.

[0052] In an embodiment, the media access control module 230 is configured with a cyclic redundancy check code generation function. The media access control module 230 is further configured to disable the cyclic redundancy check code generation function before reading the Ethernet error frames, and re-enable the cyclic redundancy check code generation function after completing the injection of the Ethernet error frames.

[0053] The cyclic redundancy check code generation function is used to ensure the integrity of normal data frames.

[0054] In this embodiment, it is considered that when it is necessary to inject Ethernet error frames, if the cyclic redundancy check code generation function of the media access control module 230 is in an enabled state, unnecessary modification or correction of these error frames may be performed, thereby affecting the effectiveness of error injection. Therefore, in order to ensure that the Ethernet error frames can be injected into the device under test in their original form containing specific errors, the media access control module 230 performs the operation of disabling the cyclic redundancy check code generation function before reading the Ethernet error frames, and re-enables the cyclic redundancy check code generation function after completing the injection of the Ethernet error frames, so as to continue to provide cyclic redundancy check when subsequent normal data frames are sent, thereby enabling more accurate and reliable error injection.

[0055] In an embodiment, please continue to refer to Figure 3The medium access control module 230 is connected with the processing system through the user interface module 210, and is further configured to monitor and record network state information and bus state information after injecting the Ethernet error frame; and receive a second read request from the processing system through the user interface module 240, and return the network state information and the bus state information to the processing system through the user interface module 240 in response to the second read request; wherein the network state information comprises a link state between the device under test, a number of error frames sent by the device under test, and a number of pause frames sent by the device under test.

[0056] The link state between the device under test indicates whether the connection of the physical layer and the data link layer is normal; the number of error frames sent by the device under test refers to the total number of data frames that do not conform to the Ethernet protocol specification sent by the device under test during the test; the number of pause frames sent by the device under test refers to the total number of pause frames sent by the device under test during the test; and the bus state information refers to the data transmission state on the bus inside the medium access control module 230 or between the medium access control module 230 and other modules of the field programmable gate array.

[0057] In this embodiment, by connecting the user interface module 240 with the medium access control module 230, the medium access control module 230 can monitor and record the network state information and the bus state information in real time after injecting the Ethernet error frame, and then return the network state information and the bus state information to the processing system through the user interface module 240, so that the specific behavior and performance of the device under test after receiving the error frame can be comprehensively and accurately understood.

[0058] In an embodiment, referring to Figure 5 , Figure 5 is a block diagram of a specific error frame injection device according to an exemplary embodiment of the present application. As shown in Figure 5 , a plurality of control register modules 210, a plurality of error frame memory modules 220, and a plurality of medium access control modules 230 are constructed in the field programmable gate array, forming a plurality of error frame injection channels; the plurality of error frame injection channels are configured with different error frame injection strategies, and are used to inject Ethernet error frames to different devices under test or different network ports of the same device under test.

[0059] Each error frame injection channel includes one control register module 210, one error frame memory module 220, and one medium access control module 230; in addition, Figure 5 The three error frame injection channels shown in

[0060] In this embodiment, considering that a single injection channel is difficult to meet the testing requirements of multiple concurrency and multiple strategies, which may lead to low testing efficiency or the inability to simulate real complex network fault scenarios. Therefore, multiple error frame injection channels are constructed to inject Ethernet error frames, realizing the testing requirements of multiple concurrency and multiple strategies.

[0061] Specifically, each control register module 210 independently receives an Ethernet data frame and a corresponding error frame injection strategy. Based on the respective received Ethernet data frame and error frame injection strategy, each control register module 210 is capable of independently generating an Ethernet error frame. When the respective corresponding injection trigger condition is detected, according to the respective corresponding error injection frequency, an injection control signal of the corresponding Ethernet error frame is independently generated. Each error frame memory module 220 is connected with the respective corresponding control register module 210, for receiving and independently storing the Ethernet error frame generated from the corresponding control register module 210. Each media access control module 230 is respectively connected with the respective corresponding control register module 210 and error frame memory module 220, independently responding to the received injection control signal, reading the Ethernet error frame from the corresponding error frame memory module 220, and injecting it into the designated device under test or its specific network port for testing. For example, different network links can be simultaneously simulated to suffer from different types of attacks, or the response capability of a multi-port device to multiple concurrent faults can be simultaneously tested.

[0062] In this way, by constructing multiple independent error frame injection channels, each channel can independently configure and execute its error frame injection strategy, realizing parallel processing of multiple error injection tasks, overcoming the limitations of a single injection channel in complex network testing scenarios, and greatly improving the injection efficiency.

[0063] Exemplarily, please continue to refer to Figure 5 Each error frame injection channel also includes a user interface module 240 and a multiplexer module 250. The principles of the user interface module 240 and the multiplexer module 250 are the same as described above, and will not be repeated here.

[0064] Please refer to Figure 6 , Figure 6 is a block diagram of still another error frame injection device according to an exemplary embodiment of the present application. As Figure 6As shown, the user interface module, the control register module, the error frame memory module, the multiplexer module and the medium access control module are implemented in the editable logic of the field programmable gate array, and a driver API (i.e., driver interface) for the PS side (i.e., processing system side) is provided, and the processing system is connected to the user interface module of the error frame injection device. The user can configure the Ethernet data frame and the corresponding error frame injection strategy by calling the user interface module in the error frame injection device through the processing system, so that various types of error frames can be injected in real time and accurately in the high-speed Ethernet environment based on the error frame injection device, a nanosecond-level response is achieved, the bottleneck of software simulation in real-time performance and throughput is effectively overcome, and the scheme based on the field programmable gate array provides higher configuration flexibility and lower cost, can support multi-port and multi-protocol expansion, is suitable for various network environments such as gigabit / terabit Ethernet and vehicle-mounted Ethernet, realizes accurate control of the error injection process, and is used for network device testing, protocol verification and fault tolerance mechanism evaluation, etc.

[0065] The error frame injection device described above comprises a control register module, an error frame memory module and a medium access control module which are respectively constructed in the field programmable gate array. The control register module is used for receiving an Ethernet data frame and a corresponding error frame injection strategy, the error frame injection strategy comprises an error injection type, an injection trigger condition and an error injection frequency, and an Ethernet error frame is generated according to the Ethernet data frame and the error injection type, and if the injection trigger condition is monitored to be established, an injection control signal of the Ethernet error frame is generated according to the error injection frequency. The error frame memory module is used for receiving and storing the Ethernet error frame from the control register module. The medium access control module is used for reading the Ethernet error frame from the error frame memory module in response to the injection control signal, and injecting the Ethernet error frame into a device under test for testing. By integrating the control register module, the error frame memory module and the medium access control module in the field programmable gate array, the Ethernet error frame can be injected in real time at the physical layer, and the error injection process can be accurately controlled. Through the configurable error injection type, the injection trigger condition and the error injection frequency, high real-time and high-flexibility injection of the Ethernet error frame is realized, complex test scenarios are supported, the error frame injection device can be integrated in an existing network interface card or test board card, low-cost Ethernet error frame injection is realized, and high scalability is provided, thereby providing an efficient, comprehensive and economical testing means for high-speed Ethernet devices.

[0066] Please refer to Figure 7 , Figure 7 is a flowchart of an error frame injection method according to an example embodiment of the present application. The method can be applied to Figure 1The illustrated implementation environment, and by the error frame injection device 110 in the implementation environment. It should be understood that the method can also be applied to other exemplary implementation environments, and by the device in other implementation environments, the embodiment does not limit the implementation environment to which the method is applied.

[0067] As Figure 7 shown, in an exemplary embodiment, the error frame injection method at least includes steps S710 to S750, which are described in detail as follows: Step S710, respectively, in the field programmable gate array Control register module, error frame memory module and media access control module are constructed; Step S720, through the control register module, receive Ethernet data frame and the corresponding error frame injection strategy, wherein the error frame injection strategy includes error injection type, injection trigger condition and error injection frequency; Step S730, by the control register module, according to the Ethernet data frame and error injection type to generate Ethernet error frame, and write Ethernet error frame into error frame memory module, to store Ethernet error frame through error frame memory module; Step S740, if the injection trigger condition is monitored to be established, the control register module generates the injection control signal of Ethernet error frame according to the error injection frequency, and sends the injection control signal to the media access control module; Step S750, through the media access control module, in response to the injection control signal, read Ethernet error frame from the error frame memory module, and inject Ethernet error frame into the device under test for testing.

[0068] It should be noted that the error frame injection method provided by the above embodiment and the error frame injection device provided by the above embodiment belong to the same concept, wherein the content of each step has been described in detail in the device embodiment, which will not be repeated here.

[0069] Please refer to Figure 8 , Figure 8 is a flowchart of a specific error frame injection method shown in an exemplary embodiment of the present application. As Figure 8 shown, the specific error frame injection method at least includes steps S810 to S890, which are described in detail as follows: Step S810, respectively, in the field programmable gate array User interface module, control register module, error frame memory module, multiplexer module and media access control module are constructed; Step S820, by the control register module, through the user interface module, receive Ethernet data frame and error frame injection strategy from the processing system; Step S830, generating an Ethernet error frame according to the error injection type in the error frame injection strategy by the control register module, and writing the Ethernet error frame into the error frame memory module; Step S840, storing the Ethernet error frame by the error frame memory module; Step S850, if the control register module monitors that the injection trigger condition in the error frame injection strategy is established, generating an injection control signal of the Ethernet error frame according to the error injection frequency in the error frame injection strategy, and sending the injection control signal to the medium access control module; Step S860, responding to the injection control signal, the medium access control module closes the cyclic redundancy check code generation function; Step S870, the medium access control module parses the error injection frequency carried in the injection control signal, and controls the multiplexer module to switch the input source based on the error injection frequency; Step S880, under the condition that the input source of the multiplexer module is the error frame memory module, the multiplexer module reads the Ethernet error frame from the error frame memory module, and transmits the Ethernet error frame to the medium access control module; Step S890, the medium access control module injects the Ethernet error frame into the device under test for testing, and after completing the injection of the Ethernet error frame, reenables the cyclic redundancy check code generation function.

[0070] The application also provides an error frame injection system comprising the error frame injection device as described above, or using the error frame injection method as described above.

[0071] The error frame injection system refers to a complete and integrated platform, which aims to provide an error frame injection function for Ethernet network for device testing.

[0072] In this embodiment, the error frame injection system not only contains the core error frame injection device or the functional modules for executing the error frame injection method, but also covers all the supporting infrastructure required to make it an operational and deployable solution. Specifically, the system generally includes hardware-level components such as field programmable gate arrays carrying the error frame injection device, power modules, physical interfaces for connecting the device under test and the control host, etc., and software-level components such as control software running on the host processor or external controller, user interfaces for configuring the error frame injection strategy, and tools for data collection and test result analysis, etc. The system organically integrates these scattered functions and components together to form a unified test environment, ensuring that the error frame injection device or method can be efficiently and accurately utilized to achieve comprehensive and repeatable testing of the device under test.

[0073] The above embodiments are only illustrative of the principles of the present application and their effects, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. An error frame injection device, characterized in that, The device includes a control register module, an error frame memory module, and a media access control module, each built in a field-programmable gate array. The control register module is used to receive Ethernet data frames and corresponding error frame injection strategies. The error frame injection strategy includes an error injection type, an injection trigger condition, and an error injection frequency. It generates Ethernet error frames based on the Ethernet data frames and the error injection type. If the injection trigger condition is detected to be met, it generates an injection control signal for the Ethernet error frames based on the error injection frequency. The error frame memory module is connected to the control register module, and the error frame memory module receives and stores the Ethernet error frames from the control register module; The media access control module is connected to the control register module and the error frame memory module respectively. In response to the injection control signal, the error frame memory module reads the Ethernet error frame from the error frame memory module and injects the Ethernet error frame into the device under test for testing.

2. The error frame injection device according to claim 1, characterized in that, The field-programmable gate array also includes a user interface module; The bus protocol of the user interface module is adapted to the bus protocol of the processing system; The control register module is connected to the processing system through the user interface module, and is used to receive the Ethernet data frames and the error frame injection strategy from the processing system through the user interface module.

3. The error frame injection device according to claim 2, characterized in that, The error frame storage module is connected to the processing system through the user interface module, and is also used to receive a first read request from the processing system through the user interface module, and in response to the first read request, return the storage result of the Ethernet error frame to the processing system through the user interface module.

4. The error frame injection device according to claim 1, characterized in that, The field-programmable gate array also includes a multiplexer module; The media access control module is used to, after receiving the injection control signal, parse out the error injection frequency carried in the injection control signal, and control the multiplexer module to switch the input source based on the error injection frequency, wherein the input source includes a normal frame input source and the error frame memory module; The multiplexer module is used to read the Ethernet error frame from the error frame memory module when the input source is the error frame memory module, and transmit the Ethernet error frame to the media access control module.

5. The error frame injection apparatus according to claim 1, characterized in that, The media access control module is equipped with a cyclic redundancy check code generation function. The media access control module is further configured to disable the cyclic redundancy check (CRC) generation function before reading the Ethernet error frame, and to re-enable the CRC generation function after the injection of the Ethernet error frame is completed.

6. The error frame injection apparatus according to claim 2, characterized in that, The media access control module is connected to the processing system through the user interface module, and is also used to monitor and record network status information and bus status information after the Ethernet error frame is injected. The system receives a second read request from the processing system through the user interface module, and in response to the second read request, returns the network status information and the bus status information to the processing system through the user interface module. The network status information includes the link status with the device under test, the number of error frames and the number of pause frames sent by the device under test.

7. The error frame injection apparatus according to claim 1, characterized in that, The field-programmable gate array is equipped with multiple control register modules, multiple error frame memory modules and multiple media access control modules, forming multiple error frame injection channels; The multiple error frame injection channels are configured with different error frame injection strategies to inject Ethernet error frames into different devices under test or different network ports of the same device under test.

8. The error frame injection apparatus according to any one of claims 1 to 7, characterized in that, The error injection types include cyclic redundancy check (CRC) errors, length errors, inter-frame gap anomalies, and preamble errors; the injection triggering conditions include time triggering conditions, count triggering conditions, and external signal triggering conditions.

9. An error frame injection method, characterized in that, The method includes: A control register module, an error frame memory module, and a media access control module are constructed in a field-programmable gate array (FPGA). The control register module receives Ethernet data frames and corresponding error frame injection strategies, wherein the error frame injection strategy includes error injection type, injection triggering conditions, and error injection frequency. The control register module generates an Ethernet error frame based on the Ethernet data frame and the error injection type, and writes the Ethernet error frame into the error frame memory module for storage. If the injection trigger condition is detected, the control register module generates an injection control signal for the Ethernet error frame according to the error injection frequency, and sends the injection control signal to the media access control module. The media access control module, in response to the injection control signal, reads the Ethernet error frame from the error frame memory module and injects the Ethernet error frame into the device under test for testing.

10. An error frame injection system, characterized in that, Includes the error frame injection apparatus as described in any one of claims 1 to 8, or uses the error frame injection method as described in claim 9.

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