Matrix transposition method

Abstract

The application relates to a matrix transposition method, which comprises: cyclically performing data reading and writing operations on a target matrix until data reading in the target matrix is completed, and obtaining a transposed matrix of the target matrix. The data reading and writing operation comprises: sequentially controlling a plurality of shift registers in a chip to read a preset number of data from the target matrix in a clock sequence; the preset number is the same as the number of the plurality of shift registers, and the stored data in each shift register is moved one bit to the high bit under each clock in the reading process; and under the condition that each shift register completes one data reading, the highest bit storage data of each shift register is controlled to be written into the transposed matrix. The method can improve the calculation speed of the chip for matrix transposition, thereby improving the running speed of the computer equipment carrying the chip.

Description

Technical Field

[0001] This application relates to the field of information processing technology, and in particular to a matrix transpose method. Background Technology

[0002] Typically, when running neural network models, artificial intelligence chips need to convert the data they are processing into matrices before performing operations on the matrices. Among these operations, the most basic matrix operation is matrix transpose.

[0003] In related technologies, when transposing a matrix, it is usually necessary to read the matrix data in address order, then address it, then convert the address to output the transposed matrix data, and repeat the above process to achieve the transpose operation of the matrix.

[0004] However, the above methods suffer from low matrix transposition efficiency, which affects the computing speed of AI chips and results in low computing power. Summary of the Invention

[0005] Therefore, it is necessary to provide a matrix transpose method that can improve the computing speed of artificial intelligence chips and thus enhance their computing efficiency, in order to address the aforementioned technical problems.

[0006] In a first aspect, this application provides a matrix transpose method, the method comprising:

[0007] The target matrix is ​​repeatedly read and written data until all data in the target matrix has been read, resulting in the transpose of the target matrix. The data read and write operations include:

[0008] According to the clock sequence, multiple shift registers in the chip are controlled sequentially to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit in each clock cycle;

[0009] After each shift register has completed one data read, the highest bit of each shift register is written into the transpose matrix.

[0010] In one embodiment, multiple shift registers are sequentially controlled to read data from the target matrix according to clock sequence, including:

[0011] Obtain the read order of multiple shift registers;

[0012] According to the clock sequence and the reading order of multiple shift registers, obtain the reading address of each shift register in the target matrix;

[0013] Based on the read address of each shift register in the target matrix, control each shift register to read data from the target matrix.

[0014] In one embodiment, obtaining the read order of multiple shift registers includes:

[0015] The lengths of multiple shift registers are determined based on the bandwidth of the memory cells in the chip; the lengths of each shift register are different.

[0016] The order of the shift registers is determined by ranking the lengths of each shift register from largest to smallest.

[0017] In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases sequentially; wherein the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

[0018] In one embodiment, the read address of each shift register in the target matrix is ​​obtained according to the clock sequence and the read order of the multiple shift registers, including:

[0019] Based on the clock sequence and the read order of multiple shift registers, obtain the shift register corresponding to each clock cycle; perform data read of one shift register at each clock cycle;

[0020] The address of the first row of data in the target matrix is ​​used as the read address of the shift register corresponding to the first clock, the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain the read address of the shift register corresponding to each clock.

[0021] In one embodiment, controlling each shift register to read data from the target matrix based on the read address of each shift register in the target matrix includes:

[0022] For any shift register, the target data corresponding to the shift register is determined based on the read address of the shift register in the target matrix;

[0023] Control the shift register to read the target data.

[0024] In one embodiment, controlling the most significant bit of each shift register to be stored in the transpose matrix includes:

[0025] Obtain the most significant bit data of each shift register, and combine the most significant bit data of each shift register to obtain the transpose vector;

[0026] The transpose vector is written into the transpose matrix.

[0027] In one embodiment, controlling the writing of the transpose vector into the transpose matrix includes:

[0028] Get the write address of the transpose vector in the transpose matrix;

[0029] Based on the write address, control the transpose vector to be written into the transpose matrix.

[0030] In one embodiment, obtaining the write address of the transpose vector in the transpose matrix includes:

[0031] Get the number of times each shift register completes one data read during the cyclic execution of data read and write operations on the target matrix;

[0032] The column address of the transpose vector in the transpose matrix is ​​determined based on the number of times it is used.

[0033] Use the column address of the transpose vector in the transpose matrix as the write address of the transpose vector in the transpose matrix.

[0034] In one embodiment, the matrix transpose method further includes:

[0035] The offset address transition step size for each clock cycle is determined based on the size of the target matrix and the bandwidth of the memory cells in the chip.

[0036] During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the bias address jump step size of the clock, and after the bias address jump is completed, the base address of the clock jumps by one address.

[0037] Secondly, this application also provides a matrix transpose device, which includes: an acquisition module, the acquisition module including a reading unit and a writing unit, wherein:

[0038] The acquisition module is used to perform data read and write operations on the target matrix in a loop until all data in the target matrix has been read, and to obtain the transpose of the target matrix.

[0039] The read unit is used to sequentially control multiple shift registers in the chip to read a preset number of data from the target matrix according to the clock sequence. The preset number is the same as the number of multiple shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit at each clock cycle.

[0040] The write unit is used to control the most significant bit of each shift register to be written into the transpose matrix after each shift register has completed one data read.

[0041] Thirdly, this application also provides a computer device including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method in any of the embodiments of the first aspect described above.

[0042] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the steps of the method in any of the embodiments of the first aspect described above.

[0043] Fifthly, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method in any of the embodiments of the first aspect described above.

[0044] The aforementioned matrix transpose method performs data read and write operations on the target matrix cyclically until all data in the target matrix has been read, thus obtaining the transpose matrix of the target matrix. The data read and write operations include: sequentially controlling multiple shift registers in the chip to read a preset number of data from the target matrix according to clock sequence; the preset number is the same as the number of shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit at each clock cycle; after each shift register has completed one data read, the most significant bit of each shift register is written into the transpose matrix. This application controls the shift registers to read a preset number of data from the target matrix at each clock cycle, while simultaneously controlling the stored data in each shift register to shift one bit to the higher bit, and also controls the most significant bit of each shift register to be written into the transpose matrix after each data read. This is equivalent to the simultaneous reading, shifting, and writing of each shift register during matrix transposition using shift registers. This pipelined read and write mode avoids idle states for each shift register while conforming to the characteristics of chip pipeline operation, saving matrix transposition operation time. Furthermore, in the matrix transposition method provided in this application, the number of data read by the shift registers from the target matrix is ​​the same as the number of shift registers. Therefore, when each shift register completes one data read, the bandwidth for reading data by the corresponding shift register at each clock cycle is consistent with the bandwidth for storing the highest bit of data output by each shift register at that clock cycle. This data read / write method with consistent input and output bandwidth facilitates regular address jumps during the writing of the transposed matrix, thereby improving the matrix transposition writing efficiency. Additionally, chips are typically integrated into computer devices. Therefore, it can be understood that improving the transposition efficiency of these matrices when performing matrix transposition processing within the chip using the matrix transposition method provided in this application is equivalent to improving the chip's operating speed, and thus also equivalent to improving the operating speed of the computer device on which the chip is integrated. Attached Figure Description

[0045] Figure 1 This is a diagram illustrating the application environment of the matrix transpose method in one embodiment;

[0046] Figure 2 This is a flowchart illustrating a matrix transpose method in one embodiment;

[0047] Figure 3 This is a flowchart illustrating the data reading steps in one embodiment;

[0048] Figure 4 This is a flowchart illustrating the data reading step in another embodiment;

[0049] Figure 5 This is a flowchart illustrating the data reading step in another embodiment;

[0050] Figure 6 This is a flowchart illustrating the data reading step in another embodiment;

[0051] Figure 7 This is a flowchart illustrating the data writing steps in one embodiment;

[0052] Figure 8 This is a flowchart illustrating the data writing step in another embodiment;

[0053] Figure 9 This is a flowchart illustrating the data writing step in another embodiment;

[0054] Figure 10 This is a schematic diagram of the address transition process in another embodiment;

[0055] Figure 11 This is a flowchart illustrating the target matrix in one embodiment;

[0056] Figure 12 This is a flowchart illustrating data read / write operations in one embodiment;

[0057] Figure 13 This is a schematic diagram of the address transition process in another embodiment;

[0058] Figure 14 This is a structural block diagram of a matrix transpose device in one embodiment. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0060] The matrix operation method provided in this application can be applied to a chip. This chip can be a voice processing chip, video processing chip, image processing chip, or other artificial intelligence chip, and its internal structure diagram can be as follows: Figure 1As shown, the chip includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and shift memory. The non-volatile storage media stores the operating system, computer programs, and a database. The shift memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores thread stack processing data. The I / O interfaces are used for information exchange between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a matrix processing method. Those skilled in the art will understand that... Figure 1 The structure shown is merely a block diagram of a portion of the structure related to the solution of this application and does not constitute a limitation on the chip to which the solution of this application is applied. The specific chip may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0061] With the rapid development of artificial intelligence (AI) technology, AI chips are widely used in various fields. Due to the powerful data processing capabilities of AI chips, the computational tasks they perform are becoming increasingly complex. When an AI chip runs a neural network model, it needs to matrix-ize the data it is processing and then perform operations on the matrices. Among these operations, the most basic matrix operation includes matrix transpose.

[0062] In artificial intelligence chips, a continuous module addressing mode is typically used, and a shift register is employed to achieve matrix transposition. Related technologies utilize a blocking matrix transposition method, controlling the shift register to perform data reading operations in address order according to the bit width during the current clock cycle, and then performing data output by changing the address in the next clock cycle, repeating this process to achieve matrix transposition.

[0063] Taking an 8-bit bandwidth for reading data from a shift register and a matrix A size of 8×16 as an example, the blocking matrix transpose method is explained as follows: First, the shift register is controlled to read 8 bits of data from matrix A row by row; then, the transpose matrix B (16×8) corresponding to matrix A is addressed, and the read data is written into the transpose matrix B column by column until the read data is written to the end; then, the shift register is controlled to read 8 bits of data from the next row of matrix A, and the above process is repeated until all the data of matrix A is written into the transpose matrix B, thus completing the transpose operation of matrix A.

[0064] However, in the aforementioned blocking matrix transpose method, the read and write operations of the shift register cannot be performed simultaneously. That is, the data reading and output processes of the shift register must occur within two clock cycles, making it incompatible with the chip's internal pipelined operation mode. Furthermore, the blocking matrix transpose method requires multiple address looks for the column-wise output data during output, and this cumbersome addressing process leads to excessively long matrix transpose times.

[0065] Based on this, this application provides a non-blocking matrix transposition method. By setting the length of each shift register and the data read / write mode, the shift registers within the chip can be pipelined to read and output data, quickly realizing matrix transposition, fully utilizing the chip's computational efficiency, and thus saving chip power consumption. The matrix transposition method is illustrated below with an embodiment.

[0066] In one embodiment, such as Figure 2 As shown, a matrix transpose method is provided, which can be applied to... Figure 1 Taking the chip in the example, the explanation includes the following steps:

[0067] The target matrix is ​​repeatedly read and written until all data in the target matrix is ​​read, resulting in the transpose of the target matrix.

[0068] The chip in this embodiment can be applied in multiple scenarios according to actual needs, such as voice processing, video processing, and image processing. Therefore, depending on the application scenario, the chip in this embodiment can be a voice processing chip, a video processing chip, an image processing chip, etc. Correspondingly, if the chip is a voice processing chip, the target matrix is ​​a voice information matrix obtained based on voice information; if the chip is a video processing chip, the target matrix is ​​a voice information matrix obtained based on video information; if the chip is an image processing chip, the target matrix is ​​an image information matrix obtained based on image information. This embodiment does not limit the type of chip.

[0069] It should be noted that, unlike the random addressing method used in computers, the chip in this embodiment performs matrix transposition by directly reading data from the matrix using consecutive module addresses. Matrix transposition is achieved by placing data from adjacent address units in different memories, such as shift registers, and combining this with the parallel operation of each shift register.

[0070] Given the target matrix, a transpose operation is performed on it. This is done by simultaneously reading and writing data to the target matrix, using a sequential addressing mechanism within the chip, to iteratively read and write the data. In this way, once all the data in the target matrix has been read, the transpose of the target matrix is ​​obtained.

[0071] The data read and write operations include:

[0072] S201, in accordance with the clock sequence, sequentially controls multiple shift registers in the chip to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit at each clock cycle.

[0073] In this embodiment, multiple shift registers in the chip are grouped together to perform the transpose operation of the target matrix, and one shift register is allowed to read data from the target matrix at each clock cycle. Following the clock sequence, one shift register from the multiple shift registers in the chip is sequentially controlled to read data from the target matrix, and the read data is stored in the least significant bit of the corresponding shift register.

[0074] In this case, the number of data read from the target matrix by different shift registers is the same, which is the same as the number of shift registers in the group. For example, if eight shift registers in the chip perform a matrix transpose operation on the target matrix, then the corresponding shift register reads 8 matrix elements from the target matrix in each clock cycle.

[0075] Meanwhile, during the data reading process of the shift register, if other shift registers have read data before the current clock, including stored data, then the stored data in the other shift registers will be shifted one bit to the higher bit.

[0076] Taking the matrix transpose operation of the target matrix performed by eight shift registers in the chip as an example, if none of the eight shift registers have read the data of the target matrix, then when the corresponding shift register reads the data in the first clock cycle, the other seven shift registers have not stored the data, and there will be no data shift to the higher bit. If all eight shift registers have read the data of the target matrix, then when the shift register corresponding to the current clock cycle reads the data, the other seven shift registers have stored the data. Therefore, in the current clock cycle, the stored data in each shift register will also shift one bit to the higher bit.

[0077] The process of reading data from eight shift registers is explained as follows: In the first clock cycle, the first register reads eight bits of the target matrix and stores the read data in its least significant bit. In the second clock cycle, the second register reads and stores eight bits of the target matrix and stores the read data in its least significant bit, while the data already stored in the first register shifts one bit to the most significant bit. In the third clock cycle, the third shift register reads eight bits of the target matrix and stores the read data in its least significant bit, while the data already stored in the first register continues to shift one bit to the most significant bit (the first register shifts two bits to the most significant bit cumulatively), and the data already stored in the second register shifts one bit to the most significant bit. In the fourth clock cycle, the fourth shift register reads eight bits of the target matrix and stores the read data in its least significant bit. The data is stored in the low bit of the fourth register, while the data stored in the first register continues to shift one bit to the high bit (the first register shifts three bits to the high bit cumulatively), and the data stored in the second register continues to shift one bit to the high bit cumulatively (the second register shifts three bits to the high bit cumulatively); and so on. On the eighth clock cycle, the eighth register reads eight bits of data from the target matrix. The data stored in the first register shifts seven bits to the high bit cumulatively, the data stored in the second register shifts six bits to the high bit cumulatively, the data stored in the third register shifts five bits to the high bit cumulatively, the data stored in the fourth register shifts four bits to the high bit cumulatively, the data stored in the fifth register shifts three bits to the high bit cumulatively, the data stored in the sixth register shifts two bits to the high bit cumulatively, and the data stored in the seventh register shifts one bit to the high bit cumulatively.

[0078] S202: After each shift register has completed one data read, control the highest bit of each shift register to be written into the transpose matrix.

[0079] After each shift register has completed one data read, meaning each shift register stores the data of the target matrix, and during the read process, the stored data in each shift register shifts one bit to the most significant bit in each clock cycle, the stored data in each shift register is now at its most significant bit. At this point, the most significant bit of each shift register is output and written into the transpose matrix.

[0080] In this embodiment, data read and write operations are performed cyclically on the target matrix until all data in the target matrix is ​​read, resulting in the transpose of the target matrix. The data read and write operations include: sequentially controlling multiple shift registers in the chip to read a preset number of data from the target matrix according to clock sequence; the preset number is the same as the number of shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit at each clock cycle; after each shift register has completed one data read, the most significant bit of each shift register is written into the transpose matrix. Because this embodiment controls the shift registers to read a preset number of data from the target matrix at each clock cycle, while simultaneously controlling the stored data in each shift register to shift one bit to the higher bit, and also controls the most significant bit of each shift register to be written into the transpose matrix after each data read, it is equivalent to simultaneously reading, shifting, and writing during the matrix transpose process using shift registers. This pipelined read and write mode avoids idle states for each shift register while conforming to the characteristics of chip pipeline operation, saving time in matrix transpose operations. Furthermore, in the matrix transposition method provided in this application embodiment, the number of data read by the shift register from the target matrix is ​​the same as the number of multiple shift registers. Therefore, when each shift register completes one data read, the bandwidth for reading data by the corresponding shift register at each clock cycle is consistent with the bandwidth of the highest bit stored in the output of each shift register at that clock cycle. This data read / write method with consistent input / output bandwidth facilitates regular address transitions during the writing of the transposed matrix, thereby improving the writing efficiency of the matrix transposition. Typically, taking the aforementioned voice processing chip, video processing chip, and image processing chip as examples, any chip in any scenario is integrated into a computer device. Therefore, it can be understood that by using the matrix transposition method provided in this application embodiment to transpose any matrix within the voice information matrix, voice information matrix, or image information matrix within the chip, improving the transposition efficiency of these matrices is equivalent to improving the chip's operating speed, and thus also equivalent to improving the operating speed of the computer device on which the chip is integrated.

[0081] During the matrix transpose operation performed by the chip, it is necessary to simultaneously read data from the target matrix and write data to the transpose matrix to improve the speed of the matrix transpose operation. Based on this, the following example illustrates the data reading steps for the target matrix.

[0082] In one embodiment, such as Figure 3 As shown, multiple shift registers are sequentially controlled to read data from the target matrix according to the clock sequence, including:

[0083] S301, obtain the read order of multiple shift registers.

[0084] Multiple shift registers in the chip are combined and ordered according to the rule of reading data from one shift register per clock cycle to obtain the reading order of multiple shift registers in the chip.

[0085] S302 obtains the read address of each shift register in the target matrix according to the clock sequence and the read order of multiple shift registers.

[0086] The read address is the basis for each shift register to read data. Each read address corresponds to a set of data. The shift register reads the data corresponding to the read address and stores it.

[0087] In this embodiment, different shift registers are controlled to read data from different rows of the target matrix according to the clock sequence and the reading order of multiple shift registers. Each clock cycle allows one shift register to acquire a read address to perform the data reading task. Given the shift register that performs data reading in each clock cycle, the read address of the shift register in the target matrix for each clock cycle is determined based on the data to be read from the target matrix in each clock cycle.

[0088] S303 controls each shift register to read data from the target matrix based on the read address of each shift register in the target matrix.

[0089] After obtaining the read address of each shift register in the target matrix, control each shift register to read data from the target matrix according to the corresponding read address, and store the read data in the low bit of the shift register in a first-in-first-out manner.

[0090] In this embodiment, at each clock cycle, the shift register is controlled to read data from the target matrix according to the read address. This is equivalent to fully utilizing the addressing mode of the chip's continuous module address during the data reading process, enabling the shift register to continuously read data and supporting the chip's pipeline operation mode.

[0091] The data reading process involves multiple shift registers within the chip. In this embodiment, only one shift register is allowed to perform data reading per clock cycle. Therefore, it is necessary to sort the multiple shift registers to determine which shift register will perform data reading at different clock cycles. Based on this, the following embodiment illustrates the steps for obtaining the reading order of multiple shift registers.

[0092] In one embodiment, such as Figure 4 As shown, the read order for obtaining multiple shift registers includes:

[0093] S401 determines the lengths of multiple shift registers based on the bandwidth of the memory cells in the chip; the lengths of each shift register are different. Specifically, the number of shift registers is the same as the bandwidth, and the lengths of each shift register decrease sequentially; the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

[0094] Based on the bandwidth of the memory cells in the chip, and following the principle of equal read and write bandwidth, the number of multiple shift registers is set, and the length of the multiple shift registers is determined.

[0095] Setting the bandwidth of the memory cell in the chip to be the same as the number of multiple shift registers ensures that, under the same clock cycle, the data written by multiple shift registers to the memory cell is consistent with the bandwidth of the memory cell.

[0096] Multiple shift registers of different lengths are determined based on the bandwidth of the memory cells in the chip. The minimum length is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth. This ensures that, when multiple shift registers include the stored data, the data stored in the highest bit of each shift register corresponds to a column of data in the target data.

[0097] Optionally, if the memory unit bandwidth is 8 bytes, then eight shift registers are set, with lengths ranging from 9 to 16 bytes. Assume each data bit is an int8 value, i.e., 1 byte. With this setup, if data is present in the most significant bit of each shift register, one register reads data per clock cycle, resulting in a data read bandwidth of 8 bytes. Furthermore, the most significant bits of all eight shift registers are simultaneously written back, also totaling 8 bytes.

[0098] S402 determines the order of multiple shift registers by ranking the lengths of each shift register from largest to smallest.

[0099] The multiple shift registers within the chip are sorted in descending order of their length to obtain the read order of the multiple shift registers.

[0100] Optionally, if the bandwidth of the storage unit is 8 bytes, then 8 shift registers are set, with the length of the shift registers varying sequentially from 9 to 16. Assuming each data is an int8 value, i.e., 1 byte, then the order of the registers for data reading is as follows: shift register of length 16, shift register of length 15, shift register of length 14, shift register of length 13, shift register of length 12, shift register of length 11, shift register of length 10, and shift register of length 9.

[0101] In this embodiment, the number of shift registers is set to be the same as the bandwidth of the storage unit. This is equivalent to ensuring that during data writing, multiple shift registers write data to the storage unit with the same bandwidth. Furthermore, the minimum length of the shift register is set to the bandwidth plus one, and the maximum length is set to twice the bandwidth. This is equivalent to providing pre-defined storage space for other shift registers to shift data while one shift register reads data from the target matrix during data reading. Therefore, the method of setting the number and length of shift registers in this embodiment ensures that the bandwidth for reading data is the same as the bandwidth for writing data during the data reading and writing process, thus fully utilizing the chip's computational efficiency.

[0102] After obtaining the read order of multiple shift registers within the chip, a read address is assigned to each shift register for data reading. The following example illustrates the steps for obtaining the read address of each shift register:

[0103] In one embodiment, such as Figure 5 As shown, the read address of each shift register in the target matrix is ​​obtained according to the clock sequence and the read order of multiple shift registers, including:

[0104] S501 obtains the shift register corresponding to each clock cycle according to the clock sequence and the reading order of multiple shift registers; and performs data reading of one shift register at each clock cycle.

[0105] According to the rule of performing data reading of one shift register per clock cycle, the clock sequence is matched with the reading order of multiple shift registers to obtain the shift register for which data reading is performed per clock cycle.

[0106] Taking a memory cell bandwidth of 8B as an example, we set up eight different shift registers with lengths ranging from 8 to 16, and the reading order of the multiple shift registers is in descending order of their lengths. Then, the shift register corresponding to the first clock cycle has a length of 16, the second clock cycle has a length of 15, the third clock cycle has a length of 14, the fourth clock cycle has a length of 13, the fifth clock cycle has a length of 12, the sixth clock cycle has a length of 11, the seventh clock cycle has a length of 10, the eighth clock cycle has a length of 9, and the ninth clock cycle has a length of 16.

[0107] S502, the address of the first row of data in the target matrix is ​​used as the read address of the shift register corresponding to the first clock, the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain the read address of the shift register corresponding to each clock.

[0108] Since each clock cycle corresponds to a shift register for data reading, and different shift registers read data from different rows of the target matrix, the row address of the data in the target matrix is ​​the read address of the shift register. Matching the row order of the target matrix with the clock order, the corresponding row address in the target matrix is ​​used as the read address of the shift register for the corresponding clock cycle.

[0109] Optionally, in the first clock cycle, the address of the first row of data in the target matrix is ​​used as the read address of the shift register under the first clock cycle; in the second clock cycle, the address of the second row of data in the target matrix is ​​used as the read address of the shift register under the second clock cycle; in the third clock cycle, the address of the third row of data in the target matrix is ​​used as the read address of the shift register under the third clock cycle; and so on, to obtain the read address of the shift register corresponding to each clock cycle.

[0110] In this embodiment, based on determining the shift register corresponding to each clock cycle, the read address of the shift register corresponding to each clock cycle is determined according to the row order of the target matrix. Since the row order is continuous and the clock order is also continuous, the read addresses of each shift register determined according to the row order are also continuous. This method of determining the read address cleverly utilizes the addressing mode of the chip's continuous module addresses, maximizing the chip's computational efficiency.

[0111] A shift register reads a row of data from a target matrix. However, if the shift register's read bandwidth is less than the number of elements in a row of the target matrix, the shift register needs to read the data multiple times to obtain a complete row of data from the target matrix. Therefore, the following example illustrates the steps of a shift register reading data from a target matrix based on a read address.

[0112] In one embodiment, such as Figure 6 As shown, based on the read address of each shift register in the target matrix, the system controls each shift register to read data from the target matrix, including:

[0113] S601: For any shift register, determine the target data corresponding to the shift register based on the read address of the shift register in the target matrix.

[0114] It should be noted that the data bandwidth corresponding to a read address is the same as the read bandwidth of the shift register. That is, one read address corresponds to multiple data points in one row of the target matrix. For example, if the read bandwidth is 8 bytes and one data point in the target matrix is ​​1 byte, then one read address corresponds to eight consecutive data points in one row of the target matrix.

[0115] For any shift register, based on the read address of the shift register in the target matrix, a set of data in the target matrix corresponding to the read address is determined as the target data to be read by the shift register.

[0116] S602 controls the shift register to read the target data.

[0117] Given a known target data for the shift register, the read address in the target matrix is ​​used as the read address of the target data, and the shift register is controlled to read the target data from the target matrix according to the read address of the target matrix.

[0118] In this embodiment, the target data corresponding to the shift register is determined according to the read address of the shift register in the target matrix, and the shift register is controlled to read the target data from the target matrix according to the read address. The design logic is clear and easy to implement.

[0119] During the matrix transpose operation performed by the chip, it is necessary to simultaneously read data from the target matrix and write data to the transpose matrix. The foregoing embodiments described the data reading steps for the target matrix. Based on this, the following embodiments will illustrate the data writing steps for the transpose matrix.

[0120] In one embodiment, such as Figure 7 As shown, the process of writing the most significant bit of each shift register into the transpose matrix includes:

[0121] S701 retrieves the most significant bit data from each shift register and combines the most significant bit data from each shift register to obtain the transpose vector.

[0122] When each shift register has completed one data read, the highest bit of each shift register stores the data of the target matrix, and the highest bit data of each shift register corresponds to the data of the same column of the target matrix. The highest bit data of each shift register is combined in the form of rows, and this combination is used as the transpose vector output by each shift register at the current clock.

[0123] S702 controls the writing of the transpose vector into the transpose matrix.

[0124] Since the transpose vector is stored in column form in the target matrix, transposing the target matrix requires writing the transpose vector into the transpose matrix in row form.

[0125] In this embodiment, based on obtaining the highest bit stored data of each shift register, the highest bit stored data of each shift register is combined to generate a transpose vector, and the transpose vector is controlled to be stored in the transpose matrix in the form of rows, thereby realizing the transpose operation of the target matrix.

[0126] Similar to the process of reading data from the target matrix, which requires obtaining the read address, the process of writing data to the transpose matrix also requires using the write address as a basis. Therefore, the following example illustrates the steps for writing data to the transpose matrix.

[0127] In one embodiment, such as Figure 8 As shown, controlling the transpose vector to be written into the transpose matrix includes:

[0128] S801, get the write address of the transpose vector in the transpose matrix.

[0129] The write address is the basis for writing the data stored in the most significant bit of each shift register into the transpose matrix. Each write address corresponds to a row of multiple consecutive data in the transpose matrix. Optionally, the write address of the transpose vector in the transpose matrix is ​​determined based on the position of the transpose vector in the transpose matrix.

[0130] S802 controls the writing of the transpose vector into the transpose matrix based on the write address.

[0131] Multiple shift registers are controlled to write the transpose vector into the transpose matrix according to the write address.

[0132] In this embodiment, the write address of the transpose vector in the transpose matrix is ​​obtained according to the position of the transpose vector in the transpose matrix, and the highest bit data stored in each shift register is written into the transpose matrix according to the write address, thereby realizing the transpose of the target matrix.

[0133] The following example illustrates one possible way to "obtain the write address of the transpose vector in the transpose matrix" as described in the aforementioned embodiments. Figure 9 As shown, obtaining the write address of the transpose vector in the transpose matrix includes:

[0134] S901, obtain the number of times each shift register has completed one data read during the cyclic execution of data read and write operations on the target matrix.

[0135] During the cyclic execution of data read and write operations on the target matrix, the number of times each shift register completes one data read is monitored, and the row position of the transpose vector in the transpose matrix is ​​determined based on the number of reads. The row address of the transpose vector in the transpose matrix is ​​then used as the write address of the transpose vector in the transpose matrix.

[0136] S902, determine the row address of the transpose vector in the transpose matrix based on the number of times.

[0137] For example, if the current shift register has completed one data read, and the transpose vector is the first column data of the target matrix, then the address of the first row in the transpose matrix is ​​the row address of the transpose vector in the transpose matrix.

[0138] S903 uses the row address of the transpose vector in the transpose matrix as the write address of the transpose vector in the transpose matrix.

[0139] In this embodiment, the row address of the transpose vector in the transpose matrix is ​​determined based on the number of times the shift register completes one data read, and then the write address of the transpose vector in the transpose matrix is ​​determined. Since both the target matrix and the transpose matrix are stored row by row in the chip, the write address confirmation method provided in this application only requires one address lookup to write the transpose vector into the transpose matrix, thereby improving the chip's computational efficiency.

[0140] In the matrix transpose process, data read and write operations are based on the read address and write address to read the data of the target matrix, and then write the data of the target matrix into the transpose matrix according to the transposed write address. In this embodiment, the read address and write address obtained by the chip are obtained by using a base address plus a bias address, and the transpose operation is performed on the target matrix through regular address jumps. Based on this, the address generation method in the matrix transpose method is described below through an embodiment.

[0141] In one embodiment, such as Figure 10 As shown, the matrix transpose method also includes:

[0142] S1001 determines the offset address transition step size for each clock cycle based on the size of the target matrix and the bandwidth of the memory cells in the chip.

[0143] During the data reading process, the read address includes the base address and the bias address. The width of the target matrix and the bandwidth of the memory cell in the chip are obtained, and the ratio of the width of the target matrix to the bandwidth of the memory cell in the chip is used as the step size of the bias address in each clock read address.

[0144] During the data writing process, the read address includes the base address and the bias address. The height of the target matrix and the bandwidth of the memory cell in the chip are obtained, and the ratio of the height of the target matrix to the bandwidth of the memory cell in the chip is used as the step size of the bias address in each clock read address.

[0145] For example, if the target matrix has a size of H (height) × W (width) and the memory cells are stored row-wise, and the bandwidth of the memory cells is 8B, meaning that each memory cell is a consecutive address unit of 8B, then the offset address transition step size for the read address in each clock cycle is ceil(W / 8), and the offset address transition step size for the write address in each clock cycle is ceil(H / 8). Here, ceil() represents the rounding up operation.

[0146] S1002, during the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the bias address jump step size of the clock, and after the bias address jump is completed, the base address of the clock is jumped by one address.

[0147] During the data reading operation, for any clock cycle, the bias address of the reading address is changed in the row direction of the target matrix according to the step size of the bias address in the reading address. After the bias address change is completed, the base address of the reading address changes by one address.

[0148] During the data write operation, for any clock cycle, the bias address of the write address is changed in the row direction of the transpose matrix according to the step size of the bias address in the write address. After the bias address change is completed, the base address of the write address changes by one address.

[0149] In this embodiment of the application, during the cyclic execution of data read and write operations on the target matrix, the read address and write address are consecutive addresses, which facilitates address transitions according to the address storage rules for each clock cycle.

[0150] In one embodiment, to Figure 11 Taking the target matrix shown as an example, the matrix transpose method will be explained. Figure 11 The target matrix shown has a size (W×H) of 64×16, and each data element in the target matrix is ​​1B. If the bandwidth of the storage unit is 8B, then 8 shift registers are set, and the lengths of the 8 shift registers decrease sequentially from 16 to 9. Figure 12 As shown. Figure 12 A schematic diagram illustrating the read / write process of transposing the target matrix using 8 shift registers.

[0151] Depend on Figure 12It can be seen that in the first clock cycle, the first register reads eight data points from the first row of the target matrix and stores them in the lower eight bits of the first register; in the second clock cycle, the second register reads eight data points from the second row of the target matrix and stores them in the lower eight bits of the second register, while the stored data in the first register shifts one bit to the left; in the third clock cycle, the third register reads eight data points from the third row of the target matrix and stores them in the lower eight bits of the third register, while the stored data in the first register continues to shift one bit to the left (the stored data in the first register has shifted a total of two bits), and the stored data in the second register shifts one bit to the left; and so on. In the eighth clock cycle, the eighth register reads eight data points from the eighth row of the target matrix and stores them in the lower eight bits of the eighth register, while the stored data in the first register has shifted a total of seven bits to the higher bits, the stored data in the second register has shifted a total of six bits to the higher bits, and the stored data in the third register... The data is shifted five bits to the most significant bit in the first register, four bits in the fourth register, three bits in the fifth register, two bits in the sixth register, and one bit in the seventh register. Since the lengths of the first to eighth registers decrease sequentially from 16 to 9, in the ninth clock cycle, the first register reads eight data points from the ninth to the fifteenth column of the first row of the target matrix. All stored data in all registers are shifted to the most significant bit, and the most significant bit of each shift register is output, representing the eight data points in the first column of the target matrix. Similarly, in the tenth clock cycle, the second register reads eight data points from the ninth to the fifteenth column of the second row of the target matrix. All stored data in all registers are shifted to the most significant bit, and the most significant bit of each shift register is output, representing the eight data points in the second column of the target matrix. In other words, after eight clock cycles, data in the target matrix can be read and written simultaneously, achieving a pipelined (non-blocking) data read / write operation. Furthermore, the bandwidth for each data read and the bandwidth for each data write are both 8 bytes, achieving the same read and write address.

[0152] and Figure 12 Corresponding to the read and write operations shown, this application also designs a corresponding address generation system, using a base address + partial address approach to provide a basis for data reading. For example... Figure 13 As shown, Figure 13 This is a schematic diagram illustrating the data write address transition pattern after the eighth clock cycle. In the ninth clock cycle, the most significant bit of each shift register stores the data and writes it to the transpose matrix in row format. Once the offset of the write address has completed its row transition in the transpose matrix, the base address of the write address transitions by one address.

[0153] In this embodiment of the application, combined with Figures 11-13The transpose operation of the target matrix is ​​explained. Based on the above operation process, the advantages of the technical solution provided by the embodiments of this application include the following three aspects:

[0154] (1) When the data reading bandwidth remains unchanged, the matrix transpose is achieved by using a shift register, and the pipeline reading and output are in line with the nature of the chip pipeline operation. This allows for faster matrix transpose, fully leveraging the chip's computing efficiency and effectiveness while saving power consumption.

[0155] (2) In terms of address addressing, the matrix transpose method provided in this application has matching input and output bandwidth and connected output data addresses, which makes it easy to realize address jump according to address storage rules.

[0156] (3) The embodiments of this application can quickly realize the transpose operation of a matrix, which provides a foundation for subsequent chips to realize other matrix operations (such as matrix multiplication).

[0157] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0158] Based on the same inventive concept, this application also provides a matrix transposition apparatus for implementing the matrix transposition method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more matrix transposition apparatus embodiments provided below can be found in the limitations of the matrix transposition method described above, and will not be repeated here.

[0159] In one embodiment, such as Figure 14 As shown, a matrix transpose device 1400 is provided, including: an acquisition module 1401, which includes a reading unit and a writing unit, wherein:

[0160] The acquisition module 1401 is used to perform data read and write operations on the target matrix in a loop until all data in the target matrix is ​​read, and to obtain the transpose of the target matrix.

[0161] The read unit is used to sequentially control multiple shift registers in the chip to read a preset number of data from the target matrix according to the clock sequence; the preset number is the same as the number of multiple shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit at each clock cycle;

[0162] The write unit is used to control the most significant bit of each shift register to be written into the transpose matrix after each shift register has completed a data read.

[0163] In one embodiment, the reading unit includes: a sequential reading subunit, an address acquisition subunit, and a data reading subunit, wherein:

[0164] Sequential read sub-unit, used to obtain the read order of multiple shift registers;

[0165] The address acquisition subunit is used to obtain the read address of each shift register in the target matrix according to the clock sequence and the read order of multiple shift registers;

[0166] The data reading subunit is used to control each shift register to read data from the target matrix according to the read address of each shift register in the target matrix.

[0167] In one embodiment, sequential reading of the sub-unit is further configured to determine the lengths of multiple shift registers based on the bandwidth of the memory units in the chip; the lengths of each shift register are different; and the order of the lengths of each shift register from largest to smallest is determined as the sorting of the multiple shift registers.

[0168] In one embodiment, the number of shift registers is the same as the bandwidth, and the length of each shift register decreases sequentially. The minimum length of each shift register is equal to the bandwidth plus 1, and the maximum length is equal to twice the bandwidth.

[0169] In one embodiment, the address acquisition subunit is further configured to acquire the shift register corresponding to each clock according to the clock sequence and the reading order of the multiple shift registers; perform data reading of one shift register at each clock; use the first row address of the data in the target matrix as the read address of the shift register corresponding to the first clock, the second row address as the read address of the shift register corresponding to the second clock, and so on, to obtain the read address of the shift register corresponding to each clock.

[0170] In one embodiment, the data reading subunit is further configured to, for any shift register, determine the target data corresponding to the shift register based on the read address of the shift register in the target matrix; and control the shift register to read the target data.

[0171] In one embodiment, the writing unit includes: a vector acquisition subunit and a vector writing subunit, wherein:

[0172] The vector acquisition subunit is used to acquire the most significant bit stored data of each shift register and combine the most significant bit stored data of each shift register to obtain the transpose vector;

[0173] The vector writing sub-cell is used to control the writing of the transpose vector into the transpose matrix.

[0174] In one embodiment, the vector writing subunit is also used to obtain the write address of the transpose vector in the transpose matrix; and control the writing of the transpose vector into the transpose matrix according to the write address.

[0175] In one embodiment, the vector writing subunit is further used to obtain the number of times each shift register has completed one data read during the cyclic execution of data read and write operations on the target matrix; determine the column address of the transposed vector in the transposed matrix based on the number of reads; and use the column address of the transposed vector in the transposed matrix as the write address of the transposed vector in the transposed matrix.

[0176] In one embodiment, the matrix transpose device 1400 further includes a determination module and a transition module, wherein:

[0177] The determination module is used to determine the offset address transition step size for each clock cycle based on the size of the target matrix and the bandwidth of the memory cells in the chip.

[0178] The jump module is used to perform a partial address jump in the row direction for any clock according to the partial address jump step size of the clock during the cyclic execution of data read and write operations on the target matrix, and jump one address to the base address of the clock after the partial address jump is completed.

[0179] Each module in the aforementioned matrix transpose device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0180] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0181] The target matrix is ​​repeatedly read and written data until all data in the target matrix has been read, resulting in the transpose of the target matrix. The data read and write operations include:

[0182] According to the clock sequence, multiple shift registers in the chip are controlled sequentially to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit in each clock cycle;

[0183] After each shift register has completed one data read, the highest bit of each shift register is written into the transpose matrix.

[0184] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0185] Obtain the read order of multiple shift registers;

[0186] According to the clock sequence and the reading order of multiple shift registers, obtain the reading address of each shift register in the target matrix;

[0187] Based on the read address of each shift register in the target matrix, control each shift register to read data from the target matrix.

[0188] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0189] The lengths of multiple shift registers are determined based on the bandwidth of the memory cells in the chip; the lengths of each shift register are different.

[0190] The order of the shift registers is determined by ranking the lengths of each shift register from largest to smallest.

[0191] In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases sequentially; wherein the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

[0192] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0193] Based on the clock sequence and the read order of multiple shift registers, obtain the shift register corresponding to each clock cycle; perform data read of one shift register at each clock cycle;

[0194] The address of the first row of data in the target matrix is ​​used as the read address of the shift register corresponding to the first clock, the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain the read address of the shift register corresponding to each clock.

[0195] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0196] For any shift register, the target data corresponding to the shift register is determined based on the read address of the shift register in the target matrix;

[0197] Control the shift register to read the target data.

[0198] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0199] Obtain the most significant bit data of each shift register, and combine the most significant bit data of each shift register to obtain the transpose vector;

[0200] The transpose vector is written into the transpose matrix.

[0201] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0202] Get the write address of the transpose vector in the transpose matrix;

[0203] Based on the write address, control the transpose vector to be written into the transpose matrix.

[0204] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0205] Get the number of times each shift register completes one data read during the cyclic execution of data read and write operations on the target matrix;

[0206] The column address of the transpose vector in the transpose matrix is ​​determined based on the number of times it is used.

[0207] Use the column address of the transpose vector in the transpose matrix as the write address of the transpose vector in the transpose matrix.

[0208] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0209] The offset address transition step size for each clock cycle is determined based on the width of the target matrix and the size of the memory cells in the chip.

[0210] During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the bias address jump step size of the clock, and after the bias address jump is completed, the base address of the clock jumps by one address.

[0211] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0212] The target matrix is ​​repeatedly read and written data until all data in the target matrix has been read, resulting in the transpose of the target matrix. The data read and write operations include:

[0213] According to the clock sequence, multiple shift registers in the chip are controlled sequentially to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit in each clock cycle;

[0214] After each shift register has completed one data read, the highest bit of each shift register is written into the transpose matrix.

[0215] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0216] Obtain the read order of multiple shift registers;

[0217] According to the clock sequence and the reading order of multiple shift registers, obtain the reading address of each shift register in the target matrix;

[0218] Based on the read address of each shift register in the target matrix, control each shift register to read data from the target matrix.

[0219] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0220] The lengths of multiple shift registers are determined based on the bandwidth of the memory cells in the chip; the lengths of each shift register are different.

[0221] The order of the shift registers is determined by ranking the lengths of each shift register from largest to smallest.

[0222] In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases sequentially; wherein the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

[0223] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0224] Based on the clock sequence and the read order of multiple shift registers, obtain the shift register corresponding to each clock cycle; perform data read of one shift register at each clock cycle;

[0225] The address of the first row of data in the target matrix is ​​used as the read address of the shift register corresponding to the first clock, the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain the read address of the shift register corresponding to each clock.

[0226] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0227] For any shift register, the target data corresponding to the shift register is determined based on the read address of the shift register in the target matrix;

[0228] Control the shift register to read the target data.

[0229] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0230] Obtain the most significant bit data of each shift register, and combine the most significant bit data of each shift register to obtain the transpose vector;

[0231] The transpose vector is written into the transpose matrix.

[0232] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0233] Get the write address of the transpose vector in the transpose matrix;

[0234] Based on the write address, control the transpose vector to be written into the transpose matrix.

[0235] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0236] Get the number of times each shift register completes one data read during the cyclic execution of data read and write operations on the target matrix;

[0237] The column address of the transpose vector in the transpose matrix is ​​determined based on the number of times it is used.

[0238] Use the column address of the transpose vector in the transpose matrix as the write address of the transpose vector in the transpose matrix.

[0239] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0240] The offset address transition step size for each clock cycle is determined based on the size of the target matrix and the bandwidth of the memory cells in the chip.

[0241] During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the bias address jump step size of the clock, and after the bias address jump is completed, the base address of the clock jumps by one address.

[0242] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0243] The target matrix is ​​repeatedly read and written data until all data in the target matrix has been read, resulting in the transpose of the target matrix. The data read and write operations include:

[0244] According to the clock sequence, multiple shift registers in the chip are controlled sequentially to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit in each clock cycle;

[0245] After each shift register has completed one data read, the highest bit of each shift register is written into the transpose matrix.

[0246] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0247] Obtain the read order of multiple shift registers;

[0248] According to the clock sequence and the reading order of multiple shift registers, obtain the reading address of each shift register in the target matrix;

[0249] Based on the read address of each shift register in the target matrix, control each shift register to read data from the target matrix.

[0250] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0251] The lengths of multiple shift registers are determined based on the bandwidth of the memory cells in the chip; the lengths of each shift register are different.

[0252] The order of the shift registers is determined by ranking the lengths of each shift register from largest to smallest.

[0253] In one embodiment, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases sequentially; wherein the minimum length of each shift register is equal to the bandwidth plus one, and the maximum length is equal to twice the bandwidth.

[0254] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0255] Based on the clock sequence and the read order of multiple shift registers, obtain the shift register corresponding to each clock cycle; perform data read of one shift register at each clock cycle;

[0256] The address of the first row of data in the target matrix is ​​used as the read address of the shift register corresponding to the first clock, the address of the second row is used as the read address of the shift register corresponding to the second clock, and so on, to obtain the read address of the shift register corresponding to each clock.

[0257] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0258] For any shift register, the target data corresponding to the shift register is determined based on the read address of the shift register in the target matrix;

[0259] Control the shift register to read the target data.

[0260] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0261] Obtain the most significant bit data of each shift register, and combine the most significant bit data of each shift register to obtain the transpose vector;

[0262] The transpose vector is written into the transpose matrix.

[0263] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0264] Get the write address of the transpose vector in the transpose matrix;

[0265] Based on the write address, control the transpose vector to be written into the transpose matrix.

[0266] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0267] Get the number of times each shift register completes one data read during the cyclic execution of data read and write operations on the target matrix;

[0268] The column address of the transpose vector in the transpose matrix is ​​determined based on the number of times it is used.

[0269] Use the column address of the transpose vector in the transpose matrix as the write address of the transpose vector in the transpose matrix.

[0270] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0271] The offset address transition step size for each clock cycle is determined based on the size of the target matrix and the bandwidth of the memory cells in the chip.

[0272] During the cyclic execution of data read and write operations on the target matrix, for any clock, a bias address jump is performed in the row direction according to the bias address jump step size of the clock, and after the bias address jump is completed, the base address of the clock jumps by one address.

[0273] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0274] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0275] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A matrix transpose method, characterized in that, The method includes: The target matrix is ​​repeatedly read and written data until all data in the target matrix has been read, resulting in the transpose of the target matrix; the data read and write operations include: The lengths of multiple shift registers are determined based on the bandwidth of the memory cells in the chip. The lengths of each shift register are different, and the order in which the lengths of the multiple shift registers are determined from largest to smallest is the reading order of the multiple shift registers. According to the clock sequence and the reading sequence, multiple shift registers in the chip are sequentially controlled to read a preset number of data from the target matrix; the preset number is the same as the number of multiple shift registers, the number of multiple shift registers is the same as the bandwidth, and the length of each shift register decreases sequentially, the minimum length of each shift register is equal to the bandwidth plus one, the maximum length is equal to twice the bandwidth, and during the reading process, the stored data in each shift register is shifted one bit to the higher bit at each clock cycle; After each shift register has completed a data read, the highest bit stored data of each shift register is obtained, and the highest bit stored data of each shift register is combined to obtain a transpose vector, which is then written into the transpose matrix.

2. The method according to claim 1, characterized in that, The step of sequentially controlling multiple shift registers in the chip to read a preset amount of data from the target matrix according to the clock sequence and the reading sequence includes: According to the clock sequence and the reading order of the multiple shift registers, obtain the reading address of each shift register in the target matrix; Based on the read address of each shift register in the target matrix, control each shift register to read data from the target matrix.

3. The method according to claim 2, characterized in that, The step of obtaining the read address of each shift register in the target matrix according to the clock sequence and the read order of the plurality of shift registers includes: Based on the clock sequence and the read order of the multiple shift registers, obtain the shift register corresponding to each clock cycle; perform data read of one shift register at each clock cycle; The first row address of the data in the target matrix is ​​used as the read address of the shift register corresponding to the first clock, the second row address is used as the read address of the shift register corresponding to the second clock, and so on, to obtain the read address of the shift register corresponding to each clock.

4. The method according to claim 2, characterized in that, The step of controlling each shift register to read data from the target matrix according to the read address of each shift register in the target matrix includes: For any shift register, the target data corresponding to the shift register is determined according to the read address of the shift register in the target matrix; Control the shift register to read the target data.

5. The method according to claim 1, characterized in that, The process of controlling the writing of the transpose vector into the transpose matrix includes: Obtain the write address of the transpose vector in the transpose matrix; Based on the write address, control the transpose vector to be written into the transpose matrix.

6. The method according to claim 5, characterized in that, The step of obtaining the write address of the transpose vector in the transpose matrix includes: Obtain the number of times each of the shift registers completes one data read during the cyclic execution of data read and write operations on the target matrix; The column address of the transpose vector in the transpose matrix is ​​determined based on the number of times; The column address of the transpose vector in the transpose matrix is ​​used as the write address of the transpose vector in the transpose matrix.

7. The method according to claim 1 or 2, characterized in that, The method further includes: The offset address transition step size for each clock cycle is determined based on the size of the target matrix and the bandwidth of the memory cells in the chip. During the cyclic execution of data read and write operations on the target matrix, for any given clock, a partial address jump is performed in the row direction according to the partial address jump step size of the clock, and after the partial address jump is completed, the base address of the clock jumps by one address.

8. A computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method according to any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of claims 1-7.

10. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-7.

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