A flip chip manufacturing method and flip chip

Abstract

The application discloses a flip chip preparation method and a flip chip, and belongs to the flip chip technical field. The flip chip preparation method provided by the application heats a first interconnection element at a first temperature, heats a second interconnection element at a second temperature which is 10 DEG C or more lower than the melting point of an interconnection structure and lower than the first temperature, and realizes flip soldering by applying force to make the first interconnection element and the second interconnection element opposite to each other. Since the first temperature can ensure that the first interconnection element reaches wetting and is combined with the second interconnection element, and the second temperature is relatively low and cannot cause the interconnection structure to soften and deform, the problem that the performance parameters of the chip are changed due to the deformation of the interconnection structure during flip soldering is avoided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of flip chip technology, especially the technical field of superconducting quantum chip, in particular, the present application relates to a preparation method of flip chip and flip chip. BACKGROUND

[0002] Flip chip welding technology as a microelectronic circuit interconnection technology, which is to interconnect the circuit structure on the lower surface of the substrate with the circuit structure on the upper surface of another substrate with solder, forming a stable and reliable mechanical and electrical connection, the process method of flip chip welding mainly includes hot press welding method.

[0003] The quantum bit on the quantum chip is the basic unit of quantum computation, in order to realize the large-scale expansion of quantum bit, it is usually necessary to realize the interconnection of the quantum circuit on the substrate through flip chip welding technology. When multiple layers are stacked through welding, the flip welding process performed later will easily affect the morphology of the interconnection structure of the previous welding, and further affect the chip performance parameters. SUMMARY

[0004] The purpose of the present application is to provide a preparation method of flip chip and flip chip, which can realize multi-layer stacking and does not affect the morphology of the interconnection structure of the previous welding.

[0005] One aspect of the present application provides a preparation method of flip chip, which comprises:

[0006] providing a substrate, the substrate is formed with a first interconnection element;

[0007] providing a welding assembly, the welding assembly is formed with a second interconnection element and an interconnection structure, and the interconnection structure is on the surface opposite to the second interconnection element; and

[0008] heating the first interconnection element at a first temperature and heating the second interconnection element at a second temperature, and applying a force to make the first interconnection element and the opposite second interconnection element joint, wherein the first temperature is higher than the second temperature, and the second temperature is lower than the melting point of the interconnection structure by more than 10℃.

[0009] As described above, in some embodiments, the first temperature is within 10℃ of the melting point of the first interconnection element.

[0010] As described above, in some embodiments, the second temperature is more than 10℃ lower than the melting point of the second interconnection element and the first temperature.

[0011] As described above, in some embodiments, the first interconnection element, the second interconnection element and the interconnection structure are all indium, and the first temperature is 150℃-155℃, and the second temperature is 20℃-30℃.

[0012] The method for preparing the flip chip as described above, in some embodiments, the solder assembly comprises a first sub-base and a second sub-base, the interconnection structure comprises a first sub-element and a second sub-element which are opposite and jointed, and the first sub-element is located on the first sub-base and the second sub-element is located on the second sub-base.

[0013] The method for preparing the flip chip as described above, in some embodiments, the cross-sectional area of the interconnection structure is larger than the cross-sectional area of the first interconnection element and the second interconnection element; and / or, the number of the interconnection structure is larger than the number of the first interconnection element.

[0014] The method for preparing the flip chip as described above, in some embodiments, before providing the solder assembly, further comprises:

[0015] providing a first sub-base, the first sub-base is formed with a first sub-element;

[0016] providing a second sub-base, the second sub-base is formed with a second sub-element;

[0017] heating the first sub-element and the second sub-element at a third temperature, and applying a force to make the first sub-element and the second sub-element opposite and jointed to form an interconnection structure.

[0018] The method for preparing the flip chip as described above, in some embodiments, the melting point of the first sub-element and the second sub-element is the same, and the third temperature is within 10℃ of the melting point.

[0019] Another aspect of the present application also provides a flip chip prepared according to the method as described above, comprising:

[0020] a base formed with a first interconnection element;

[0021] a solder assembly formed with a second interconnection element and an interconnection structure, and the interconnection structure is on the surface opposite to the second interconnection element, and the first interconnection element and the second interconnection element are opposite and jointed.

[0022] Compared with the prior art, in flip-chip soldering the base formed with the first interconnection element and the solder assembly formed with the second interconnection element and the interconnection structure, the method for preparing the flip chip provided by the present application heats the first interconnection element at a first temperature, heats the second interconnection element at a second temperature which is 10℃ or more lower than the melting point of the interconnection structure and lower than the first temperature, and realizes flip-chip soldering by applying a force to make the first interconnection element jointed with the opposite second interconnection element. Since the first temperature can ensure that the first interconnection element reaches a wetting state to realize jointing with the second interconnection element, and the second temperature is relatively low and thus will not cause the interconnection structure to soften and deform, the deformation of the interconnection structure during flip-chip soldering is avoided, i.e. the consistency of the interconnection structure which has been flip-chip soldered is ensured, and thus it is also helpful to avoid the change of chip performance parameters caused by the change of the appearance of the interconnection structure. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the substrate and welding assembly in one embodiment of this application;

[0024] Figure 2 A schematic diagram of a flip chip fabrication method provided in one embodiment of this application;

[0025] Figure 3 A structural diagram of a flip chip provided in one embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the first inversion in one embodiment provided in this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 1 – substrate; 11 – first interconnect element;

[0029] 2 – Welding assembly, 21 – Second interconnecting element, 22 – Interconnecting structure;

[0030] 23 - First sub-subbase, 24 - Second sub-subbase, 221 - First sub-element, 222 - Second sub-element. Detailed Implementation

[0031] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the various embodiments may be combined with and referenced to each other without contradiction.

[0033] It is to be understood that the terms "first", "second", and the like, used in the description and the claims of the application, as well as above-mentioned figures, are used to distinguish between similar objects and are not necessarily used to describe a particular sequential or chronological order. It is to be understood that the use of the terms first, second, etc., meaning that a particular step involving a feature can be performed prior to, concurrent to or subsequent to another step. Moreover, the terms "comprising", "having", "including", and the like, when used in the context of specifying

[0034] In addition, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" another layer, region, pattern, or structure, it can be directly on the other layer or substrate, and / or there can also be one or more intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and / or there can also be one or more intervening layers. In addition, references can be made to layers "above" and "below" based on the figures.

[0035] A quantum chip is a processor that performs quantum computation in a quantum computer. The circuit structure of the processor as a processing unit is generally referred to as a quantum bit. The quantum bit can be understood as a two-level system that follows the laws of quantum mechanics and can be in an arbitrary superposition state of 0 and 1. There are various circuit structures around the quantum bit, such as an xy-control line (also referred to as an xy control line or a pulse control signal line) for performing an XY rotation operation on the quantum bit, a z-control line (also referred to as a z control signal line or a frequency control signal line) for performing a Z rotation operation on the quantum bit, a resonant cavity for reading, and a coupler for coupling between quantum bits. In a quantum chip, the circuit structures described above are generally referred to as quantum circuits.

[0036] Traditional quantum circuits are all prepared on the same substrate, which causes the space for forming quantum bits on the substrate to be very limited, so that the number of quantum bits is difficult to expand on a large scale. In order to realize large-scale expansion of quantum bits, the related technology classifies quantum circuits located on the substrate and prepares them on different substrates, and then realizes stacked interconnection through flip chip soldering technology. Flip chip soldering technology, as a microelectronic circuit interconnection technology, is to interconnect the circuit structure on the lower surface of the substrate with the circuit structure on the upper surface of another substrate with solder to form stable and reliable mechanical and electrical connections. Compared with the traditional wire bonding interconnection technology, the flip chip soldering technology has higher density and can increase the number of I / O per unit area. The preparation of flip chip bumps is basically in wafer or chip units, which has higher production efficiency and reduces the cost of batch packaging compared with wire bonding interconnection in single wire units.

[0037] When using flip chip soldering technology to stack interconnect three or more substrates to expand the number of quantum bits, it is generally necessary to realize the stacked interconnection between different layers one by one through multiple soldering. The subsequent flip chip soldering process is easy to affect the morphology and structure of the previously soldered components, and further affect the chip performance parameters. For example, the subsequent flip chip soldering process is easy to change the height of the interconnection structure formed by the previous flip chip soldering, thereby affecting the uniformity of the substrate spacing, causing the substrates to tilt relative to each other, which ultimately leads to changes in chip performance parameters.

[0038] When flip chip soldering technology is used to stack interconnect three or more substrates to expand the number of quantum bits, it is generally necessary to realize the stacked interconnection between different layers one by one through multiple soldering. The subsequent flip chip soldering process is easy to affect the morphology and structure of the previously soldered components, and further affect the chip performance parameters. For example, the subsequent flip chip soldering process is easy to change the height of the interconnection structure formed by the previous flip chip soldering, thereby affecting the uniformity of the substrate spacing, causing the substrates to tilt relative to each other, which ultimately leads to changes in chip performance parameters.

[0039] Figure 1 The structure diagram of the substrate and the soldering assembly before heating in an embodiment provided by the present application.

[0040] Figure 2 The structure diagram of the substrate and the soldering assembly before heating in an embodiment provided by the present application.

[0041] Figure 3 The structure diagram of the substrate and the soldering assembly before heating in an embodiment provided by the present application.

[0042] Combining Figures 1 to 3As shown, an embodiment of this application provides a method for fabricating a flip chip, comprising: providing a substrate 1, which may be made of a dielectric material such as silicon or sapphire, wherein a first interconnect element 11 is formed on the substrate 1, and the first interconnect element 11 may be directly formed on a circuit structure on the substrate 1; and providing a bonding assembly 2, wherein a second interconnect element 21 and an interconnect structure 22 are formed on the bonding assembly 2, wherein the second interconnect element 21 may be directly formed on a circuit structure of the bonding assembly 2, and the interconnect structure 22 is located on the bottom surface of another substrate, and the second interconnect element 21 is located on the top surface of the other substrate, i.e., the interconnect structure. 22 On the surface opposite to the second interconnect element 21, it is understood that the bottom and top here are relative to the accompanying drawings of the embodiments provided in this application; and, the first interconnect element 11 is heated at a first temperature and the second interconnect element 21 is heated at a second temperature, and a force is applied to make the first interconnect element 11 and the opposing second interconnect element 21 come into contact and fuse to achieve bonding, wherein the first temperature is higher than the second temperature, and the second temperature is lower than the melting point of the interconnect structure 22 by more than 10°C, for example, the second temperature is 10°C, 11°C, 12°C, 12.5°C, 14°C, etc., lower than the melting point. The welding assembly described above is a stacked device formed by a pre-performed flip-chip bonding technique, the stacked device includes at least two substrates and the at least two substrates are interconnected by flip-chip bonding technique, and the fabrication method provided in the embodiments of this application can prepare a multi-layer stacked interconnected chip by multiple welding processes.

[0043] See Figure 2 And compare Figure 1 As shown (relative to) Figure 1 , Figure 2 The end of the first interconnect element 11 is heated and wetted at the first temperature (therefore it is distinguished in the illustration). Since the heat provided by the first temperature can ensure that the first interconnect element 11 is heated and wetted, the wettability causes a portion of the first interconnect element 11 near the end to melt and become adhesive and atomically permeable, thereby enabling the first interconnect element to bond with the second interconnect element. The ends of the first interconnect element 11 and the second interconnect element 21 come into contact with each other under the action of external force and generate friction. Due to the bonding ability described above, the first interconnect element 11 and the second interconnect element 21 are bonded together. In this process, the second temperature used is far from the melting point of the interconnect structure, more than 10°C lower than the melting point, which ensures that the heat conducted will not cause the interconnect structure 22 to soften and deform. The interconnect structure 22 also still has a certain rigidity. Therefore, the preparation method of this embodiment avoids the change in the morphology of the interconnect structure 22 during flip-chip bonding, which affects the performance parameters of the chip.

[0044] It should be noted that the manner of providing the first temperature or the second temperature can be ultrasonic heating, or flat plate heating, hot air heating, laser heating, etc., and the specific implementation is not limited to the manner described above, as long as the first interconnection element 11 can be heated to the required first temperature, and the second interconnection element 21 can be heated to the required second temperature.

[0045] One of the commonly used process methods for flip chip soldering is thermal compression bonding. Figure 2 The force applied by the supporting table in the direction opposite to the direction of the arrow Figure 2 The working principle of thermal compression flip chip soldering is that under a certain pressure and temperature, ultrasonic energy is applied to the protruding element (i.e. the interconnection element described above) on a substrate, and within a certain time, the protruding element generates a binding force with the protruding element on another substrate, thereby realizing the interconnection of the protruding elements of the two substrates. The interface bonding of the protruding element of the thermal compression bonding is a friction process, which first involves interface contact and pre-deformation, i.e. under a given pressure, the protruding elements are in contact and are compressed and deformed to a certain extent; then ultrasonic action is applied to remove the oxide and contamination layer on the surface of the protruding element, and then the temperature rises sharply, the protruding element deforms, and the atoms of the protruding element penetrate each other until they are within a certain range. Therefore, the key process parameters of thermal compression flip chip soldering are pressure, temperature, ultrasonic power and soldering time.

[0046] The operation method of thermal compression flip chip soldering is to place one substrate to be flip chip soldered on the supporting table, pick up the other substrate with a pick-up soldering head, and place the substrate with protruding elements downward against the one substrate, adjust the alignment to make the two substrates parallel to each other and the soldering positions aligned. During flip chip soldering, the parallelism between the substrates is very important. If they are not parallel, the deformation of the protruding elements after soldering will vary greatly, resulting in different tensile strengths, and some soldering points may not meet the use requirements. Therefore, parallelism is crucial to the quality of soldering. During ultrasonic thermal compression, the protruding elements tend to melt under the action of temperature and pressure. The deformation occurring in this process is prone to tilting, which also leads to the fact that the flip chip soldering method is particularly sensitive to the consistency of the distance between the substrates.

[0047] In order to ensure that the first interconnection element 11 can achieve effective wetting when receiving heat provided by the first temperature, in some embodiments of the present application, the first temperature is lower than the melting point of the first interconnection element 11 and within 10°C of the melting point, for example, 10°C, 9°C, 8°C, 8.5°C, 7°C, etc. A temperature close to the melting point but not reaching the melting point can make the first interconnection element 11 achieve a molten wetting. It should be noted that wetting refers to the fact that the part close to the surface has been melted and forms an adherent layer on the surface of the base material by means of capillary force, and the melted part and the base material are close to each other and reach the distance at which atomic attraction acts.

[0048] In some embodiments of the present application, the second temperature is lower than the melting point of the second interconnection element 21 and the first temperature, and both are lower than 10°C, and in some embodiments, the second temperature is lower than 10°C, 11°C, 12°C, 12.5°C, 14°C, and so on, and the first temperature is lower than 10°C, 11°C, 12°C, 12.5°C, 14°C, and so on, so as to form a large enough temperature gradient in the direction from the first interconnection element 11 to the interconnection structure 22, and the large enough temperature gradient further ensures that the interconnection structure 22 does not deform.

[0049] In some embodiments of the present application, the first interconnection element 11, the second interconnection element 21, and the interconnection structure 22 are all superconductors. The superconductor can be formed of a superconductor material that exhibits superconducting properties at a temperature equal to or lower than a critical temperature, for example, at about 10-100 millikelvin (mK) or about 4K, such as aluminum, niobium, tantalum, or titanium nitride, and the like, and in some embodiments, the first interconnection element 11, the second interconnection element 21, and the interconnection structure 22 can be formed of indium (with a melting point of 157°C), the first temperature is 150°C-155°C (in some embodiments, the first temperature can be 150°C, 151°C, 152°C, 153°C, 154°C, 155°C, and the like), and the second temperature is 20°C-30°C (in some embodiments, the second temperature can be 20°C, 21°C, 23°C, 25°C, 28°C, 30°C, and the like), and in a preferred embodiment, the first temperature is 155°C and the second temperature is 20°C, so that the first interconnection element 11 and the second interconnection element 21, both of which are indium, can be bonded with high quality, and the interconnection structure 22 does not deform.

[0050] The solder assembly 2 is a device that is interconnected by flip-chip bonding technology, and can be a device with two substrates stacked on top of each other, and the circuit structures on the two substrates are interconnected by the interconnection structure 22. The solder assembly 2 can also be a device with three substrates stacked in an upper-middle-lower manner, and the substrate in the middle position is interconnected with the substrates above and below it by the interconnection structure 22. The substrates used in the solder assembly 2 can also be dielectric materials such as silicon or sapphire as described above.

[0051] The solder assembly 2 includes a structure with two substrates stacked on top of each other, as described below with reference to the accompanying drawings.

[0052] In combination with Figure 1 , Figure 2 and Figure 3As shown, the solder assembly 2 includes a first sub-substrate 23 at the bottom and a second sub-substrate 24 at the top, the top and bottom described herein are relative, the interconnection structure 22 includes a first sub-element 221 and a second sub-element 222 opposite and joined, the first sub-element 221 is located at the first sub-substrate 23, and the first sub-element 221 can be directly formed on a circuit structure at the first sub-substrate 23, and the second sub-element 222 is located at the second sub-substrate 24, and the second sub-element 222 can be directly formed on a circuit structure at the second sub-substrate 24, the joining of the first sub-element 221 and the second sub-element 222 can realize the connection of the circuit structure at the first sub-substrate 23 and the circuit structure at the second sub-substrate 24.

[0053] In order to prevent the first sub-substrate 23 and the second sub-substrate 24 from being tilted due to the pressing force in the subsequent flip soldering process. In some embodiments, the cross-sectional area of the interconnection structure 22 at any position is greater than the cross-sectional area of the first interconnection element 11 and the second interconnection element 21, so as to increase the pressure resistance of the single interconnection structure 22, and it should be noted that the cross section is perpendicular to the joining direction of the first sub-element 221 and the second sub-element 222, and the cross section of the interconnection structure 22 is shown in combination with Figure 1 、 Figure 2 and Figure 3 In other embodiments, the number of interconnection structures 22 is greater than the number of first interconnection elements 11, so as to increase the overall pressure resistance of the interconnection structure 22 to ensure the stability of the distance between the first sub-substrate 23 and the second sub-substrate 24.

[0054] Figure 4 The schematic diagram of the first flip in one embodiment of the present application.

[0055] Referring to Figure 4 , and in combination with Figure 2 In some embodiments of the present application, when the preparation method described above is implemented, the following steps are further included before the solder assembly 2 is provided: providing the first sub-substrate 23, the first sub-substrate 23 is formed with the first sub-element 221, and the material of the first sub-element 221 is exemplary the same as that of the first interconnection element 11; providing the second sub-substrate 24, the second sub-substrate 24 is formed with the second sub-element 222, and the material of the second sub-element 222 is exemplary the same as that of the first interconnection element 11; and heating the first sub-element 221 and the second sub-element 222 at a first temperature, and applying a force to make the first sub-element 221 and the second sub-element 222 opposite and joined to form the interconnection structure 22. The first sub-element 221 and the second sub-element 222 are the same as the melting point of the first interconnection element 11, so that a similar temperature can be used.

[0056] In the first flip-chip implementation, the first sub-element 221 and the second sub-element 222 can be made of a material different from the first interconnection element 11, and can be heated at a third temperature different from the first temperature, as long as the third temperature is lower than the melting point of the first sub-element 221 and the second sub-element 222 by 10°C or less.

[0057] Another aspect of the present application also provides a flip-chip prepared according to the method as described above, which will be described again below Figure 3 for description.

[0058] The flip-chip includes: a substrate 1 formed with the first interconnection element 11; and a solder assembly 2 formed with the second interconnection element 21 and the interconnection structure 22, and the interconnection structure 22 is on the surface opposite to the second interconnection element 21, and the first interconnection element 11 and the second interconnection element 21 are oppositely joined.

[0059] In the flip-chip, the solder assembly 2 is a device with stacked interconnections realized by the flip-chip soldering technology, which can be a device with two-layer substrates stacked in up-down manner, and the two-layer substrates are interconnected by the interconnection structure 22; the solder assembly 2 can also be a device with three-layer substrates stacked in up-middle-down manner, and the substrate in the middle position is interconnected with the substrates above and below it by the interconnection structure 22.

[0060] The solder assembly 2 includes the structure of two-layer substrates stacked in up-down manner, which will be described below in combination with the drawings.

[0061] Again in combination with Figure 1 and Figure 2 As shown in the drawings, the solder assembly 2 includes a first sub-substrate 23 and a second sub-substrate 24, the interconnection structure 22 includes oppositely joined first sub-element 221 and second sub-element 222, and the first sub-element 221 is located on the first sub-substrate 23, and the second sub-element 222 is located on the second sub-substrate 24. In some embodiments, the cross-sectional area of the interconnection structure 22 is greater than the cross-sectional area of the first interconnection element 11 and the second interconnection element 21; and / or, the number of the interconnection structure 2 is greater than the number of the first interconnection element 11. In some embodiments, the melting point of the first sub-element 221 and the second sub-element 222 is the same, and the third temperature is lower than the melting point by 10°C or less.

[0062] The above flip-chip has multiple layers of stacked substrates, and the spacing consistency of the substrates is relatively high, the performance parameters of the chip are stable, and the process preparation is easy, which has the same or similar beneficial effects as the above-described preparation method embodiments, and thus will not be described again. For technical details not disclosed in the flip-chip embodiments of the present application, those skilled in the art please refer to the description of the above preparation method, and for the sake of saving space, they will not be described again here.

[0063] The above detailed description of the application, features and effects of the application is based on the embodiments shown in the drawings, the above description is only the preferred embodiment of the application, but the application is not limited to the embodiments shown in the drawings, any changes or modifications made in accordance with the concept of the application, or equivalent embodiments with equivalent changes, are still within the scope of the application.

Claims

1. A method of fabricating a flip chip, comprising: The method comprises: providing a substrate, the substrate being formed with a first interconnection element; providing a solder assembly, the solder assembly being formed with a second interconnection element and an interconnection structure, the interconnection structure being located on a bottom surface of another substrate, and the second interconnection element being located on a top surface of the another substrate; heating the first interconnection element at a first temperature and heating the second interconnection element at a second temperature, and applying a force to make the first interconnection element and the opposing second interconnection element joint, wherein the first temperature is higher than the second temperature, the first temperature ensures the first interconnection element to reach a wetting state to realize the joint with the second interconnection element, and the second temperature is lower than the melting point of the interconnection structure by more than 10℃, avoiding the interconnection structure to soften and deform.

2. The method of claim 1, wherein, The first temperature is within 10℃ of the melting point of the first interconnection element.

3. The method according to claim 1 or 2, characterized in that, The second temperature is lower than the melting point of the second interconnection element and the first temperature by more than 10℃.

4. The method according to claim 1 or 2, characterized in that, The first interconnection element, the second interconnection element and the interconnection structure are all indium, and the first temperature is 150℃-155℃, and the second temperature is 20℃-30℃.

5. The method of claim 1, wherein, The solder assembly comprises a first sub-substrate and a second sub-substrate, the interconnection structure comprises a first sub-element and a second sub-element which are opposite and joint, and the first sub-element is located on the first sub-substrate, and the second sub-element is located on the second sub-substrate.

6. The method of claim 5, wherein, The cross-sectional area of the interconnection structure is greater than the cross-sectional area of the first interconnection element and the second interconnection element; and / or, the number of the interconnection structure is greater than the number of the first interconnection element.

7. The method of claim 5, wherein, Before providing the solder assembly, the method further comprises: providing a first sub-substrate, the first sub-substrate being formed with a first sub-element; providing a second sub-substrate, the second sub-substrate being formed with a second sub-element; heating the first sub-element and the second sub-element at a third temperature, and applying a force to make the first sub-element and the second sub-element opposite and joint to form the interconnection structure.

8. The method of claim 7, wherein, The first sub-element and the second sub-element have the same melting point, and the third temperature is within 10℃ of the melting point.

9. A flip chip prepared according to the method of any one of claims 1 to 8, characterized in that, The method comprises: providing a substrate, the substrate being formed with a first interconnection element; providing a solder assembly, the solder assembly being formed with a second interconnection element and an interconnection structure, the interconnection structure being located on a surface opposite to the second interconnection element, and the first interconnection element and the second interconnection element being opposite and joint.

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