Data clock tracking system and phase error generation improvement method

Abstract

The present application discloses a data clock tracking system, comprising a linear phase detection circuit and a binary phase detection circuit. Based on the linear phase detection circuit as a base, through the design of a specific edge distribution detection circuit, the binary phase detection circuit is started at different data edges to provide additional loop gain. The data clock tracking system appropriately distributes the number of linear phase detection circuits and binary phase detection circuits on multiple data edges of multiple data.

Description

Technical Field

[0001] This invention relates to data clock tracking, and more particularly to a data clock tracking system and a method for improving phase error generation. Background Technology

[0002] Generally, current phase detection circuits mainly have two design architectures: one is the binary phase detection (Bang-Bang Phase Detection, BBPD) architecture, and the other is the linear phase detection (Linear PD) architecture. Please refer to... Figure 1 and Figure 2 , Figure 1 and Figure 2 The figures show a comparison of phase error and phase detection gain for the traditional binary phase detection (BBPD) architecture and the linear phase detection (Linear PD) architecture, respectively.

[0003] Traditional binary phase sensing architectures generate fixed integral and proportional gains after each comparison of the phase lead / lag relationship between the system clock and the input data, outputting the same gain to adjust the system clock signal regardless of the magnitude of the phase lead / lag. Therefore, traditional binary phase sensing architectures do not suffer from phase shifts due to circuit delays in determining phase lead / lag, and the fixed phase lead / lag gain ratio provides better resistance to process variations.

[0004] However, a drawback of traditional binary phase sensing architectures is that they constantly maintain a dynamic balance between phase lead and lag. Even when the circuit is stable, the resulting clock jitter is still significant. This makes traditional binary phase sensing architectures highly dependent on data patterns, thus making it difficult to achieve a good balance between clock jitter and signal tracking capability. Please refer to... Figure 3 , Figure 3 This diagram illustrates the differences in data tracking and locking status with different data types.

[0005] The reason why traditional linear phase sensing architectures typically have smaller clock jitter and better signal tracking ability is that when the phase error is close to zero, the traditional linear phase sensing architecture produces a small integral gain—that is, the amount of frequency change tracking—while it provides a larger integral gain to track the signal when encountering a large phase lead / lag. Therefore, when the circuit is stable, it only produces a small clock jitter.

[0006] However, traditional linear phase sensing architectures can also suffer from additional phase offset due to the inherent delays in their circuitry. This makes them susceptible to process voltage temperature (PVT) variations caused by non-ideal factors. This phase offset cannot be reflected in the lead / lag calibration in traditional linear phase sensing architectures, and this phenomenon becomes more pronounced with increased bandwidth and higher data clock speeds. Figure 4 As shown, the phase error generated by the traditional linear phase detection architecture is normally stable, resulting in a sampling data setup time T. setup With hold time T hold It is compressed.

[0007] As can be seen from the above, the problems encountered by the existing technology still urgently need to be solved. Summary of the Invention

[0008] Therefore, this invention proposes a data clock tracking system and a phase error generation improvement method that combines the advantages of both binary phase detection (BBPD) and linear phase detection (Linear PD) architectures, so as to effectively solve the above-mentioned problems encountered in the prior art.

[0009] A preferred embodiment of the present invention provides a data clock tracking system. In this embodiment, the data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. Based on the linear phase detection circuit, the binary phase detection circuit is activated at different data edges through edge-specific detection circuit design to provide additional loop gain. The data clock tracking system appropriately allocates the number of linear and binary phase detection circuits across multiple data edges of multiple data records.

[0010] In one embodiment, different locking architectures are employed at the multiple data edges.

[0011] In one embodiment, the same locking architecture is used on the plurality of data edges.

[0012] In one embodiment, the multiple data sets have different data transformation densities.

[0013] In one embodiment, the multiple data entries have the same data transformation density.

[0014] In one embodiment, the binary phase detection circuit generates a binary phase detection signal while simultaneously providing the loop's integral gain and the loop's proportional gain.

[0015] In one embodiment, the linear phase detection circuit also synchronously generates a linear phase detection signal, while providing the integral gain and the proportional gain of the loop.

[0016] In one embodiment, the data clock tracking system is a clock data recovery circuit (CDR), a phase-lock loop (PLL), and / or other circuits with phase tracking functionality.

[0017] In one embodiment, the data clock tracking system may include a phase error judgment circuit, which is coupled to a linear phase detection circuit and a binary phase detection circuit respectively, to determine whether the phase error is greater than a preset value. If the judgment result is yes, the binary phase detection circuit is activated simultaneously to perform phase detection in order to provide additional loop gain.

[0018] In one embodiment, the binary phase detection circuit (BBPD) can be synchronized and normally activated at different data edges.

[0019] Another preferred embodiment of the present invention is a method for improving phase error generation. In this embodiment, the phase error generation improvement method is applied to a data clock tracking system. The data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. The phase error generation improvement method includes the following steps: (a) activating the linear phase detection circuit to perform phase detection; (b) activating the binary phase detection circuit at different data edges; and (c) the binary phase detection circuit assisting the linear phase detection circuit in locking at different data edges. The phase error generation improvement method appropriately allocates the number of linear phase detection circuits and binary phase detection circuits used at multiple data edges.

[0020] In one embodiment, different locking architectures are employed at the multiple data edges.

[0021] In one embodiment, the same locking architecture is used on the plurality of data edges.

[0022] In one embodiment, the multiple data sets have different data transformation densities.

[0023] In one embodiment, the multiple data entries have the same data transformation density.

[0024] In one embodiment, the binary phase detection circuit generates a binary phase detection signal while simultaneously providing the loop's integral gain and the loop's proportional gain.

[0025] In one embodiment, the linear phase detection circuit also synchronously generates a linear phase detection signal, while providing the integral gain and the proportional gain of the loop.

[0026] In one embodiment, the data clock tracking system is a clock data recovery circuit (CDR), a phase-lock loop (PLL), and / or other circuits with phase tracking functionality.

[0027] In one embodiment, step (b) may first determine whether the phase error of the data edge is greater than a preset value. If the determination result is yes, then the binary phase detection circuit is started to perform phase detection to provide additional loop gain.

[0028] In one embodiment, step (b) can be performed synchronously and normally on different data edges to activate the binary phase detection circuit.

[0029] Compared to existing technologies, the data clock tracking system and phase error generation improvement method of the present invention combine the advantages of both linear phase detection circuit and binary phase detection circuit architecture, which not only has better tracking capability but also generates less clock jitter to maintain circuit stability, and has lower dependence on changes in data conversion density, thereby enhancing the circuit's resistance to process variations during mass production. Attached Figure Description

[0030] Figure 1 This is a comparison chart of phase error and phase detection gain in a traditional binary phase detection (BBPD) architecture.

[0031] Figure 2 This is a comparison chart of phase error and phase detection gain for a traditional linear phase detection architecture.

[0032] Figure 3 This diagram illustrates the differences in data tracking and locking status with different data types.

[0033] Figure 4 This is a schematic diagram illustrating the stability characteristics of a traditional linear phase detection architecture.

[0034] Figure 5 This is a schematic diagram illustrating how the data clock tracking system of the present invention appropriately allocates the number of linear phase detection circuits and binary phase detection circuits across multiple data edges.

[0035] Figure 6 This is a comparison diagram of phase error and phase detection gain of the hybrid mode phase detection architecture of the present invention.

[0036] Figure 7 This is a schematic diagram of a data clock tracking system in a preferred embodiment of the present invention.

[0037] Figure 8This invention provides a timing diagram showing how different data edge detection architectures can be configured by the user to be applied to different types of data as needed.

[0038] Figure 9 This is a schematic diagram of another embodiment of the data clock tracking system of the present invention.

[0039] Figure 10 This is an embodiment of a phase error detection circuit.

[0040] Figure 11 This is a timing diagram when the phase error is less than the delay time.

[0041] Figure 12 This is a timing diagram when the phase error is greater than the delay time.

[0042] Figure 13 This is a flowchart of a phase error generation improvement method in another preferred embodiment of the present invention.

[0043] Explanation of key component symbols:

[0044] UP…Rising signal

[0045] DN…falling signal

[0046] DAT…data signal

[0047] Data D0~Dn…

[0048] CLK… clock signal

[0049] Thold…Reservation Time

[0050] Tsetup... Creation Time

[0051] E0~En… data edge

[0052] 5…Data Clock Tracking System

[0053] 50…Linear Phase Detection Circuit

[0054] 52…(Auxiliary) Binary Phase Detection Circuit

[0055] 7…Data Clock Tracking System

[0056] 70…Linear Phase Detection Circuit

[0057] 72… Binary Phase Detection Circuit

[0058] 74…Phase Error Judgment Circuit

[0059] CP1…First Charge Pump

[0060] CP2…Second charge pump

[0061] VCO…Voltage-controlled oscillator

[0062] R…resistance

[0063] C…capacitor

[0064] I CP1 …first current

[0065] I CP2 …second current

[0066] Φ…phase error

[0067] Td…Preset value (delay time)

[0068] FLAG…flag signal

[0069] SDATA[n:0]...data signal

[0070] 9…Data Clock Tracking System

[0071] 90…Linear Phase Detection Circuit

[0072] 92…Phase Error Judgment Circuit

[0073] 94… Binary Phase Detection Circuit

[0074] CLK[d]...delayed clock signal

[0075] IN1~IN3… Input terminals

[0076] OUT… Output terminal

[0077] td1~td2… delay unit

[0078] DFF1~DFF2…D-type flip-flop

[0079] NAND1~NAND2…reverse and gate

[0080] UPd…delayed rising signal

[0081] DNd…delayed falling signal

[0082] Steps S10~S16… Detailed Implementation

[0083] This invention provides a novel loop tracking circuit architecture design that combines the advantages of a linear phase detector (LINPD or PFD) and a binary phase detector (BBPD). Furthermore, by designing the circuit architecture, it reduces the generation of phase errors and lowers its dependence on data density, thereby achieving the effects of improved tracking capability and enhanced circuit stability.

[0084] A preferred embodiment of the present invention is a data clock tracking system. In this embodiment, the data clock tracking system of the present invention includes at least a linear phase detection circuit and a binary phase detection circuit. In practice, the data clock tracking system can be a clock data recovery circuit (CDR), a phase-frequency lock loop (PLL), and / or other circuits with phase tracking function, and there are no specific limitations.

[0085] It should be noted that the data clock tracking system of this invention mainly uses a linear phase detection circuit for phase locking, and is combined with a binary phase detection circuit to synchronously detect the leading / lagging of the data phase. Once the detected phase error is too large, the binary phase detection circuit will be activated to assist in loop locking. Therefore, once the circuit is stable, it not only has the advantage of low jitter of the linear phase detection circuit, but also the advantage of low phase error of the binary phase detection circuit itself.

[0086] In detail, the data clock tracking system of the present invention is based on a linear phase detection circuit. By designing a specific data edge allocation detection circuit, the number of linear phase detection circuits and binary phase detection circuits are appropriately allocated on multiple data edges of multiple data, so as to activate the binary phase detection circuit at different data edges to provide additional loop gain.

[0087] For example, such as Figure 5 As shown, assuming that the data signal DAT sequentially includes multiple data points D0 to D9 and these multiple data points D0 to D9 have multiple data edges E0 to E10, the data clock tracking system 5 can selectively use binary phase detection on data edges E1, E3, E5, E7, and E9, and use mixed-mode phase detection on data edges E2, E4, E6, E8, and E10, but is not limited thereto.

[0088] When the data clock tracking system 5 employs binary phase detection at data edges E1, E3, E5, E7, and E9, it bypasses the linear phase detection unit 50 by using the binary phase detection unit 52 for phase locking. When the data clock tracking system 5 employs mixed-mode phase detection at data edges E2, E4, E6, E8, and E10, it primarily uses the linear phase detection circuit 50 for phase locking. Figure 6 As shown, once the phase error detected synchronously is too large (e.g., greater than KΦ), the (auxiliary) binary phase detection circuit 52 will be activated to assist loop locking in order to provide additional phase detection gain.

[0089] Therefore, compared to traditional data clock tracking circuits that configure phase detection circuits at the data edges of each data entry to ensure tracking changes at each data edge, this invention allows users to configure different data edge detection architectures and can be applied to different types of data as needed. By designing the tracking pattern of each data edge, its dependence on the data can be effectively reduced.

[0090] In practical applications, the data clock tracking system of this invention can employ different or the same locking architecture at the multiple data edges, and the multiple data entries can have different or the same data conversion density without specific limitations. The binary phase detection circuit generates a binary phase detection signal and simultaneously provides the loop's integral gain and proportional gain. Similarly, the linear phase detection circuit also synchronously generates a linear phase detection signal and simultaneously provides the loop's integral gain and proportional gain.

[0091] Figure 7 This is a schematic diagram of a data clock tracking system according to a preferred embodiment of the present invention. Figure 7 As shown, in this embodiment, the data clock tracking system 7 includes a linear phase detection circuit 70, a binary phase detection circuit 72, a phase error judgment circuit 74, a first charge pump CP1, a second charge pump CP2, and a voltage-controlled oscillator (VCO). The linear phase detection circuit 70 is coupled to the first charge pump CP1. The binary phase detection circuit 72 is coupled to the second charge pump CP2. Both the first charge pump CP1 and the second charge pump CP2 are coupled to the VCO. The VCO is coupled to both the linear phase detection circuit 70 and the binary phase detection circuit 72.

[0092] The phase error judgment circuit 74 is coupled to the linear phase detection circuit 70 and the binary phase detection circuit 72 to determine whether the phase error is greater than a preset value. If the judgment result of the phase error judgment circuit 74 is yes, that is, the phase error is greater than the preset value, then in addition to the originally activated linear phase detection circuit 70, the data clock tracking system 7 will also simultaneously activate the binary phase detection circuit 72 for phase locking to provide additional loop gain. If the judgment result of the phase error judgment circuit 74 is no, that is, the phase error is not greater than the preset value, then only the linear phase detection circuit 70 remains activated. The first charge pump CP1 and the second charge pump CP2 generate the first current ICP1 and the second current ICP2 to the voltage-controlled oscillator VCO, respectively, and the first current ICP1 >> the second current ICP2. The voltage-controlled oscillator VCO outputs m phase clocks to the binary phase detection circuit 72.

[0093] Figure 8 This is a timing diagram illustrating how the detection architecture of the present invention can be configured by the user to be applied to different types of data as needed. For example... Figure 8 As shown, assume that the data signal DAT sequentially includes (n+1) data points D0 to Dn, and these (n+1) data points D0 to Dn have (n+1) data edges E0 to En. At data edge E1 between data D0 and D1, the linear phase detection circuit will start, and its output linear phase detection signal includes a rising signal UP and a falling signal DN. At this time, since the phase error Φ of the rising signal UP leading the falling signal DN is not greater than the preset value (delay time) Td, the auxiliary binary phase detection circuit and the binary phase detection circuit will not start. At data edge E2 between data D1 and D2, the linear phase detection circuit remains running, and the phase error Φ of its output rising signal UP leading the falling signal DN is greater than the preset value (delay time) Td. Therefore, the auxiliary binary phase detection circuit will start simultaneously and output the rising signal UP. Similarly, at the data edge En between data Dn-1 and Dn, the linear phase detection circuit will start and its output falling signal DN will lead the rising signal UP by a phase error Φ greater than the preset value Td. Therefore, the auxiliary binary phase detection circuit will start at the same time and output the falling signal DN.

[0094] Figure 9 This is a schematic diagram of another embodiment of the data clock tracking system of the present invention. Figure 9As shown, the data clock tracking system 9 may include multiple linear phase detection circuits 90, multiple phase error judgment circuits 92, and multiple binary phase detection circuits 94. The linear phase detection circuits 90 are coupled to the phase error judgment circuits 92. The phase error judgment circuits 92 are coupled to the binary phase detection circuits 94. Both the linear phase detection circuits 90 and the phase error judgment circuits 92 receive a delayed clock signal CLK[d] and operate according to the delayed clock signal CLK[d]. The linear phase detection circuits 90 output linear phase detection signals (including a rising signal UP and a falling signal DN) to the phase error judgment circuits 92. The phase error judgment circuits 92 determine whether the phase error Φ between the rising signal UP and the falling signal DN is greater than a preset value (delay time) Td, and then output a high-level or low-level flag signal FLAG to the binary phase detection circuits 94 to control the binary phase detection circuits 94 to turn them on or off.

[0095] Figure 10 This is one embodiment of a phase error detection circuit. For example... Figure 10 As shown, the phase error judgment circuit 92 includes input terminals IN1~IN3, output terminal OUT, delay units td1~td2, D-type flip-flops DFF1~DFF2, and inverting gates NAND1~NAND2. Input terminal IN1 is coupled to delay unit td1 and D-type flip-flop DFF2. Input terminal IN2 is coupled to delay unit td2 and D-type flip-flop DFF1. Delay unit td1 is coupled to D-type flip-flop DFF1. Delay unit td2 is coupled to D-type flip-flop DFF2. The output terminals of D-type flip-flops DFF1 and DFF2 are coupled to the two input terminals of inverting gates NAND1. The output terminal of inverting gates NAND1 is coupled to output terminal OUT. The two input terminals of inverting gates NAND2 are coupled to the output terminal and input terminal IN3 of inverting gates NAND1. The output terminals of inverting gates NAND2 are coupled to D-type flip-flops DFF1 and DFF2.

[0096] Inputs IN1 to IN3 receive the rising signal UP, the falling signal DN, and the delayed clock signal CLK[d], respectively. Delay circuit td1 receives the rising signal UP and delays it by a preset value (delay time) to become a delayed rising signal UPd, which is then output to input D of D-type flip-flop DFF1. Delay circuit td2 receives the falling signal DN and delays it by a preset value (delay time) to become a delayed falling signal DNd, which is then output to input D of D-type flip-flop DFF2. Input CLK of D-type flip-flop DFF1 receives the falling signal DN. Input CLK of D-type flip-flop DFF2 receives the rising signal UP. The output of the inverting gate NAND1 outputs a flag signal FLAG to control the binary phase detection circuit BBPD to turn on or off.

[0097] like Figure 11As shown, because the phase error Φ between the falling signal DN and the rising signal UP output by the linear phase detection circuit is less than the preset value (delay time) Td, the flag signal FLAG remains at a low level and will not simultaneously activate the binary phase detection circuit. Figure 12 As shown, since the phase error Φ of the falling signal DN output by the linear phase detection circuit leading the rising signal UP is greater than the preset value (delay time) Td, the flag signal FLAG will change from the low level to the high level at the same time as the rising signal UP to simultaneously turn on the binary phase detection circuit. The flag signal FLAG will only change from the high level to the low level when the delayed clock signal CLK[d] changes from the high level to the low level to turn off the binary phase detection circuit.

[0098] In practical applications, binary phase detection circuits can be synchronously activated at different data edges and are normally enabled, but this is not a limitation.

[0099] Another preferred embodiment of the present invention is a method for improving phase error generation. In this embodiment, the method for improving phase error generation is applied to a data clock tracking system, and the data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. In practice, the data clock tracking system may be a data clock recovery circuit, a phase-frequency tracking loop, and / or other circuits with phase tracking functionality, but is not limited thereto.

[0100] Figure 13 A flowchart of the phase error improvement method in this embodiment is provided. Figure 13 As shown, the method for improving phase error generation may include the following steps:

[0101] Step S10: Start the linear phase detection circuit to perform phase detection;

[0102] Step S12: Determine if the circuit frequency is locked;

[0103] Step S14: If the judgment result of step S12 is yes, activate the binary phase detection circuit on different data edges; and

[0104] Step S16: The binary phase detection circuit assists the linear phase detection circuit in locking at different data edges;

[0105] If the result of step S12 is negative, then return to step S10.

[0106] One method to improve phase error generation is to appropriately allocate the number of linear phase detection circuits and binary phase detection circuits across multiple data edges.

[0107] In practical applications, the binary phase detection circuit can employ different or identical locking architectures at these multiple data edges to assist the linear phase detection circuit in locking, without any specific restrictions. Furthermore, these multiple data points can have different or identical data transformation densities, without any specific restrictions.

[0108] In this embodiment, the binary phase detection circuit generates binary phase detection signals (e.g., rising signal UP and falling signal DN) and simultaneously provides the loop's integral gain and proportional gain. Similarly, the linear phase detection circuit also synchronously generates linear phase detection signals (e.g., rising signal UP and falling signal DN) and simultaneously provides the loop's integral gain and proportional gain.

[0109] It should be noted that step S14 can first determine whether the phase error at the data edge (e.g., the phase difference between the rising signal UP and the falling signal DN) is greater than a preset value (e.g., delay time). If the determination result is yes, then the binary phase detection circuit is simultaneously activated to perform phase detection, in order to provide additional loop gain. In addition, step S14 can also synchronously and normally activate the binary phase detection circuit on different data edges, but this is not a limitation.

[0110] Compared to existing technologies, the data clock tracking system and phase error generation improvement method of the present invention combine the advantages of both linear phase detection circuit and binary phase detection circuit architecture, which not only has better tracking capability but also generates less clock jitter to maintain circuit stability, and has lower dependence on changes in data conversion density, thereby enhancing the circuit's resistance to process variations during mass production.

Claims

1. A data clock tracking system, characterized in that, include: Linear phase detection circuit; as well as Binary phase detection circuit; The data clock tracking system allocates the number of linear phase detection circuits and binary phase detection circuits at multiple data edges of multiple data records. When the data clock tracking system uses binary phase detection on the multiple data edges, the data clock tracking system bypasses the linear phase detection unit by phase locking through the binary phase detection circuit. When the data clock tracking system uses hybrid mode phase detection on multiple data edges, the data clock tracking system uses the linear phase detection circuit for phase locking. Once the phase error detected by the linear phase detection circuit is too large, the data clock tracking system simultaneously activates the binary phase detection circuit to assist loop locking, thereby providing additional phase detection gain.

2. The data clock tracking system as described in claim 1, characterized in that, Different locking architectures are used on these multiple data edges.

3. The data clock tracking system as described in claim 1, characterized in that, The same locking architecture is used on these multiple data edges.

4. The data clock tracking system as described in claim 1, characterized in that, These multiple data sets have different data transformation densities.

5. The data clock tracking system as described in claim 1, characterized in that, These multiple data sets have the same data transformation density.

6. The data clock tracking system as described in claim 1, characterized in that, This binary phase detection circuit generates a binary phase detection signal and simultaneously provides the loop's integral gain and the loop's proportional gain.

7. The data clock tracking system as described in claim 1, characterized in that, The linear phase detection circuit also generates a linear phase detection signal simultaneously, while providing the loop's integral gain and the loop's proportional gain.

8. The data clock tracking system as described in claim 1, characterized in that, The data clock tracking system is a data clock recovery circuit, a phase-frequency tracking loop, and / or other circuits with phase tracking functionality.

9. The data clock tracking system as described in claim 1, characterized in that it can... include: The phase error judgment circuit is coupled to the linear phase detection circuit and the binary phase detection circuit respectively, and is used to determine whether the phase error is greater than a preset value. If the judgment result is yes, the binary phase detection circuit is activated at the same time to perform phase detection to provide additional loop gain.

10. The data clock tracking system as described in claim 1, characterized in that, This binary phase detection circuit can be synchronized at different data edges and is normally activated.

11. A method for improving phase error generation, applied to a data clock tracking system, characterized in that, The data clock tracking system includes a linear phase detection circuit and a binary phase detection circuit. The method for improving phase error generation includes the following steps: (a) Start the linear phase detection circuit to perform phase detection; (b) Activate the binary phase detection circuit at different data edges; as well as (c) The binary phase detection circuit assists the linear phase detection circuit in locking at different data edges; The phase error generation improvement method allocates the number of linear phase detection circuits and binary phase detection circuits at multiple data edges of multiple data sets. Wherein, when the phase error generation improvement method uses binary phase detection on the multiple data edges, the binary phase detection circuit performs phase locking to bypass the linear phase detection unit; In this phase error generation improvement method, when hybrid-mode phase detection is used on multiple data edges, phase locking is performed using the linear phase detection circuit. Once the phase error detected by the linear phase detection circuit is too large, the phase error generation improvement method simultaneously activates the binary phase detection circuit to assist loop locking, thereby providing additional phase detection gain.

12. The phase error generation improvement method as described in claim 11, characterized in that, Different locking architectures are used on these multiple data edges.

13. The phase error generation improvement method as described in claim 11, characterized in that, The same locking architecture is used on these multiple data edges.

14. The phase error generation improvement method as described in claim 11, characterized in that, These multiple data sets have different data transformation densities.

15. The phase error generation improvement method as described in claim 11, characterized in that, These multiple data sets have the same data transformation density.

16. The phase error generation improvement method as described in claim 11, characterized in that, This binary phase detection circuit generates a binary phase detection signal and simultaneously provides the loop's integral gain and the loop's proportional gain.

17. The phase error generation improvement method as described in claim 11, characterized in that, The linear phase detection circuit also generates a linear phase detection signal simultaneously, while providing the loop's integral gain and the loop's proportional gain.

18. The phase error generation improvement method as described in claim 11, characterized in that, The data clock tracking system is a data clock recovery circuit, a phase-frequency tracking loop, and / or other circuits with phase tracking functionality.

19. The phase error generation improvement method as described in claim 11, characterized in that, Step (b) can first determine whether the phase error at the data edge is greater than a preset value. If the determination result is yes, the binary phase detection circuit is started at the same time to perform phase detection in order to provide additional loop gain.

20. The phase error generation improvement method as described in claim 11, characterized in that, Step (b) can be used to synchronously and normally start the binary phase detection circuit at different data edges.

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