Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes a first transistor. The first transistor includes a gate (G1), a first electrode (E1) located on the gate (G1), a semiconductor material layer (SML) located on a side of the first electrode (E1) away from the gate (G1), a second electrode (E2) located on a side of the semiconductor material layer (SML) away from the first electrode (E1), an organic layer (OL) located on a side of the second electrode (E2) away from the semiconductor material layer (SML), and a third electrode (E3) located on a side of the organic layer (OL) away from the second electrode (E2). A normal projection of the second electrode (E2) on a base substrate (BS) at least partially overlaps with a normal projection of the organic layer (OL) on the base substrate (BS).

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, and in particular, to an array substrate and a display device. BACKGROUND

[0002] Display technology continues to evolve to achieve higher resolution, higher aperture ratio, and higher display quality. Related display panels (e.g., organic light-emitting diode display panels) have a highly complex layout. Vertical organic light-emitting transistor display panels have a relatively simple layout and have been variously applied in the display field, particularly in the field of high-resolution displays. SUMMARY

[0003] In one aspect, the present disclosure provides an array substrate comprising a plurality of sub-pixels, wherein each of the plurality of sub-pixels comprises a first transistor; wherein the first transistor comprises: a gate; a first electrode on the gate; a semiconductor material layer on a side of the first electrode distal to the gate; a second electrode on a side of the semiconductor material layer distal to the first electrode; an organic layer on a side of the second electrode distal to the semiconductor material layer; and a third electrode on a side of the organic layer distal to the second electrode; wherein a footprint of the second electrode on a base overlaps at least partially with a footprint of the organic layer on the base.

[0004] Optionally, a footprint of the second electrode on the base overlaps at least partially with a footprint of the semiconductor material layer on the base, and overlaps at least partially with a footprint of the first electrode on the base.

[0005] Optionally, a footprint of the gate on the base overlaps at least partially with a footprint of the semiconductor material layer on the base.

[0006] Optionally, the second electrode is a reflective electrode.

[0007] Optionally, the array substrate further comprises a capping layer on a side of the third electrode distal to the second electrode and configured to extract light reflected by the second electrode.

[0008] Optionally, the array substrate further comprises an encapsulation layer on a side of the third electrode distal to the second electrode, the encapsulation layer encapsulating the first transistor.

[0009] Optionally, the first transistor is a top-emission light-emitting transistor; the array substrate is a top-emission array substrate; and light emitted from the organic layer is emitted from the first transistor in a direction from the second electrode to the third electrode.

[0010] Optionally, the first transistor is a bottom-emitting light-emitting transistor; the array substrate is a bottom-emitting array substrate; and light emitted from the organic layer is emitted from the first transistor along the direction from the third electrode to the second electrode.

[0011] Optionally, each sub-pixel further includes a second transistor coupled to the second electrode; the second transistor is configured to connect or disconnect the second electrode from the voltage signal line; and the voltage signal line is a signal line configured to provide a signal to the third electrode.

[0012] Optionally, the second electrode is electrically connected to the semiconductor material layer and the organic layer, and is electrically isolated from the pixel defining layer.

[0013] Optionally, the second electrode is a substantially transparent electrode.

[0014] Optionally, the first electrode is a through electrode configured to allow an electric field generated by the gate to modulate the semiconductor material layer, which serves as at least a portion of the active layer of the first transistor.

[0015] Optionally, the first electrode comprises a carbon nanotube material.

[0016] Optionally, the first electrode includes a patterned electrode with multiple openings.

[0017] Optionally, the array substrate further includes a protective layer defining a plurality of first openings, wherein a corresponding first opening of the plurality of first openings accommodates the second electrode of a corresponding sub-pixel.

[0018] Optionally, the thickness of the protective layer is 10% to 80% of the thickness of the second electrode.

[0019] Optionally, the protective layer may include an organic topological insulating material.

[0020] Optionally, the array substrate further includes a pixel defining layer that defines a plurality of second openings, wherein a respective second opening of the plurality of second openings accommodates the semiconductor material layer of a respective sub-pixel and accommodates at least a portion of the second electrode of the respective sub-pixel.

[0021] Optionally, each sub-pixel also includes a third transistor configured to connect or disconnect the gate from a control signal line.

[0022] In another aspect, this disclosure provides a display device including the array substrate described herein. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2 This is a cross-sectional view of the stacked structure in each sub-pixel according to some embodiments of the present disclosure.

[0026] Figure 3 These are circuit diagrams of various sub-pixels according to some embodiments of this disclosure.

[0027] Figure 4A A planar diagram structure of at least a portion of the stacked structure in each sub-pixel according to some embodiments of the present disclosure is shown.

[0028] Figure 4B It shows Figure 4A The structure of the gate in each sub-pixel.

[0029] Figure 4C It shows Figure 4A The structure of the first electrode in each sub-pixel.

[0030] Figure 4D It shows Figure 4A The structure of the semiconductor material layer in each sub-pixel.

[0031] Figure 4E It shows Figure 4A The structure of the second electrode in each sub-pixel.

[0032] Figure 4F It shows Figure 4A The structure of organic layers in each sub-pixel.

[0033] Figure 4G It shows Figure 4A The structure of the third electrode in each sub-pixel.

[0034] Figure 5 It is a cross-sectional view of each sub-pixel according to some embodiments of this disclosure.

[0035] Figure 6 These are circuit diagrams of various sub-pixels according to some embodiments of this disclosure.

[0036] Figure 7 This is a cross-sectional view of the stacked structure in each sub-pixel according to some embodiments of the present disclosure.

[0037] Figure 8 It is a cross-sectional view of each sub-pixel according to some embodiments of this disclosure.

[0038] Figure 9 The structure of each first opening according to some embodiments of the present disclosure is shown.

[0039] Figure 10 The structure of a perforated electrode according to some embodiments of the present disclosure is shown.

[0040] Figure 11 This is a cross-sectional view of the stacked structure in each sub-pixel according to some embodiments of the present disclosure.

[0041] Figure 12 It is a cross-sectional view of each sub-pixel according to some embodiments of this disclosure.

[0042] Figure 13 This is a cross-sectional view of the stacked structure in each sub-pixel according to some embodiments of the present disclosure.

[0043] Figures 14A to 14E The process of manufacturing an array substrate according to some embodiments of the present disclosure is illustrated.

[0044] Figures 15A to 15B The process of manufacturing an array substrate according to some embodiments of the present disclosure is illustrated.

[0045] Figures 16A to 16E The process of manufacturing an array substrate according to some embodiments of the present disclosure is illustrated. Detailed Implementation

[0046] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0047] This disclosure particularly provides an array substrate and a display device that substantially overcomes one or more problems caused by limitations and disadvantages of related technologies. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, each sub-pixel of the plurality of sub-pixels includes a first transistor. In some embodiments, the first transistor includes: a gate; a first electrode located on the gate; a semiconductor material layer located on a side of the first electrode away from the gate; a second electrode located on a side of the semiconductor material layer away from the first electrode; an organic layer located on a side of the second electrode away from the semiconductor material layer; and a third electrode located on a side of the organic layer away from the second electrode. Optionally, the orthographic projection of the second electrode onto the substrate at least partially overlaps with the orthographic projection of the organic layer onto the substrate.

[0048] Figure 1This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 In some embodiments, the array substrate includes multiple sub-pixels, multiple data lines, multiple control signal lines, and multiple voltage signal lines. Each sub-pixel Sp is connected to the voltage signal line VSL, the data line DL, and the control signal line CSL.

[0049] Figure 2 This is a cross-sectional view of the stacking structure in each sub-pixel according to some embodiments of this disclosure. Reference Figure 2 In some embodiments, the array substrate includes a first transistor T1. In one example, the first transistor T1 is a vertical organic light-emitting transistor configured to emit light when driven. In some embodiments, the first transistor T1 has a stacked structure. In some embodiments, the stacked structure includes a gate G1; a first electrode E1 on the gate G1; a semiconductor material layer SML located on the side of the first electrode E1 away from the gate G1; a second electrode E2 located on the side of the semiconductor material layer SML away from the first electrode E1; an organic layer OL located on the side of the second electrode away from the semiconductor material layer; and a third electrode E3 located on the side of the organic layer OL away from the second electrode E2.

[0050] Various suitable semiconductor materials and various suitable manufacturing methods can be used to fabricate semiconductor material layers (SMLs). For example, semiconductor materials can be deposited on a substrate by inkjet printing, spin coating, vapor deposition (e.g., plasma-enhanced chemical vapor deposition), magnetron sputtering, or vacuum deposition. Examples of suitable semiconductor materials for fabricating SMLs include inorganic and organic semiconductor materials. Examples of organic semiconductor materials include organic polymer semiconductor materials and organic small molecule semiconductor materials, such as vanadium phthalocyanine oxide. Examples of inorganic semiconductor materials include amorphous silicon, polycrystalline silicon, and metal oxides. Examples of suitable metal oxide semiconductor materials include, but are not limited to, indium gallium zinc oxide, zinc oxide, gallium oxide, and indium oxide.

[0051] In some embodiments, the semiconductor material layer SML serves as at least a portion of the active layer of the first transistor T1, the first electrode E1 serves as at least a portion of the source of the first transistor T1, and the third electrode E3 serves as at least a portion of the drain of the first transistor T1.

[0052] Figure 3 These are circuit diagrams of various sub-pixels according to some embodiments of this disclosure. (See reference...) Figure 2 and Figure 3In some embodiments, the third electrode E3 is coupled to a voltage signal line VSL, which is configured to provide a voltage signal to the third electrode E3. In one example, the voltage signal provided to the third electrode E3 is a low voltage signal, such as a ground voltage signal. In some embodiments, the first electrode E1 is coupled to a data line DL, which is configured to provide a data signal to the first electrode E1. In some embodiments, the gate G1 is coupled to a control signal line, which is configured to provide a control signal to the gate G1. When the gate G1 receives a turn-on signal from the control signal line CSL, the first transistor T1 turns on, and the data signal applies a voltage across the first electrode E1 to the third electrode E3 to drive the first transistor T1 to emit light. Different voltage data signals correspond to different gray levels of the image displayed by the respective sub-pixels.

[0053] As described above, in some embodiments, the first transistor T1 includes an organic layer OL, which includes a light-emitting material. In some embodiments, the organic layer OL has a multilayer structure including a light-emitting layer. Optionally, the organic layer includes at least one of the following: an organic light-emitting layer; a hole transport layer; a hole injection layer; an electron transport layer; an electron injection layer; a hole blocking layer; or an electron blocking layer. Optionally, the organic layer includes one or more of a hole transport layer, a hole injection layer, a light-emitting layer (e.g., a red light-emitting layer, a blue light-emitting layer, and a green light-emitting layer), an electron transport layer, an electron injection layer, a charge generation layer, an electron blocking layer, a hole blocking layer, an undercoat layer (e.g., a red undercoat layer, a green undercoat layer, and a blue undercoat layer), and a capping layer. When the gate G1 receives a conduction signal from the control signal line CSL, the first transistor T1 is turned on, and the data signal drives the organic layer OL to emit light. Figure 2 In one example shown, the organic layer OL includes a hole transport layer (HTL), a light-emitting layer (EML), and an electron transport layer (ETL).

[0054] Various suitable conductive materials can be used to fabricate the second electrode E2, the third electrode E3, and the gate G1. For example, the conductive material can be deposited on a substrate by magnetron sputtering, vapor deposition (e.g., plasma-enhanced chemical vapor deposition), or vacuum deposition. Examples of suitable conductive materials for fabricating the second electrode E2, the third electrode E3, or the gate G1 include substantially transparent conductive materials (for fabricating substantially transparent second electrodes) and reflective conductive materials (for fabricating reflective second electrodes). Examples of suitable reflective conductive materials include, but are not limited to, silver, copper, aluminum, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, and tungsten. Examples of suitable substantially transparent conductive materials include substantially transparent metallic conductive materials and substantially transparent non-metallic conductive materials. Examples of substantially transparent non-metallic conductive materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide. Examples of substantially transparent metallic conductive materials include nano-silver.

[0055] Depending on the material used for the second electrode E2, the first transistor T1 can be a top-emitting light-emitting transistor (LED), a bottom-emitting LED, or a dual-emitting LED. In one example, the second electrode E2 is a reflective electrode, the third electrode E3 is a substantially transparent electrode, the first transistor T1 is a top-emitting LED, and the array substrate is a top-emitting array substrate. In another example, the second electrode E2 is a substantially transparent electrode, the third electrode E3 is a reflective electrode, the first transistor T1 is a bottom-emitting LED, and the array substrate is a bottom-emitting array substrate. In yet another example, the second electrode E2 is a substantially transparent electrode, the third electrode E3 is a substantially transparent electrode, the first transistor T1 is a dual-emitting LED, and the array substrate is a dual-emitting array substrate.

[0056] refer to Figure 2 The second electrode E2 separates the semiconductor material layer SML from the organic layer OL. Optionally, the second electrode E2 is in direct contact with the semiconductor material layer SML on one side and in direct contact with the organic layer OL on the other side.

[0057] refer to Figure 2 The first electrode E1 is located between the gate G1 and the semiconductor material layer SML. The first electrode E1 is spaced apart from the gate G1 by one or more insulating layers. Optionally, the first electrode E1 is in direct contact with the semiconductor material layer SML.

[0058] Various suitable conductive materials can be used to fabricate the first electrode E1. For example, conductive materials can be deposited on a substrate by spin coating, inkjet printing, magnetron sputtering, vapor deposition (e.g., plasma-enhanced chemical vapor deposition), or vacuum deposition. In some embodiments, the first electrode E1 is a perforated electrode that allows the electric field generated by the gate to modulate the semiconductor material layer SML, which serves as at least a portion of the active layer of the first transistor T1. The perforated electrode serves as at least a portion of the source of the first transistor T1. As used herein, the term "perforated" means that the first electrode E1 does not completely cover the underlying layer (e.g., Figure 2 The entire surface of the passivation layer (PVX) in the middle. Optionally, at least 1% (e.g., at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) of the lower layer is not covered by the perforated electrode (e.g., exposed).

[0059] Examples of suitable conductive materials for fabricating the first electrode E1 include conductive materials with a perforated network, such as nanotube materials and nanowire materials. Examples of materials with a perforated network include carbon nanotubes, graphene, metallic or non-metallic mesh electrodes, and metallic or non-metallic nanowires. In one example, the first electrode E1 is made of carbon nanotubes. The material with a perforated network in the first electrode E1 can have various suitable densities (e.g., corresponding to the percentage of exposed surface of the underlying layer described above) to allow the electric field generated by the gate to modulate the semiconductor material layer.

[0060] In some embodiments, the first electrode E1 is a patterned electrode having a plurality of openings. Examples of suitable conductive materials for fabricating the first electrode E1 include silver, copper, aluminum, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide. In one example, the conductive material is deposited on a substrate, followed by a patterning process using a photomask to create a perforated pattern. In one example, the first electrode E1 is a patterned electrode having a plurality of strips spaced apart by a plurality of slits. In another example, the first electrode E1 is a mesh electrode.

[0061] refer to Figure 2 The first transistor T1 has a storage capacitor in the stacked structure. The storage capacitor includes at least a first storage capacitor Cst1 formed between the gate G1 and the third electrode E3. Optionally, the storage capacitor further includes a second storage capacitor Cst2 formed between the first electrode E1 and the third electrode E3. In some embodiments, the storage capacitor may also include an additional component, such as a component between the second electrode E2 and the third electrode E3. Because the storage capacitor is inherently included in the stacked structure, a separate storage capacitor is not required. Due to this unique structure, the array substrate has an increased aperture ratio and lower power consumption.

[0062] Figure 4A A planar diagram structure of at least a portion of the stacked structure in each sub-pixel according to some embodiments of the present disclosure is shown. Figure 4B It shows Figure 4A The structure of the gate in each sub-pixel. Figure 4C It shows Figure 4A The structure of the first electrode in each sub-pixel. Figure 4D It shows Figure 4A The structure of the semiconductor material layer in each sub-pixel. Figure 4E It shows Figure 4A The structure of the second electrode in each sub-pixel. Figure 4F It shows Figure 4A The structure of organic layers in each sub-pixel. Figure 4G It showsFigure 4A The structure of the third electrode in each sub-pixel. (See reference) Figures 4A to 4G In some embodiments, the orthographic projection of the second electrode E2 onto the substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%) with the orthographic projection of the organic layer OL onto the substrate. Optionally, the orthographic projection of the organic layer OL onto the substrate covers the orthographic projection of the second electrode E2 onto the substrate.

[0063] In some embodiments, the orthographic projection of the second electrode E2 on the substrate at least partially overlaps with the orthographic projection of the semiconductor material layer SML on the substrate, and at least partially overlaps with the orthographic projection of the first electrode E1 on the substrate.

[0064] In some embodiments, the orthographic projection of the gate G1 onto the substrate overlaps at least partially (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%) with the orthographic projection of the semiconductor material layer SML onto the substrate. Increased overlap between the gate G1 and the semiconductor material layer SML results in an increase in the area of ​​the semiconductor material layer SML, which is modulated by the electric field generated by the gate. Optionally, the orthographic projection of the gate G1 onto the substrate covers the orthographic projection of the semiconductor material layer SML onto the substrate.

[0065] Figure 5 It is a cross-sectional view of each sub-pixel according to some embodiments of this disclosure. Figure 6 These are circuit diagrams of various sub-pixels according to some embodiments of this disclosure. Figure 7 This is a cross-sectional view of the stacking structure in each sub-pixel according to some embodiments of this disclosure. Reference Figures 5 to 7 In some embodiments, the second electrode E2 is a reflective electrode. For example... Figure 7 As shown, light emitted from the light-emitting layer EML is reflected by the second electrode E2, and the light reflected by the second electrode E2 is emitted from the top side of the first transistor. The third electrode E3 is a substantially transparent electrode. In some embodiments, the stacked structure further includes a capping layer CPL, which is configured to extract the light reflected by the second electrode E2. In one example, the capping layer CPL is made of a low-refractive-index material such as LiF. In another example, the capping layer CPL is made of a high-refractive-index material such as silicon nitride. In some embodiments, the stacked structure further includes a packaging layer EN that encapsulates the first transistor.

[0066] exist Figures 5 to 7 In the array substrate shown, the second electrode E2 is located between the semiconductor material layer SML and the organic layer OL. By having a reflective second electrode, the semiconductor material layer SML and the passivation layer PVX are excluded from the microcavity portion of the first transistor T1, thereby enhancing the luminous efficiency of the light-emitting transistor.

[0067] ReferenceFigures 5 to 7 In some embodiments, each sub-pixel further includes a second transistor T2 coupled to the second electrode E2. The second transistor T2 is configured to connect or disconnect the second electrode E2 from the voltage signal line VSL. In some embodiments, the voltage signal line VSL is a signal line configured to provide a signal (e.g., a low voltage signal) to the third electrode E3.

[0068] In the relevant array substrate, when the first transistor T1 is turned off, switching each sub-pixel to a dark state, residual charge carriers in the semiconductor material layer SML can still drive the light-emitting layer EML to emit a small amount of light. In some embodiments, when the first transistor T1 is turned off, the second electrode E2 is configured to receive a signal (e.g., a low-voltage signal) from the voltage signal line VSL. When the second electrode E2 is connected to the voltage signal line VSL, the light-emitting layer EML is prevented from emitting light, maintaining the dark state of each sub-pixel. The second electrode E2 is in direct contact with the semiconductor material layer SML. Residual charge carriers in the semiconductor material layer SML can be eliminated by having the second electrode E2 receive a low-voltage signal.

[0069] Optionally, the second transistor T2 is configured to electrically connect the second electrode E2 to the voltage signal line VSL when the gate G1 is configured to receive a cutoff signal. The second electrode E2 connects the semiconductor material layer SML to the voltage signal line VSL, thereby keeping each sub-pixel in a dark state.

[0070] Optionally, the second transistor T2 is configured to electrically disconnect the second electrode E2 from the voltage signal line VSL when the gate G1 is configured to receive a conduction signal. When the second electrode E2 is disconnected from the voltage signal line VSL, the second electrode E2, together with the first electrode E1, can be considered as part of the source of the first transistor T1.

[0071] refer to Figure 5In some embodiments, the array substrate includes a substrate BS; control signal lines CSL and voltage signal lines VSL on the substrate BS; a buffer layer BUF located on the side of the control signal lines CSL and voltage signal lines VSL away from the substrate BS; active layers of the second transistor T2 and the third transistor T3 located on the side of the buffer layer BUF away from the substrate BS; a first gate insulating layer GI1 located on the side of the active layers of the second transistor T2 and the third transistor T3 away from the buffer layer BUF; a first gate of the second transistor T2 and the third transistor T3 located on the side of the first gate insulating layer GI1 away from the buffer layer BUF; and a second gate insulating layer GI2. The first gates of the second transistor T2 and the third transistor T3 are located on the side away from the first gate insulating layer GI1; the data line DL and the second gates of the second transistor T2 and the third transistor T3 are located on the side away from the first gate insulating layer GI1; the interlayer dielectric layer ILD is located on the side away from the second gate insulating layer GI2 of the data line DL and the second gates of the second transistor T2 and the third transistor T3; the source and drain of the second transistor T2 and the third transistor T3 are located on the side away from the second gate insulating layer GI2 of the interlayer dielectric layer ILD; and the planarization layer PLN is located on the side away from the second transistor T2 and the third transistor T3. The source and drain of T3 are located on the side away from the interlayer dielectric layer (ILD); the gate G1 of the first transistor T1 is located on the side of the planarization layer (PLN) away from the ILD; the passivation layer (PVX) is located on the side of the gate G1 away from the PLN; the first electrode E1 is located on the side of the passivation layer (PVX) away from the PLN, and the first electrode E1 is connected to the data line through a via extending through the passivation layer (PVX), the planarization layer (PLN), and the ILD; the pixel defining layer (PDL) is located on the side of the passivation layer (PVX) away from the PLN, and the pixel defining layer (PDL) defines a plurality of first openings; the semiconductor material layer S The first electrode E1 is located on the side away from the passivation layer PVX, and the semiconductor material layer SML is housed in a plurality of first openings defined by the pixel defining layer PDL; the second electrode E2 is located on the side of the semiconductor material layer SML away from the first electrode E1, and the second electrode E2 is connected to the second transistor T2 through vias extending through the pixel defining layer PDL, the passivation layer PVX and the planarization layer PLN; the organic layer OL is located on the side of the second electrode E2 away from the semiconductor material layer SML; the third electrode E3 is located on the side of the organic layer OL away from the second electrode E2; and the encapsulation layer EN is located on the side of the third electrode E3 away from the organic layer OL.

[0072] exist Figure 5 and Figure 7 In the example shown, the first electrode E1 is made of carbon nanotubes.

[0073] In one example, the second electrode E2 has a thickness in the range of 30 nm to 200 nm.

[0074] In one example, the semiconductor material layer SML has a thickness ranging from 300 nm to 1000 nm.

[0075] In one example, the passivation layer PVX has a thickness ranging from 20 nm to 2000 nm.

[0076] Figure 8 These are cross-sectional views of individual sub-pixels according to some embodiments of this disclosure. (Refer to...) Figure 8 In some embodiments, the array substrate further includes a repellent protective layer (RPL). Optionally, the repellent protective layer RPL is located on the side of the pixel defining layer (PDL) away from the substrate (BS).

[0077] The protective layer RPL defines multiple first openings AP1. Figure 9 The structure of various first openings according to some embodiments of the present disclosure is shown. (Refer to...) Figure 8 and Figure 9 Each of the multiple first openings AP1 is configured to accommodate the second electrode E2 of the corresponding sub-pixel.

[0078] The protective layer RPL provides a clear boundary for the second electrode E2, especially when the second electrode E2 is made of a metal such as silver. The protective material in the protective layer RPL prevents electrode material from depositing on its surface. The desorption activation energy of the surface of the protective layer RPL relative to the electrode material of the second electrode E2 (metal, such as magnesium and silver) is greater than or equal to the diffusion activation energy of that surface. Optionally, the desorption activation energy of this surface is less than or equal to approximately 2.5 times the diffusion activation energy of the second electrode E2.

[0079] A pixel-defining layer (PDL) defines a plurality of second openings (AP2). Each of the plurality of second openings (AP2) is configured to accommodate a semiconductor material layer (SML) of the corresponding sub-pixel. Optionally, each second opening is further configured to accommodate at least a portion of a second electrode (E2) of the corresponding sub-pixel.

[0080] Various suitable protective materials and manufacturing methods can be used to fabricate protective layers (RPLs). For example, protective materials can be deposited on a substrate by inkjet printing, spin coating, vapor deposition (e.g., plasma-enhanced chemical vapor deposition), magnetron sputtering, or vacuum deposition. Examples of suitable protective materials include organic topological insulating materials. Topological insulating materials are materials that have an insulating body and conductive edges or surfaces. Examples of organic topological insulating materials include 2-(4-tert-butylphenyl)-5-(4-biphenyl)-1,3,4-oxadiazole, 2-(4-biphenyl)-5-phenyl-1,3,4-oxadiazole, 1,3-bis(N-carbazolyl)benzene, 3-(biphenyl-4-yl)-5-(4-tert-butylphenyl)-4-phenyl-4H-1,2,4-triazole, N,N'-bis-(1-naphthyl)–N,N'-bis-phenyl-(1,1'-biphenyl)-4,4'-diamine, 4-(1-naphthyl)-3,5-diphenyl-1 2,4-triazole, 3,5-bis(4-tert-butylphenyl)-4-phenyl-1,2,4-triazole, 2,5-bis(naphthylacetamide-1-yl)-1,3,4-oxadiazole, 2-(tert-butyl)-9,10-bis(2-naphthylacetamide)anthracene, 4,4'-bis(N-carbazolyl)-1,1'-biphenyl, bis(8-hydroxy-2-methylquinoline)-(4-phenylphenoxy)aluminum, 9-([1,1'-biphenyl]-3-yl)-3-bromo-9H-carbazole, and tris[2-phenylpyridine-C2,N]iridium(III).

[0081] In one example, the protective layer RPL has a thickness greater than 15 nm. The thickness of the protective layer RPL is less than the thickness of the second electrode E2. In another example, the thickness of the protective layer RPL is 10% to 80% of the thickness of the second electrode E2 (e.g., 10% to 20%, 20% to 30%, 30% to 40%, 40% to 50%, 50% to 60%, 60% to 70%, or 70% to 80%).

[0082] Reference Figures 5 to 8 In some embodiments, each sub-pixel further includes a third transistor T3, which is configured to connect or disconnect the gate G1 from the control signal line CSL. When the third transistor is turned on, the third transistor T3 is configured to allow a control signal to be passed from the control signal line CSL to the gate G1 to drive the first transistor T1 to emit light.

[0083] As described above, the first electrode E1 is a patterned electrode with multiple openings. Figure 10 The structure of a perforated electrode according to some embodiments of the present disclosure is shown. Reference Figure 10 In some embodiments, the first electrode E1 is a patterned electrode having multiple stripes spaced apart by multiple slits. The multiple slits allow the electric field generated by the gate to modulate the semiconductor material layer.

[0084] Figure 11 This is a cross-sectional view of the stacked structure in each sub-pixel according to some embodiments of the present disclosure. Figure 12 It is a cross-sectional view of each sub-pixel according to some embodiments of this disclosure. Figure 11 and Figure 12 The corresponding sub-pixel with a first electrode E1 serving as a patterned electrode is shown.

[0085] refer to Figure 12 In some embodiments, the array substrate does not include a second transistor. In some embodiments, the second electrode E2 is electrically connected to the semiconductor material layer SML and the organic layer OL, but is otherwise electrically isolated. For example, the second electrode E2 is only in contact with the pixel defining layer PDL made of an insulating material. In this embodiment, the second electrode E2 serves as part of the source of the first transistor T1. For example, the second electrode E2, together with the first electrode E1, can be considered as part of the source of the first transistor T1.

[0086] refer to Figure 11 and Figure 12 In some embodiments, the second electrode E2 is a reflective electrode. For example... Figure 11 As shown, light emitted from the light-emitting layer EML is reflected by the second electrode E2, and the light reflected by the second electrode E2 is emitted from the top side of the first transistor. The third electrode E3 is a substantially transparent electrode.

[0087] Figure 13 This is a cross-sectional view of the stacking structure in each sub-pixel according to some embodiments of this disclosure. Reference Figures 14A to 14E In some embodiments, the second electrode E2 is a substantially transparent electrode. In some embodiments, the third electrode E3 is a reflective electrode, the first electrode E1 is a substantially transparent electrode, and the gate G1 is a substantially transparent electrode. Light emitted from the light-emitting layer EML is reflected by the third electrode E3, and the light reflected by the third electrode E3 substantially transmits through the second electrode E2, the first electrode E1, and the gate G1, and is emitted from the bottom side of the first transistor. The array substrate is a bottom-emitting array substrate.

[0088] In another aspect, this disclosure provides a display device including an array substrate manufactured as described herein or by methods thereof, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc.

[0089] In another aspect, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of sub-pixels. In some embodiments, forming each sub-pixel of the plurality of sub-pixels includes forming a first transistor. In some embodiments, forming the first transistor includes: forming a gate; forming a first electrode located on the gate; forming a semiconductor material layer located on a side of the first electrode away from the gate; forming a second electrode located on a side of the semiconductor material layer away from the first electrode; forming an organic layer located on a side of the second electrode away from the semiconductor material layer; and forming a third electrode located on a side of the organic layer away from the second electrode. Optionally, the orthographic projection of the second electrode onto the substrate at least partially overlaps with the orthographic projection of the organic layer onto the substrate. Optionally, the orthographic projection of the second electrode onto the substrate at least partially overlaps with the orthographic projection of the semiconductor material layer onto the substrate, and at least partially overlaps with the orthographic projection of the first electrode onto the substrate. Optionally, the orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of the semiconductor material layer onto the substrate.

[0090] Figure 14A The process of manufacturing an array substrate according to some embodiments of the present disclosure is illustrated. (Refer to...) Figure 14B A backplane is formed, which includes a second transistor T2, a third transistor T3, a data line DL, a control signal line CSL, a voltage signal line VSL, and a gate G1. A first via v1 is formed extending through the passivation layer PVX, the planarization layer PLN, and the interlayer dielectric layer ILD, thereby exposing the surface of the data line DL.

[0091] Reference Figure 14C A first electrode E1 is formed, located on the side of the passivation layer PVX away from the planarization layer PLN. In one example, the first electrode E1 is formed by inkjet printing or spin-coating an electrode material (such as carbon nanotubes). The first electrode E1 extends through a first via to connect to the data line DL.

[0092] Reference Figure 14D A pixel defining layer PDL is formed on the side of the first electrode E1 and passivation layer PVX away from the planarization layer PLN. The pixel defining layer PDL is formed to define a plurality of second openings AP2. Next, a second via v2 extending through the pixel defining layer PDL, passivation layer PVX and planarization layer PLN is formed to expose the surface of the drain of the second transistor T2.

[0093] refer to Figure 14E A semiconductor material layer SML is formed in multiple second openings AP2. The semiconductor material layer SML can be formed by inkjet printing or vapor deposition.

[0094] Reference Figure 5A second electrode E2 is formed, located on one side of the semiconductor material layer SML and the pixel defining layer PDL. A portion of the second electrode E2 is accommodated in a corresponding second opening among a plurality of second openings AP2. The second electrode E2 extends through a second via v2 to connect to the drain of the second transistor T2.

[0095] Reference Figures 15A to 15B An organic layer OL is formed on the side of the second electrode E2 away from the semiconductor material layer SML; a third electrode E3 is formed on the side of the organic layer OL away from the second electrode E2; and an encapsulation layer EN is formed on the side of the third electrode E3 away from the organic layer OL.

[0096] Figure 15A The process of manufacturing an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figures 14A to 14D The semiconductor material layer SML is formed in multiple second openings AP2 (e.g. Figure 15B (As shown). For example, a protective layer RPL is formed on the side of the pixel-defining layer PDL away from the substrate BS by vapor deposition using a fine metal mask. The protective layer RPL is formed to define a plurality of first openings AP1.

[0097] Reference Figure 8 The second electrode E2 is formed, for example, by vapor deposition on one side of the semiconductor material layer SML and the pixel defining layer PDL. A portion of the second electrode E2 is housed in a corresponding second opening among a plurality of second openings AP2. The second electrode E2 extends through a second via v2 to connect to the drain of the second transistor T2.

[0098] Reference Figures 16A to 16E The organic layer OL is formed on the side of the second electrode E2 away from the semiconductor material layer SML; the third electrode E3 is formed on the side of the organic layer OL away from the second electrode E2; and the encapsulation layer EN is formed on the side of the third electrode E3 away from the organic layer OL.

[0099] Figure 16A The process of manufacturing an array substrate according to some embodiments of the present disclosure is illustrated. (Refer to...) Figure 16B A backplane is formed, which includes a second transistor T2, a third transistor T3, a data line DL, a control signal line CSL, a voltage signal line VSL, and a gate G1. A first via v1 is formed extending through the passivation layer PVX, the planarization layer PLN, and the interlayer dielectric layer ILD, thereby exposing the surface of the data line DL.

[0100] Reference Figure 16CThe first electrode E1 is formed on the side of the passivation layer PVX away from the planarization layer PLN. In one example, the first electrode E1 is formed by depositing electrode material on the passivation layer PVX and then patterning the electrode material to form a patterned electrode. The first electrode E1 extends through a first via to connect to the data line DL.

[0101] Reference Figure 16D A pixel defining layer PDL is formed on the side of the first electrode E1 and the passivation layer PVX away from the planarization layer PLN. The pixel defining layer PDL is formed to define a plurality of second openings AP2.

[0102] refer to Figure 16E The semiconductor material layer SML is formed in multiple second openings AP2. The semiconductor material layer SML can be formed by inkjet printing or vapor deposition.

[0103] Reference Figure 12 The second electrode E2 is formed on one side of the semiconductor material layer SML and the pixel defining layer PDL. A portion of the second electrode E2 is accommodated in a corresponding second opening among a plurality of second openings AP2.

[0104] Reference ​ An organic layer OL is formed on the side of the second electrode E2 away from the semiconductor material layer SML; a third electrode E3 is formed on the side of the organic layer OL away from the second electrode E2; and an encapsulation layer EN is formed on the side of the third electrode E3 away from the organic layer OL.

[0105] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising a plurality of sub-pixels, wherein, Each of the plurality of sub-pixels includes a first transistor; The first transistor includes: Gate; A first electrode is located on the gate; the first electrode is coupled to a data line; A semiconductor material layer is located on the side of the first electrode away from the gate. The second electrode is located on the side of the semiconductor material layer away from the first electrode; An organic layer, located on the side of the second electrode away from the semiconductor material layer; and A third electrode is located on the side of the organic layer away from the second electrode; the third electrode is coupled to a voltage signal line; the voltage signal line is a signal line configured to provide a low voltage signal to the third electrode, the low voltage signal being a ground voltage signal; Wherein, the orthogonal projection of the second electrode on the substrate at least partially overlaps with the orthogonal projection of the organic layer on the substrate; Each sub-pixel further includes a second transistor coupled to the second electrode; the second transistor is configured to connect or disconnect the second electrode from the voltage signal line. The second transistor is configured to electrically connect the second electrode to the voltage signal line when the gate is configured to receive a cutoff signal.

2. The array substrate according to claim 1, wherein, The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the semiconductor material layer on the substrate, and at least partially overlaps with the orthographic projection of the first electrode on the substrate.

3. The array substrate according to claim 1, wherein, The orthogonal projection of the gate onto the substrate at least partially overlaps with the orthogonal projection of the semiconductor material layer onto the substrate.

4. The array substrate according to any one of claims 1 to 3, wherein, The second electrode is a reflective electrode.

5. The array substrate according to any one of claims 1 to 3, further comprising a cover layer located on the side of the third electrode away from the second electrode, and configured to extract light reflected by the second electrode.

6. The array substrate according to any one of claims 1 to 3 further includes an encapsulation layer located on the side of the third electrode away from the second electrode, the encapsulation layer encapsulating the first transistor.

7. The array substrate according to any one of claims 1 to 3, wherein, The first transistor is a top-emitting light-emitting transistor; The array substrate is a top-emitting array substrate; and Light emitted from the organic layer travels along the direction from the second electrode to the third electrode from the first transistor.

8. The array substrate according to any one of claims 1 to 3, wherein, The first transistor is a bottom-emitting light-emitting transistor; The array substrate is a bottom-emitting array substrate; as well as Light emitted from the organic layer travels along the direction from the third electrode to the second electrode from the first transistor.

9. The array substrate according to any one of claims 1 to 3, wherein, The second electrode is electrically connected to the semiconductor material layer and the organic layer, and is electrically isolated from the pixel defining layer.

10. The array substrate according to any one of claims 1 to 3, wherein, The second electrode is a substantially transparent electrode.

11. The array substrate according to any one of claims 1 to 3, wherein, The first electrode is a through electrode, which is configured to allow an electric field generated by the gate to modulate the semiconductor material layer, which serves as at least a portion of the active layer of the first transistor.

12. The array substrate according to claim 11, wherein, The first electrode comprises carbon nanotube material.

13. The array substrate according to claim 11, wherein, The first electrode includes a patterned electrode with multiple openings.

14. The array substrate according to any one of claims 1 to 3, further comprising a protective layer defining a plurality of first openings, wherein a corresponding first opening of the plurality of first openings accommodates a second electrode of a corresponding sub-pixel.

15. The array substrate according to claim 14, wherein, The thickness of the protective layer is 10% to 80% of the thickness of the second electrode.

16. The array substrate according to claim 15, wherein, The protective layer comprises organic topological insulating material.

17. The array substrate according to any one of claims 1 to 3, further comprising a pixel defining layer defining a plurality of second openings, wherein a respective second opening of the plurality of second openings accommodates a semiconductor material layer of a respective sub-pixel and accommodates at least a portion of the second electrode of the respective sub-pixel.

18. The array substrate according to any one of claims 1 to 3, wherein, Each sub-pixel also includes a third transistor configured to connect or disconnect the gate from a control signal line.

19. A display device comprising an array substrate according to any one of claims 1 to 18.

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