Liquid ejection device and capacitive load driving circuit

Abstract

The present invention provides a liquid ejection device and a capacitive load driving circuit having improved waveform accuracy of a drive signal. In the capacitive load driving circuit that outputs a drive signal to a capacitive load, when switching from a first mode of outputting a level-converted amplified modulated signal in which a reference potential of an amplified modulated signal output by an amplifier circuit is set to a first potential to a second mode of outputting a level-converted amplified modulated signal in which the reference potential of the amplified modulated signal is level-converted to a second potential, the level conversion circuit performs a second control one or more times based on a voltage value of a capacitor of a bootstrap circuit detected by a voltage detection circuit, the second control being control of outputting a third gate signal for controlling a third transistor to be non-conductive and a fourth gate signal for controlling a fourth transistor to be conductive, and then outputting the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be non-conductive.

Description

Technical Field

[0001] The invention relates to a liquid ejecting device and a capacitive load driving circuit. Background Art

[0002] Among liquid ejecting devices that eject liquid to form images and documents on a medium, there is known a liquid ejecting device that uses a capacitive load such as a piezoelectric element. In such a liquid ejecting device, a capacitive load is provided corresponding to each of a plurality of nozzles that eject liquid, and is driven according to a drive signal. Therefore, by driving the capacitive load, liquid is ejected from the nozzle provided corresponding to the capacitive load. In order for such a capacitive load to operate, it is necessary to supply sufficient current. Therefore, a capacitive load driving circuit that outputs a drive signal to drive the capacitive load is constructed to include an amplifier circuit that amplifies a source signal that serves as a basis for the drive signal through an amplifier circuit.

[0003] In patent document 1, a driving circuit is disclosed, which is a driving circuit (capacitive load driving circuit) that outputs a driving signal to drive a piezoelectric element as one of the capacitive loads, and includes a class D amplifier circuit as an amplifier circuit, and reduces the power consumption associated with the output of the driving signal COM.

[0004] However, from the perspective of further improving the ejection accuracy of the liquid in the liquid ejection device, specifically, from the perspective of further improving the waveform accuracy of the driving signal output by the capacitive load driving circuit, the technology described in Patent Document 1 is not sufficient and there is room for improvement.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-124040 Summary of the Invention

[0006] One embodiment of the liquid ejection device involved in the present invention comprises: a liquid ejection head, which has a capacitive load driven by being supplied with a driving signal, and ejects liquid by being driven by the capacitive load; a capacitive load driving circuit, which outputs the driving signal, and the capacitive load driving circuit has: a modulation circuit, which outputs a modulation signal obtained by modulating a basic driving signal serving as a basis for the driving signal; an amplifier circuit, which outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit, which outputs a level-converted amplified modulation signal obtained by level-converting a reference potential of the amplified modulation signal to a second output point; a demodulation circuit, which outputs the driving signal by demodulating the level-converted amplified modulation signal, and the amplifier circuit includes: a first gate driver circuit, which outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor, one end of which is supplied with a first voltage signal and the other end of which is electrically connected to the first output point, and operates based on the first gate signal; a second transistor, one end of which is electrically connected to the first output point; an output point, and the other end of which is supplied with a second voltage signal, and operates based on the second gate signal; the level shifter circuit includes: a bootstrap circuit including a capacitor, inputted with a third voltage signal and the amplified modulation signal, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit detecting the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic drive signal; a third transistor having one end supplied with the fourth voltage signal and the other end electrically connected to the second output point, and operating based on the third gate signal; and a fourth transistor having one end electrically connected to the second output point, the other end supplied with the amplified modulation signal, and operating based on the fourth gate signal; the level shifter circuit including: a first mode in which the third transistor is controlled to be non-conductive and the fourth transistor is controlled to be conductive, thereby outputting the level-shifted amplified modulation signal with the reference potential of the amplified modulation signal set to a first potential;The second mode is a mode in which the level-converted amplified modulation signal is outputted by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby converting the reference potential level of the amplified modulation signal to a second potential higher than the first potential. When the first mode is changed to the second mode, the level conversion circuit performs a first control in which the second gate driver circuit outputs a signal for controlling the third transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and after the first control, the level shifter circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state.

[0007] One embodiment of the liquid ejection device involved in the present invention comprises: a liquid ejection head, which has a capacitive load driven by being supplied with a driving signal, and ejects liquid by being driven by the capacitive load; a capacitive load driving circuit, which outputs the driving signal, and the capacitive load driving circuit has: a modulation circuit, which outputs a modulation signal obtained by modulating a basic driving signal serving as a basis for the driving signal; an amplifier circuit, which outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit, which outputs a level-converted amplified modulation signal obtained by level-converting a reference potential of the amplified modulation signal to a second output point; a demodulation circuit, which outputs the driving signal by demodulating the level-converted amplified modulation signal, and the amplifier circuit includes: a first gate driver circuit, which outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor, one end of which is supplied with a first voltage signal and the other end of which is electrically connected to the first output point, and operates based on the first gate signal; a second transistor, one end of which is electrically connected to the first output point; an output point, and the other end of which is supplied with a second voltage signal, and operates based on the second gate signal; the level shifter circuit includes: a bootstrap circuit including a capacitor, inputted with a third voltage signal and the amplified modulation signal, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit detecting the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic drive signal; a third transistor having one end supplied with the fourth voltage signal and the other end electrically connected to the second output point, and operating based on the third gate signal; and a fourth transistor having one end electrically connected to the second output point, the other end supplied with the amplified modulation signal, and operating based on the fourth gate signal; the level shifter circuit including: a first mode in which the third transistor is controlled to be non-conductive and the fourth transistor is controlled to be conductive, thereby outputting the level-shifted amplified modulation signal with the reference potential of the amplified modulation signal set to a first potential;The second mode is a mode in which the level-converted amplified modulation signal is outputted by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby converting the reference potential level of the amplified modulation signal to a second potential higher than the first potential. When the second mode is changed to the first mode, the level conversion circuit performs a third control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, starting from the state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and after the third control, the level shifter circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the fourth control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state.

[0008] One embodiment of the capacitive load driving circuit of the present invention is a capacitive load driving circuit that outputs a driving signal to a liquid ejecting head, wherein the liquid ejecting head has a capacitive load driven by being supplied with a driving signal and ejects liquid by the driving of the capacitive load, and the capacitive load driving circuit has: a modulation circuit that outputs a modulation signal obtained by modulating a basic driving signal that serves as a basis for the driving signal; an amplifier circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting a reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the driving signal by demodulating the level-converted amplified modulation signal, and the amplifier circuit includes: a first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor, one end of which is supplied with a first voltage signal and the other end is electrically connected to the first output point, and operates based on the first gate signal; a second transistor, one end of which is electrically connected to the first output point; The level shifter circuit is electrically connected to an output point and supplied with a second voltage signal at the other end, and operates based on the second gate signal. The level shifter circuit includes: a bootstrap circuit including a capacitor, receiving a third voltage signal and the amplified modulation signal as inputs, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit detecting the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic drive signal; a third transistor having one end supplied with the fourth voltage signal and the other end electrically connected to the second output point, and operating based on the third gate signal; and a fourth transistor having one end electrically connected to the second output point and supplied with the amplified modulation signal at the other end, and operating based on the fourth gate signal. The level shifter circuit includes: a first mode in which the third transistor is controlled to be non-conductive and the fourth transistor is controlled to be conductive, thereby outputting the level-shifted amplified modulation signal with the reference potential of the amplified modulation signal set to a first potential.The second mode is a mode in which the level-converted amplified modulation signal is outputted by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby converting the reference potential level of the amplified modulation signal to a second potential higher than the first potential. When the first mode is changed to the second mode, the level conversion circuit performs a first control in which the second gate driver circuit outputs a signal for controlling the third transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and after the first control, the level shifter circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state.

[0009] One embodiment of the capacitive load driving circuit of the present invention is a capacitive load driving circuit that outputs a driving signal to a liquid ejecting head, wherein the liquid ejecting head has a capacitive load driven by being supplied with a driving signal and ejects liquid by the driving of the capacitive load, and the capacitive load driving circuit has: a modulation circuit that outputs a modulation signal obtained by modulating a basic driving signal that serves as a basis for the driving signal; an amplifier circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting a reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the driving signal by demodulating the level-converted amplified modulation signal, and the amplifier circuit includes: a first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor, one end of which is supplied with a first voltage signal and the other end is electrically connected to the first output point, and operates based on the first gate signal; a second transistor, one end of which is electrically connected to the first output point; The level shifter circuit is electrically connected to an output point and supplied with a second voltage signal at the other end, and operates based on the second gate signal. The level shifter circuit includes: a bootstrap circuit including a capacitor, receiving a third voltage signal and the amplified modulation signal as inputs, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit detecting the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic drive signal; a third transistor having one end supplied with the fourth voltage signal and the other end electrically connected to the second output point, and operating based on the third gate signal; and a fourth transistor having one end electrically connected to the second output point and supplied with the amplified modulation signal at the other end, and operating based on the fourth gate signal. The level shifter circuit includes: a first mode in which the third transistor is controlled to be non-conductive and the fourth transistor is controlled to be conductive, thereby outputting the level-shifted amplified modulation signal with the reference potential of the amplified modulation signal set to a first potential.The second mode is a mode in which the level-converted amplified modulation signal is outputted by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby converting the reference potential level of the amplified modulation signal to a second potential higher than the first potential. When the second mode is changed to the first mode, the level conversion circuit performs a third control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, starting from the state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and after the third control, the level conversion circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the fourth control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A diagram showing an example of the structure of a liquid ejecting device.

[0011] Figure 2 A diagram showing the functional structure of a liquid ejecting device.

[0012] Figure 3 A diagram showing an example of the arrangement of a plurality of ejection parts in a head unit.

[0013] Figure 4 This is a diagram showing an example of the structure of the ejection portion.

[0014] Figure 5 3 is a diagram showing an example of the signal waveform of the drive signal COM.

[0015] Figure 6 A diagram showing an example of the functional structure of a driving circuit.

[0016] Figure 7 A diagram for explaining the operation of the driving circuit.

[0017] Figure 8 1 is a diagram showing an example of a counter pulse when the second mode is shifted to the first mode and an example of the operations of the transistors M3 and M4 based on the counter pulse.

[0018] Figure 9 1 and 2 are diagrams showing an example of a counter pulse when the first mode is switched to the second mode and an example of the operation of the transistors M3 and M4 based on the counter pulse. DETAILED DESCRIPTION

[0019] The following drawings illustrate preferred embodiments of the present invention. The drawings are provided for ease of explanation. The embodiments described below are not intended to unduly limit the scope of the present invention as set forth in the claims. Furthermore, not all of the structures described below are necessarily essential components of the present invention.

[0020] In the following description, a consumer inkjet printer is used as an example of the liquid ejection device involved in the present invention. However, the liquid ejection device is not limited to inkjet printers. Examples of such devices include color material ejection devices used in the manufacture of color filters for liquid crystal displays, electrode material ejection devices used in the formation of electrodes for organic EL (electroluminescence) displays and surface-emitting displays, and bio-organic material ejection devices used in the manufacture of biochips.

[0021] 1. Overview of Liquid Dispensing Device

[0022] Figure 1 FIG. 1 is a diagram showing an example of the structure of the liquid ejecting device 1. Figure 1 As shown, the liquid ejecting apparatus 1 includes a movable body 2 and a moving unit 3 that moves the movable body 2 back and forth in a main scanning direction.

[0023] The moving unit 3 includes a carriage motor 31 serving as a driving source for reciprocating movement along the main scanning direction of the movable body 2 , a carriage guide shaft 32 fixed at both ends, and a timing belt 33 extending substantially parallel to the carriage guide shaft 32 and driven by the carriage motor 31 .

[0024] The movable body 2 has a carriage 24. The carriage 24 is supported on a carriage guide shaft 32 so as to be able to move back and forth freely, and is fixed to a portion of a timing belt 33. Moreover, by utilizing the carriage motor 31 to move the timing belt 33 forward and backward, the movable body 2 having the carriage 24 is guided by the carriage guide shaft 32 and moves back and forth. In addition, the head unit 20 is located on a portion of the movable body 2 that is opposite to the medium P. That is, the head unit 20 is mounted on the carriage 24. Many nozzles that eject ink as a liquid are located on the surface of the head unit 20 that is opposite to the medium P. In addition, various control signals for controlling the operation of the head unit 20 are supplied to the head unit 20 via a cable 190. As such a cable 190, a flexible flat cable or the like that can slide to follow the back and forth movement of the movable body 2 can be used.

[0025] The liquid ejecting device 1 also includes a transport unit 4 that transports the medium P along a transport direction onto a platen 40. The transport unit 4 includes a transport motor 41 that serves as a drive source for transporting the medium P, and a transport roller 42 that rotates with the driving force of the transport motor 41 to transport the medium P along the transport direction.

[0026] In the liquid ejection device 1 configured as described above, the head unit 20 ejects ink onto the medium P in synchronization with the timing at which the medium P is transported by the transport unit 4. Thus, the ink ejected by the head unit 20 lands at a desired position on the medium P, thereby forming a desired image and text on the surface of the medium P.

[0027] Next, the functional structure of the liquid ejecting device 1 will be described. Figure 2 1 is a diagram showing the functional structure of the liquid ejection device 1. Figure 2 As shown, the liquid ejecting device 1 includes a control unit 10, a head unit 20, a moving unit 3, a transport unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0028] The control unit 10 includes a power supply circuit 11 , a control unit 100 , and a drive circuit 50 .

[0029] The power supply circuit 11 generates voltage signals VHV1, VHV2, and VDD of predetermined voltage values ​​from a commercial AC power source supplied from outside the liquid ejection device 1, and outputs these voltage signals to various components of the liquid ejection device 1. Here, the voltage signals VHV1 and VHV2 output by the power supply circuit 11 are, for example, 25V DC voltages, and the voltage signal VDD is, for example, 3.3V DC voltages. Such a power supply circuit 11 may also be configured to include, for example, an AC / DC converter that generates a DC voltage of a predetermined voltage value from a commercial AC power source, and a DC / DC converter that converts the voltage value of the generated DC voltage to generate the voltage signals VHV1, VHV2, and VDD. Furthermore, in addition to outputting the voltage signals VHV1, VHV2, and VDD, the power supply circuit 11 may also output DC voltages of varying voltage values. Here, in the following description, the voltage value of the voltage signal VHV1 may be referred to as voltage vhv1 , the voltage value of the voltage signal VHV2 may be referred to as voltage vhv2 , and the voltage value of the voltage signal VDD may be referred to as voltage vdd.

[0030] The control unit 100 is supplied with image data from an external device (not shown) provided outside the liquid ejection apparatus 1, such as a host computer. The control unit 100 applies various image processing and the like to the supplied image data to generate various control signals for controlling various components of the liquid ejection apparatus 1, and outputs the signals to the corresponding components.

[0031] Specifically, the control unit 100 generates a control signal Ctrl1 based on the image data to control the reciprocating movement of the movable body 2 and outputs it to the carriage motor 31 included in the movable unit 3. Furthermore, the control unit 100 generates a control signal Ctrl2 based on the image data to control the conveyance of the medium P and outputs it to the conveyance motor 41 included in the conveyance unit 4. Thus, the reciprocating movement of the movable body 2 in the main scanning direction and the conveyance of the medium P in the conveyance direction are controlled by the control unit 100. Specifically, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the conveyance of the medium P. This allows the ink to land at a desired location on the medium P, thereby forming a desired image or text on the medium P.

[0032] In addition, the control unit 100 can also convert the control signal Ctrl1 used to control the reciprocating movement of the movable body 2 into a signal through an unillustrated slide motor driver and then supply it to the moving unit 3. Similarly, the control unit 100 can also convert the control signal Ctrl2 used to control the conveyance of the medium P into a signal through an unillustrated conveying motor driver and then supply it to the conveying unit 4.

[0033] In addition, the control unit 100 outputs a basic drive signal dA to the drive circuit 50. The basic drive signal dA output by the control unit 100 is a signal that includes information that specifies the signal waveform of the drive signal COM supplied to the head unit 20, for example, a digital signal. The drive circuit 50 generates the drive signal COM by converting the input digital basic drive signal dA into an analog signal and amplifying the converted signal. The drive circuit 50 then supplies the generated drive signal COM to the head unit 20. The structure and operation of the drive circuit 50 will be described in detail later.

[0034] The control unit 100 also generates a drive data signal DATA for controlling the operation of the head unit 20 and outputs it to the head unit 20. The head unit 20 includes a selection control unit 210, a plurality of selection units 230, and a P121. Furthermore, the liquid ejection head 21 includes a plurality of ejection units 600 each including a piezoelectric element 60. Each of the plurality of selection units 230 is provided so as to correspond to a piezoelectric element 60 included in each of the plurality of ejection units 600 of the liquid ejection head 21.

[0035] The drive data signal DATA is input to the selection control unit 210. The selection control unit 210 generates a selection signal S based on the input drive data signal DATA and outputs it to each of the multiple selection units 230. The selection signal S indicates to each of the selection units 230 whether the drive signal COM should be selected or not. The drive signal COM and the corresponding selection signal S are input to each of the multiple selection units 230. Each of the multiple selection units 230 generates and outputs the drive signal VOUT by setting the drive signal COM to be selected or not based on the input selection signal S. That is, each of the multiple selection units 230 generates a drive signal VOUT based on the drive signal COM and supplies it to one end of the piezoelectric element 60 included in the corresponding ejection unit 600 included in the liquid ejection head 21.

[0036] Furthermore, a reference voltage signal VBS is commonly supplied to the other ends of the piezoelectric elements 60 included in the plurality of ejection units 600. The reference voltage signal VBS serves as a reference potential for driving the piezoelectric elements 60 driven by the drive signal VOUT, and is a signal having a constant potential such as 5.5V, 6V, or ground potential.

[0037] The piezoelectric elements 60 are arranged so as to correspond to each of the multiple nozzles in the head unit 20. The piezoelectric elements 60 are driven based on the potential difference between a drive signal VOUT supplied to one end and a reference voltage signal VBS supplied to the other end. As a result, the ejection unit 600, which includes the piezoelectric elements 60, ejects an amount of ink corresponding to the amount by which the piezoelectric elements 60 are driven.

[0038] In addition, although Figure 2 The figure shows a case where the head unit 20 has one liquid ejecting head 21, but the number of liquid ejecting heads 21 of the head unit 20 is not limited to one. The head unit 20 may have multiple liquid ejecting heads 21 depending on the type and amount of ink ejected.

[0039] As described above, the liquid ejection device 1 in this embodiment includes a liquid ejection head 21 and a driving circuit 50, wherein the liquid ejection head 21 has a plurality of piezoelectric elements 60 that are driven by being supplied with driving signals COM and VOUT, and ink as an example of liquid is ejected by driving the plurality of piezoelectric elements 60, and the driving circuit 50 outputs the driving signal COM.

[0040] 2. Structure of the ejection part

[0041] Next, an example of the structure of the plurality of ejection portions 600 included in the liquid ejection head 21 and the arrangement of the plurality of ejection portions 600 in the head unit 20 will be described. Figure 3 FIG. 1 is a diagram showing an example of the arrangement of the plurality of ejection parts 600 in the head unit 20. Figure 3 In FIG. 1 , a case where the head unit 20 includes four liquid ejection heads 21 is illustrated.

[0042] like Figure 3 As shown, the four liquid ejection heads 21 each have a plurality of ejection sections 600 arranged in a row in one direction. That is, the liquid ejection head 21 includes a nozzle row L in which the nozzles 651 described later included in the ejection section 600 are arranged in one direction. In addition, the liquid ejection heads 21 are arranged in a direction intersecting the nozzle row L in the head unit 20. That is, the same number of nozzle rows L as the number of liquid ejection heads 21 are formed in the head unit 20. In addition, the arrangement of the nozzles 651 in the nozzle row L of the liquid ejection head 21 is not limited to one row. For example, the nozzles 651 may be arranged in a staggered manner in such a manner that the positions of the even-numbered nozzles 651 and the odd-numbered nozzles 651 are different from those of the odd-numbered nozzles 651. Alternatively, one nozzle row L may be formed by arranging the plurality of nozzles 651 in parallel in two or more rows in the liquid ejection head 21.

[0043] Next, an example of the structure of the ejection portion 600 will be described. Figure 4 FIG. 6 is a diagram showing an example of the structure of the ejection portion 600. Figure 4 As shown, the ejection unit 600 includes a piezoelectric element 60, a vibration plate 621, a chamber 631, and a nozzle 651. The vibration plate 621 is accompanied by Figure 4 The vibrating plate 621 is driven by the piezoelectric element 60 provided on the upper surface of the cavity 631 and is displaced. The vibrating plate 621 functions as a diaphragm that enlarges or reduces the internal volume of the cavity 631. The interior of the cavity 631 is filled with ink. The cavity 631 functions as a pressure chamber whose internal volume changes due to the displacement of the vibrating plate 621 caused by the drive of the piezoelectric element 60. The nozzle 651 is an opening portion formed on the nozzle plate 632 and connected to the cavity 631. Moreover, as the internal volume of the cavity 631 changes, the ink stored in the interior of the cavity 631 is ejected from the nozzle 651.

[0044] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is clamped by a pair of electrodes 611 and 612. The piezoelectric body 601 of this structure causes the electrodes 611 and 612 and the center portion of the vibration plate 621 to be oriented relative to the end portions according to the potential difference between the electrodes 611 and 612. Figure 4 Deflection in the up and down directions.

[0045] Specifically, a drive signal VOUT is supplied to electrode 611 at one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to electrode 612 at the other end. Furthermore, when the piezoelectric element 60 is driven upward in response to changes in the voltage value of the drive signal VOUT, the vibration plate 621 displaces upward. As a result, the internal volume of the cavity 631 expands. Therefore, the ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven downward in response to changes in the voltage value of the drive signal VOUT, the vibration plate 621 displaces downward. As a result, the internal volume of the cavity 631 decreases. Therefore, an amount of ink corresponding to the degree of reduction in the internal volume of the cavity 631 is ejected from the nozzle 651.

[0046] As described above, the liquid ejection head 21 includes the piezoelectric element 60 and ejects ink onto the medium P by driving the piezoelectric element 60. The ejection unit 600 and the piezoelectric element 60 included in the ejection unit 600 are not limited to the structure shown in the figure, and any structure is sufficient as long as the piezoelectric element 60 can be driven based on the drive signal VOUT and ink can be ejected from the corresponding nozzle 651 by the drive of the piezoelectric element 60.

[0047] 3. Structure and operation of the driving circuit

[0048] As described above, the piezoelectric element 60 included in the ejection section 600 of the liquid ejection head 21 is driven by the drive signal VOUT based on the drive signal COM output by the drive circuit 50. Furthermore, the piezoelectric element 60 is driven, so that ink is ejected from the ejection section 600 including the piezoelectric element 60. Next, the structure and operation of the drive circuit 50 that outputs the drive signal COM, which serves as the basis for the drive signal VOUT that drives the piezoelectric element 60, will be described.

[0049] 3.1 Signal waveform of driving signal COM

[0050] When describing the configuration and operation of the drive circuit 50 , first, an example of the signal waveform of the drive signal COM output by the drive circuit 50 will be described. Figure 5 FIG. 1 is a diagram showing an example of a signal waveform of the driving signal COM. Figure 5 As shown, the drive signal COM includes a trapezoidal waveform Adp in each cycle T. The trapezoidal waveform Adp includes a period in which the voltage vc is constant, a period in which the voltage vc is constant followed by a period in which the voltage vb is constant, a period in which the voltage vb is constant, a period in which the voltage vt is constant, a period in which the voltage vc is constant, and a period in which the voltage vt is constant followed by a period in which the voltage vc is constant. In other words, the drive signal COM includes a trapezoidal waveform Adp whose voltage value varies between the voltage vt and the voltage vb, and which starts and ends at the voltage vc within the cycle T.

[0051] The voltage vc corresponds to a potential that serves as a reference for the displacement of the piezoelectric element 60. When the voltage value of the driving signal COM supplied to the piezoelectric element 60 changes from the voltage vc to the voltage vb, the piezoelectric element 60 is displaced. Figure 4 As a result, the vibration plate 621 moves in the upward direction. Figure 4 Furthermore, when the vibration plate 621 moves Figure 4 When the piezoelectric element 60 is displaced in the upward direction shown in FIG. 1 , the internal volume of the cavity 631 is expanded, so that the ink is introduced from the reservoir 641 into the cavity 631. Thereafter, the voltage value of the driving signal COM supplied to the piezoelectric element 60 changes from the voltage vb to the voltage vt, so that the piezoelectric element 60 moves in the upward direction. Figure 4 As a result, the vibration plate 621 moves in the downward direction. Figure 4 Furthermore, when the vibration plate 621 moves Figure 4When the cavity 631 is displaced in the downward direction shown, the internal volume of the cavity 631 is reduced, so that the ink stored in the cavity 631 is ejected from the nozzle 651 .

[0052] Furthermore, the ink near the nozzle 651 or the vibration plate 621 may continue to vibrate for a fixed period after the ink is ejected from the nozzle 651 by driving the piezoelectric element 60. The period during which the voltage vc included in the driving signal COM is constant also serves as a period for stabilizing the vibration that does not contribute to the ejection of the ink or the vibration plate 621.

[0053] Here, Figure 5 The signal waveform of the driving signal COM shown is an example and is not limited to this. It can also include signal waveforms of various shapes corresponding to the physical properties of the ink ejected by the liquid ejection head 21, the length of the period T of the driving signal COM, the conveying speed of the medium P, etc.

[0054] 3.2 Structure and operation of the drive signal output circuit

[0055] Next, the configuration and operation of the drive circuit 50 that generates and outputs the drive signal COM will be described. Figure 6 FIG. 5 is a diagram showing an example of the functional structure of the driving circuit 50. Figure 6 As shown, the driving circuit 50 includes a basic driving signal output circuit 510 , an adder 511 , a modulation circuit 520 , an inverter 521 , an amplifier circuit 550 , a demodulation circuit 560 , a feedback circuit 570 , and a level conversion circuit 70 .

[0056] The basic drive signal output circuit 510 receives a digital basic drive signal dA from the control unit 100. The basic drive signal output circuit 510 performs digital-to-analog conversion on the input basic drive signal dA and outputs the converted analog signal as the basic drive signal aA. That is, the basic drive signal output circuit 510 includes a D / A (Digital to Analog Converter) converter. The voltage amplitude of the basic drive signal aA is, for example, 1 to 2V. The drive circuit 50 outputs the amplified version of the basic drive signal aA as the drive signal COM. In other words, the basic drive signal aA corresponds to the target signal of the drive signal COM before amplification.

[0057] The basic drive signal aA is input to the positive input terminal of the adder 511. The feedback signal VFB, which is the result of feedback of the drive signal COM via the feedback circuit 570 described later, is input to the negative input terminal of the adder 511. The adder 511 then subtracts the feedback signal VFB input to the negative input terminal from the basic drive signal aA input to the positive input terminal, and outputs the resulting signal to the modulation circuit 520.

[0058] The modulation circuit 520 generates a modulation signal MS by pulse-modulating the signal output from the adder 511. The modulation circuit 520 then outputs the generated modulation signal MS to the amplifier circuit 550. The modulation circuit 520 generates a pulse density modulated signal (PDM signal) by modulating the signal output from the adder 511 using a pulse density modulation (PDM) method, and outputs this PDM signal as the modulation signal MS to the amplifier circuit 550. Specifically, the modulation circuit 520 outputs the modulation signal MS by modulating the base drive signal aA corresponding to the base drive signal dA, which serves as the basis for the drive signal COM. Specifically, the modulation circuit 520 compares the voltage value of the base drive signal aA with a predetermined reference voltage, vref. Then, the modulation circuit 520 generates and outputs the following modulation signal MS, which is a modulation signal that becomes an H level when the voltage value of the input basic drive signal aA is greater than the voltage vref, and becomes an L level when the voltage value of the input basic drive signal aA is less than the voltage vref.

[0059] The amplifier circuit 550 includes a gate driver circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. The amplifier circuit 550 generates an amplified modulation signal AMS1 by amplifying the modulation signal MS, and outputs the amplified modulation signal AMS1 from a midpoint CP1.

[0060] Specifically, the modulation signal MS is input to the gate driver 531 included in the gate driver circuit 530. The gate driver 531 generates and outputs a gate signal HGD1 obtained by level-converting the input modulation signal MS. Furthermore, the modulation signal MS is inverted in logic level by the inverter 521 and then input to the gate driver 532 included in the gate driver circuit 530. The gate driver 532 generates and outputs a gate signal LGD1 obtained by level-converting the signal obtained by inverting the logic level of the input modulation signal MS.

[0061] Transistors M1 and M2 are both composed of N-channel MOS-FETs (Metal Oxide Semiconductor Field-Effect Transistors). A gate signal HGD1 output by gate driver 531 is input to the gate terminal of transistor M1. A voltage signal VHV1 is supplied to the drain terminal of transistor M1. The source terminal of transistor M1 is electrically connected to midpoint CP1. Furthermore, a gate signal LGD1 output by gate driver 532 is input to the gate terminal of transistor M2. The drain terminal of transistor M2 is electrically connected to midpoint CP1. A ground potential is supplied to the source terminal of transistor M2. Furthermore, by operating transistor M1 based on gate signal HGD1 and transistor M2 based on gate signal LGD1, an amplified modulation signal AMS1 is generated at midpoint CP1 connecting transistors M1 and M2, resulting from amplifying modulation signal MS with a voltage vhv1 having the voltage value of voltage signal VHV1.

[0062] Here, the operation of gate driver circuit 530, which outputs gate signal HGD1 and gate signal LGD1 based on modulation signal MS, is described. Gate driver circuit 530 includes gate drivers 531 and 532. As described above, modulation signal MS is input to gate driver 531, and a signal obtained by inverting the logic level of modulation signal MS via inverter 521 is input to gate driver 532. In other words, the signal input to gate driver 531 and the signal input to gate driver 532 are exclusively at the H level. Here, "exclusively at the H level" includes the case where an H-level signal is not simultaneously input to gate driver 531 and gate driver 532. This does not exclude the case where an L-level signal is simultaneously input to gate driver 531 and gate driver 532.

[0063] The low-potential-side power supply terminal of the gate driver 531 is electrically connected to the midpoint CP1. Therefore, the signal generated at the midpoint CP1 is supplied to the low-potential-side power supply terminal of the gate driver 531 as the voltage signal HVS1. Furthermore, the high-potential-side power supply terminal of the gate driver 531 is electrically connected to the cathode terminal of the diode D1 and one end of the capacitor C1. Furthermore, the anode terminal of the diode D1 is supplied with the voltage vm, and the other end of the capacitor C1 is electrically connected to the midpoint CP1. In other words, the diode D1 and the capacitor C1 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential-side power supply terminal of the gate driver 531. Therefore, the high-potential-side power supply terminal of the gate driver 531 is supplied with the voltage signal HVD1, which is a voltage value increased by the voltage vm compared to the voltage signal HVS1 input to the low-potential-side power supply terminal of the gate driver 531.

[0064] Therefore, when the modulation signal MS of the H level is input to the gate driver 531, the gate driver 531 will output the gate signal HGD1 based on the voltage value of the voltage signal HVD1 increased by the voltage vm compared to the voltage value of the midpoint CP1, and when the modulation signal MS of the L level is input to the gate driver 531, the gate driver 531 will output the gate signal HGD1 based on the voltage value of the midpoint CP1, that is, the voltage value of the voltage signal HVS1.

[0065] Here, voltage vm is a voltage value capable of driving transistors M1, M2 and transistors M3, M4 described later, and is, for example, a DC voltage of 7.5 V. Such voltage vm is generated, for example, by stepping down or stepping up voltage signals VHV1, VHV2, and VDD output by power supply circuit 11.

[0066] A ground potential signal is supplied as the voltage signal LVS1 to the low-potential power supply terminal of the gate driver 532. Furthermore, a voltage vm is supplied as the voltage signal LVD1 to the high-potential power supply terminal of the gate driver 532. Therefore, when the gate driver 532 receives an H-level signal obtained by inverting the logic level of the L-level modulation signal MS via the inverter 521, the gate driver 532 outputs a gate signal LGD1 based on the voltage value of the voltage signal LVD1 of the voltage vm. Furthermore, when the gate driver 532 receives an L-level signal obtained by inverting the logic level of the H-level modulation signal MS via the inverter 521, the gate driver 532 outputs a gate signal LGD based on the voltage value of the ground potential voltage signal LVS1.

[0067] As described above, the amplifier circuit 550 includes: a gate driver circuit 530, which outputs a gate signal HGD1 and a gate signal LGD1 based on the modulation signal MS; a transistor M1, one end of which, i.e., the drain terminal, is supplied with a voltage signal VHV1, and the other end, i.e., the source terminal, is electrically connected to the midpoint CP1, and the transistor M1 operates based on the gate signal HGD1 input to the gate terminal; and a transistor M2, one end of which, i.e., the drain terminal, is electrically connected to the midpoint CP1, and the other end, i.e., the source terminal, is supplied with a ground potential, and the transistor M2 operates based on the gate signal LGD1 input to the gate terminal.

[0068] The level shifter circuit 70 includes a reference level switching circuit 710, a gate driver circuit 730, diodes D11 and D12, capacitors C11 and C12, transistors M3 and M4, a bootstrap circuit BS, and a voltage detection circuit 760. The level shifter circuit 70 outputs a level-shifted amplified modulation signal AMS2 obtained by level-shifting the reference potential of the amplified modulation signal AMS1 to a midpoint CP2.

[0069] Specifically, the base drive signal aA is input to the reference level switching circuit 710 included in the level shifter circuit 70. The reference level switching circuit 710 generates a reference level switching signal LS based on the base drive signal aA and outputs it to the gate driver circuit 730. Specifically, when the voltage value specified by the base drive signal aA is equal to or greater than a predetermined threshold voltage, the reference level switching circuit 710 generates an H-level reference level switching signal LS and outputs it to the gate driver circuit 730. When the voltage value specified by the base drive signal aA is less than the threshold voltage, the reference level switching circuit 710 generates an L-level reference level switching signal LS and outputs it to the gate driver circuit 730. Here, the predetermined threshold voltage is a voltage value equal to or less than voltage vhv1, which is the voltage value of the voltage signal VHV1 supplied to the amplifier circuit 550, and preferably a voltage value close to voltage vhv1.

[0070] The gate driver circuit 730 outputs a gate signal HGD2 for driving the transistor M3 and a gate signal LGD2 for driving the transistor M4 according to the logic level of the reference level switching signal LS.

[0071] Specifically, the reference level switching signal LS output by the reference level switching circuit 710 is input to the gate driver 731 included in the gate driver circuit 730. The gate driver 731 generates and outputs a gate signal HGD2 obtained by level-converting the input reference level switching signal LS. Furthermore, the reference level switching signal LS output by the reference level switching circuit 710 is inverted in logic level by the inverter 721 and then input to the gate driver 732 included in the gate driver circuit 730. The gate driver 732 generates and outputs a gate signal LGD2 obtained by level-converting the input reference level switching signal LS obtained by inverting its logic level.

[0072] Transistors M3 and M4 are both composed of N-channel MOS FETs. A gate signal HGD2 output by gate driver 731 is input to the gate terminal of transistor M3. A voltage signal VHV3 output by bootstrap circuit BS is supplied to the drain terminal of transistor M3. The source terminal of transistor M3 is electrically connected to midpoint CP2. Furthermore, a gate signal LGD2 output by gate driver 732 is input to the gate terminal of transistor M4. The drain terminal of transistor M4 is electrically connected to midpoint CP2. The source terminal of transistor M4 is electrically connected to midpoint CP1. Furthermore, by operating transistor M3 based on gate signal HGD2 and transistor M4 based on gate signal LGD2, a level-converted amplified modulation signal AMS2 is generated at midpoint CP2 connecting transistors M3 and M4, resulting from a level shift of the reference potential of amplified modulation signal AMS1.

[0073] Specifically, transistor M3 included in level shifter circuit 70 has voltage signal VHV3 output by bootstrap circuit BS supplied to its drain terminal at one end, and its source terminal at the other end electrically connected to midpoint CP2. The transistor M3 operates based on gate signal HGD2 output by gate driver 731. Transistor M4 included in level shifter circuit 70 has a drain terminal at one end electrically connected to midpoint CP2, and an amplified modulation signal AMS1 supplied to its source terminal at the other end, and operates based on gate signal LGD2 output by gate driver 732. Furthermore, level shifter circuit 70 outputs a signal generated at midpoint CP2 connecting transistors M3 and M4 as level-shifted amplified modulation signal AMS2.

[0074] The bootstrap circuit BS includes a diode D13 and a capacitor C13. The anode terminal of diode D13 is supplied with a voltage signal VHV2, and the cathode terminal of diode D13 is electrically connected to one end of capacitor C13. Furthermore, the other end of capacitor C13 is electrically connected to midpoint CP1. Specifically, the bootstrap circuit BS includes capacitor C13 and receives inputs of the voltage signal VHV2 and the amplified modulation signal AMS1 output to midpoint CP1. Furthermore, the bootstrap circuit BS generates a voltage signal VHV3 by adding the voltage value of the voltage signal VHV2 (i.e., the voltage value based on voltage vhv2) to the voltage value of the amplified modulation signal AMS1, and outputs the generated voltage signal VHV3 to the drain terminal of transistor M3. In other words, the bootstrap circuit BS outputs a voltage signal VHV3 corresponding to the voltage signal VHV2 and the amplified modulation signal AMS1, and also by level-shifting the reference potential of the amplified modulation signal AMS1 based on voltage vhv2.

[0075] Here, the operation of gate driver circuit 730 is described. Gate driver circuit 730 includes gate drivers 731 and 732. As described above, reference level switching signal LS is input to gate driver 731, and a signal obtained by inverting the logic level of reference level switching signal LS via inverter 721 is input to gate driver 732. In other words, the signal input to gate driver 731 and the signal input to gate driver 732 are exclusively at the H level. Here, "exclusively at the H level" includes the case where an H-level signal is not simultaneously input to gate driver 731 and gate driver 732. This does not exclude the case where an L-level signal is simultaneously input to gate driver 731 and gate driver 732.

[0076] The low-potential-side power supply terminal of the gate driver 731 is electrically connected to the midpoint CP2. Therefore, the signal generated at the midpoint CP2 is supplied to the low-potential-side power supply terminal of the gate driver 731 as the voltage signal HVS2. Furthermore, the high-potential-side power supply terminal of the gate driver 731 is electrically connected to the cathode terminal of the diode D11 and one end of the capacitor C11. Furthermore, the anode terminal of the diode D11 is supplied with the voltage vm, and the other end of the capacitor C11 is electrically connected to the midpoint CP2. In other words, the diode D11 and the capacitor C11 constitute a bootstrap circuit, and the output voltage of this bootstrap circuit is supplied to the high-potential-side power supply terminal of the gate driver 731. In other words, the high-potential-side power supply terminal of the gate driver 731 is supplied with the voltage signal HVD2, which is a voltage value increased by the voltage vm compared to the voltage signal HVS2 input to the low-potential-side power supply terminal of the gate driver 731. Therefore, when an H-level reference level switching signal LS is input to the gate driver 731, the gate driver 731 will output a gate signal HGD2 based on the voltage value of the voltage signal HVD2 increased by the voltage vm compared to the voltage value of the midpoint CP2, and when an L-level reference level switching signal LS is input to the gate driver 731, the gate driver 731 will output the voltage value of the midpoint CP2, that is, the gate signal HGD2 based on the voltage value of the voltage signal HVS2.

[0077] The low-potential-side power supply terminal of the gate driver 732 is electrically connected to the midpoint CP1. Therefore, the signal generated at the midpoint CP1 is supplied to the low-potential-side power supply terminal of the gate driver 732 as the voltage signal LVS2, thereby amplifying the modulated signal AMS1. Furthermore, the high-potential-side power supply terminal of the gate driver 732 is electrically connected to the cathode terminal of the diode D12 and one end of the capacitor C12. Furthermore, the anode terminal of the diode D12 is supplied with the voltage vm, and the other end of the capacitor C12 is electrically connected to the midpoint CP1. In other words, the diode D12 and the capacitor C12 form a bootstrap circuit, and the output voltage of this bootstrap circuit is supplied to the high-potential-side power supply terminal of the gate driver 732. In other words, the high-potential-side power supply terminal of the gate driver 732 is supplied with the voltage signal LVD2, which is a voltage value increased by the voltage vm compared to the voltage signal LVS2 input to the low-potential-side power supply terminal of the gate driver 732. Therefore, when an H-level signal obtained by inverting the logic level of the L-level reference level switching signal LS through the inverter 721 is input to the gate driver 732, the gate driver 732 will output a gate signal LGD2 based on the voltage value of the voltage signal LVD2 increased by the voltage vm compared to the voltage value of the midpoint CP1, and when an L-level signal obtained by inverting the logic level of the H-level reference level switching signal LS through the inverter 721 is input to the gate driver 732, the gate driver 732 will output a gate signal HGD2 based on the voltage value of the midpoint CP1, that is, the voltage value of the voltage signal LVS2.

[0078] As described above, the gate driver circuit 730 outputs gate signals HGD2 and LGD2 corresponding to the logic level of the reference-level switching signal LS. Furthermore, as previously described, the logic level of the reference-level switching signal LS is determined by whether the voltage value specified by the base drive signal aA input to the reference-level switching circuit 710 is above a predetermined threshold voltage. In other words, the gate driver circuit 730 outputs gate signals HGD2 and LGD2 based on the base drive signals dA and aA.

[0079] In the level shifter circuit 70 configured as described above, when the drain and source terminals of transistor M3 are controlled to a non-conductive state based on an L-level gate signal HGD2 and the drain and source terminals of transistor M4 are controlled to a conductive state based on an H-level gate signal LGD2, that is, when the reference level switching circuit 710 outputs an L-level reference level switching signal LS based on the base drive signal aA, the midpoint CP1 of the amplifier circuit 550 and the midpoint CP2 of the level shifter circuit 70 are electrically connected via transistor M4. Therefore, the level shifter circuit 70 outputs the amplified modulation signal AMS1 supplied to the midpoint CP2 via transistor M4 as the level-converted amplified modulation signal AMS2.

[0080] On the other hand, when the drain and source terminals of transistor M3 are controlled to be conductive based on an H-level gate signal HGD2 and the drain and source terminals of transistor M4 are controlled to be non-conductive based on an L-level gate signal LGD2, that is, when the reference level switching circuit 710 outputs an H-level reference level switching signal LS based on the basic drive signal aA, the midpoint CP1 of the amplifier circuit 550 and the midpoint CP2 of the level shifter circuit 70 are electrically connected via the bootstrap circuit BS and the transistor M3. Therefore, the level shifter circuit 70 outputs a voltage signal VHV3, which is obtained by level-shifting the reference potential of the amplified modulation signal AMS1 based on the voltage vhv2 of the voltage signal VHV2, as the level-shifted amplified modulation signal AMS2.

[0081] That is, when the voltage value specified by the basic drive signal dA is less than a predetermined threshold voltage, the level conversion circuit 70 controls the transistor M3 to a non-conducting state and the transistor M4 to a conducting state, thereby outputting the amplified modulation signal AMS1 as a level-converted amplified modulation signal AMS2 having the reference potential of the amplified modulation signal AMS1 as the ground potential. And when the voltage value specified by the basic drive signal dA is greater than the predetermined threshold voltage, the level conversion circuit 70 controls the transistor M3 to a conducting state and the transistor M4 to a non-conducting state, thereby outputting a signal obtained by converting the reference potential level of the amplified modulation signal AMS1 to a voltage value based on the voltage signal VHV2 having a higher potential than the ground potential as the level-converted amplified modulation signal AMS2.

[0082] In the following description, the operating mode in which the level shifter circuit 70 outputs the amplified modulation signal AMS1 as the level-shifted amplified modulation signal AMS2 is referred to as the first mode MD1, and the operating mode in which the level shifter circuit 70 outputs the level-shifted amplified modulation signal AMS2, which is a voltage value based on the voltage vhv2 and the reference potential level of the amplified modulation signal AMS1, is shifted to the voltage value of the voltage signal VHV2. Specifically, when the voltage value specified by the base drive signals dA and aA is a first voltage value less than a predetermined threshold voltage, the level shifter circuit 70 operates in the first mode MD1, and when the voltage value specified by the base drive signals dA and aA is a second voltage value greater than the predetermined threshold voltage, the level shifter circuit 70 operates in the second mode MD2.

[0083] The voltage detection circuit 760 detects the voltage value of the capacitor C13 included in the bootstrap circuit BS, and outputs a voltage detection signal VCAP indicating the detection result to the reference level switching circuit 710 .

[0084] Specifically, the voltage detection circuit 760 receives inputs of the voltage value at one end of capacitor C13 and the voltage value at the other end of capacitor C13. The voltage detection circuit 760 calculates the difference between the input voltage value at one end of capacitor C13 and the voltage value at the other end of capacitor C13. The voltage detection circuit 760 generates a voltage detection signal VCAP at a logic level corresponding to whether the calculated difference is above a predetermined threshold. Such a voltage detection circuit 760 includes an operational amplifier that calculates the difference between the voltage value at one end of capacitor C13 and the voltage value at the other end of capacitor C13, and a comparator that determines whether the potential difference between the two ends of capacitor C13 is above a predetermined threshold. In other words, the voltage detection circuit 760 includes a comparator. The voltage detection circuit 760 outputs the output of the comparator as the voltage detection signal VCAP to the reference level switching circuit 710.

[0085] Here, the voltage detection circuit 760 of this embodiment will be described as a configuration in which the voltage detection signal VCAP is output at an H level when the difference between the voltage value at one end of the capacitor C13 and the voltage value at the other end of the capacitor C13 is greater than a predetermined threshold value, and outputs the voltage detection signal VCAP at an L level when the difference between the voltage value at one end of the capacitor C13 and the voltage value at the other end of the capacitor C13 is less than the predetermined threshold value. In other words, the voltage detection circuit 760 of this embodiment will be described as a configuration in which the voltage detection signal VCAP is output at an H level when the voltage across the capacitor C13 and the amount of charge accumulated in the capacitor C13 are greater than a predetermined threshold value, and outputs the voltage detection signal VCAP at an L level when the voltage across the capacitor C13 and the amount of charge accumulated in the capacitor C13 are less than the predetermined threshold value. In addition, the logic level of the voltage detection signal VCAP output by the voltage detection circuit 760 is not limited to the above content, and the voltage detection signal VCAP output by the voltage detection circuit 760 may also be a signal including a predetermined command.

[0086] The reference level switching circuit 710 switches the logic level of the reference level switching signal LS according to the logic level of the input voltage detection signal VCAP.

[0087] Specifically, the reference level switching circuit 710 obtains and maintains the logic level of the voltage detection signal VCAP while the voltage value specified by the input basic drive signal aA is below a predetermined threshold, preferably while the voltage value of the drive signal COM specified by the basic drive signal aA remains within a fixed period. Thereafter, when the voltage value specified by the input basic drive signal aA to the reference level switching circuit 710 exceeds the predetermined threshold, the reference level switching circuit 710 switches the logic level of the output reference level switching signal LS from an L level to an H level. In other words, the operating mode of the level shifter circuit 70 switches from the first mode MD1 to the second mode MD2. Furthermore, immediately after the reference level switching circuit 710 switches the operating mode of the level shifter circuit 70 from the first mode MD1 to the second mode MD2, specifically, immediately after the reference level switching circuit 710 switches the logic level of the reference level switching signal LS from the L level to the H level, in order to reduce waveform distortion of the drive signal COM that may occur with the switching of the operating mode, the reference level switching circuit 710 outputs a pulse signal whose logic level briefly changes to the L level as the reference level switching signal LS one or more times. The number of times the reference level switching circuit 710 outputs the pulse signal is determined by the logic level of the voltage detection signal VCAP input from the voltage detection circuit 760.

[0088] On the other hand, the reference level switching circuit 710 obtains and maintains the logic level of the voltage detection signal VCAP when the voltage value specified by the input basic drive signal aA is above a predetermined threshold, preferably when the voltage value of the drive signal COM specified by the basic drive signal aA remains above a predetermined threshold. Thereafter, when the voltage value specified by the input basic drive signal aA falls below the predetermined threshold, the reference level switching circuit 710 switches the logic level of the output reference level switching signal LS from an H level to an L level. In other words, the operating mode of the level shifter circuit 70 switches from the second mode MD2 to the first mode MD1. Furthermore, immediately after the reference level switching circuit 710 switches the operating mode of the level shifter circuit 70 from the second mode MD2 to the first mode MD1, specifically, immediately after the reference level switching circuit 710 switches the logic level of the reference level switching signal LS from an H level to an L level, in order to reduce waveform distortion of the drive signal COM that may occur with the switching of the operating modes, the reference level switching circuit 710 outputs a pulse signal whose logic level briefly remains at an H level as the reference level switching signal LS one or more times. The number of times the pulse signal output by the reference level switching circuit 710 is output is determined by the logic level of the voltage detection signal VCAP input from the voltage detection circuit 760 .

[0089] In the following description, the pulse signal output by the reference level switching circuit 710, which briefly changes its logic level to an L level when the operating mode of the level shifter circuit 70 switches from the first mode MD1 to the second mode MD2, and the pulse signal output by the reference level switching circuit 710, which briefly changes its logic level to an H level when the operating mode of the level shifter circuit 70 switches from the second mode MD2 to the first mode MD1, are sometimes collectively referred to as counter pulses CP. Specifically, in the driver circuit 50 of this embodiment, the reference level switching circuit 710 outputs one or more counter pulses CP when the operating mode of the level shifter circuit 70 switches from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1. Furthermore, the number of counter pulses CP output by the reference level switching circuit 710 is determined by the logic level of the voltage detection signal VCAP output by the voltage detection circuit 760.

[0090] The level-converted, amplified, and modulated signal AMS2 output by the level shifter circuit 70 is input to the demodulator circuit 560. The demodulator circuit 560 smoothes and demodulates the level-converted, amplified, and modulated signal AMS2 output by the level shifter circuit 70, thereby generating and outputting the drive signal COM. In other words, the demodulator circuit 560 demodulates the level-converted, amplified, and modulated signal AMS2 to output the drive signal COM.

[0091] Demodulation circuit 560 includes an inductor L10 and a capacitor C10. One end of inductor L10 is electrically connected to midpoint CP2. The other end of inductor L10 is electrically connected to one end of capacitor C10. Furthermore, the other end of capacitor C10 is supplied with a ground potential. In other words, inductor L10 and capacitor C10 form a low-pass filter circuit. This smoothes the level-converted, amplified, and modulated signal AMS2 output from level shifter circuit 70 and outputs it from driver circuit 50 as drive signal COM.

[0092] The feedback circuit 570 supplies the adder 511 with a feedback signal VFB obtained by attenuating the drive signal COM generated by the demodulation circuit 560. As a result, the drive signal COM output by the demodulation circuit 560 is fed back to the modulation circuit 520. As a result, the accuracy of the signal waveform of the drive signal COM output by the drive circuit 50 is improved. Here, the feedback circuit 570 may also feed back multiple signals as the feedback signal VFB, including a signal obtained by attenuating the drive signal COM generated by the demodulation circuit 560 and a signal obtained by attenuating a signal extracted from the high-frequency components of the drive signal COM generated by the demodulation circuit 560. That is, the feedback circuit 570 may include multiple feedback circuits, each of which includes a circuit for feeding back a signal obtained by attenuating the drive signal COM generated by the demodulation circuit 560 and a circuit for feeding back a signal obtained by attenuating a signal extracted from the high-frequency components of the drive signal COM generated by the demodulation circuit 560.

[0093] This allows the high-frequency component contained in the drive signal COM to be independently fed back. As a result, the drive circuit 50 can self-oscillate based on this high-frequency component, increasing the frequency of the modulation signal MS to a level sufficient to ensure the accuracy of the drive signal COM. This further improves the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0094] 3.3 Operation of the drive signal output circuit

[0095] Next, the operation of the drive circuit 50 will be described. Figure 7 50 is a diagram for explaining the operation of the driving circuit 50. Figure 7 In FIG, only the drive signal COM outputted by the drive circuit 50 within an arbitrary period T is shown. Figure 7In FIG, the predetermined threshold voltage of the drive signal COM for switching whether the reference level switching circuit 710 outputs the reference level switching signal LS of the H level or the reference level switching signal LS of the L level is illustrated as voltage vth, and the voltage value of the basic drive signal aA corresponding to the voltage vth is illustrated as voltage avth. Moreover, the voltage value of the basic drive signal aA corresponding to the voltage vt of the drive signal COM is illustrated as voltage avt, the voltage value of the basic drive signal aA corresponding to the voltage vb of the drive signal COM is illustrated as voltage avb, and the voltage value of the basic drive signal aA corresponding to the voltage vc of the drive signal COM is illustrated as voltage avc. In addition, although in Figure 7 2 shows a case where the voltage vth is a voltage value smaller than the voltage vc and the voltage avth is a voltage value smaller than the voltage avc, but the present invention is not limited thereto.

[0096] like Figure 7 As shown, during the period from time t0 to time t10, the drive circuit 50 outputs a drive signal COM whose voltage value is constant at voltage vc. Specifically, during the period from time t0 to time t10, the basic drive signal output circuit 510 receives input of a basic drive signal dA for generating a drive signal COM whose voltage value is constant at voltage vc. Therefore, the basic drive signal output circuit 510 generates a basic drive signal aA, which is constant at voltage avc, based on the input basic drive signal dA. The basic drive signal output circuit 510 then outputs the generated basic drive signal aA to the modulation circuit 520 via the adder 511.

[0097] The modulation circuit 520 modulates the basic drive signal aA output by the basic drive signal output circuit 510 to generate a modulation signal MS. The modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logic level of the modulation signal MS is input to the gate driver 532. Consequently, the gate driver circuit 530 outputs a gate signal HGD1 corresponding to the logic level of the modulation signal MS and a gate signal LGD1 corresponding to the signal obtained by inverting the logic level of the modulation signal MS. Furthermore, transistors M1 and M2 of the amplifier circuit 550 operate based on the gate signals HGD1 and LGD1, respectively, to amplify the modulation signal MS based on the voltage value vhv1 of the voltage signal VHV1, thereby outputting an amplified modulation signal AMS1 from the midpoint CP1.

[0098] Furthermore, the base drive signal output circuit 510 also outputs the base drive signal aA to the reference level switching circuit 710 included in the level shifter circuit 70. During the period from time t0 to time t10, the voltage value of the drive signal COM is greater than the voltage vth. Therefore, the voltage value of the base drive signal aA is greater than the voltage avth. Consequently, the reference level switching circuit 710 generates an H-level reference level switching signal LS. The H-level reference level switching signal LS is input to the gate driver 731, and the L-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an H-level gate signal HGD2 and an L-level gate signal LGD2.

[0099] Furthermore, transistor M3 is controlled to be conductive by an H-level gate signal HGD2 output by gate driver circuit 730, while transistor M4 is controlled to be non-conductive by an L-level gate signal LGD2. Consequently, a level-converted amplified modulated signal AMS2 is output from midpoint CP2, which is a level-converted amplified modulated signal AMS1 output from midpoint CP1 of amplifier circuit 550, by level-converting the reference potential of amplified modulated signal AMS1 according to voltage vhv2, the voltage value of voltage signal VHV2 input to bootstrap circuit BS. Furthermore, level-converted amplified modulated signal AMS2 output by level converter circuit 70 is demodulated by demodulator circuit 560, resulting in drive circuit 50 outputting drive signal COM having a constant voltage value of voltage vc.

[0100] Furthermore, during the period from time t0 to time t10, the reference level switching circuit 710 acquires and holds the voltage detection signal VCAP output by the voltage detection circuit 760. Alternatively, the reference level switching circuit 710 may acquire and hold the logic level of the voltage detection signal VCAP input to the reference level switching circuit 710 at predetermined timings during the period from time t0 to time t10. Alternatively, the reference level switching circuit 710 may acquire the logic level of the voltage detection signal VCAP multiple times during the period from time t0 to time t10, compare the number of times the voltage detection signal VCAP was acquired at an H level with the number of times the voltage detection signal VCAP was acquired at an L level, and hold the logic level with the greater number of acquisitions. Alternatively, the reference level switching circuit 710 may continuously acquire the logic level of the voltage detection signal VCAP during a predetermined period and, near time t10, hold the logic level of the voltage detection signal VCAP that was continuously input multiple times. In addition, the reference level switching circuit 710 may discard the already held logic level of the voltage detection signal VCAP when acquiring and holding the voltage detection signal VCAP at a new logic level.

[0101] During the period from time t10 to time t20, the drive circuit 50 outputs the drive signal COM whose voltage value changes from voltage vc to voltage vb. Specifically, during the period from time t10 to time t20, the basic drive signal output circuit 510 receives input of the basic drive signal dA used to generate the drive signal COM whose voltage value changes from voltage vc to voltage vb. Therefore, based on the input basic drive signal dA, the basic drive signal output circuit 510 generates the basic drive signal aA whose voltage value changes from voltage avc to voltage avb. The basic drive signal output circuit 510 then outputs the generated basic drive signal aA to the modulation circuit 520 via the adder 511.

[0102] The modulation circuit 520 modulates the basic drive signal aA output by the basic drive signal output circuit 510 to generate a modulation signal MS. The modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logic level of the modulation signal MS is input to the gate driver 532. Consequently, the gate driver circuit 530 outputs a gate signal HGD1 corresponding to the logic level of the modulation signal MS and a gate signal LGD1 corresponding to the signal obtained by inverting the logic level of the modulation signal MS. Furthermore, transistors M1 and M2 of the amplifier circuit 550 operate based on the gate signals HGD1 and LGD1, amplifying the modulation signal MS based on the voltage value vhv1 of the voltage signal VHV1. The resulting amplified modulation signal AMS1 is output from the midpoint CP1.

[0103] Furthermore, the base drive signal output circuit 510 also outputs the base drive signal aA to the reference level switching circuit 710 included in the level shifter circuit 70. During the period from time t10 to time t20, while the voltage value of the drive signal COM is greater than the voltage vth, and during the period from time t10 to time tc1 when the voltage value of the base drive signal aA is greater than the voltage avth, the reference level switching circuit 710 generates an H-level reference level switching signal LS. The H-level reference level switching signal LS is input to the gate driver 731, and the L-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an H-level gate signal HGD2 and an L-level gate signal LGD2.

[0104] Furthermore, transistor M3 is controlled to be conductive by an H-level gate signal HGD2 output by gate driver circuit 730, and transistor M4 is controlled to be non-conductive by an L-level gate signal LGD2. Consequently, a level-converted amplified modulation signal AMS2 is output from midpoint CP2, resulting from level-converting the reference potential of amplified modulation signal AMS1 output from midpoint CP1 of amplifier circuit 550 according to voltage vhv2, which is the voltage value of voltage signal VHV2 input to bootstrap circuit BS.

[0105] During the period from time t10 to time t20, while the voltage value of the drive signal COM is less than the voltage vth, and during the period from time tc1 to time t20, while the voltage value of the basic drive signal aA is less than the voltage avth, the reference level switching circuit 710 generates an L-level reference level switching signal LS. The L-level reference level switching signal LS is input to the gate driver 731, and the H-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an L-level gate signal HGD2 and an H-level gate signal LGD2.

[0106] Transistor M3 is controlled to a non-conducting state by an L-level gate signal HGD2 output by gate driver circuit 730, while transistor M4 is controlled to a conducting state by an H-level gate signal LGD2. Consequently, amplified modulation signal AMS1 output from midpoint CP1 of amplifier circuit 550 is output from midpoint CP2 as level-shifted amplified modulation signal AMS2. Specifically, during the period from time t10 to time tc1 between time t10 and time t20, the operating mode of level shifter circuit 70 is in the second mode MD2. During the period from time tc1 to time t20 between time t10 and time t20, the operating mode of level shifter circuit 70 is in the first mode MD1. In other words, at time tc1, the operating mode of level shifter circuit 70 transitions from the second mode MD2 to the first mode MD1.

[0107] Furthermore, the level-converted amplified modulated signal AMS2 outputted by the level conversion circuit 70 is demodulated in the demodulation circuit 560 , so that the driving circuit 50 outputs the driving signal COM whose voltage value is changed from the voltage vc to the voltage vb.

[0108] Furthermore, at time Tc1 , after the operation mode of the level conversion circuit 70 changes from the second mode MD2 to the first mode MD1 , the reference level switching circuit 710 generates a counter pulse CP that briefly inverts the logic level of the reference level switching signal LS. Figure 81 and 2 are diagrams showing an example of the counter pulse CP when the second mode MD2 transitions to the first mode MD1 and an example of the operations of the transistors M3 and M4 based on the counter pulse CP.

[0109] like Figure 8 As shown, before time Tc1, level shifter circuit 70 operates in second mode MD2. At this time, reference level switching circuit 710 outputs an H-level reference level switching signal LS, and gate driver circuit 730 outputs an H-level gate signal HGD2 and an L-level gate signal LGD2. That is, transistor M3 is controlled to be conductive, and transistor M4 is controlled to be non-conductive.

[0110] Then, at time Tc1, the operating mode of the level shifter circuit 70 transitions from the second mode MD2 to the first mode MD1. Specifically, the reference level switching circuit 710 switches the logic level of the output reference level switching signal LS from an H level to an L level. Consequently, the gate driver circuit 730 outputs an L-level gate signal HGD2 and an H-level gate signal LGD2. As a result, transistor M3 is controlled to a non-conducting state, and transistor M4 is controlled to a conducting state. That is, when the operating mode of the level shifter circuit 70 transitions from the second mode MD2 to the first mode MD1, the gate driver circuit 730, starting from the state in which it was outputting the gate signal HGD2 that controls transistor M3 to a conducting state and the gate signal LGD2 that controls transistor M4 to a non-conducting state, now outputs the gate signal HGD2 that controls transistor M3 to a non-conducting state and the gate signal LGD2 that controls transistor M4 to a conducting state.

[0111] Here, in the following description, the following operation is referred to as mode switching control MC21, and the operation is that when the operating mode of the level conversion circuit 70 changes from the second mode MD2 to the first mode MD1, the gate driver circuit 730 changes from the state of outputting the gate signal HGD2 for controlling the transistor M3 to be in the on state and the gate signal LGD2 for controlling the transistor M4 to be in the non-conducting state to outputting the gate signal HGD2 for controlling the transistor M3 to be in the non-conducting state and the gate signal LGD2 for controlling the transistor M4 to be in the on state.

[0112] After executing the mode switching control MC21, the reference level switching circuit 710 outputs the counter pulse CP as the reference level switching signal LS one or more times. In other words, after the operating mode of the level conversion circuit 70 changes from the second mode MD2 to the first mode MD1, the reference level switching circuit 710 outputs the counter pulse CP one or more times.

[0113] Specifically, at time Tc1, the reference level switching circuit 710 switches the logic level of the reference level switching signal LS from an H level to an L level. Thus, mode switching control MC21 is executed. Furthermore, after mode switching control MC21, the reference level switching circuit 710 outputs a counter pulse CP that briefly switches the logic level of the reference level switching signal LS to an L level and then switches it back to an H level. Consequently, the gate driver circuit 730 outputs a gate signal HGD2 that controls transistor M3 to a conductive state and a gate signal LGD2 that controls transistor M4 to a non-conductive state. Thereafter, the gate driver circuit 730 outputs the gate signal HGD2 that controls transistor M3 to a non-conductive state and the gate signal LGD2 that controls transistor M4 to a conductive state.

[0114] Here, in the following description, the following operation is referred to as counter pulse control DCP, which is to output a counter pulse CP that briefly sets the logic level of the reference level switching signal LS to the L level and then to the H level again through the reference level switching circuit 710, so that the gate driver circuit 730 outputs the gate signal HGD2 that controls the transistor M3 to be in the conductive state and the gate signal LGD2 that controls the transistor M4 to be in the non-conductive state. Thereafter, the gate signal HGD2 that controls the transistor M3 to be in the non-conductive state and the gate signal LGD2 that controls the transistor M4 to be in the conductive state are output.

[0115] After the mode switching control MC21, the level shifter circuit 70 performs the aforementioned counter pulse control DCP once or repeatedly multiple times. When the operating mode of the level shifter circuit 70 changes from the second mode MD2 to the first mode MD1, the reference potential of the amplified modulation signal AMS1 output as the level-converted amplified modulation signal AMS2 suddenly changes from a potential based on the voltage vhv2 to the ground potential. If the response speed of the driver circuit 50 cannot keep up with this sudden change in the reference potential, the signal waveform of the drive signal COM output by the driver circuit 50 may be distorted. In contrast, in the driver circuit 50 of this embodiment, the reference level switching circuit 710 performs the counter pulse control DCP when the operating mode of the level shifter circuit 70 changes from the second mode MD2 to the first mode MD1. This slows down the change in the reference potential of the amplified modulation signal AMS1 output as the level-converted amplified modulation signal AMS2, thereby reducing the possibility of distortion in the signal waveform of the drive signal COM output by the driver circuit 50.

[0116] Furthermore, in the driving circuit 50 of the liquid ejection device 1 of the present embodiment, the number of times the level conversion circuit 70 repeatedly executes the counter pulse control DCP is determined based on the logic level of the voltage detection signal VCAP obtained and held by the reference level switching circuit 710. In other words, the counter pulse control DCP is executed once or multiple times based on the voltage value of the capacitor C13 included in the bootstrap circuit BS. The counter pulse control DCP is a control in which the reference level switching circuit 710 outputs the counter pulse CP, causing the gate driver circuit 730 to output the gate signal HGD2 for controlling the transistor M3 to be conductive and the gate signal LGD2 for controlling the transistor M4 to be non-conductive, and then outputs the gate signal HGD2 for controlling the transistor M3 to be non-conductive and the gate signal LGD2 for controlling the transistor M4 to be conductive.

[0117] As described above, during the period from time t10 to time t20, the drive circuit 50 outputs the drive signal COM whose voltage value decreases from voltage vc to voltage vb. At this time, the charge accumulated in the piezoelectric element 60 and the demodulation circuit 560 is released toward the drive circuit 50. In other words, the current generated by the release of the charge accumulated in the piezoelectric element 60 and the demodulation circuit 560 is supplied to the drive circuit 50. During this period from time t10 to time t20, while the level shifter circuit 70 executes counter pulse control DCP, causing the gate driver circuit 730 to output gate signal HGD2 that controls transistor M3 to be conductive and gate signal LGD2 that controls transistor M4 to be non-conductive, the current supplied to the drive circuit 50 is supplied to capacitor C13 via transistor M3. That is, during the period from time t10 to time t20 , the counter pulse control DCP is executed, so that the regenerative current flows through the capacitor C13 of the bootstrap circuit BS, and as a result, electric charge is accumulated in the capacitor C13 .

[0118] If the voltage value of capacitor C13 in bootstrap circuit BS drops, the reference potential of amplified modulation signal AMS1, output as level-shifted amplified modulation signal AMS2 in second mode MD2, will not be sufficiently obtained. As a result, the signal waveform of drive signal COM output by drive circuit 50 may be distorted. In contrast, in the drive circuit 50 of the liquid ejection device 1 of this embodiment, counter pulse control DCP is executed during the period from time t10 to time t20 to increase the voltage value held by capacitor C13. As a result, the voltage value of capacitor C13 drops, reducing the possibility of distortion in the signal waveform of drive signal COM output by drive circuit 50.

[0119] Furthermore, since the number of counter pulse control DCPs executed by the level shifter circuit 70 during the period from time t10 to time t20 is determined by the voltage value of capacitor C13 included in the bootstrap circuit BS, the possibility of excessive charge being supplied to capacitor C13 is reduced even when sufficient charge is stored in capacitor C13. As a result, the possibility of increased power consumption associated with the counter pulse control DCP can be reduced. Furthermore, if sufficient charge is not stored in capacitor C13, sufficient charge can be stored in capacitor C13, thereby reducing the possibility of distortion in the signal waveform of the drive signal COM output by the drive circuit 50. Therefore, it is preferable that the number of counter pulse control DCPs executed by the level shifter circuit 70 be increased when the voltage value of capacitor C13 included in the bootstrap circuit BS decreases.

[0120] Back to Figure 7 During the period from time t20 to time t30, the drive circuit 50 outputs a drive signal COM whose voltage value is constant at voltage vb. Specifically, during the period from time t20 to time t30, the basic drive signal output circuit 510 receives input of a basic drive signal dA for generating a drive signal COM whose voltage value is constant at voltage vb. Therefore, the basic drive signal output circuit 510 generates a basic drive signal aA constant at voltage avb based on the input basic drive signal dA. The basic drive signal output circuit 510 then outputs the generated basic drive signal aA to the modulation circuit 520 via the adder 511.

[0121] The modulation circuit 520 modulates the basic drive signal aA output by the basic drive signal output circuit 510 to generate a modulation signal MS. The modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logic level of the modulation signal MS is input to the gate driver 532. As a result, the gate driver circuit 530 outputs a gate signal HGD1 corresponding to the logic level of the modulation signal MS and a gate signal LGD1 corresponding to the signal obtained by inverting the logic level of the modulation signal MS. Then, transistors M1 and M2 of the amplifier circuit 550 operate based on the gate signals HGD1 and LGD1, amplifying the modulation signal MS based on the voltage value vhv1 of the voltage signal VHV1. The resulting amplified modulation signal AMS1 is output from the midpoint CP1.

[0122] Furthermore, the base drive signal output circuit 510 also outputs the base drive signal aA to the reference level switching circuit 710 included in the level shifter circuit 70. During the period from time t20 to time t30, the voltage value of the drive signal COM is less than the voltage vth. Therefore, the voltage value of the base drive signal aA is less than the voltage avth. Consequently, the reference level switching circuit 710 generates an L-level reference level switching signal LS. The L-level reference level switching signal LS is input to the gate driver 731, and the H-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an L-level gate signal HGD2 and an H-level gate signal LGD2.

[0123] Then, transistor M3 is controlled to a non-conductive state by an L-level gate signal HGD2 output by gate driver circuit 730, and transistor M4 is controlled to a conductive state by an H-level gate signal LGD2. Consequently, amplified modulation signal AMS1 output from midpoint CP1 of amplifier circuit 550 is output from midpoint CP2 as level-converted amplified modulation signal AMS2. Level-converted amplified modulation signal AMS2 output by level shifter circuit 70 is then demodulated by demodulator circuit 560, causing driver circuit 50 to output a drive signal COM whose voltage value is constant at voltage vb.

[0124] Furthermore, during the period from time t20 to time t30, the reference level switching circuit 710 acquires and holds the voltage detection signal VCAP output by the voltage detection circuit 760. Here, the reference level switching circuit 710 acquires and holds the logic level of the voltage detection signal VCAP input to the reference level switching circuit 710 at predetermined timings during the period from time t20 to time t30. Alternatively, the reference level switching circuit 710 may acquire the logic level of the voltage detection signal VCAP multiple times during the period from time t20 to time t30, compare the number of times the voltage detection signal VCAP was acquired at an H level with the number of times the voltage detection signal VCAP was acquired at an L level, and hold the logic level with the greater number of acquisitions. Furthermore, the reference level switching circuit 710 may continuously acquire the logic level of the voltage detection signal VCAP at a predetermined period and, near time t10, hold the logic level of the voltage detection signal VCAP that has been continuously input multiple times. In addition, the reference level switching circuit 710 may discard the logic level of the voltage detection signal VCAP that has been held, when acquiring and holding the voltage detection signal VCAP at a new logic level.

[0125] During the period from time t30 to time t40, the drive circuit 50 outputs the drive signal COM whose voltage value changes from voltage vb to voltage vt. Specifically, during the period from time t30 to time t40, the basic drive signal output circuit 510 receives input of the basic drive signal dA used to generate the drive signal COM whose voltage value changes from voltage vb to voltage vt. Therefore, based on the input basic drive signal dA, the basic drive signal output circuit 510 generates the basic drive signal aA whose voltage value changes from voltage avb to voltage avt. The basic drive signal output circuit 510 then outputs the generated basic drive signal aA to the modulation circuit 520 via the adder 511.

[0126] The modulation circuit 520 modulates the basic drive signal aA output by the basic drive signal output circuit 510 to generate a modulation signal MS. The modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logic level of the modulation signal MS is input to the gate driver 532. As a result, the gate driver circuit 530 outputs a gate signal HGD1 corresponding to the logic level of the modulation signal MS and a gate signal LGD1 corresponding to the signal obtained by inverting the logic level of the modulation signal MS. Then, transistors M1 and M2 of the amplifier circuit 550 operate based on the gate signals HGD1 and LGD1, amplifying the modulation signal MS based on the voltage value vhv1 of the voltage signal VHV1. The resulting amplified modulation signal AMS1 is output from the midpoint CP1.

[0127] Furthermore, the base drive signal output circuit 510 also outputs the base drive signal aA to the reference level switching circuit 710 included in the level shifter circuit 70. During the period from time t30 to time t40 when the voltage value of the drive signal COM is less than the voltage vth, and during the period from time t30 to time tc2 when the voltage value of the base drive signal aA is less than the voltage avth, the reference level switching circuit 710 generates an L-level reference level switching signal LS. The L-level reference level switching signal LS is input to the gate driver 731, and the H-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an L-level gate signal HGD2 and an H-level gate signal LGD2.

[0128] Then, transistor M3 is controlled to a non-conductive state by an L-level gate signal HGD2 output by gate driver circuit 730, and transistor M4 is controlled to a conductive state by an H-level gate signal LGD2. Consequently, amplified modulation signal AMS1 output from midpoint CP1 of amplifier circuit 550 is output from midpoint CP2 as a level-converted amplified modulation signal AMS2.

[0129] During the period from time t30 to time t40 when the voltage value of the drive signal COM is greater than voltage vth, and during the period from time tc2 to time t40 when the voltage value of the basic drive signal aA is greater than voltage avth, the reference level switching circuit 710 generates an H-level reference level switching signal LS. The H-level reference level switching signal LS is input to the gate driver 731, and the L-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an H-level gate signal HGD2 and an L-level gate signal LGD2.

[0130] Transistor M3 is controlled to be conductive by an H-level gate signal HGD2 output by gate driver circuit 730, while transistor M4 is controlled to be non-conductive by an L-level gate signal LGD2. Consequently, a level-shifted amplified modulation signal AMS2 is output from midpoint CP2, resulting from level shifting the reference potential of amplified modulation signal AMS1 output from midpoint CP1 of amplifier circuit 550 according to voltage vhv2, the voltage value of voltage signal VHV2 input to bootstrap circuit BS. Specifically, during the period from time t30 to time tc2 between time t30 and time t40, the operating mode of level shifter circuit 70 is in first mode MD1. During the period from time tc2 to time t40 between time t30 and time t40, the operating mode of level shifter circuit 70 is in second mode MD2. In other words, at time tc2, the operating mode of level shifter circuit 70 transitions from first mode MD1 to second mode MD2.

[0131] Then, the level-converted amplified modulated signal AMS2 outputted by the level conversion circuit 70 is demodulated in the demodulation circuit 560 , so that the driving circuit 50 outputs the driving signal COM whose voltage value changes from the voltage vb to the voltage vt.

[0132] Furthermore, at time Tc2 , after the operation mode of the level conversion circuit 70 changes from the first mode MD1 to the second mode MD2 , the reference level switching circuit 710 outputs a counter pulse CP that briefly inverts the logic level of the reference level switching signal LS. Figure 9 1 and 2 are diagrams showing an example of the counter pulse CP when the first mode MD1 transitions to the second mode MD2 and an example of the operations of the transistors M3 and M4 based on the counter pulse CP.

[0133] like Figure 9As shown, before time Tc2, level shifter circuit 70 operates in first mode MD1. At this time, reference level switching circuit 710 outputs an L-level reference level switching signal LS, and gate driver circuit 730 outputs an L-level gate signal HGD2 and an H-level gate signal LGD2. Specifically, transistor M3 is controlled to a non-conductive state, while transistor M4 is controlled to a conductive state.

[0134] Then, at time Tc2, the operating mode of the level shifter circuit 70 changes from the first mode MD1 to the second mode MD2. Specifically, the reference level switching circuit 710 switches the logic level of the output reference level switching signal LS from the low level to the high level. Consequently, the gate driver circuit 730 outputs an high-level gate signal HGD2 and an low-level gate signal LGD2. As a result, transistor M3 is controlled to be in a conductive state, and transistor M4 is controlled to be in a non-conductive state. That is, when the operating mode of the level shifter circuit 70 changes from the first mode MD1 to the second mode MD2, the gate driver circuit 730, starting from the state in which it was outputting the gate signal HGD2 that controlled transistor M3 to be in a non-conductive state and the gate signal LGD2 that controlled transistor M4 to be in a conductive state, outputs the gate signal HGD2 that controlled transistor M3 to be in a conductive state and the gate signal LGD2 that controlled transistor M4 to be in a non-conductive state.

[0135] Here, in the following description, the following operation is referred to as mode switching control MC12, and the operation is that when the operating mode of the level conversion circuit 70 changes from the first mode MD1 to the second mode MD2, the gate driver circuit 730 changes from the state of outputting the gate signal HGD2 for controlling the transistor M3 to the non-conducting state and the gate signal LGD2 for controlling the transistor M4 to the conducting state to outputting the gate signal HGD2 for controlling the transistor M3 to the conducting state and the gate signal LGD2 for controlling the transistor M4 to the non-conducting state.

[0136] After executing mode switching control MC12, reference level switching circuit 710 outputs counter pulse CP as reference level switching signal LS one or more times. In other words, after the operating mode of level conversion circuit 70 changes from first mode MD1 to second mode MD2, reference level switching circuit 710 outputs counter pulse CP one or more times.

[0137] Specifically, at time Tc2, the reference level switching circuit 710 switches the logic level of the reference level switching signal LS from L to H. Thus, mode switching control MC12 is executed. Then, after mode switching control MC12, the reference level switching circuit 710 outputs a counter pulse CP that briefly switches the logic level of the reference level switching signal LS to H before returning it to L. Consequently, the gate driver circuit 730 outputs a gate signal HGD2 that controls transistor M3 to a non-conductive state and a gate signal LGD2 that controls transistor M4 to a conductive state. Thereafter, the gate driver circuit 730 outputs a gate signal HGD2 that controls transistor M3 to a conductive state and a gate signal LGD2 that controls transistor M4 to a non-conductive state.

[0138] Here, in the following description, the following operation is referred to as counter pulse control UCP, which is to output a counter pulse CP that briefly sets the logic level of the reference level switching signal LS to the H level and then to the L level again through the reference level switching circuit 710, so that the gate driver circuit 730 outputs the gate signal HGD2 that controls the transistor M3 to the non-conducting state and the gate signal LGD2 that controls the transistor M4 to the conducting state, and thereafter, outputs the gate signal HGD2 that controls the transistor M3 to the conducting state and the gate signal LGD2 that controls the transistor M4 to the non-conducting state.

[0139] After the mode switching control MC12, the level shifter circuit 70 performs the aforementioned counter pulse control UCP once or repeatedly multiple times. When the operating mode of the level shifter circuit 70 changes from the first mode MD1 to the second mode MD2, the reference potential of the amplified modulation signal AMS1 output as the level-converted amplified modulation signal AMS2 suddenly changes from the ground potential to a potential based on the voltage vhv2. If the response speed of the driver circuit 50 cannot keep up with this abrupt change in the reference potential, the signal waveform of the drive signal COM output by the driver circuit 50 may be distorted. To address this issue, in the driver circuit 50 of this embodiment, the reference level switching circuit 710 performs the counter pulse control UCP when the operating mode of the level shifter circuit 70 changes from the first mode MD1 to the second mode MD2. This slows down the change in the reference potential of the amplified modulation signal AMS1 output as the level-converted amplified modulation signal AMS2, thereby reducing the possibility of distortion in the signal waveform of the drive signal COM output by the driver circuit 50.

[0140] Furthermore, in the driving circuit 50 of the liquid ejection device 1 of the present embodiment, the number of times the level conversion circuit 70 repeatedly executes the counter pulse control UCP is regulated according to the logic level of the voltage detection signal VCAP obtained and held by the reference level switching circuit 710. In other words, the counter pulse control UCP is executed once or multiple times according to the voltage value of the capacitor C13 included in the bootstrap circuit BS. The counter pulse control UCP is a control in which the reference level switching circuit 710 outputs a counter pulse CP, causing the gate driver circuit 730 to output a gate signal HGD2 for controlling the transistor M3 to be non-conductive and a gate signal LGD2 for controlling the transistor M4 to be conductive, and then outputs the gate signal HGD2 for controlling the transistor M3 to be conductive and the gate signal LGD2 for controlling the transistor M4 to be non-conductive.

[0141] As described above, during the period from time t30 to time t40, the drive circuit 50 outputs the drive signal COM, whose voltage value increases from voltage vb to voltage vt. At this time, current is supplied to the piezoelectric element 60 and the demodulation circuit 560 by the level-converted, amplified modulation signal AMS2 output by the drive circuit 50, and charge is accumulated. The current used to accumulate charge in the piezoelectric element 60 and the demodulation circuit 560 is supplied via capacitor C13 included in the drive circuit 50. As a result, the charge accumulated in capacitor C13 is released, increasing the likelihood that the voltage value of capacitor C13 will drop. During the period from time t30 to time t40, while the level shifter circuit 70 executes counter pulse control UCP, causing the gate driver circuit 730 to output the gate signal HGD2 that controls the transistor M3 to a non-conductive state and the gate signal LGD2 that controls the transistor M4 to a conductive state, current is supplied to the piezoelectric element 60 and the demodulation circuit 560 without passing through the capacitor C13 of the bootstrap circuit BS. Specifically, the execution of counter pulse control UCP during the period from time t30 to time t40 reduces the likelihood of charge accumulated in the capacitor C13 of the bootstrap circuit BS being discharged. In other words, the likelihood of a voltage drop across the capacitor C13 of the bootstrap circuit BS is reduced.

[0142] As previously mentioned, if the voltage value of capacitor C13 included in bootstrap circuit BS drops, there is a risk of distortion in the signal waveform of drive signal COM output by drive circuit 50. In contrast, in the drive circuit 50 included in the liquid ejection device 1 of this embodiment, the possibility of a drop in the voltage value held by capacitor C13 is reduced by executing counter pulse control UCP during the period from time t30 to time t40. As a result, the drop in the voltage value of capacitor C13 reduces the possibility of distortion in the signal waveform of drive signal COM output by drive circuit 50.

[0143] Furthermore, since the number of counter pulse control UCPs executed by the level shifter circuit 70 during the period from time t30 to time t40 is determined by the voltage value of the capacitor C13 included in the bootstrap circuit BS, the possibility of increased power consumption can be reduced by executing the counter pulse control UCP even when sufficient charge is stored in the capacitor C13. Furthermore, when sufficient charge is not stored in the capacitor C13, the discharge of the charge stored in the capacitor C13 can be reduced, thereby reducing the possibility of distortion in the signal waveform of the drive signal COM output by the drive circuit 50. Therefore, it is preferable that the number of counter pulse control UCPs executed by the level shifter circuit 70 be increased when the voltage value of the capacitor C13 included in the bootstrap circuit BS decreases.

[0144] Back to Figure 7 During the period from time t40 to time t50, the drive circuit 50 outputs a drive signal COM whose voltage value is constant at voltage vt. Specifically, during the period from time t40 to time t50, the basic drive signal output circuit 510 receives input of a basic drive signal dA for generating a drive signal COM whose voltage value is constant at voltage vt. Therefore, the basic drive signal output circuit 510 generates a basic drive signal aA, which is constant at voltage avt, based on the input basic drive signal dA. The basic drive signal output circuit 510 then outputs the generated basic drive signal aA to the modulation circuit 520 via the adder 511.

[0145] The modulation circuit 520 modulates the basic drive signal aA output by the basic drive signal output circuit 510 to generate a modulation signal MS. The modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logic level of the modulation signal MS is input to the gate driver 532. As a result, the gate driver circuit 530 outputs a gate signal HGD1 corresponding to the logic level of the modulation signal MS and a gate signal LGD1 corresponding to the signal obtained by inverting the logic level of the modulation signal MS. Then, transistors M1 and M2 of the amplifier circuit 550 operate based on the gate signals HGD1 and LGD1, respectively, to amplify the modulation signal MS based on the voltage value vhv1 of the voltage signal VHV1, resulting in an amplified modulation signal AMS1, which is output from the midpoint CP1.

[0146] Furthermore, the base drive signal output circuit 510 also outputs the base drive signal aA to the reference level switching circuit 710 included in the level shifter circuit 70. During the period from time t40 to time t50, the voltage value of the drive signal COM is greater than the voltage vth. Therefore, the voltage value of the base drive signal aA is greater than the voltage avth. Consequently, the reference level switching circuit 710 generates an H-level reference level switching signal LS. The H-level reference level switching signal LS is input to the gate driver 731, and the L-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an H-level gate signal HGD2 and an L-level gate signal LGD2.

[0147] Then, transistor M3 is controlled to be conductive by an H-level gate signal HGD2 output by gate driver circuit 730, and transistor M4 is controlled to be non-conductive by an L-level gate signal LGD2. Consequently, a level-converted amplified modulated signal AMS2 is output from midpoint CP2. The level-converted amplified modulated signal AMS1 output from midpoint CP1 of amplifier circuit 550 is level-converted based on voltage vhv2, the voltage value of voltage signal VHV2 input from bootstrap circuit BS. The resulting signal is then demodulated by demodulation circuit 560, and drive circuit 50 outputs drive signal COM, whose voltage value is constant at voltage vb.

[0148] Furthermore, during the period from time t40 to time t50, the reference level switching circuit 710 acquires and holds the voltage detection signal VCAP output by the voltage detection circuit 760. Alternatively, the reference level switching circuit 710 may acquire and hold the logic level of the voltage detection signal VCAP input to the reference level switching circuit 710 at predetermined timings during the period from time t40 to time t50. Alternatively, the reference level switching circuit 710 may acquire the logic level of the voltage detection signal VCAP multiple times during the period from time t40 to time t50, compare the number of times the voltage detection signal VCAP was acquired at an H level with the number of times the voltage detection signal VCAP was acquired at an L level, and hold the logic level with the greater number of acquisitions. Furthermore, the reference level switching circuit 710 may continuously acquire the logic level of the voltage detection signal VCAP at a predetermined period and, near time t50, hold the logic level of the voltage detection signal VCAP that has been continuously input multiple times. In addition, the reference level switching circuit 710 may discard the logic level of the voltage detection signal VCAP that has been held, when acquiring and holding the voltage detection signal VCAP at a new logic level.

[0149] During the period from time t50 to time t60, the drive circuit 50 outputs the drive signal COM whose voltage value changes from voltage vt to voltage vc. Specifically, during the period from time t50 to time t60, the basic drive signal output circuit 510 receives input of the basic drive signal dA used to generate the drive signal COM whose voltage value changes from voltage vt to voltage vc. Therefore, based on the input basic drive signal dA, the basic drive signal output circuit 510 generates the basic drive signal aA whose voltage value changes from voltage avt to voltage avc. The basic drive signal output circuit 510 then outputs the generated basic drive signal aA to the modulation circuit 520 via the adder 511.

[0150] The modulation circuit 520 modulates the basic drive signal aA output by the basic drive signal output circuit 510 to generate a modulation signal MS. The modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logic level of the modulation signal MS is input to the gate driver 532. As a result, the gate driver circuit 530 outputs a gate signal HGD1 corresponding to the logic level of the modulation signal MS and a gate signal LGD1 corresponding to the signal obtained by inverting the logic level of the modulation signal MS. Then, transistors M1 and M2 of the amplifier circuit 550 operate based on the gate signals HGD1 and LGD1, respectively, to amplify the modulation signal MS based on the voltage value vhv1 of the voltage signal VHV1, resulting in an amplified modulation signal AMS1, which is output from the midpoint CP1.

[0151] Furthermore, the base drive signal output circuit 510 also outputs the base drive signal aA to the reference level switching circuit 710 included in the level shifter circuit 70. During the period from time t50 to time t60, the voltage value of the drive signal COM is greater than the voltage vth. Therefore, the voltage value of the base drive signal aA is greater than the voltage avth. Consequently, the reference level switching circuit 710 generates an H-level reference level switching signal LS. The H-level reference level switching signal LS is input to the gate driver 731, and the L-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an H-level gate signal HGD2 and an L-level gate signal LGD2.

[0152] Then, transistor M3 is controlled to be conductive by an H-level gate signal HGD2 output by gate driver circuit 730, and transistor M4 is controlled to be non-conductive by an L-level gate signal LGD2. Consequently, a level-converted amplified modulated signal AMS2 is output from midpoint CP2. This level-converted amplified modulated signal AMS1, output from midpoint CP1 of amplifier circuit 550, is converted to a level based on voltage vhv2, the voltage value of voltage signal VHV2 input to bootstrap circuit BS. The resulting signal is then demodulated by demodulation circuit 560, causing driver circuit 50 to output a drive signal COM whose voltage value has been changed from voltage vt to voltage vc.

[0153] During the period from time t60 to time t70, the drive circuit 50 outputs a drive signal COM whose voltage value is constant at voltage vc. Specifically, during the period from time t60 to time t70, the basic drive signal output circuit 510 receives input of a basic drive signal dA for generating a drive signal COM whose voltage value is constant at voltage vc. Therefore, the basic drive signal output circuit 510 generates a basic drive signal aA, which is constant at voltage ac, based on the input basic drive signal dA. The basic drive signal output circuit 510 then outputs the generated basic drive signal aA to the modulation circuit 520 via the adder 511.

[0154] The modulation circuit 520 modulates the basic drive signal aA output by the basic drive signal output circuit 510 to generate a modulation signal MS. The modulation signal MS is input to the gate driver 531, and a signal obtained by inverting the logic level of the modulation signal MS is input to the gate driver 532. As a result, the gate driver circuit 530 outputs a gate signal HGD1 corresponding to the logic level of the modulation signal MS and a gate signal LGD1 corresponding to the signal obtained by inverting the logic level of the modulation signal MS. Then, transistors M1 and M2 of the amplifier circuit 550 operate based on the gate signals HGD1 and LGD1, respectively, to amplify the modulation signal MS based on the voltage value vhv1 of the voltage signal VHV1, resulting in an amplified modulation signal AMS1, which is output from the midpoint CP1.

[0155] Furthermore, the base drive signal output circuit 510 also outputs the base drive signal aA to the reference level switching circuit 710 included in the level shifter circuit 70. During the period from time t60 to time t70, the voltage value of the drive signal COM is greater than the voltage vth. Therefore, the voltage value of the base drive signal aA is greater than the voltage avth. Consequently, the reference level switching circuit 710 generates an H-level reference level switching signal LS. The H-level reference level switching signal LS is input to the gate driver 731, and the L-level signal obtained by inverting the logic level is input to the gate driver 732. As a result, the gate driver circuit 730 outputs an H-level gate signal HGD2 and an L-level gate signal LGD2.

[0156] Then, transistor M3 is controlled to be conductive by an H-level gate signal HGD2 output by gate driver circuit 730, and transistor M4 is controlled to be non-conductive by an L-level gate signal LGD2. Consequently, a level-converted amplified modulated signal AMS2 is output from midpoint CP2. This level-converted amplified modulated signal AMS1, output from midpoint CP1 of amplifier circuit 550, is converted to a level based on voltage vhv2, the voltage value of voltage signal VHV2 input to bootstrap circuit BS. The resulting signal is then demodulated by demodulation circuit 560, causing driver circuit 50 to output a drive signal COM whose voltage value is constant at voltage vc.

[0157] Furthermore, during the period from time t60 to time t70, the reference level switching circuit 710 acquires and holds the voltage detection signal VCAP output by the voltage detection circuit 760. Alternatively, the reference level switching circuit 710 may acquire and hold the logic level of the voltage detection signal VCAP input to the reference level switching circuit 710 at predetermined timings during the period from time t60 to time t70. Alternatively, the reference level switching circuit 710 may acquire the logic level of the voltage detection signal VCAP multiple times during the period from time t60 to time t70, compare the number of times the voltage detection signal VCAP was acquired at an H level with the number of times the voltage detection signal VCAP was acquired at an L level, and hold the logic level with the greater number of acquisitions. Furthermore, the reference level switching circuit 710 may continuously acquire the logic level of the voltage detection signal VCAP at a predetermined period and, near time t70, hold the logic level of the voltage detection signal VCAP that has been continuously input multiple times. In addition, the reference level switching circuit 710 may discard the logic level of the voltage detection signal VCAP that is already held, when acquiring and holding the voltage detection signal VCAP at a new logic level.

[0158] Here, as described above, the driving signal COM includes a signal waveform that is repeatedly executed with a period T. That is, Figure 7Time t70 shown corresponds to time t0 described above. As a result, the drive circuit 50 generates and outputs a drive signal COM including a signal waveform whose voltage value begins and ends at voltage vc. In this way, the reference level switching circuit 710 can also obtain and hold the voltage detection signal VCAP output by the voltage detection circuit 760 during the periods from time t60 to time t70 and from time t0 to time t10. That is, the reference level switching circuit 710 obtains and holds the logic level of the voltage detection signal VCAP input to the reference level switching circuit 710 at predetermined timings during the periods from time t60 to time t70 and from time t0 to time t10. Furthermore, the reference level switching circuit 710 acquires the logic level of the voltage detection signal VCAP multiple times between time t60 and time t70 and time t0 and time t10, and compares the number of times the voltage detection signal VCAP is acquired at an H level with the number of times the voltage detection signal VCAP is acquired at an L level, and holds the logic level with the greater number of acquisitions. Furthermore, the reference level switching circuit 710 may continuously acquire the logic level of the voltage detection signal VCAP at a predetermined period, and hold the logic level of the voltage detection signal VCAP that has been continuously input multiple times near time t10. Furthermore, the reference level switching circuit 710 may discard the previously held logic level of the voltage detection signal VCAP when acquiring and holding a new logic level of the voltage detection signal VCAP.

[0159] Here, the piezoelectric element 60 is an example of a capacitive load, and the drive circuit 50 corresponds to a capacitive load drive circuit. Furthermore, the drive signal COM output by the drive circuit 50 is an example of a drive signal. Since the drive signal VOUT is generated by selecting or deselecting the signal waveform of the drive signal COM, the drive signal VOUT is also an example of a drive signal. Furthermore, the base drive signal aA is an example of a base drive signal that serves as the basis for the drive signal COM. Since the base drive signal aA is a signal obtained by performing digital-to-analog conversion on the base drive signal dA, the base drive signal dA is also an example of a base drive signal that serves as the basis for the drive signal COM. Furthermore, the midpoint CP1 at which the amplifier circuit 550 outputs the amplified modulation signal AMS1 is an example of a first output point, and the midpoint CP2 at which the level shifter circuit 70 outputs the level-shifted amplified modulation signal AMS2 is an example of a second output point. Furthermore, the transistor M1 is an example of a first transistor, the gate signal HGD1 that activates the transistor M1 is an example of a first gate signal, and the voltage signal VHV1 input to the drain terminal of the transistor M1 is an example of a first voltage signal. Transistor M2 is an example of a second transistor, gate signal LGD1 that activates transistor M2 is an example of a second gate signal, and the ground potential signal supplied to the source terminal of transistor M2 is an example of a second voltage signal. Furthermore, gate driver circuit 530 that outputs gate signals HGD1 and LGD1 is an example of a first gate driver circuit. Furthermore, bootstrap circuit BS is an example of a bootstrap circuit, voltage signal VHV2 input to bootstrap circuit BS is an example of a third voltage signal, voltage signal VHV3 output by bootstrap circuit BS is an example of a fourth voltage signal, and capacitor C13 included in bootstrap circuit BS is an example of a capacitor. Furthermore, transistor M3 is an example of a third transistor, gate signal HGD2 that activates transistor M3 is an example of a third gate signal, transistor M2 is an example of a fourth transistor, and gate signal LGD2 that activates transistor M2 is an example of a fourth gate signal. Furthermore, gate driver circuit 730 that outputs gate signals HGD2 and LGD2 is an example of a second gate driver circuit. The ground potential is an example of a first potential, and the voltage value of the voltage signal VHV2, i.e., the potential of the voltage vhv2, is an example of a second potential. Furthermore, the mode switching control MC12 is an example of a first control, the counter pulse control UCP is an example of a second control, the mode switching control MC21 is an example of a third control, and the counter pulse control DCP is an example of a fourth control.

[0160] 4. Effects

[0161] As described above, in the liquid ejection device 1 of the present embodiment, the driving circuit 50 includes: a modulation circuit 520, which outputs a modulation signal MS obtained by modulating the basic driving signal aA which is the basis of the driving signal COM; an amplifier circuit 550, which outputs an amplified modulation signal AMS1 obtained by amplifying the modulation signal MS to the midpoint CP1; a level conversion circuit 70, which outputs a level-converted amplified modulation signal AMS2 obtained by level-converting the reference potential of the amplified modulation signal AMS1 to the midpoint CP2; and a demodulation circuit 560, which outputs the driving signal COM by demodulating the level-converted amplified modulation signal AMS2.

[0162] Furthermore, when the level conversion circuit 70 switches from the first mode MD1 in which the transistor M3 is controlled to be in a non-conducting state and the transistor M4 is controlled to be in a conducting state, thereby outputting the level conversion amplified modulation signal AMS2 with the reference potential of the amplified modulation signal AMS1 set to the ground potential, to the second mode MD2 in which the transistor M3 is controlled to be in a conducting state and the transistor M4 is controlled to be in a non-conducting state, thereby outputting the level conversion amplified modulation signal AMS2 with the reference potential of the amplified modulation signal AMS1 converted to a potential based on a voltage vhv2 which is a higher potential than the ground potential, the gate driver circuit 730 switches from outputting the gate signal HGD2 which controls the transistor M3 to be in a non-conducting state and outputting the gate signal HGD2 which controls the transistor M3 to be in a conducting state and outputting the gate signal HGD2 which controls the transistor M3 to be in a non-conducting state and outputting the gate signal HGD2 which controls the transistor M4 to be in a conducting state The gate driver circuit 730 outputs the gate signal HGD2 for controlling the transistor M3 to be in the non-conducting state and the gate signal LGD2 for controlling the transistor M4 to be in the conducting state, and then outputs the gate signal HGD2 for controlling the transistor M3 to be in the conducting state and the gate signal LGD2 for controlling the transistor M4 to be in the non-conducting state, and after the mode switching control MC12, the counter pulse control UCP is executed once or multiple times, wherein the counter pulse control UCP is that the gate driver circuit 730 outputs the gate signal HGD2 for controlling the transistor M3 to be in the non-conducting state and the gate signal LGD2 for controlling the transistor M4 to be in the conducting state, and then outputs the gate signal HGD2 for controlling the transistor M3 to be in the conducting state and the gate signal LGD2 for controlling the transistor M4 to be in the non-conducting state.

[0163] Therefore, even when the operating mode of the level conversion circuit 70 changes from the first mode MD1 to the second mode MD2, the change in the reference potential of the amplified modulation signal AMS1 output as the level conversion amplified modulation signal AMS2 will be slowed down, resulting in a reduction in the possibility of deformation in the signal waveform of the drive signal COM output by the drive circuit 50.

[0164] Furthermore, when the level shifter circuit 70 transitions from the first mode MD1 in which it outputs the level-shifted amplified modulation signal AMS2, which sets the reference potential of the amplified modulation signal AMS1 to the ground potential, to the second mode MD2 in which it outputs the level-shifted amplified modulation signal AMS2, which shifts the reference potential of the amplified modulation signal AMS1 to a potential based on a voltage vhv2 that is higher than the ground potential, a current is supplied to the piezoelectric element 60 and the demodulation circuit 560 in response to the level-shifted amplified modulation signal AMS2 output by the drive circuit 50. Consequently, the charge accumulated in the capacitor C13 included in the bootstrap circuit BS of the drive circuit 50 decreases, increasing the likelihood that the voltage value of the capacitor C13 will decrease, and the likelihood that the signal waveform of the drive signal COM output by the drive circuit 50 will be distorted.

[0165] In contrast, by executing counter pulse control UCP in the level shifter circuit 70, current can be supplied to the piezoelectric element 60 and the demodulation circuit 560 without passing through the capacitor C13 of the bootstrap circuit BS. This reduces the amount of charge released from the capacitor C13 of the bootstrap circuit BS. In other words, the likelihood of a voltage drop across the capacitor C13 of the bootstrap circuit BS is reduced. As a result, in the second mode MD2, the potential of the level-shifted, amplified, and modulated signal AMS2 is more stable, thereby improving the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0166] Furthermore, the number of times the level shifter circuit 70 executes the counter pulse control UCP is determined based on the voltage value of the capacitor C13 detected by the voltage detection circuit 760. Thus, even when sufficient charge is stored in the capacitor C13, it is possible to reduce the increase in power consumption that would otherwise occur due to the execution of the counter pulse control UCP. Furthermore, when sufficient charge is not stored in the capacitor C13, the possibility of the charge stored in the capacitor C13 being discharged is reduced, thereby reducing the possibility of a decrease in the voltage value held by the capacitor C13. Consequently, the possibility of distortion in the signal waveform of the drive signal COM output by the drive circuit 50 is reduced.

[0167] That is, in the liquid ejection device 1 of this embodiment, when changing from the first mode MD1 to the second mode MD2, the counter pulse control UCP is executed once or multiple times according to the voltage value maintained by the capacitor C13, thereby reducing the possibility of increased power consumption while reducing the possibility of deformation in the signal waveform of the drive signal COM.

[0168] In addition, the level conversion circuit 70 of the driving circuit 50 in the liquid ejection device 1 of the present embodiment switches from the second mode MD2 in which the reference potential level of the amplified modulation signal AMS1 is converted to a potential based on a voltage vhv2 which is a higher potential than the ground potential, to the first mode MD1 in which the reference potential of the amplified modulation signal AMS1 is set to the ground potential, and the gate driver circuit 730 switches from outputting the gate signal HGD2 which controls the transistor M3 to be in the conductive state and the gate signal LGD which controls the transistor M4 to be in the non-conductive state. 2, and after the mode switching control MC21, the counter pulse control UCP is executed once or multiple times, wherein the gate driver circuit 730 outputs the gate signal HGD2 for controlling the transistor M3 to be in the conductive state and the gate signal LGD2 for controlling the transistor M4 to be in the non-conductive state, and then outputs the gate signal HGD2 for controlling the transistor M3 to be in the non-conductive state and the gate signal LGD2 for controlling the transistor M4 to be in the conductive state.

[0169] Therefore, even when the operating mode of the level conversion circuit 70 changes from the second mode MD2 to the first mode MD1, the change in the reference potential of the amplified modulation signal AMS1 output as the level conversion amplified modulation signal AMS2 will be slowed down, resulting in a reduction in the possibility of deformation in the signal waveform of the drive signal COM output by the drive circuit 50.

[0170] Furthermore, when the circuit 70 transitions from the second mode MD2 in which the level-converted amplified modulation signal AMS2 is output, which converts the reference potential of the amplified modulation signal AMS1 to a potential based on a voltage vhv2 higher than the ground potential, to the first mode MD1 in which the level-converted amplified modulation signal AMS2 is output, with the reference potential of the amplified modulation signal AMS1 set to the ground potential, the charge accumulated in the piezoelectric element 60 and the demodulation circuit 560 is discharged toward the driver circuit 50. At this time, while the level-converting circuit 70 executes counter pulse control DCP, causing the gate driver circuit 730 to output a gate signal HGD2 that turns on transistor M3 and a gate signal LGD2 that turns off transistor M4, the current supplied to the driver circuit 50 is supplied to capacitor C13 via transistor M3. Specifically, the execution of counter pulse control DCP causes a regenerative current to flow through capacitor C13 of the bootstrap circuit BS, resulting in charge accumulation in capacitor C13. As a result, the possibility of the voltage value of the capacitor C13 of the bootstrap circuit BS decreasing is reduced, and as a result, the potential of the level-converting amplified modulation signal AMS2 in the second mode MD2 is relatively stable, thereby improving the waveform accuracy of the signal waveform of the drive signal COM output by the drive circuit 50.

[0171] Furthermore, because the number of counter pulse control DCPs executed by the level shifter circuit 70 is determined by the voltage value of the capacitor C13 included in the bootstrap circuit BS, the likelihood of excessive charge being supplied to the capacitor C13 is reduced even when sufficient charge is stored in the capacitor C13, thereby reducing the likelihood of increased power consumption associated with the counter pulse control DCP. Furthermore, if sufficient charge is not stored in the capacitor C13, sufficient charge can be stored in the capacitor C13 through the regenerative current. Consequently, the likelihood of distortion in the signal waveform of the drive signal COM output by the drive circuit 50 is reduced.

[0172] That is, in the liquid ejection device 1 of this embodiment, by executing the counter pulse control DCP once or multiple times according to the voltage value maintained by the capacitor C13 when changing from the second mode MD2 to the first mode MD1, the possibility of increased power consumption can be reduced while reducing the possibility of deformation in the signal waveform of the drive signal COM.

[0173] 5. Modifications

[0174] Although the driving circuit 50 of the liquid ejection device 1 of the present embodiment described above is described as follows, that is, the mode switching control MC21 is implemented during the period from time t10 to time t20, and thereafter, the counter pulse control DCP is executed once or repeatedly executed multiple times based on the voltage detection signal VCAP, and the mode switching control MC12 is implemented during the period from time t30 to time t40, and thereafter, the counter pulse control UCP is executed once or repeatedly executed multiple times based on the voltage detection signal VCAP, either the counter pulse control DCP during the period from time t10 to time t20 or the counter pulse control UCP during the period from time t30 to time t40 may be executed independently of the number of times the voltage detection signal VCAP is output, or may not be executed.

[0175] Furthermore, in the above-described drive circuit 50 of the liquid ejection device 1, the voltage detection circuit 760 includes a comparator that generates a logic-level signal indicating whether the acquired voltage value of the capacitor C13 is equal to or greater than a predetermined threshold value, and the voltage detection circuit 760 outputs the logic-level signal as the voltage detection signal VCAP to the reference-level switching circuit 710. However, the voltage detection circuit 760 may also include an analog-to-digital converter that generates a digital signal including the acquired voltage value of the capacitor C13, and the voltage detection circuit 760 outputs the digital signal as the voltage detection signal VCAP to the reference-level switching circuit 710. In this case, the reference-level switching circuit 710 may acquire and hold the voltage detection signal VCAP of the digital signal input at a predetermined timing, or may calculate an arithmetic average, a moving average, a weighted average, or the like of the voltage detection signal VCAP of the digital signal input over a predetermined period and hold the calculation result.

[0176] Furthermore, in the drive circuit 50 of the liquid ejection device 1 described above, the period T of the drive signal COM output by the drive circuit 50 can be changed based on the voltage value of the capacitor C13 detected by the voltage detection circuit 760, and the number of nozzles driven by the drive signal VOUT based on the drive signal COM can be limited. This improves the charging efficiency of the capacitor C13 included in the bootstrap circuit BS of the drive circuit 50, and as a result, further reduces the possibility of a drop in the voltage value of the capacitor C13.

[0177] Furthermore, the drive circuit 50 of the liquid ejection device 1 described above may be configured so that when the voltage value of the capacitor C13 measured by the voltage detection circuit 760 falls below a predetermined voltage value, the drive circuit 50 notifies the control unit 100 of this fact, and the control unit 100 stops the operation of the drive circuit 50 based on the notification from the drive circuit 50. Thus, when the voltage value of the capacitor C13 falls to a level that makes it difficult to reduce the distortion of the waveform of the drive signal COM, the possibility of the drive circuit 50 continuing to operate is reduced.

[0178] Furthermore, the drive circuit 50 of the liquid ejection device 1 described above may be configured so that, when the voltage value of the capacitor C13 measured by the voltage detection circuit 760 falls below a predetermined voltage value, the drive circuit 50 notifies the control unit 100 of this fact, and the control unit 100 causes an external device (not shown) provided outside the liquid ejection device 1, such as a host computer, to display information indicating that an abnormality has occurred in the drive circuit 50. Thus, when the voltage value of the capacitor C13 falls to a level that makes it difficult to reduce the distortion of the waveform of the drive signal COM, this fact can be notified to the user.

[0179] In addition, although the above-described drive circuit 50 of the liquid ejection device 1 is described as a structure in which the voltage detection circuit 760 measures the voltage value between the two terminals of the capacitor C13, the voltage detection circuit 760 may also measure the voltage at the cathode terminal of the diode D13 electrically connected to the capacitor C13. This simplifies the structure of the voltage detection circuit 760 and enables miniaturization and cost reduction of the drive circuit 50 and the liquid ejection device 1.

[0180] Although the embodiments have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit and scope of the present invention. For example, the above-described embodiments can be appropriately combined.

[0181] The present invention includes structures that are substantially the same as the structures described in the embodiments (for example, structures having the same functions, methods, and results, or structures having the same purposes and effects). In addition, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that have the same effects as the structures described in the embodiments, or structures that can achieve the same purposes. In addition, the present invention includes structures that add known technologies to the structures described in the embodiments.

[0182] The following can be derived from the above-mentioned embodiments.

[0183] One embodiment of a liquid ejection device comprises: a liquid ejection head having a capacitive load driven by a supply of a drive signal, and ejecting liquid by driving the capacitive load; a capacitive load drive circuit that outputs the drive signal, the capacitive load drive circuit comprising: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulated signal obtained by level-converting a reference potential of the amplified modulated signal to a second output point; a demodulation circuit that outputs the drive signal by demodulating the level-converted amplified modulated signal, the amplifier circuit comprising: a first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulated signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point The first gate driver circuit includes a first transistor and a second transistor connected to the first output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second transistor connected to the second output point, and the fourth transistor connected to the second output point, and the fourth transistor connected to the second gate driver circuit includes a first mode in which the first transistor and the second transistor are controlled to be non-conductive and conductive, thereby outputting the level-converted amplified modulated signal with the reference potential of the amplified modulated signal set to a first potential.The second mode is a mode in which the level-converted amplified modulation signal is outputted by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby converting the reference potential level of the amplified modulation signal to a second potential higher than the first potential. When the first mode is changed to the second mode, the level conversion circuit performs a first control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conducting state and the fourth gate signal for controlling the fourth transistor to be in a non-conducting state, and after the first control, the level shifter circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conducting state and the fourth gate signal for controlling the fourth transistor to be in a conducting state, and then outputs the third gate signal for controlling the third transistor to be in a conducting state and the fourth gate signal for controlling the fourth transistor to be in a non-conducting state.

[0184] According to this liquid ejection device, in the driving circuit, when a mode is changed from a first mode in which a level-converted amplified modulated signal is outputted, which sets the reference potential of the amplified modulated signal to a first potential, to a second mode in which a level-converted amplified modulated signal is outputted, which converts the reference potential of the amplified modulated signal to a second potential higher than the first potential, first control is executed. The first control is control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to a non-conductive state and the fourth gate signal for controlling the fourth transistor to a conductive state, and then outputs the third gate signal for controlling the third transistor to a conductive state and the fourth gate signal for controlling the fourth transistor to a non-conductive state. After the first control, the second control is executed one or more times based on the voltage value of the capacitor detected by the voltage detection circuit. The second control is control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to a non-conductive state and the fourth gate signal for controlling the fourth transistor to a conductive state, and then outputs the third gate signal for controlling the third transistor to a conductive state and the fourth gate signal for controlling the fourth transistor to a non-conductive state. Thus, when transitioning from the first mode to the second mode, the likelihood of distortion in the drive signal waveform due to fluctuations in the reference potential of the amplified modulation signal output as the level-shifted amplified modulation signal is reduced. Furthermore, in the second control, the second gate driver circuit outputs a third gate signal for controlling the third transistor to a non-conductive state and a fourth gate signal for controlling the fourth transistor to a conductive state. This reduces the likelihood of charge being released from the capacitor included in the bootstrap circuit, thereby reducing the likelihood of a drop in the voltage value held by the capacitor included in the bootstrap circuit. Consequently, the potential of the level-shifted amplified modulation signal is stabilized, reducing the likelihood of distortion in the drive signal waveform.

[0185] In addition, by determining the number of times the second control is performed according to the voltage value of the capacitor detected by the voltage detection circuit, it is possible to control whether the charge of the capacitor is released according to the amount of charge accumulated in the capacitor, thereby reducing the power consumption of the capacitive load driving circuit.

[0186] That is, according to the liquid ejection device, the waveform accuracy of the driving signal output by the capacitive load driving circuit can be improved, and the power consumption of the capacitive load driving circuit can be reduced.

[0187] In one aspect of the liquid ejection device, when the voltage value of the capacitor detected by the voltage detection circuit decreases, the number of times the second control is performed by the level conversion circuit may be increased.

[0188] According to this liquid ejection device, when the voltage value of the capacitor drops, the possibility of the charge accumulated in the capacitor being discharged can be further reduced by increasing the number of times the second control is performed by the level conversion circuit.

[0189] In one embodiment of the liquid ejection device, the level conversion circuit may execute a third control when transitioning from the second mode to the first mode, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conducting state and the fourth gate signal for controlling the fourth transistor to be in a non-conducting state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conducting state, and after the third control, the level conversion circuit executes a fourth control one or more times based on the voltage value of the capacitor detected by the voltage detection circuit, wherein the fourth control is control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conducting state, and then outputs the third gate signal for controlling the third transistor to be in a non-conducting state and the fourth gate signal for controlling the fourth transistor to be in a conductive state.

[0190] According to this liquid ejection device, in the driving circuit, when the second mode in which the level-converted amplified modulated signal is output, which converts the reference potential level of the amplified modulated signal to a second potential higher than the first potential, is changed to the first mode in which the level-converted amplified modulated signal is output, which sets the reference potential of the amplified modulated signal to the first potential, third control is executed. The third control is control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be non-conductive, and then outputs the third gate signal for controlling the third transistor to be non-conductive and the fourth gate signal for controlling the fourth transistor to be conductive. After the third control, the fourth control is executed one or more times based on the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be non-conductive, and then outputs the third gate signal for controlling the third transistor to be non-conductive and the fourth gate signal for controlling the fourth transistor to be conductive. Thus, when transitioning from the second mode to the first mode, the likelihood of distortion in the drive signal's waveform due to fluctuations in the reference potential of the amplified modulation signal output as the level-shifted amplified modulation signal is reduced. Furthermore, in the fourth control, the second gate driver circuit outputs a third gate signal that turns the third transistor on and a fourth gate signal that turns the fourth transistor off, thereby charging the capacitor included in the bootstrap circuit with a regenerative current. As a result, the likelihood of a drop in the voltage value held by the capacitor included in the bootstrap circuit is reduced. Consequently, the potential of the level-shifted amplified modulation signal is more stable, reducing the likelihood of distortion in the drive signal's waveform.

[0191] In addition, by determining the number of times the fourth control is performed according to the voltage value of the capacitor detected by the voltage detection circuit, it is possible to control whether the charge is charged to the capacitor according to the amount of charge accumulated in the capacitor, thereby reducing the power consumption of the capacitive load driving circuit.

[0192] That is, according to the liquid ejection device, the waveform accuracy of the driving signal output by the capacitive load driving circuit can be further improved, and the power consumption of the capacitive load driving circuit can be further reduced.

[0193] One embodiment of a liquid ejection device comprises: a liquid ejection head having a capacitive load driven by a supply of a drive signal, and ejecting liquid by driving the capacitive load; a capacitive load drive circuit that outputs the drive signal, the capacitive load drive circuit comprising: a modulation circuit that outputs a modulation signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting a reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the drive signal by demodulating the level-converted amplified modulation signal, the amplifier circuit comprising: a first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point The first gate driver circuit includes a first transistor and a second transistor connected to the first output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second gate driver circuit includes a first transistor and a second transistor connected to the second output point, and the second transistor connected to the second output point, and the fourth transistor connected to the second output point, and the fourth transistor connected to the second gate driver circuit includes a first mode in which the first transistor is controlled to be non-conductive and the fourth transistor is controlled to be conductive, thereby outputting the level-converted amplified modulation signal with the reference potential of the amplified modulation signal set to a first potential.The second mode is a mode in which the level-converted amplified modulation signal is outputted by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby converting the reference potential level of the amplified modulation signal to a second potential higher than the first potential. When the second mode is changed to the first mode, the level conversion circuit performs a third control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, starting from the state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and after the third control, the level shifter circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the fourth control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state.

[0194] According to this liquid ejection device, in the driving circuit, when the second mode of outputting the level-converted amplified modulated signal that converts the reference potential level of the amplified modulated signal to a second potential higher than the first potential is changed to the first mode of outputting the level-converted amplified modulated signal that sets the reference potential of the amplified modulated signal to the first potential, third control is executed. The third control is control in which the second gate driver circuit, starting from a state in which the third gate signal that controls the third transistor to be conductive and the fourth gate signal that controls the fourth transistor to be non-conductive, outputs the third gate signal that controls the third transistor to be non-conductive and the fourth gate signal that controls the fourth transistor to be conductive. After the third control, fourth control is executed one or more times based on the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is control in which the second gate driver circuit outputs the third gate signal that controls the third transistor to be conductive and the fourth gate signal that controls the fourth transistor to be non-conductive, and then outputs the third gate signal that controls the third transistor to be conductive and the fourth gate signal that controls the fourth transistor to be conductive. Thus, when transitioning from the second mode to the first mode, the likelihood of distortion in the drive signal's waveform due to fluctuations in the reference potential of the amplified modulation signal output as the level-shifted amplified modulation signal is reduced. Furthermore, in the fourth control, the second gate driver circuit outputs a third gate signal that turns the third transistor on and a fourth gate signal that turns the fourth transistor off, thereby charging the capacitor included in the bootstrap circuit with a regenerative current. As a result, the likelihood of a drop in the voltage value held by the capacitor included in the bootstrap circuit is reduced. Consequently, the potential of the level-shifted amplified modulation signal is more stable, reducing the likelihood of distortion in the drive signal's waveform.

[0195] Furthermore, by determining the number of times the fourth control is executed based on the voltage value of the capacitor detected by the voltage detection circuit, whether or not to charge the capacitor can be controlled based on the amount of charge accumulated in the capacitor, thereby reducing power consumption of the drive circuit.

[0196] That is, according to this liquid ejection device, the waveform accuracy of the drive signal output by the drive circuit is improved, and the power consumption of the drive circuit can be reduced.

[0197] In one aspect of the liquid ejection device, when the voltage value of the capacitor detected by the voltage detection circuit decreases, the number of times the fourth control is executed by the level conversion circuit may be increased.

[0198] According to this liquid ejection device, when the voltage value of the capacitor drops, the possibility of the charge accumulated in the capacitor being discharged can be further reduced by increasing the number of times the level shift circuit performs the fourth control.

[0199] In one aspect of the liquid ejection device, the voltage detection circuit may include a comparator.

[0200] In one aspect of the liquid ejection device, the voltage detection circuit may include an analog-to-digital converter.

[0201] In one embodiment of the liquid ejection device, the level conversion circuit can also be set to become the first mode when the voltage value specified by the basic drive signal is a first voltage value, and to become the second mode when the voltage value specified by the basic drive signal is a second voltage value larger than the first voltage value.

[0202] In one embodiment of the liquid ejection device, the capacitive load may be a piezoelectric element.

[0203] One embodiment of a capacitive load driving circuit is a capacitive load driving circuit that outputs a driving signal to a liquid ejecting head, wherein the liquid ejecting head has a capacitive load driven by being supplied with the driving signal and ejects liquid by being driven by the capacitive load, and the capacitive load driving circuit has: a modulation circuit that outputs a modulation signal obtained by modulating a basic driving signal serving as a basis for the driving signal; an amplifier circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting a reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the driving signal by demodulating the level-converted amplified modulation signal, and the amplifier circuit includes: a first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor, one end of which is supplied with a first voltage signal and the other end of which is electrically connected to the first output point and operates based on the first gate signal; a second transistor, one end of which is electrically connected to the first output point; a first gate driver circuit configured to output a first gate signal and a second gate signal; a first gate driver circuit configured to output a first gate signal and a second gate signal; a first gate driver circuit configured to output a first gate signal and a fourth gate signal based on the first gate signal; a first transistor configured to output a first gate signal and a second ...The second mode is a mode in which the level-converted amplified modulation signal is outputted by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby converting the reference potential level of the amplified modulation signal to a second potential higher than the first potential. When the first mode is changed to the second mode, the level conversion circuit performs a first control in which the second gate driver circuit outputs a signal for controlling the third transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and after the first control, the level shifter circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state.

[0204] According to this capacitive load driving circuit, when a transition is made from a first mode in which a level-converted amplified modulated signal is outputted, in which the reference potential of the amplified modulated signal is set to a first potential, to a second mode in which a level-converted amplified modulated signal is outputted, in which the second gate driver circuit outputs a third gate signal for controlling the third transistor to be in a non-conductive state and a fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs a third gate signal for controlling the third transistor to be in a conductive state and a fourth gate signal for controlling the fourth transistor to be in a non-conductive state. Furthermore, after the first control, a second control is executed one or more times based on the voltage value of the capacitor detected by the voltage detection circuit. The second control is executed in which the second gate driver circuit outputs a third gate signal for controlling the third transistor to be in a non-conductive state and a fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs a third gate signal for controlling the third transistor to be in a conductive state and a fourth gate signal for controlling the fourth transistor to be in a non-conductive state. Thus, when transitioning from the first mode to the second mode, the likelihood of distortion in the drive signal waveform due to fluctuations in the reference potential of the amplified modulation signal output as the level-shifted amplified modulation signal is reduced. Furthermore, in the second control, the second gate driver circuit outputs a third gate signal for controlling the third transistor to a non-conductive state and a fourth gate signal for controlling the fourth transistor to a conductive state. This reduces the likelihood of charge being discharged from the capacitor included in the bootstrap circuit, thereby reducing the likelihood of a drop in the voltage value held by the capacitor included in the bootstrap circuit. Consequently, the potential of the level-shifted amplified modulation signal is stabilized, reducing the likelihood of distortion in the drive signal waveform.

[0205] Furthermore, by defining the number of times the second control is executed based on the voltage value of the capacitor detected by the voltage detection circuit, whether or not the charge of the capacitor is discharged can be controlled based on the amount of charge stored in the capacitor, resulting in reduced power consumption.

[0206] That is, according to this capacitive load driving circuit, the waveform accuracy of the driving signal can be improved and the power consumption can be reduced.

[0207] One embodiment of a capacitive load driving circuit is a capacitive load driving circuit that outputs a driving signal to a liquid ejecting head, wherein the liquid ejecting head has a capacitive load driven by being supplied with the driving signal and ejects liquid by being driven by the capacitive load, and the capacitive load driving circuit has: a modulation circuit that outputs a modulation signal obtained by modulating a basic driving signal serving as a basis for the driving signal; an amplifier circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal to a first output point; a level conversion circuit that outputs a level-converted amplified modulation signal obtained by level-converting a reference potential of the amplified modulation signal to a second output point; a demodulation circuit that outputs the driving signal by demodulating the level-converted amplified modulation signal, and the amplifier circuit includes: a first gate driver circuit that outputs a first gate signal and a second gate signal based on the modulation signal; a first transistor, one end of which is supplied with a first voltage signal and the other end of which is electrically connected to the first output point and operates based on the first gate signal; a second transistor, one end of which is electrically connected to the first output point; a first gate driver circuit configured to output a first gate signal and a second gate signal; a first gate driver circuit configured to output a first gate signal and a second gate signal; a first gate driver circuit configured to output a first gate signal and a fourth ...The second mode is a mode in which the reference potential level of the amplified modulation signal is converted to a second potential higher than the first potential by controlling the third transistor to be in a conductive state and the fourth transistor to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal. When the second mode is changed to the first mode, the level conversion circuit performs a third control, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state. The second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and after the third control, the level conversion circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the fourth control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and thereafter outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state.

[0208] According to this capacitive load driving circuit, when the mode changes from the second mode of outputting the level-converted amplified modulated signal that converts the reference potential level of the amplified modulated signal to a second potential higher than the first potential to the first mode of outputting the level-converted amplified modulated signal that sets the reference potential of the amplified modulated signal to the first potential, a third control is executed. The third control is control in which the second gate driver circuit outputs the third gate signal that controls the third transistor to be in a non-conductive state and the fourth gate signal that controls the fourth transistor to be in a conductive state, starting from the state in which the third gate signal that controls the third transistor to be in a conductive state and the fourth gate signal that controls the fourth transistor to be in a non-conductive state. After the third control, the fourth control is executed one or more times based on the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is control in which the second gate driver circuit outputs the third gate signal that controls the third transistor to be in a conductive state and the fourth gate signal that controls the fourth transistor to be in a non-conductive state, and then outputs the third gate signal that controls the third transistor to be in a non-conductive state and the fourth gate signal that controls the fourth transistor to be in a conductive state. Thus, when transitioning from the second mode to the first mode, the likelihood of distortion in the drive signal's waveform due to fluctuations in the reference potential of the amplified modulation signal output as the level-shifted amplified modulation signal is reduced. Furthermore, in the fourth control, the second gate driver circuit outputs a third gate signal that turns the third transistor on and a fourth gate signal that turns the fourth transistor off, thereby charging the capacitor included in the bootstrap circuit with a regenerative current. As a result, the likelihood of a drop in the voltage value held by the capacitor included in the bootstrap circuit is reduced. Consequently, the potential of the level-shifted amplified modulation signal is more stable, reducing the likelihood of distortion in the drive signal's waveform.

[0209] Furthermore, by defining the number of times the fourth control is executed based on the voltage value of the capacitor detected by the voltage detection circuit, whether or not to charge the capacitor can be controlled based on the amount of charge stored in the capacitor, thereby reducing power consumption.

[0210] That is, according to the capacitive load driving circuit, the waveform accuracy of the driving signal is improved and the power consumption can be reduced.

[0211] Explanation of symbols

[0212] 1…Liquid ejecting device; 2…Moving body; 3…Moving unit; 4…Conveying unit; 10…Control unit; 11…Power supply circuit; 20…Head unit; 21…Liquid ejecting head; 24…Slide; 31…Slide motor; 32…Slide guide shaft; 33…Timing belt; 40…Platen; 41…Conveying motor; 42…Conveying roller; 50…Drive circuit; 60…Piezoelectric element; 70…Level conversion circuit; 100…Control unit; 190…Cable; 210…Selection control unit; 230…Selection unit; 510…Basic drive signal output circuit; 511…Adder; 520…Modulation circuit; 521…Inverter; 530…Gate driver circuit; 531, 532…Gate driver ;550…amplifier circuit;560…demodulator circuit;570…feedback circuit;600…ejector;601…piezoelectric body;611, 612…electrode;621…vibration plate;631…chamber;632…nozzle plate;641…reservoir;651…nozzle;710…reference level switching circuit;721…inverter;730…gate driver circuit;731, 732…gate driver;760…voltage detection circuit;BS…bootstrap circuit;C1…capacitor;C10~C13…capacitors;CP1, CP2…midpoint;D1…diode;D11~D13…diode;L…nozzle array;L10…inductor;M1~M4…transistor;P…dielectric.

Claims

1. A liquid ejection device, characterized in that: have: a liquid ejection head having a capacitive load driven by supplying a driving signal and ejecting liquid by driving the capacitive load; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential that is higher than the first potential; In the case of transition from the first mode to the second mode, The level conversion circuit performs a first control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and After the first control, the level conversion circuit performs a second control once or multiple times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conducting state and the fourth gate signal for controlling the fourth transistor to be in a conducting state, and then outputs the third gate signal for controlling the third transistor to be in a conducting state and the fourth gate signal for controlling the fourth transistor to be in a non-conducting state.

2. The liquid ejection device according to claim 1, wherein When the voltage value of the capacitor detected by the voltage detection circuit decreases, the number of times the second control is performed by the level conversion circuit increases.

3. A liquid ejection device, characterized in that: have: a liquid ejection head having a capacitive load driven by supplying a driving signal and ejecting liquid by driving the capacitive load; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential that is higher than the first potential; In the case of transition from the first mode to the second mode, The level conversion circuit performs a first control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and After the first control, the level conversion circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state. The level conversion circuit performs third control when transitioning from the second mode to the first mode, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and After the third control, the level conversion circuit performs a fourth control once or multiple times according to the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state.

4. A liquid ejection device, characterized in that: have: a liquid ejection head having a capacitive load driven by supplying a driving signal and ejecting liquid by driving the capacitive load; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential that is higher than the first potential; In the case of transition from the first mode to the second mode, The level conversion circuit performs a first control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and After the first control, the level conversion circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state. The level conversion circuit performs third control when transitioning from the second mode to the first mode, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and After the third control, the level conversion circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. When the voltage value of the capacitor detected by the voltage detection circuit decreases, the number of times the second control is performed by the level conversion circuit increases.

5. A liquid ejection device, characterized in that: have: a liquid ejection head having a capacitive load driven by supplying a driving signal and ejecting liquid by driving the capacitive load; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential higher than the first potential; In the case of transition from the second mode to the first mode, The level conversion circuit performs third control, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and After the third control, the level conversion circuit performs a fourth control once or multiple times according to the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state.

6. A liquid ejection device, characterized in that: have: a liquid ejection head having a capacitive load driven by supplying a driving signal and ejecting liquid by driving the capacitive load; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential that is higher than the first potential; In the case of transition from the first mode to the second mode, The level conversion circuit performs a first control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and After the first control, the level conversion circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state. The level conversion circuit performs third control when transitioning from the second mode to the first mode, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and After the third control, the level conversion circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. When the voltage value of the capacitor detected by the voltage detection circuit decreases, the number of times the fourth control is performed by the level conversion circuit increases.

7. A liquid ejection device, characterized in that: have: a liquid ejection head having a capacitive load driven by supplying a driving signal and ejecting liquid by driving the capacitive load; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential that is higher than the first potential; In the case of transition from the first mode to the second mode, The level conversion circuit performs a first control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and After the first control, the level conversion circuit performs a second control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and then outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state. The level conversion circuit performs third control when transitioning from the second mode to the first mode, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and After the third control, the level conversion circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. When the voltage value of the capacitor detected by the voltage detection circuit decreases, the number of times the second control and the number of times the fourth control are performed by the level conversion circuit increase.

8. A liquid ejection device, characterized in that: have: a liquid ejection head having a capacitive load driven by supplying a driving signal and ejecting liquid by driving the capacitive load; a capacitive load driving circuit, which outputs the driving signal, The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential higher than the first potential; In the case of transition from the second mode to the first mode, The level conversion circuit performs third control, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and After the third control, the level conversion circuit performs a fourth control one or more times according to the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is a control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state. When the voltage value of the capacitor detected by the voltage detection circuit decreases, the number of times the fourth control is performed by the level conversion circuit increases.

9. The liquid ejection device according to any one of claims 1 to 8, wherein: The voltage detection circuit includes a comparator.

10. The liquid ejection device according to any one of claims 1 to 8, wherein: The voltage detection circuit includes an analog-to-digital converter.

11. The liquid ejecting device according to any one of claims 1 to 8, wherein: The level shifter circuit enters the first mode when the voltage value specified by the basic drive signal is a first voltage value, and enters the second mode when the voltage value specified by the basic drive signal is a second voltage value greater than the first voltage value.

12. The liquid ejection device according to any one of claims 1 to 8, wherein: The capacitive load is a piezoelectric element.

13. A capacitive load driving circuit, characterized in that: The liquid ejection head outputs a driving signal to the liquid ejection head. The liquid ejection head has a capacitive load driven by the driving signal and ejects liquid by the driving of the capacitive load. The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential higher than the first potential; In the case of transition from the first mode to the second mode, The level conversion circuit performs a first control in which the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, and After the first control, the level conversion circuit performs a second control once or multiple times according to the voltage value of the capacitor detected by the voltage detection circuit, wherein the second control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conducting state and the fourth gate signal for controlling the fourth transistor to be in a conducting state, and then outputs the third gate signal for controlling the third transistor to be in a conducting state and the fourth gate signal for controlling the fourth transistor to be in a non-conducting state.

14. A capacitive load driving circuit, characterized in that: The liquid ejection head outputs a driving signal to the liquid ejection head. The liquid ejection head has a capacitive load driven by the driving signal and ejects liquid by the driving of the capacitive load. The capacitive load driving circuit comprises: a modulation circuit that outputs a modulated signal obtained by modulating a basic drive signal serving as a basis for the drive signal; an amplifier circuit configured to amplify the modulation signal and output an amplified modulation signal to a first output point; a level conversion circuit configured to output a level-converted amplified modulated signal obtained by level-converting the reference potential of the amplified modulated signal to a second output point; a demodulation circuit that demodulates the level-converted amplified modulation signal to output the driving signal; The amplifying circuit comprises: a first gate driver circuit outputting a first gate signal and a second gate signal based on the modulation signal; a first transistor having one end supplied with a first voltage signal and the other end electrically connected to the first output point, and operating based on the first gate signal; a second transistor having one end electrically connected to the first output point and the other end supplied with a second voltage signal and operating based on the second gate signal; The level conversion circuit includes: a bootstrap circuit comprising a capacitor, receiving a third voltage signal and the amplified modulation signal as input, and outputting a fourth voltage signal corresponding to the third voltage signal and the amplified modulation signal; a voltage detection circuit, which detects the voltage value of the capacitor; a second gate driver circuit outputting a third gate signal and a fourth gate signal based on the basic driving signal; a third transistor, one end of which is supplied with the fourth voltage signal, the other end of which is electrically connected to the second output point, and operates based on the third gate signal; a fourth transistor having one end electrically connected to the second output point and the other end supplied with the amplified modulation signal and operating based on the fourth gate signal; The level conversion circuit includes: a first mode in which the third transistor is controlled to be in a non-conductive state and the fourth transistor is controlled to be in a conductive state, thereby outputting the level-converted amplified modulation signal having a reference potential of the amplified modulation signal set to a first potential; a second mode in which the third transistor is controlled to be in a conductive state and the fourth transistor is controlled to be in a non-conductive state, thereby outputting the level-converted amplified modulation signal in which the reference potential level of the amplified modulation signal is converted to a second potential higher than the first potential; In the case of transition from the second mode to the first mode, The level conversion circuit performs third control, wherein the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state, starting from a state in which the second gate driver circuit is outputting the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and After the third control, the level conversion circuit performs a fourth control once or multiple times according to the voltage value of the capacitor detected by the voltage detection circuit. The fourth control is that the second gate driver circuit outputs the third gate signal for controlling the third transistor to be in a conductive state and the fourth gate signal for controlling the fourth transistor to be in a non-conductive state, and then outputs the third gate signal for controlling the third transistor to be in a non-conductive state and the fourth gate signal for controlling the fourth transistor to be in a conductive state.

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