Overcurrent protection circuit, driving circuit and display device

Abstract

The present application relates to an overcurrent protection circuit, a driving circuit and a display device. The overcurrent protection circuit includes: a detection resistor, a control switch, a differential operation amplifier module, a reference voltage generation module, a voltage comparison module and a logic control module; wherein, the detection resistor and the control switch are both serially arranged between a voltage source and a load in a level conversion chip. A first end of the differential operation amplifier module is connected to a first end of the detection resistor, and a second end of the differential operation amplifier module is connected to a second end of the detection resistor; a first end of the reference voltage generation module is connected to the voltage source, a second end of the reference voltage generation module is connected to a first end of the voltage comparison module, and a third end of the differential operation amplifier module is connected to a second end of the voltage comparison module; a third end of the voltage comparison module is connected to a first end of the logic control module, and a second end of the logic control module is connected to the control switch. In this way, the function of overcurrent protection can be further achieved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an overcurrent protection circuit, a driving circuit, and a display device. Background Art

[0002] Since the gate driven on array (GOA) circuit is a row scanning driving circuit fabricated by using the same process as that of thin film transistors (TFTs), it can achieve the function of progressive scanning driving based on only a few control signals provided by an external circuit. Therefore, driving by using the GOA circuit can reduce the manufacturing cost of liquid crystal displays, and thus it is widely used.

[0003] When driving a liquid crystal panel by using the GOA circuit, a level shifter (LS) chip is usually added to the front stage of the GOA circuit. The LS chip is used to convert the row scanning signals output by a timer control (TCON) chip into the VGL voltage (i.e., the TFT off voltage) and the VGH voltage (i.e., the TFT on voltage) required by the GOA circuit, and provide multiple signals required by the GOA circuit, such as a row driving start signal, a signal for turning on each row, a GOA circuit switching signal, a low level maintaining signal for turning off each row, etc. At the same time, in order to prevent the glass panel from causing a fire hazard due to abnormal high temperature when being accidentally damaged, the LS chip usually needs to have an over current protection (OCP) function. In this way, when the GOA circuit of the liquid crystal panel is accidentally damaged, the signals output by the LS chip may be short-circuited together, and the OCP function can achieve the effect of protecting the liquid crystal panel and preventing overheating.

[0004] However, in the prior art, the LS chip usually performs overcurrent protection only on the signals output from a single channel, that is, the OCP function is triggered only when the signal of any one channel reaches the threshold current. When multiple channels of signals output by the LS chip are short-circuited at the same time and the signals of multiple channels do not reach the threshold current, the LS chip cannot play the role of overcurrent protection. Therefore, how to further improve the overcurrent protection ability of the LS chip has become a technical problem to be solved urgently. Summary of the Invention

[0005] The present application provides an overcurrent protection circuit, a driving circuit, and a display device to solve the problem in the prior art that the LS chip usually performs overcurrent protection only on the signals output from a single channel, and when multiple channels of signals output by the LS chip are short-circuited at the same time and the signals of multiple channels do not reach the threshold current, the LS chip cannot play the role of overcurrent protection.

[0006] In a first aspect, an embodiment of the present application provides an overcurrent protection circuit, which is applied to a level conversion chip. The overcurrent protection circuit includes: a detection resistor, a control switch, a differential operational amplifier module, a reference voltage generation module, a voltage comparison module, and a logic control module;

[0007] Among them, the detection resistor and the control switch are both connected in series between the voltage source and the load in the level conversion chip. The first end of the differential operational amplifier module is connected to the first end of the detection resistor, and the second end of the differential operational amplifier module is connected to the second end of the detection resistor;

[0008] The first end of the reference voltage generation module is connected to the voltage source, the second end of the reference voltage generation module is connected to the first end of the voltage comparison module, and the third end of the differential operational amplifier module is connected to the second end of the voltage comparison module;

[0009] The third end of the voltage comparison module is connected to the first end of the logic control module, and the second end of the logic control module is connected to the control switch.

[0010] Optionally, the logic control module includes a first capacitor, a second capacitor, and a latch;

[0011] Among them, the first end of the first capacitor is connected to the voltage source, the second end of the first capacitor is respectively connected to the first end of the second capacitor and the first end of the latch, and the second end of the second capacitor is connected to the ground terminal;

[0012] The second end of the latch serves as the first end of the logic control module and is connected to the third end of the voltage comparison module. The third end of the latch serves as the second end of the logic control module and is connected to the control switch.

[0013] Optionally, the latch is composed of two NOR gates.

[0014] Optionally, the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0015] Optionally, the reference voltage generation module includes a third capacitor, a first resistor, a second resistor, and a zener diode;

[0016] Among them, the first end of the third capacitor and the first end of the first resistor are respectively connected to the voltage source. The second end of the third capacitor and the first end of the second resistor jointly serve as the second end of the reference voltage generation module and are connected to the first end of the voltage comparison module. The second end of the second resistor and the second end of the first resistor are respectively connected to the first end of the zener diode, and the second end of the zener diode is connected to the ground terminal.

[0017] Optionally, the differential operational amplifier module includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an operational amplifier;

[0018] Wherein, the first end of the third resistor serves as the first end of the differential operational amplifier module and is connected to the first end of the detection resistor. The second end of the third resistor is respectively connected to the first end of the fourth resistor and the first end of the operational amplifier. The second end of the fourth resistor is connected to the ground terminal;

[0019] The first end of the fifth resistor serves as the second end of the differential operational amplifier module and is connected to the second end of the detection resistor. The second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the second end of the operational amplifier. The second end of the sixth resistor and the third end of the operational amplifier jointly serve as the third end of the differential operational amplifier module and are connected to the second end of the voltage comparison module.

[0020] Optionally, the ratio of the resistance value of the fourth resistor to the resistance value of the third resistor is equal to the ratio of the resistance value of the sixth resistor to the resistance value of the fifth resistor. Optionally, the control switch is a field effect transistor;

[0021] Wherein, the source electrode of the field effect transistor is connected to the second end of the detection resistor, the drain electrode of the field effect transistor is connected to the load, and the gate electrode of the field effect transistor is connected to the second end of the logic control module.

[0022] In a second aspect, an embodiment of the present application further provides a driving circuit, including the overcurrent protection circuit described in the first aspect.

[0023] In a third aspect, an embodiment of the present application further provides a display device, including a display panel, a housing, and the driving circuit described in the second aspect.

[0024] In an embodiment of the present application, the overcurrent protection circuit is applied to a level conversion chip and includes a detection resistor, a control switch, a differential operational amplifier module, a reference voltage generation module, a voltage comparison module, and a logic control module. Among them, the detection resistor and the control switch are both serially arranged between a voltage source and a load in the level conversion chip. A first end of the differential operational amplifier module is connected to a first end of the detection resistor, and a second end of the differential operational amplifier module is connected to a second end of the detection resistor. A first end of the reference voltage generation module is connected to the voltage source, a second end of the reference voltage generation module is connected to a first end of the voltage comparison module, and a third end of the differential operational amplifier module is connected to a second end of the voltage comparison module. A third end of the voltage comparison module is connected to a first end of the logic control module, and a second end of the logic control module is connected to the control switch. In this way, the differential operational amplifier module can detect and amplify the current flowing through the detection resistor to obtain a detection voltage value, then the voltage comparison module compares the size of the detection voltage value with the reference voltage, outputs a level signal according to the comparison result, and then the logic control module outputs a control signal for controlling the working state of the control switch according to the level signal. When the current flowing through the detection resistor is large, that is, when the signals output by multiple channels of the level conversion chip are short-circuited at the same time, the overcurrent protection circuit can disconnect the load from the voltage source, thus solving the problem that the LS chip cannot provide overcurrent protection when the signals output by multiple channels are short-circuited at the same time and the signals output by multiple channels do not reach the threshold current. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention and used together with the specification to explain the principles of the present invention.

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 FIG. [ID] is a schematic structural diagram of an overcurrent protection circuit provided by an embodiment of the present application;

[0028] Figure 2 FIG. [ID] is another schematic structural diagram of an overcurrent protection circuit provided by an embodiment of the present application;

[0029] Figure 3 FIG. [ID] is a schematic structural diagram of a latch provided by an embodiment of the present application;

[0030] Figure 4This application example provides a simulation diagram of the input voltage at the R terminal of the latch U3;

[0031] Figure 5 This application example provides a simulation diagram of the output voltage at the second terminal of the reference voltage generation module;

[0032] Figure 6 This application example provides a schematic structural diagram of a drive circuit;

[0033] Figure 7 This application example provides a schematic structural diagram of a display device.

[0034] Among them, 100 is a differential operational amplifier module; 200 is a reference voltage generation module; 300 is a voltage comparison module; 400 is a logic control module; 500 is an overcurrent protection circuit; 600 is a drive circuit; 610 is a display panel; 620 is a housing. Detailed implementation manners

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are some but not all of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts shall fall within the protection scope of this application.

[0036] Refer to Figure 1 , Figure 1 This application example provides a schematic structural diagram of an overcurrent protection circuit. As Figure 1 shown, this overcurrent protection circuit is applied to a level conversion chip, and this overcurrent protection circuit includes: a detection resistor Rsense, a control switch M1, a differential operational amplifier module 100, a reference voltage generation module 200, a voltage comparison module 300, and a logic control module 400;

[0037] Among them, the detection resistor Rsense and the control switch M1 are both serially arranged between the voltage source and the load in the level conversion chip. The first terminal of the differential operational amplifier module 100 is connected to the first terminal of the detection resistor Rsense, and the second terminal of the differential operational amplifier module 100 is connected to the second terminal of the detection resistor Rsense;

[0038] The first terminal of the reference voltage generation module 200 is connected to the voltage source, the second terminal of the reference voltage generation module 200 is connected to the first terminal of the voltage comparison module 300, and the third terminal of the differential operational amplifier module 100 is connected to the second terminal of the voltage comparison module 300;

[0039] The third terminal of the voltage comparison module 300 is connected to the first terminal of the logic control module 400, and the second terminal of the logic control module 400 is connected to the control switch M1.

[0040] Specifically, the overcurrent protection circuit can be integrated inside the level conversion chip (i.e., LS chip) or outside the LS chip, and the embodiments of the present application do not make specific limitations. The above LS chip can be used to convert the row scanning signal output by the TCON chip into the VGL voltage (i.e., TFT off voltage) and VGH voltage (i.e., TFT on voltage) required by the GOA circuit, and provide multiple signals required by the GOA circuit, such as row driving start signal, each row on signal, GOA circuit switching signal, each row off low level maintaining signal, etc. The above voltage source can be the VGH voltage source inside the level conversion chip. The above load is an analog load, which can be understood as all the GOA circuit loads of the display panel. Of course, the load can also include other circuit loads inside the level conversion chip that require power supply from the VGH voltage source.

[0041] The above detection resistor Rsense can be used to convert the current flowing through itself into a voltage signal. The above control switch M1 can be a switch with turn-off control, such as a field effect transistor, etc. The first terminal and the second terminal of the differential operational amplifier module 100 are respectively connected to both ends of the detection resistor Rsense. The differential operational amplifier module 100 is used to detect and amplify the current flowing through the detection resistor Rsense to obtain a detection voltage value. The above reference voltage generation module 200 is used to generate a reference voltage, and the magnitude of the reference voltage is determined by the magnitude of the current when the signals of multiple channels output by the LS chip are short-circuited simultaneously. The first terminal and the second terminal of the voltage comparison module 300 are respectively connected to the third terminal of the differential operational amplifier module 100 and the second terminal of the reference voltage generation module 200. The voltage comparison module 300 is used to compare the magnitude of the detection voltage value with the reference voltage and output a level signal according to the comparison result. Specifically, when the voltage at the second terminal of the voltage comparison module 300 is greater than the voltage at the first terminal, the voltage comparison module 300 outputs its supply voltage VGH; when the voltage at the second terminal of the voltage comparison module 300 is less than or equal to the voltage at the first terminal, the voltage comparison module 300 outputs 0V. The first terminal of the above logic control module 400 is connected to the third terminal of the voltage comparison module 300, and the second terminal of the logic control module 400 is connected to the control switch M1. The logic control module 400 is used to output a control signal for controlling the working state of the control switch M1 according to the level signal.

[0042] In this way, the differential operation amplification module 100 can detect and amplify the current flowing through the detection resistor Rsense to obtain a detection voltage value. Then, the voltage comparison module 300 compares the magnitude of the detection voltage value with the reference voltage, outputs a level signal according to the comparison result, and then the logic control module 400 outputs a control signal for controlling the working state of the control switch M1 according to the level signal. When the current flowing through the detection resistor Rsense is large, that is, when the signals output by multiple channels of the level conversion chip are short-circuited simultaneously, the overcurrent protection circuit can disconnect the load from the voltage source, thus solving the problem that the LS chip cannot provide overcurrent protection when the signals output by multiple channels are short-circuited simultaneously and the signals output by multiple channels do not reach the threshold current.

[0043] Further, referring to Figure 2 , the logic control module 400 includes a first capacitor C2, a second capacitor C3, and a latch U3;

[0044] Among them, the first end of the first capacitor C2 is connected to the voltage source, the second end of the first capacitor C2 is respectively connected to the first end of the second capacitor C3 and the first end of the latch U3, and the second end of the second capacitor C3 is connected to the ground terminal;

[0045] The second end of the latch U3 serves as the first end of the logic control module 400 and is connected to the third end of the voltage comparison module 300, and the third end of the latch U3 serves as the second end of the logic control module 400 and is connected to the control switch M1.

[0046] Specifically, the above latch U3 can be composed of NAND gates or NOR gates, and the embodiments of the present application do not make specific limitations. The latch U3 can determine the level state of the Q end (i.e., the third end of the latch U3) according to the level signals input to the S end (i.e., the second end of the latch U3) and the R end (i.e., the first end of the latch U3), and further control the working state of the control switch M1. Here, the level signal input to the S end of the latch U3 is jointly determined by the capacitance values of the first capacitor C2 and the second capacitor C3 and the VGH voltage. The level signal input to the R end of the latch U3 is determined by the level signal output from the third end of the voltage comparison module 300.

[0047] In this way, different control signals can be output according to the truth table of the latch U3, the input level of the R end, and the input level of the S end to control the working state of the control switch M1.

[0048] Further, referring to Figure 3 , the latch U3 is composed of two NOR gates. Specifically, the latch U3 composed of two NOR gates can implement the following truth table:

[0049]

[0050] As can be seen from the above table, when both the inputs of the S terminal and the R terminal are 0, the output state of the Q terminal remains unchanged; when the input of the S terminal is 0 and the input of the R terminal is 1, the Q terminal is set to 0; when the input of the S terminal is 1 and the input of the R terminal is 0, the Q terminal is set to 1; when both the inputs of the S terminal and the R terminal are 1, the output state of the Q terminal is uncertain, and this state should be avoided.

[0051] It should be noted that the above 0 and 1 are both logical states. When the device supply voltage is the VGH voltage, 1 represents the VGH voltage and 0 represents OV. To avoid abnormal output of the SR latch U3 during power-on startup, it is usually necessary to reset it during power-on. The reset principle is as follows: when the LS chip is powered on, the circuit composed of the first capacitor C2 and the second capacitor C3 can bring a pulse voltage of several milliseconds (that is, the input of the R terminal is 1 at this time), and the output of the voltage comparison module 300 realizes the generation delay of the reference voltage through C1 in the reference voltage generation module 200 (that is, the input of the S terminal is 0 at this time). Therefore, a few milliseconds before the LS chip is powered on, S = 0 and R = 1 of the SR latch U3, which can set the output of the SR latch U3 to 0 and realize the reset of the SR latch U3.

[0052] In this embodiment, the first capacitor C2 and the second capacitor C3 are connected in series, and the R terminal of the SR latch U3 is connected to the middle position between the first capacitor C2 and the second capacitor C3. In this way, the first capacitor C2 and the second capacitor C3 can divide the VGH voltage at the initial stage of power-on, and use the divided voltage value obtained by the second capacitor C3 as the input value of the first terminal of the latch U3, so as to make the R terminal of the SR latch U3 be 1; it can also be discharged later through the equivalent series internal resistance of the second capacitor C3 itself and the input bias current of the R terminal of the SR latch U3, so as to make the R terminal of the SR latch U3 be 0, thereby realizing different level signals for the R terminal of the SR latch U3 at different power-on stages.

[0053] Furthermore, the capacitance value of the first capacitor C2 is greater than the capacitance value of the second capacitor C3.

[0054] In one embodiment, since the voltage division is opposite to the capacitance value, the capacitance value of the first capacitor C2 needs to be greater than that of the second capacitor C3. For example, assuming that the capacitance value of the first capacitor C2 is 100 pF, the capacitance value of the second capacitor C3 is 10 pF, and the VGH voltage is 30 V, then when LS is powered on, the voltage at point b (i.e., the first terminal of the latch U3) is divided to about 27.27 V, which can be regarded as a high level, that is, the R terminal of the SR latch U3 is 1 in the first few milliseconds before power on. Subsequently, due to the equivalent series internal resistance of the second capacitor C3 itself and the input bias current of the R terminal of the SR latch U3 (i.e., when the SR latch U3 works, the R terminal will draw current), the voltage at point b will drop to 0 V within a few milliseconds, that is, the R terminal of the SR latch U3 is 0. The simulation diagram of the input voltage at the R terminal of the SR latch U3 is as Figure 4 shown.

[0055] In this embodiment, by setting the capacitance value of the first capacitor C2 to be larger than that of the second capacitor C3, it can better ensure that the first terminal of the latch U3 is at a high level when LS is powered on, and thus can better realize the reset of the SR latch U3.

[0056] Furthermore, continue to refer to Figure 2 , the reference voltage generation module 200 includes a third capacitor C1, a first resistor R9, a second resistor R8, and a zener diode D1;

[0057] Among them, the first terminal of the third capacitor C1 and the first terminal of the first resistor R9 are respectively connected to the voltage source. The second terminal of the third capacitor C1 and the first terminal of the second resistor R8 are jointly used as the second terminal of the reference voltage generation module 200 and are connected to the first terminal of the voltage comparison module 300. The second terminal of the second resistor R8 and the second terminal of the first resistor R9 are respectively connected to the first terminal of the zener diode D1, and the second terminal of the zener diode D1 is connected to the ground terminal.

[0058] In one embodiment, due to the characteristic that the voltage across the capacitor does not change suddenly, within a few milliseconds after the LS chip is powered on, the voltage at point a (i.e., the second terminal of the reference voltage generation module 200) will immediately be the same as the VGH voltage. Subsequently, it discharges through the second resistor R8 and the zener diode D1. The zener diode D1 is in the reverse breakdown state, and the discharge speed depends on the resistance value of the second resistor R8. By reasonably configuring the resistance value of the second resistor R8, a high voltage can be achieved within a few milliseconds. After the discharge is completed, the voltage at point a is regulated by the reverse breakdown voltage of the zener diode D1 to provide the reference voltage. Within these few milliseconds after power-on, since the voltage at the first terminal of the voltage comparison module 300 is a relatively high voltage and the voltage at the second terminal of the voltage comparison module 300 will not exceed this voltage, the output of the voltage comparison module 300 is 0, that is, the S terminal of the SR latch U3 is 0, which facilitates the reset function of the SR latch U3. When the SR latch U3 completes power-on reset and enters the normal working state, the voltage at point a stabilizes at the reference voltage. At this time, the voltage comparison module 300 can compare the detected voltage value with the reference voltage and output the corresponding level signal to the S terminal of the SR latch U3. Assuming that the VGH voltage is 30V and the reference voltage is 6.8V, the simulation diagram of the output voltage of the second terminal of the reference voltage generation module 200 is as shown in Figure 5 shown. It can be seen that the reference voltage generation module 200 can realize the delayed generation of the reference voltage.

[0059] Furthermore, continuing to refer to Figure 2 , the differential operational amplifier module 100 includes: a third resistor R1, a fourth resistor R4, a fifth resistor R2, a sixth resistor R3, and an operational amplifier U1;

[0060] Among them, the first terminal of the third resistor R1 serves as the first terminal of the differential operational amplifier module 100 and is connected to the first terminal of the detection resistor Rsense. The second terminal of the third resistor R1 is respectively connected to the first terminal of the fourth resistor R4 and the first terminal (also known as the non-inverting input terminal) of the operational amplifier U1. The second terminal of the fourth resistor R4 is connected to the ground terminal;

[0061] The first terminal of the fifth resistor R2 serves as the second terminal of the differential operational amplifier module 100 and is connected to the second terminal of the detection resistor Rsense. The second terminal of the fifth resistor R2 is respectively connected to the first terminal of the sixth resistor R3 and the second terminal (also known as the inverting input terminal) of the operational amplifier U1. The second terminal of the sixth resistor R3 and the third terminal (also known as the output terminal) of the operational amplifier U1 together serve as the third terminal of the differential operational amplifier module 100 and are connected to the second terminal of the voltage comparison module 300.

[0062] In one embodiment, after the LS chip is powered on, a voltage will be generated across the detection resistor Rsense. The differential operational amplifier module 100 composed of the operational amplifier U1 and the resistors around it amplifies the voltage across the detection resistor Rsense. At this time, the output voltage Vout(U1) of the operational amplifier U1 can be:

[0063] Vout(U1) = VRsense * R3 / R2;

[0064] where VRsense is the voltage across the detection resistor Rsense, R3 is the resistance value of the sixth resistor, and R2 is the resistance value of the fifth resistor.

[0065] In this way, by adjusting the resistance values of the sixth resistor R3 and the fifth resistor R2, the Vrsense voltage can be amplified to obtain the detection voltage value, thereby realizing the detection of the magnitude of the current near the voltage source end in the LS chip. When the multiple signals output by the LS chip are short-circuited, overcurrent protection can be performed in a timely manner.

[0066] Further, the ratio of the resistance value of the fourth resistor R4 to the resistance value of the third resistor R1 is equal to the ratio of the resistance value of the sixth resistor R3 to the resistance value of the fifth resistor R2. In one embodiment, the third resistor R1 and the fourth resistor R4 are used as matching resistors, and it is required that the ratio of the resistance value of the fourth resistor R4 to the resistance value of the third resistor R1 is equal to the ratio of the resistance value of the sixth resistor R3 to the resistance value of the fifth resistor R2. In this way, the differential operational amplifier module 100 can work normally. As an alternative implementation, the resistance value of the third resistor R1 can be set equal to the resistance value of the fifth resistor R2, and the resistance value of the fourth resistor R4 can be set equal to the resistance value of the sixth resistor R3.

[0067] Further, the control switch M1 is a field effect transistor;

[0068] where the source electrode of the field effect transistor is connected to the second end of the detection resistor Rsense, the drain electrode of the field effect transistor is connected to the load, and the gate electrode of the field effect transistor is connected to the second end of the logic control module 400. In one embodiment, a field effect transistor such as a Pmos transistor can be used as the control switch M1. In this way, after the SR latch U3 is powered on and reset, it enters the normal working state. According to the truth table of the SR latch U3, it can be obtained that when the VGH input current detected and amplified by the differential operational amplifier module 100 does not exceed a certain value (that is, when the detection voltage value is lower than the reference voltage), the output of the voltage comparison module 300 is 0, the output Q of the SR latch U3 is 0. At this time, the gate-source voltage Vgs of the control switch M1 = -VGH, satisfying that the absolute value of Vgs is greater than the absolute value of the threshold voltage Vth of the control switch M1, and the control switch M1 is normally turned on, and the LS chip works normally.

[0069] When the differential operation amplifier module 100 detects and amplifies that the input current of VGH exceeds a certain value (i.e., when the detected voltage value exceeds the reference voltage), the voltage comparison module 300 outputs the VGH voltage, and the Q output of the SR latch U3 is 1 (i.e., the VGH voltage). At this time, the gate-source voltage Vgs of the control switch M1 is 0V, which does not satisfy that the absolute value of Vgs is greater than the absolute value of the threshold voltage Vth of the control switch M1, so the control switch M1 is turned off, cutting off the VGH input of the LS chip until the power is reapplied. If the short circuit is not handled, the control switch M1 will be triggered to be protected and turned off again during the next power-on, achieving the effect of protecting the LS chip and the display panel.

[0070] In this way, by adding the overcurrent protection circuit inside the LS chip to detect the total input current of the VGH voltage source, it is possible to prevent the GOA circuit from drawing too much load and overheating when the panel is damaged, avoid the short circuit of multiple GOA signals, and solve the problem of the protection failure when a single signal does not reach the overcurrent protection point of the LS.

[0071] In addition, referring to Figure 6 , the embodiment of the present application also provides a driving circuit 600, including the overcurrent protection circuit 500 in the above embodiment. It should be noted that the overcurrent protection circuit 500 in the driving circuit 600 has the same structure as the above overcurrent protection circuit 500 and can achieve the same technical effects, which will not be elaborated here one by one.

[0072] In addition, referring to Figure 7 , the embodiment of the present application also provides a display device, including a display panel 610, a housing 620, and the driving circuit 600 in the above embodiment. It should be noted that the driving circuit 600 in the display device has the same structure as the above driving circuit 600 and can achieve the same technical effects, which will not be elaborated here one by one.

[0073] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0074] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. An overcurrent protection circuit, characterized in that, Applied to a level conversion chip, the overcurrent protection circuit includes: a detection resistor, a control switch, a differential operation amplifier module, a reference voltage generation module, a voltage comparison module, and a logic control module; Wherein, the detection resistor and the control switch are both connected in series between the voltage source and the load in the level conversion chip. The first end of the differential operation amplifier module is connected to the first end of the detection resistor, and the second end of the differential operation amplifier module is connected to the second end of the detection resistor; The first end of the reference voltage generation module is connected to the voltage source, the second end of the reference voltage generation module is connected to the first end of the voltage comparison module, and the third end of the differential operation amplifier module is connected to the second end of the voltage comparison module; The third end of the voltage comparison module is connected to the first end of the logic control module, and the second end of the logic control module is connected to the control switch; Wherein, the logic control module includes a first capacitor, a second capacitor, and a latch; Wherein, the first end of the first capacitor is connected to the voltage source, the second end of the first capacitor is respectively connected to the first end of the second capacitor and the first end of the latch, and the second end of the second capacitor is connected to the ground terminal; The second end of the latch serves as the first end of the logic control module and is connected to the third end of the voltage comparison module, and the third end of the latch serves as the second end of the logic control module and is connected to the control switch.

2. The overcurrent protection circuit according to claim 1, wherein The latch is composed of two NOR gates.

3. The overcurrent protection circuit according to claim 1, characterized in that, The capacitance value of the first capacitor is greater than that of the second capacitor.

4. The overcurrent protection circuit according to claim 1, wherein The reference voltage generation module includes a third capacitor, a first resistor, a second resistor, and a voltage stabilizing diode; Wherein, the first end of the third capacitor and the first end of the first resistor are respectively connected to the voltage source. The second end of the third capacitor and the first end of the second resistor together serve as the second end of the reference voltage generation module and are connected to the first end of the voltage comparison module. The second end of the second resistor and the second end of the first resistor are respectively connected to the first end of the voltage stabilizing diode, and the second end of the voltage stabilizing diode is connected to the ground terminal.

5. The overcurrent protection circuit according to claim 1, characterized in that, The differential operation amplifier module includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an operational amplifier; Wherein, the first end of the third resistor serves as the first end of the differential operation amplifier module and is connected to the first end of the detection resistor. The second end of the third resistor is respectively connected to the first end of the fourth resistor and the first end of the operational amplifier, and the second end of the fourth resistor is connected to the ground terminal; The first end of the fifth resistor serves as the second end of the differential operation amplifier module and is connected to the second end of the detection resistor. The second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the second end of the operational amplifier. The second end of the sixth resistor and the third end of the operational amplifier together serve as the third end of the differential operation amplifier module and are connected to the second end of the voltage comparison module.

6. The overcurrent protection circuit according to claim 5, wherein, The ratio of the resistance value of the fourth resistor to the resistance value of the third resistor is equal to the ratio of the resistance value of the sixth resistor to the resistance value of the fifth resistor.

7. The overcurrent protection circuit according to claim 1, wherein The control switch is a field effect transistor; Wherein, the source electrode of the field effect transistor is connected to the second end of the detection resistor, the drain electrode of the field effect transistor is connected to the load, and the gate electrode of the field effect transistor is connected to the second end of the logic control module.

8. A driving circuit, characterized in that, Comprising the overcurrent protection circuit according to any one of claims 1-7.

9. A display device, characterized in that, Comprising a display panel, a housing, and the driving circuit according to claim 8.

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