CMOS structure and its manufacturing method

Abstract

This disclosure relates to a CMOS structure and a method for manufacturing the same. The CMOS structure includes a wafer, a first semiconductor device and a second semiconductor device on the front side of the wafer, a power rail on the back side of the wafer, a back-side power distribution network (PDN) grid on the back side of the wafer, and front-side signal wiring on the front side of the wafer above the first and second semiconductor devices. The second semiconductor device is stacked on the first semiconductor device, and the back-side PDN grid is connected to the power rail, which is connected to the first and second semiconductor devices.

Description

Technical Field

[0001] This disclosure relates to various embodiments of stacked semiconductor devices having a backside power distribution network (BSPDN) and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices come in a variety of configurations. Two types of semiconductor devices include non-stacked device architectures and stacked device architectures. Non-stacked device architectures in related technologies typically include an NMOS device region, a PMOS device region above the NMOS device region, a mid-section (MOL) region between the NMOS and PMOS device regions, a power rail region (VDD) above the PMOS device region, and a power rail region (GND) below the NMOS device region. Stacked device architectures in related technologies typically include PMOS devices stacked above NMOS devices, with each of the PMOS and NMOS devices including a separate voltage source supply (VSS) power rail below the respective device and a VDD power rail above the respective device. Furthermore, stacked device architectures in related technologies typically include a front-side power distribution network (PDN) mesh and front-side signal routing lines above the stacked NMOS and PMOS devices. However, providing both a PDN mesh and signal routing lines above the NMOS and PMOS devices leads to routing congestion, thus limiting block area scaling. Summary of the Invention

[0003] This disclosure relates to various embodiments of a CMOS structure. In one embodiment, the CMOS structure includes a wafer, a first semiconductor device on the front side of the wafer and a second semiconductor device stacked on the first semiconductor device, power rails on the back side of the wafer connected to the first and second semiconductor devices, a back-side power distribution network (PDN) mesh on the back side of the wafer connected to the power rails, and front-side signal wiring on the front side of the wafer connected to and above the first and second semiconductor devices.

[0004] This disclosure also relates to various embodiments of a method for manufacturing a CMOS device. In one embodiment, the method includes forming channels for a lower semiconductor device and an upper semiconductor device in a bulk material on a silicon substrate including an etch stop layer; forming a first connection from the lower semiconductor device to the etch stop layer; forming a second connection from the upper semiconductor device to the etch stop layer; subsequently forming signal lines connected to the lower semiconductor device and the upper semiconductor device; bonding a carrier wafer to the signal lines via a bonding interface; performing a wafer flip; removing a portion of the silicon substrate and the etch stop layer; forming power rails connected to the first and second connections; and forming a back-side power distribution network mesh connected to the power rails such that the back-side power distribution network mesh and the signal lines are on opposite sides of the silicon substrate.

[0005] This summary is provided to introduce the selection of concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. One or more described features may be combined with one or more other described features to provide a functional device. Attached Figure Description

[0006] The features and advantages of embodiments of this disclosure will be better understood when considered in conjunction with the accompanying drawings, by referring to the following detailed description. Throughout the drawings, the same reference numerals are used to refer to the same features and components. The drawings are not necessarily drawn to scale.

[0007] Figure 1A-1E This is a schematic cross-sectional view of a stacked semiconductor device having a back-side power distribution network (PDN) mesh according to various embodiments of the present disclosure;

[0008] Figure 2 It shows the manufacturing process. Figure 1A-1B A flowchart illustrating the task of a method for implementing a stacked semiconductor device;

[0009] Figures 3A-3H Manufacturing process is shown Figure 1A-1B The task of the method in the embodiment of the stacked semiconductor device shown;

[0010] Figure 4 It shows the manufacturing process. Figure 1C A flowchart illustrating the task of a method for implementing a stacked semiconductor device;

[0011] Figure 5A-5I Manufacturing process is shown Figure 1C The task of the method in the embodiment of the stacked semiconductor device shown;

[0012] Figure 6 It shows the manufacturing process. Figure 1D A flowchart illustrating the task of a method for implementing a stacked semiconductor device;

[0013] Figures 7A-7H Manufacturing process is shown Figure 1D The task of the method in the embodiment of the stacked semiconductor device shown;

[0014] Figure 8 It shows the manufacturing process. Figure 1E A flowchart illustrating the task of the method in the embodiment of the stacked semiconductor device shown; and

[0015] Figure 9A-9G Manufacturing process is shown Figure 1E The task of the method in the embodiment of the stacked semiconductor device shown. Detailed Implementation

[0016] This disclosure relates to various embodiments of semiconductor devices having a stacked architecture, front-side signal routing lines, and a back-side power distribution network (PDN) mesh. Separating the signal routing lines and the PDN mesh on opposite sides of the wafer reduces routing congestion and can improve block-level area scaling. Furthermore, placing the PDN mesh and power rails on the back side of the wafer is configured to avoid (or at least mitigate) thermal degradation and contamination problems that can occur in related technology semiconductor devices, such as buried power rails and through-silicon vias (TSVs) used in a back-side PDN mesh, when the power rails are formed prior to the front-end (FEOL) process.

[0017] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout refer to the same elements. However, the invention may be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey aspects and features of the invention to those skilled in the art. Therefore, processes, elements, and techniques unnecessary for those skilled in the art to fully understand aspects and features of the invention are not described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description is not repeated.

[0018] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of explanation, spatial relation terms such as “below,” “under,” “down,” “below,” “above,” “above,” etc., may be used herein to describe the relationship of an element or feature to other elements(s)(s)(s)(s) as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relation terms are intended to also cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” or “below” other elements or features will be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both upper and lower orientations. Devices may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relation descriptions used herein should be interpreted accordingly.

[0019] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion without departing from the spirit and scope of the invention.

[0020] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected" to another element or layer, or "linked" to another element or layer, it can be directly on, directly connected to, or directly linked to another element or layer, or there can be one or more intervening elements or layers. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between those two elements or layers, or there can be one or more intervening elements or layers.

[0021] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the invention. As used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising,” “including,” “including,” and “comprising” as used in this specification indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more associated listed items. Expressions such as “at least one of…” when following a list of elements modify the entire list of elements without modifying any individual element in the list.

[0022] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. Furthermore, the use of “may” when describing embodiments of the invention means “one or more embodiments of the invention.” As used herein, the terms “use,” “using…,” and “being used” can be considered synonymous with the terms “utilize,” “using…,” and “being exploited,” respectively. Additionally, the term “exemplary” is intended to refer to an example or illustration.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and / or in the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0024] Now refer to Figure 1A According to one embodiment of the present disclosure, a CMOS structure 100 includes a wafer 101, a first semiconductor device 102 (e.g., an NMOS device), and a second semiconductor device 103 (e.g., a PMOS device) stacked on the first semiconductor device 102. The first semiconductor device 102 and the second semiconductor device 103 are located on the front side of the wafer 101. In the illustrated embodiment, the CMOS structure 100 also includes signal wiring 104 on the front side of the wafer 101, which is connected to the first semiconductor device 102 and the second semiconductor device 103 to transmit signals to them. Furthermore, in the illustrated embodiment, the CMOS structure 100 also includes a back power rail 105 on the back side of the wafer 101, which is connected to the first semiconductor device 102 and the second semiconductor device 103. In the illustrated embodiment, the CMOS structure 100 also includes a back power distribution network (PDN) grid 106 connected to the back power rail 105. The rear PDN grid 106 and the rear power rail 105 are configured together to deliver power to the first semiconductor device 102 and the second semiconductor device 103.

[0025] Therefore, in the illustrated embodiment, the back-side PDN grid 106 and signal wiring lines 104 are separated on opposite sides of the wafer 101. Compared to related technologies utilizing a front-side PDN grid and signal lines on a stacked semiconductor device, this reduces wiring congestion and can improve block-level area scaling. Furthermore, providing a back-side power rail 105 and a back-side PDN grid 106 on the back side of the wafer 101 can prevent (or at least mitigate) thermal degradation and contamination problems that can occur if the power rails are formed prior to the front-end (FEOL) process, such as those caused by buried power rails and through-silicon vias (TSVs) in related technologies used in the back-side PDN grid.

[0026] Figure 1A-1E Different schemes or architectures for connecting power rails to the first and second semiconductor devices are illustrated. Figure 1AIn the illustrated embodiment, the first semiconductor device 102 is wider than the second semiconductor device 103, such that a portion of the first semiconductor device 102 is not covered by the second semiconductor device 103. In the illustrated embodiment, the first semiconductor device 102 is partially (towards) the second semiconductor device 103. Figure 1A The left side of the first semiconductor device 102 is laterally offset, so that a portion of the first semiconductor device 102 is not covered by the second semiconductor device 103 (relative to the front side). Furthermore, in the illustrated embodiment, the CMOS structure 100 includes a first power path 107 and a first power contact 109. The first power path 107 has a lower end portion 108 connected to one of the power rails 1051 on the back side. The first power contact 109 is connected to the upper end 110 of the first power path 107 and the upper end 111 of the portion of the first semiconductor device 102 not covered by the second semiconductor 103. In the illustrated embodiment, the first power path 107 extends vertically upward from the power rail 1051, such that the upper end 110 of the first power path 107 is flush with (i.e., coplanar) the upper end 111 of the first semiconductor device 102. The first power contact 109 extends horizontally, such that the lower end 112 of the first power contact 109 contacts the upper end 110 of the first power path 107 and the upper end 111 of the first semiconductor device 102, respectively. Furthermore, in the illustrated embodiment, the first power path 107 is laterally spaced from the side portion 113 of the first semiconductor device 102 (for example, the side portion 114 of the first power path 107 is spaced from the side portion 113 of the first semiconductor device 102).

[0027] In addition, Figure 1A In the illustrated embodiment, the CMOS structure 100 includes a second power path 115 and a second power contact 117. The second power path 115 has a lower end portion 116 connected to a second back power rail 1052 in the back power rail. The second power contact 117 is connected to the upper end 118 of the second power path 115 and the upper end 119 of the second semiconductor device 103. In the illustrated embodiment, the second power path 115 extends vertically upward from the power rail 1052 such that the upper end 118 of the second power path 115 is flush with (i.e., coplanar) the upper end 119 of the second semiconductor device 103. The second power contact 117 extends horizontally such that the lower surface 120 of the second power contact 117 contacts the upper end 118 of the second power path 115 and the upper end 119 of the second semiconductor device 103, respectively.

[0028] Now refer to Figure 1BAccording to another embodiment of the present disclosure, the CMOS structure 200 includes a wafer 201, a first semiconductor device 202 (e.g., an NMOS device), a second semiconductor device 203 (e.g., a PMOS device) stacked on the first semiconductor device 202, signal wiring lines 204 on the front side of the wafer 201 connected to the first semiconductor device 202 and the second semiconductor device 203, a back power rail 205 on the back side of the wafer 201 connected to the first semiconductor device 202 and the second semiconductor device 203, and a back power distribution network (PDN) grid 206 connected to the back power rail 205.

[0029] Furthermore, in the illustrated embodiment, the CMOS structure 200 includes a first power path 207 and a first power contact 209. The first power path 207 has a lower end portion 208 connected to one of the power rails 2051 on the back side. The first power contact 209 is connected to the upper end 210 of the first power path 207 and the upper end 211 of the portion of the first semiconductor device 202 not covered by the second semiconductor 203. In the illustrated embodiment, the first power path 207 extends vertically upward from the power rail 2051 such that the upper end 210 of the first power path 207 is flush with (i.e., coplanar) the upper end 211 of the first semiconductor device 202. The first power contact 209 extends horizontally such that the lower end 212 of the first power contact 209 contacts the upper end 210 of the first power path 207 and the upper end 211 of the first semiconductor device 202, respectively. In the illustrated embodiment, the first power path 207 is laterally aligned with the side portion 213 of the first semiconductor device 202 (for example, the side portion 214 of the first power path 207 contacts the side portion 213 of the first semiconductor device 202).

[0030] In addition, Figure 1B In the illustrated embodiment, the CMOS structure 200 includes a second power path 215 and a second power contact 217. The second power path 215 has a lower end portion 216 connected to a second back power rail 2052 in the back power rail. The second power contact 217 is connected to the upper end 218 of the second power path 215 and the upper end 219 of the second semiconductor device 203. In the illustrated embodiment, the second power path 215 extends vertically upward from the power rail 2052, such that the upper end 218 of the second power path 215 is flush with (i.e., coplanar) the upper end 219 of the second semiconductor device 203. The second power contact 217 extends horizontally, such that the lower surface 220 of the second power contact 217 contacts the upper end 218 of the second power path 215 and the upper end 219 of the second semiconductor device 203, respectively.

[0031] Now refer to Figure 1CAccording to another embodiment of the present disclosure, the CMOS structure 300 includes a wafer 301, a first semiconductor device 302 (e.g., an NMOS device), a second semiconductor device 303 (e.g., a PMOS device) stacked on the front side of the wafer 301 on the first semiconductor device 302, signal wiring lines 304 on the front side of the wafer 301 connected to the first semiconductor device 302 and the second semiconductor device 303, a back power rail 305 on the back side of the wafer 301 connected to the first semiconductor device 302 and the second semiconductor device 303, and a back power distribution network (PDN) grid 306 connected to the back power rail 305.

[0032] Furthermore, in the illustrated embodiment, the CMOS structure 300 includes a first power path 307 having a lower end 308 connected to one of the power rails 3051 on the back and the first semiconductor device 302. In the illustrated embodiment, the first power path 307 extends vertically upward from the power rail 3051. The first power path 307 includes a lower narrower portion (or segment) 309 below and beside the first semiconductor device 302, and an upper wider portion (or segment) 310 above the first semiconductor device 302. The wider portion 310 of the first power path 307 extends horizontally toward the first semiconductor device 302 and hangs over the upper end 311 of the portion of the first semiconductor device 302 not covered by the second semiconductor 303. The lower surface 312 of the wider portion 310 of the first power path 307 contacts the upper end 311 of the first semiconductor device 302. In the illustrated embodiment, the narrower portion 309 of the first power path 307 is laterally aligned with the side portion 313 of the first semiconductor device 302 (for example, the side 314 of the narrower portion 309 of the first power path 307 contacts the side portion 313 of the first semiconductor device 302).

[0033] In addition, Figure 1C In the illustrated embodiment, the CMOS structure 300 includes a second power path 315 and a second power contact 317. The second power path 315 has a lower end portion 316 connected to a second back power rail 3052 in the back power rail. The second power contact 317 is connected to the upper end 318 of the second power path 315 and the upper end 319 of the second semiconductor device 303. In the illustrated embodiment, the second power path 315 extends vertically upward from the power rail 3052, such that the upper end 318 of the second power path 315 is flush with (i.e., coplanar) the upper end 319 of the second semiconductor device 303. The second power contact 317 extends horizontally, such that the lower surface 320 of the second power contact 317 contacts the upper end 318 of the second power path 315 and the upper end 319 of the second semiconductor device 303, respectively.

[0034] Now refer to Figure 1D According to another embodiment of the present disclosure, the CMOS structure 400 includes a wafer 401, a first semiconductor device 402 (e.g., an NMOS device), a second semiconductor device 403 (e.g., a PMOS device) stacked on the front side of the wafer 401 on the first semiconductor device 402, signal wiring lines 404 on the front side of the wafer 401 connected to the first semiconductor device 402 and the second semiconductor device 403, a back power rail 405 on the back side of the wafer 401 connected to the first semiconductor device 402 and the second semiconductor device 403, and a back power distribution network (PDN) grid 406 connected to the back power rail 405.

[0035] In addition, Figure 1D In the illustrated embodiment, the CMOS structure 400 includes a first power path 407 having a lower end 408 connected to one of the back power rails 4051 and an upper end 409 connected to a first semiconductor device 402. The first power path 407 extends vertically upward from the back power rail 4051 and directly contacts the lower side 410 of the first semiconductor device 402 (i.e., the upper end 409 of the first power path 407 is directly connected to the first semiconductor device 402 without a separate power contact).

[0036] In addition, Figure 1D In the illustrated embodiment, the CMOS structure 400 includes a second power path 411 and a power contact 413. The second power path 411 has a lower end portion 412 connected to a second back power rail 4052 in the back power rail. The power contact 413 is connected to the upper end 414 of the second power path 411 and the upper end 415 of the second semiconductor device 403. In the illustrated embodiment, the second power path 411 extends vertically upward from the power rail 4052 such that the upper end 414 of the second power path 411 is flush with (e.g., coplanar) the upper end 415 of the second semiconductor device 403. The power contact 413 extends horizontally such that the lower surface 416 of the power contact 413 contacts the upper end 414 of the second power path 411 and the upper end 415 of the second semiconductor device 403, respectively.

[0037] Now refer to Figure 1EAccording to another embodiment of the present disclosure, a CMOS structure 500 includes a wafer 501, a first semiconductor device 502 (e.g., an NMOS device), a second semiconductor device 503 (e.g., a PMOS device) stacked on the front side of the wafer 501 on the first semiconductor device 502, signal wiring lines 504 on the front side of the wafer 501 connected to the first semiconductor device 502 and the second semiconductor device 503, a back power rail 505 on the back side of the wafer 501 connected to the first semiconductor device 502 and the second semiconductor device 503, and a back power distribution network (PDN) mesh 506 connected to the back power rail 505. In the illustrated embodiment, the first semiconductor device 502 (towards...) Figure 1E The left side of the second semiconductor device 503 extends laterally beyond the second semiconductor device 503. Figure 1E The right side of the semiconductor device 502 extends laterally beyond the first semiconductor device 502 (e.g., the first semiconductor device 502 and the second semiconductor device 503 are interleaved).

[0038] In addition, Figure 1E In the illustrated embodiment, the CMOS structure 500 includes a first power path 507 having a lower end 508 connected to one of the back power rails 5051 and an upper end 509 connected to a first semiconductor device 502. The first power path 507 extends vertically upward from the back power rail 5051 and directly contacts the lower side 510 of the first semiconductor device 502 (i.e., the upper end 509 of the first power path 507 is directly connected to the first semiconductor device 502 without a separate power contact).

[0039] In addition, Figure 1E In the illustrated embodiment, the CMOS structure 500 includes a second power path 511 having a lower end 512 connected to one of the back power rails 5052 and an upper end 513 connected to the second semiconductor device 503. The second power path 511 extends vertically upward from the back power rail 5052 and directly contacts the lower side 514 of the second semiconductor device 503 (i.e., the upper end 513 of the second power path 511 is directly connected to the second semiconductor device 503 without a separate power contact).

[0040] Figure 2 It is to draw the manufacturing Figure 1A The drawn CMOS structure 100 and Figure 1B The flowchart of the task of method 600 in CMOS structure 200 is shown. Figures 3A-3H This is a schematic diagram illustrating the tasks involved in manufacturing CMOS structures 100 and 200. (Example) Figure 2 and Figure 3AAs shown, method 600 includes task 605 of forming channels 701 and 702, respectively, stacked on a lower semiconductor device 703 for a lower semiconductor device 703 (e.g., an nFET) and an upper semiconductor device 704 (e.g., a pFET). In the illustrated embodiment, channels 701 and 702 are formed on a silicon (Si) substrate 705 in which an etch stop layer 706 is formed and are formed of a bulk material.

[0041] like Figure 2 and Figure 3B As shown, method 600 also includes task 610 of forming the remainder of the lower semiconductor device 703 and the remainder of the upper semiconductor device 704 (e.g., patterning contacts on top of the source / drain epitaxial regions). In the illustrated embodiment, the lower semiconductor device 703 is laterally offset relative to the upper semiconductor device 704 (in... Figure 3B (From center to left), such that a portion of the upper side 707 of the lower semiconductor device 703 is not covered by (or is exposed by) the upper semiconductor device 704. In the illustrated embodiment, task 610 also includes a first power contact 708 formed on the exposed portion of the upper side 707 of the lower semiconductor device 703 (e.g., directly contacting the exposed portion of the upper side 707 of the lower semiconductor device 703) and a second power contact 709 formed on the upper side 710 of the upper semiconductor device 704 (e.g., directly contacting the upper side 710 of the upper semiconductor device 704). In the illustrated embodiment, the first power contact 708 and the second power contact 709 formed in task 610 extend horizontally outward in opposite directions, away from each other.

[0042] like Figure 2 and Figure 3C As shown, method 600 also includes task 615 of forming a first power path 711 extending vertically from the first power contact 708 to the etch stop layer 706 and a second power path 712 extending vertically from the second power contact 709 to the etch stop layer 706.

[0043] like Figure 2 and Figure 3D As shown, method 600 also includes task 620 for forming the front rear section (BEOL) of signal line 713.

[0044] like Figure 2 and Figure 3E As shown, method 600 also includes a task 625 of bonding a second wafer (i.e., carrier wafer) 714 to a signal line 713 via a bonding interface 715 (i.e., task 625 includes performing wafer-to-wafer (W2W) bonding).

[0045] like Figure 2 and Figure 3F-3GAs shown, method 600 further includes a wafer flipping task 630, followed by grinding and / or etching to remove portions of the Si substrate 705 beneath the etch stop layer 706 and a task 635 of the etch stop layer 706. After removing portions of the Si substrate 705 beneath the etch stop layer 706 and the etch stop layer 706 in task 635, portions of the first power path 711 and the second power path 712 are exposed.

[0046] like Figure 2 and Figure 3H As shown, method 600 also includes a task 640 of forming a power rail 716 connected to the exposed portions of the first power path 711 and the exposed portions of the second power path 712, and a backside power distribution network (BSPDN) mesh 717 coupled to the power rail 716. After task 640 of forming the power rail 716 and the BSPDN mesh 717, the BSPDN mesh 717 and signal lines 713 are on opposite sides of the stacked semiconductor devices 703 and 704. Compared to related technology devices that utilize a front-side PDN mesh and signal lines on top of the stacked semiconductor devices, this reduces wiring congestion and can improve block-level area scaling.

[0047] Figure 4 It is to draw the manufacturing Figure 1C The flowchart of the task of method 800 in CMOS structure 300 is shown. Figure 5A-5I This is a schematic diagram illustrating the process of fabricating the CMOS structure 300. (For example...) Figure 4 and Figure 5A As shown, method 800 includes task 805 of forming channels 901 and 902 for a lower semiconductor device 903 (e.g., nFET) and an upper semiconductor device 904 (e.g., pFET) stacked on the lower semiconductor device 903, respectively. In the illustrated embodiment, channels 901 and 902 are formed on a silicon (Si) substrate 905 in which an etch stop layer 906 is formed and are formed of a bulk material.

[0048] like Figure 4 and Figure 5B As shown, method 800 further includes a task 810 of forming the remainder of the lower semiconductor device 903 and the remainder of the upper semiconductor device 904. In the illustrated embodiment, the lower semiconductor device 903 is laterally offset relative to the upper semiconductor device 904 (in... Figure 5B(From center to left), such that a portion of the upper side 907 of the lower semiconductor device 903 is not covered by (or is exposed by) the upper semiconductor device 904. In the illustrated embodiment, task 810 also includes a power contact 908 formed on the upper side 909 of the upper semiconductor device 904 (e.g., in direct contact with the upper side 909 of the upper semiconductor device 904). In the illustrated embodiment, the power contact 908 formed in task 810 extends horizontally outward away from the upper semiconductor device 904.

[0049] like Figure 4 and Figure 5C As shown, method 800 also includes a first portion 910 that forms a first power path 911 extending vertically upward from the exposed portion of the upper side 907 of the lower semiconductor device 904, and a second power path 912 that extends vertically downward from the power contact 908 to the etch stop layer 906.

[0050] like Figure 4 and Figure 5D As shown, method 800 further includes a task 820 that forms a first power path 911 extending vertically downward from a first portion 910 of the first power path 911 to a second portion 913 of the etch stop layer 906. Following task 820, the first power path 911 includes a lower narrower portion (or segment) formed below the lower semiconductor device 903 by the second portion 913 and an upper wider portion (or segment) formed above the lower semiconductor device 903 by a combination of the first portion 910 and the second portion 913. The wider portion of the first power path 911 extends horizontally toward the lower semiconductor device 903 and hangs over an upper side 907 of the portion of the lower semiconductor device 903 not covered by the upper semiconductor device 904. The lower surface of the wider portion of the first power path 911 contacts the upper side 907 of the lower semiconductor device 903. Furthermore, in the illustrated embodiment, the narrower portion of the first power path 911 is laterally aligned with the side of the lower semiconductor device 903 (for example, the side of the narrower portion of the first power path 911 contacts the side of the lower semiconductor device 903).

[0051] like Figure 4 and Figure 5E As shown, method 800 also includes task 825 for forming the front rear section (BEOL) of signal line 914.

[0052] like Figure 4 and Figure 5F As shown, method 800 also includes task 830 of bonding a second wafer (i.e., carrier wafer) 915 to signal line 914 via bonding interface 916 (i.e., task 830 includes performing wafer-to-wafer (W2W) bonding).

[0053] like Figure 4 and Figure 5G-5H As shown, method 800 further includes a task 835 of performing wafer flipping, followed by grinding and / or etching to remove portions of the Si substrate 905 beneath the etch stop layer 906 and the etch stop layer 906, and a task 840 thereof. After task 840 of removing portions of the Si substrate 905 beneath the etch stop layer 906 and the etch stop layer 906, portions of the first power path 911 and the second power path 912 are exposed.

[0054] like Figure 4 and Figure 5I As shown, method 800 also includes a task 845 of forming a power rail 917 connected to the exposed portions of the first power path 911 and the exposed portions of the second power path 912, and a backside power distribution network (BSPDN) mesh 918 coupled to the power rail 917. After task 845 of forming the power rail 917 and the BSPDN mesh 918, the BSPDN 918 and signal lines 914 are on opposite sides of the stacked semiconductor devices 903 and 904. Compared to related technology devices that utilize a front-side PDN mesh and signal lines on top of the stacked semiconductor devices, this reduces wiring congestion and can improve block-level area scaling.

[0055] Figure 6 It is to draw the manufacturing Figure 1D The flowchart of the task of method 1000 in CMOS structure 400 is shown. Figures 7A-7H This is a schematic diagram illustrating the process of fabricating the CMOS structure 400. (Example) Figure 6 and Figure 7A As shown, method 1000 includes task 1005 of forming channels 1101 and 1102 for a lower semiconductor device 1103 (e.g., nFET) and an upper semiconductor device 1104 (e.g., pFET) stacked on the lower semiconductor device 1103, respectively. In the illustrated embodiment, channels 1101 and 1102 are formed on a silicon (Si) substrate 1105 in which an etch stop layer 1106 is formed and are formed of a bulk material.

[0056] like Figure 6 and Figure 7B As shown, method 1000 also includes a task 1010 of forming the remainder of the upper semiconductor device 1104 (e.g., forming a contact on top of the source / drain epitaxial region of the upper semiconductor device 1104). In the illustrated embodiment, the lower semiconductor device 1103 is laterally offset relative to the upper semiconductor device 1104 (in... Figure 7B(From center to left). In the illustrated embodiment, task 1010 further includes a power contact 1107 formed on the upper side 1108 of the upper semiconductor device 1104 (e.g., in direct contact with the upper side 1108 of the upper semiconductor device 1104). In the illustrated embodiment, the power contact 1107 formed in task 1010 extends horizontally outward away from the upper semiconductor device 1104.

[0057] like Figure 6 and Figure 7C As shown, method 1000 also includes task 1015 of forming a first power path 1109 extending vertically downward from the lower side 1110 of the lower semiconductor device 1103 to the etch stop layer 1106 and a second power path 1111 extending vertically downward from the power contact 1107 to the etch stop layer 1106.

[0058] like Figure 6 and Figure 7D As shown, method 1000 also includes task 1020 for forming the front rear section (BEOL) of signal line 1112.

[0059] like Figure 6 and Figure 7E As shown, method 1000 also includes task 1025 of bonding a second wafer (i.e., carrier wafer) 1113 to signal line 1112 via bonding interface 1114 (i.e., task 1025 includes performing wafer-to-wafer (W2W) bonding).

[0060] like Figure 6 and Figure 7F-7G As shown, method 1000 further includes a task 1030 of performing a wafer flipping, followed by grinding and / or etching to remove portions of the Si substrate 1105 under the etch stop layer 1106 and a task 1035 of the etch stop layer 1106. After task 1035 of removing portions of the Si substrate 1105 under the etch stop layer 1106 and the etch stop layer 1106, portions of the first power path 1109 and the second power path 1111 are exposed.

[0061] like Figure 6 and Figure 7HAs shown, method 1000 also includes task 1040 of forming power rails 1115 connected to exposed portions of the first power path 1109 and the second power path 1111, and a backside power distribution network (BSPDN) mesh 1116 coupled to the power rails 1115. After task 1040 of forming the power rails 1115 and the BSPDN mesh 1116, the BSPDN 1116 and signal lines 1112 are on opposite sides of the stacked semiconductor devices 1103 and 1104. Compared to related technology devices that utilize front-side PDN meshes and signal lines above the stacked semiconductor devices, this reduces wiring congestion and can improve block-level area scaling.

[0062] Figure 8 It is to draw the manufacturing Figure 1E The flowchart of the task of method 1200 in CMOS structure 500 is shown. Figure 9A-9G This is a schematic diagram illustrating the task of fabricating the CMOS structure 500. (Example) Figure 8 and Figure 9A As shown, method 1200 includes a task 1205 of forming channels 1301 and 1302 for a lower semiconductor device 1303 (e.g., nFET) and an upper semiconductor device 1304 (e.g., pFET) stacked on the lower semiconductor device 1303, respectively. In the illustrated embodiment, channels 1301 and 1302 are formed on a silicon (Si) substrate 1305 in which an etch stop layer 1306 is formed and are formed of a bulk material.

[0063] like Figure 8 and Figure 9B As shown, method 1200 also includes task 1210 of forming the remainder of lower semiconductor device 1303 and the remainder of upper semiconductor device 1304. In the illustrated embodiment, lower semiconductor device 1303 is laterally offset relative to upper semiconductor device 1304 (in... Figure 9B (From center to left). In the illustrated embodiment, task 1210 further includes forming a first power path 1307 extending vertically downward from the lower side 1308 of the lower semiconductor device 1303 to the etch stop layer 1306, and a second power path 1309 extending vertically downward from the lower side 1310 of the upper semiconductor device 1304 to the etch stop layer 1306.

[0064] like Figure 8 and Figure 9C As shown, method 1200 also includes task 1215 for forming the front rear section (BEOL) of signal line 1311.

[0065] like Figure 8 and Figure 9DAs shown, method 1200 also includes task 1220 of bonding a second wafer (i.e., carrier wafer) 1312 to signal line 1311 via bonding interface 1313 (i.e., task 1220 includes performing wafer-to-wafer (W2W) bonding).

[0066] like Figure 8 and Figure 9E-9F As shown, method 1200 further includes a task 1225 of performing wafer flipping, followed by grinding and / or etching to remove portions of the Si substrate 1305 and the etch stop layer 1306 below the etch stop layer 1306. After task 1230 of removing portions of the Si substrate 1305 and the etch stop layer 1306 below the etch stop layer 1306, portions of the first power path 1307 and the second power path 1309 are exposed.

[0067] like Figure 8 and Figure 9G As shown, method 1200 also includes a task 1230 of forming a power rail 1314 connected to the exposed portions of the first power path 1307 and the exposed portions of the second power path 1309, and a backside power distribution network (BSPDN) mesh 1315 coupled to the power rail 1314. After task 1230 of forming the power rail 1314 and the BSPDN mesh 1315, the BSPDN 1315 and signal lines 1311 are on opposite sides of the stacked semiconductor devices 1303 and 1304. Compared to related technology devices that utilize a front-side PDN mesh and signal lines on top of the stacked semiconductor devices, this reduces wiring congestion and can improve block-level area scaling.

[0068] Although the invention has been described in detail with reference to specific embodiments thereof, the embodiments described herein are not intended to be exhaustive or to limit the scope of the invention to the exact forms disclosed. Those skilled in the art will understand that changes and modifications can be made to the described structures and methods of assembly and operation without explicitly departing from the principles, spirit, and scope of the invention. One or more features described with reference to one embodiment may be combined with one or more features described with reference to another embodiment to provide a working stacked semiconductor device. Although various mechanisms and structures have been described above for connecting bottom and top transistors, these mechanisms and structures can be combined in any suitable manner to form a working stacked semiconductor device.

[0069] This application claims priority and benefit to U.S. Provisional Application No. 63 / 324,558, filed March 28, 2022, entitled “Stacked Device with BSPDNScheme,” the entire contents of which are incorporated herein by reference.

Claims

1. A CMOS structure, comprising: Chips; A first semiconductor device and a second semiconductor device are located on the front side of the wafer, with the second semiconductor device stacked on top of the first semiconductor device; A power rail is located on the back side of the wafer, and the power rail is connected to the first semiconductor device and the second semiconductor device; A back-side power distribution network (PDN) mesh on the back side of the wafer, the back-side power distribution network mesh being connected to the power rail; as well as The front-side signal wiring on the front side of the wafer is connected to the first semiconductor device and the second semiconductor device and is above the first semiconductor device and the second semiconductor device. A first power path is connected to the power rail and directly connected to the upper surface of the first semiconductor device; A second power supply path is connected to the power rail; as well as The power contact is connected to the second power path and to the upper surface of the second semiconductor device. The first power path includes a narrower portion below the first semiconductor device and a wider portion above the first semiconductor device. The first semiconductor device and the second semiconductor device are configured to receive power only from the back-side power distribution network grid.

2. The CMOS structure according to claim 1, wherein the first power supply path is adjacent to the side of the first semiconductor device.

3. The CMOS structure according to claim 1, wherein the first power supply path is in contact with the side of the first semiconductor device.

4. The CMOS structure according to claim 1, wherein the first semiconductor device is laterally offset from the second semiconductor device.

5. A CMOS structure, comprising: Chips; A first semiconductor device and a second semiconductor device are located on the front side of the wafer, with the second semiconductor device stacked on top of the first semiconductor device; A power rail is located on the back side of the wafer, and the power rail is connected to the first semiconductor device and the second semiconductor device; A back-side power distribution network (PDN) mesh on the back side of the wafer, the back-side power distribution network mesh being connected to the power rail; A front-side signal wiring line on the front side of the wafer, the front-side signal wiring line being connected to the first semiconductor device and the second semiconductor device and being on the first semiconductor device and the second semiconductor device; A first power path is connected to the power rail and directly connected to the upper surface of the first semiconductor device; A second power supply path is connected to the power rail; as well as The power contact is connected to the second power path and to the upper surface of the second semiconductor device. The first power path includes a narrower portion below the first semiconductor device and a wider portion above the first semiconductor device. Wherein the first semiconductor device is laterally offset from the second semiconductor device, and The wider portion of the first power path contacts only the portion of the upper surface of the first semiconductor device that is not covered by the second semiconductor device.

6. The CMOS structure according to claim 5, wherein the first power supply path contacts the side of the first semiconductor device.

7. The CMOS structure of claim 5, wherein the wider portion of the first power path extends over the first semiconductor device.

Images