Semiconductor structure and method of manufacturing the same, memory and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof, wherein the semiconductor structure comprises at least one transistor, and the transistor comprises: a channel, the channel comprising a first semiconductor layer and a second semiconductor layer arranged around the first semiconductor layer; and the second semiconductor layer introduces strain in the channel.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its manufacturing method, and a memory and its manufacturing method. Background Technology

[0002] With the miniaturization, increasing density, and higher integration of semiconductor devices, and the continuous shrinking of memory sizes, the feature size of transistors in semiconductor devices has shrunk to the nanoscale. This has pushed the power density and mobility of transistors to their physical limits, posing a greater challenge to improving transistor performance. Transistors in related technologies are constrained by physical limits such as power density and mobility, making it difficult to reduce power consumption and increase speed. Summary of the Invention

[0003] To address the related technical issues, embodiments of this application propose a semiconductor structure and its manufacturing method, as well as a memory and its manufacturing method.

[0004] This application provides a semiconductor structure, the semiconductor structure including at least one transistor, the transistor comprising:

[0005] A channel, the channel including a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer; the second semiconductor layer introduces strain in the channel.

[0006] In the above scheme, the transistor further includes:

[0007] A gate, covering at least one side of the channel;

[0008] The source and drain are located at opposite ends of the channel's extension direction.

[0009] In the above scheme, the gate is disposed around the channel.

[0010] In the above scheme, the lattice constant of the first element contained in the first semiconductor layer is different from the lattice constant of the second element contained in the second semiconductor layer.

[0011] In the above scheme, the material of the first semiconductor layer includes silicon germanium, and the material of the second semiconductor layer includes silicon.

[0012] In the above scheme, the cross-sectional shape of the channel includes one of the following:

[0013] Circular;

[0014] Oval shape;

[0015] rectangle.

[0016] In the above scheme, the semiconductor structure includes multiple transistors, and the multiple channels corresponding to the multiple transistors are arranged in an array along a first direction and a second direction; both the first direction and the second direction are perpendicular to the extension direction of the channels; wherein,

[0017] The gates of each transistor in each row of transistors arranged along the first direction are physically connected to each other; the gates of two adjacent rows of transistors arranged along the first direction are electrically isolated from each other.

[0018] In the above scheme, the transistor is N-type and the strain is tensile strain; or, the transistor is P-type and the strain is compressive strain.

[0019] This application provides a method for manufacturing a semiconductor structure, the method comprising:

[0020] A channel is formed; the channel includes a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer; the second semiconductor layer introduces strain in the channel.

[0021] The manufacturing method described above further includes:

[0022] Form the gate of a transistor covering at least one side of the channel;

[0023] The source and drain of the transistor are formed at both ends of the extension direction of the channel, respectively.

[0024] In the above scheme, the material of the first semiconductor layer includes silicon germanium, and the material of the second semiconductor layer includes silicon.

[0025] In the above scheme, forming the trench includes:

[0026] Provide an active layer;

[0027] The active layer is partially etched to form a columnar first semiconductor layer; the first semiconductor layer extends along a direction perpendicular to the surface of the active layer;

[0028] A second semiconductor layer is formed on the sidewalls and top surface of the first semiconductor layer.

[0029] The method in the above scheme further includes:

[0030] A first semiconductor layer with a rectangular cross-sectional shape is formed in the active layer;

[0031] Through an oxidation process, the cross-sectional shape of the first semiconductor layer is changed from rectangular to elliptical.

[0032] In the above scheme, the semiconductor structure includes multiple transistors, and the multiple transistors correspond to multiple channels; forming multiple channels includes:

[0033] Provide an active layer;

[0034] The active layer is partially etched to form multiple first trenches extending along a first direction and multiple second trenches extending along a second direction, as well as multiple first semiconductor layers located at the intersection of the first trenches and the second trenches; the sidewalls of each first semiconductor layer are exposed in the first trenches and the second trenches and extend along a direction perpendicular to the surface of the active layer; the first direction and the second direction are parallel to the surface of the active layer;

[0035] A second semiconductor layer is formed on the sidewalls and top surface of the first semiconductor layer.

[0036] In the above scheme, the first trench and the second trench have a first depth and a second depth respectively along the extension direction of the channel, and the first depth and the second depth are different.

[0037] In the above scheme, after the trench is formed, the method further includes:

[0038] A first dielectric layer is filled in the first trench and the second trench having the second semiconductor layer;

[0039] Partial etching of the first dielectric layer forms a third trench, and filling the third trench with insulating material forms a gate isolation structure;

[0040] Partial etching of the first dielectric layer forms an exposed second semiconductor layer;

[0041] A gate oxide layer is formed on the exposed second semiconductor layer;

[0042] A first conductive material and a second dielectric layer are sequentially filled; the first conductive material is used to form the gate of each transistor.

[0043] This application embodiment further provides a memory, including:

[0044] Multiple storage cells are arranged in an array along a first direction and a second direction;

[0045] A transistor array comprising a plurality of semiconductor structures as described in the above embodiments; the gates of each row of transistors in the transistor array along the first direction are physically connected to each other, and the physically connected gates form word lines; each memory cell is connected to the source or drain of a transistor in the transistor array; both the first direction and the second direction are perpendicular to the extension direction of the channel of the transistor.

[0046] Multiple bit lines are arranged parallel to each other along the second direction, and each bit line is connected to the drain or source of a row of transistors arranged along the second direction in the transistor array.

[0047] In the above scheme, the memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

[0048] In the above scheme, the memory includes: dynamic random access memory, and the memory cell includes: a capacitor; the capacitor includes a columnar second electrode, a dielectric covering the sidewall and bottom of the second electrode, and a first electrode covering the dielectric.

[0049] This application embodiment further provides a method for manufacturing a memory, the method comprising:

[0050] Multiple storage cells are formed, and the multiple storage cells are arranged in an array along a first direction and a second direction;

[0051] A transistor array is formed, which is manufactured by the semiconductor structure manufacturing method described in the above scheme; the gates of each row of transistors in the transistor array along the first direction are physically connected to each other, and the physically connected gates form word lines; each memory cell is connected to the source or drain of a transistor in the transistor array; both the first direction and the second direction are perpendicular to the extension direction of the channel of the transistor.

[0052] Multiple bit lines are formed and arranged in parallel along the second direction, and each bit line is connected to the drain or source of a row of transistors arranged along the second direction in the transistor array.

[0053] This application provides a semiconductor structure and its manufacturing method, as well as a memory and its manufacturing method. The semiconductor structure includes at least one transistor, which includes a channel comprising a first semiconductor layer and a second semiconductor layer surrounding the first semiconductor layer. The second semiconductor layer introduces strain into the channel. In various embodiments of this application, the transistor channel comprises a double-layered semiconductor layer, and strain is introduced into the double-layered semiconductor layer. The introduced strain can lengthen the distance between atoms in the semiconductor layer, reducing the number of atoms per unit length, decreasing the energy of electron / hole migration, thereby increasing the electron / hole mobility of the channel, and further improving the current velocity of the channel, reducing transistor power consumption, increasing transistor speed, etc., to obtain better transistor performance. Attached Figure Description

[0054] Figure 1a This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this application;

[0055] Figure 1b This is a three-dimensional structural diagram of another semiconductor structure provided in an embodiment of this application;

[0056] Figure 2 A schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in this application embodiment;

[0057] Figures 3a to 3j A three-dimensional structural schematic diagram of the manufacturing process of a semiconductor structure provided in this application embodiment;

[0058] Figure 4 A three-dimensional structural diagram of a memory provided in an embodiment of this application;

[0059] Figure 5 A schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in this application embodiment;

[0060] Figure 6 This is a three-dimensional structural diagram illustrating the manufacturing process of a memory provided in an embodiment of this application.

[0061] Explanation of reference numerals in the attached figures

[0062] 20 - Semiconductor structure / transistor array; 100 - Substrate; 101 - Active layer; T1 - First trench; T2 - Second trench; H1 - First depth / first thickness; H2 - Second depth / second thickness; C - Channel; 203 - First semiconductor layer; 202 - Second semiconductor layer; 201 - First dielectric layer; T3 - Third trench; H3 - Third depth / third thickness; 207 - Gate isolation structure; T4 - Fourth trench / fourth thickness; H4 - Fourth depth / fourth thickness; 204 - Gate oxide layer; 205 - Gate; 206 - Second dielectric layer; S - Source; D - Drain; TR - Transistor;

[0063] 30 - Memory; AT1 / AT2 - Each row of transistors; BL - Bit line; WL - Word line. Detailed Implementation

[0064] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0065] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0066] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0067] It should be understood that spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0070] Transistors can be used in various types of memory, such as Dynamic Random Access Memory (DRAM). Typically, DRAM is an architecture consisting of one transistor (T) and one capacitor (C) (1T1C).

[0071] As memory size decreases, the transistor size in the memory region also continues to shrink. The transistor size is becoming increasingly smaller, but this is limited by physical limits such as power density and mobility. Specifically, the carrier mobility μ (hereinafter referred to as μ, μ) of some continuously shrinking transistors, such as thin-film transistors (TFTs), is... e μ h It is expressed as μ, where μ represents the carrier mobility. e μ represents electron mobility. h While the hole mobility (μ) may meet design requirements after feature size reduction, its low μ value may not. Related technologies cannot achieve high μ while minimizing transistor feature size, thus failing to reduce transistor power consumption, increase transistor speed, and meet high performance requirements while increasing integration density.

[0072] To address at least one of the aforementioned problems, embodiments of this application provide a semiconductor structure and a method for manufacturing the same, as well as a memory and a method for manufacturing the same.

[0073] Based on at least one of the aforementioned problems existing in related technologies, embodiments of this application provide a semiconductor structure and a method for manufacturing the same, as well as a memory and a method for manufacturing the same.

[0074] This application provides a semiconductor structure. Figure 1a This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this application (which can be understood as a three-dimensional diagram in which a transistor in the semiconductor structure is cut open along the XZ plane and the YZ plane respectively). The semiconductor structure includes at least one transistor. The transistor 20 includes a channel C, which includes a first semiconductor layer 203 and a second semiconductor layer 202 disposed around the first semiconductor layer 203. The second semiconductor layer 202 introduces strain in the channel C.

[0075] In some embodiments, the transistor TR further includes: a gate 205 covering at least one side of the channel C; a source S and a drain D, respectively located at both ends of the extension direction of the channel C.

[0076] It should be noted that the transistors provided in the embodiments of this application may include vertical transistors and transistors with buried gates. Figure 1a In addition to illustrating the components of the transistor, the diagram also shows the dielectric layers required to bury the gate 205 (the first dielectric layer 201 and the second dielectric layer 206 described below).

[0077] It is understood that, in the embodiments of this application, the channel C, including the provision of a strained second semiconductor layer 202 and a first semiconductor layer 203, enables the transistor TR to have a required high μ. When a strained second semiconductor layer 202 is formed outside the first semiconductor layer 203, strain can be introduced into the second semiconductor layer 202. Since the introduced strain can increase the carrier mobility in the second semiconductor layer 202, the μ of the channel C is increased. Because the strain introduced into the second semiconductor layer 202 in the channel C lengthens the atomic distance in the semiconductor layer, the number of atoms per unit length is reduced, the energy of carrier migration is reduced, the carrier mobility μ of the channel is increased, and the current velocity of the channel is increased.

[0078] In practical applications, high μ channel C can be obtained by selecting the channel material and the thin film deposition process to introduce strain in the second semiconductor layer 202.

[0079] In some embodiments, when the material composition of the first semiconductor layer 203 and the material composition of the second semiconductor layer 202 are different, a transition region with material composition mismatch is formed between the first semiconductor layer 203 and the second semiconductor layer 202. At this time, strain is introduced into the transition region, which is equivalent to the first semiconductor layer 203 applying strain to the second semiconductor layer 202 through the transition region with material composition mismatch.

[0080] In some specific embodiments, the lattice constant of the first element contained in the first semiconductor layer 203 is different from the lattice constant of the second element contained in the second semiconductor layer 202.

[0081] For example, the material of the first semiconductor layer 203 includes silicon germanium, and the material of the second semiconductor layer 202 includes silicon.

[0082] In some embodiments, during the deposition of thin films, such as the first semiconductor layer 201 and the second semiconductor layer 202, strain can be introduced into the second semiconductor layer 202 by adjusting the deposition process parameters such as rate, temperature, and pressure. In a specific example, strain can be introduced by adjusting the density difference between the thin films by adjusting the deposition process parameters (see the related description below for specific implementation details).

[0083] In some embodiments, the gate 205 is disposed around the channel C. That is, the vertical transistor in the embodiments of this application may specifically be a full-around gate transistor. It should be noted that the vertical transistor in the embodiments of this application is not limited to a full-around gate transistor, and may also include other types of vertical transistors, such as a half-around gate transistor, a pillar gate transistor, etc.

[0084] In practical applications, a gate oxide layer 204 is also formed between the gate 205 and the channel C, that is, between the gate 205 and the second semiconductor layer 203.

[0085] In some embodiments, such as Figure 1a As shown, the positions of the source S and drain D can be interchanged. The source S is located at the first end of the channel C; the drain D is located at the second end of the channel C; or, the drain D is located at the first end of the channel C; the source S is located at the second end of the channel C. The first end and the second end are the two opposite ends of the channel C in a third direction. Here, the third direction refers to the extension direction of the channel C.

[0086] Please refer to Figure 1b In some embodiments, the semiconductor structure includes a plurality of transistors, and a plurality of channels C corresponding to the plurality of transistors are arranged in an array along a first direction X and a second direction Y; both the first direction X and the second direction Y are perpendicular to the extension direction of the channel C; wherein,

[0087] The gates of each transistor in each row of transistors AT1 / AT2 arranged along the first direction are physically connected to each other; the gates of two adjacent rows of transistors AT1 and AT2 arranged along the first direction are electrically isolated from each other.

[0088] In practical applications, Figure 1b The diagram also shows the dielectric layers required to bury the gate 205 (the first dielectric layer 201, the gate isolation structure 207, and the second dielectric layer 206 described below). It is understood that the gates 205 of each transistor in each row of transistors AT1 / AT2 arranged along the first direction X are physically connected to form a word line, which is a buried word line; the gates 205 of adjacent rows of transistors AT1 and AT2 arranged along the first direction X are electrically isolated from each other by the isolation structure 206; along the third direction Z, the gate 205 is isolated from other components by the first dielectric layer 201 and the second dielectric layer 207.

[0089] In some embodiments, the first direction intersects the second direction, and the angle between the first direction and the second direction can be any angle between 0 and 90 degrees; for example, the first direction can be perpendicular to the second direction. It is understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of the transistors along the first direction and the second direction.

[0090] In this document and hereinafter, for ease of description, the first and second directions in the embodiments of this application are represented as two orthogonal directions parallel to the substrate plane; the third direction is a direction perpendicular to the substrate plane, that is, the extension direction of the channel; wherein, the substrate plane can be understood as a plane perpendicular to the extension direction of the channel. The first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; the third direction can be represented as the Z direction in the figures.

[0091] In some embodiments, the cross-sectional shape of the channel C along a direction perpendicular to the third direction and passing through the channel C can be circular, square, elliptical, or rhomboid. In practical applications, the shape can be selected according to the specific process; for example, a circular channel hole can be formed by etching using a patterning process, and the channel C can be deposited in the circular channel hole, with the cross-sectional shape of the channel C along a direction perpendicular to the third direction being circular (which can be understood as a cylindrical channel). The cylindrical channel C also provides a stable structure for the subsequent formation of the transistor TR, helping to reduce transistor defects, leakage current, etc., and achieving better transistor performance.

[0092] In various embodiments of this application, the channel of the transistor includes a double-layered semiconductor layer, and strain is introduced into the double-layered semiconductor layer to lengthen the atomic distance, thereby reducing the number of atoms per unit length, reducing the energy required for carrier migration, increasing the carrier mobility of the channel, improving the current velocity of the channel, reducing the power consumption of the transistor, and increasing the speed of the transistor, thus achieving better transistor performance. Simultaneously, in various embodiments of this application, the source and drain of the transistor are arranged along the transistor's extension direction, thereby reducing the area occupied by a single transistor in the horizontal direction and increasing the number of transistors that can be placed per unit area, thus meeting the requirement for small transistor size.

[0093] The semiconductor structure provided in this application embodiment can be formed by the semiconductor structure manufacturing method provided in the following embodiment. The semiconductor structure manufactured by the semiconductor structure manufacturing method provided in this application embodiment is similar to the semiconductor structure in the above embodiment. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiment for understanding, and will not be repeated here.

[0094] Figure 2 A schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in this application embodiment; Figures 3a to 3j A three-dimensional structural diagram illustrating the manufacturing process of the semiconductor structure provided in the embodiments of this application.

[0095] The following is combined Figure 2 and Figures 3a to 3j The manufacturing method of the semiconductor structure provided in the embodiments of this application will be described in detail. It is understood that the manufacturing method of the semiconductor structure described in the embodiments of this application is not limited to manufacturing a specific number of transistors: it can be a manufacturing method for manufacturing a single transistor or a manufacturing method for manufacturing a transistor array. The following text and accompanying drawings will exemplify the manufacturing method for manufacturing a transistor array. Figures 3a to 3j This is a three-dimensional structural diagram illustrating the manufacturing process of a semiconductor structure provided in an embodiment of this application. It should be understood that... Figures 3a to 3j The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figures 3a to 3j The steps shown can be adjusted in order according to actual needs.

[0096] Please refer to Figure 2 The method for manufacturing the semiconductor structure includes:

[0097] Step 2001, forming a channel; the channel includes a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer; the second semiconductor layer introduces strain in the channel.

[0098] In some embodiments, the method further includes:

[0099] Step 2002: Form the gate of a transistor covering at least one side of the channel;

[0100] Step 2003: The source and drain of the transistor are formed at both ends of the extension direction of the channel.

[0101] Please refer to step 2001 for execution instructions. Figures 3a to 3d In some embodiments, the semiconductor structure includes a plurality of transistors, the plurality of transistors corresponding to a plurality of channels; forming the plurality of channels includes: providing an active layer 101;

[0102] The active layer 101 is partially etched to form multiple first trenches T1 extending along a first direction and multiple second trenches T2 extending along a second direction, as well as multiple first semiconductor layers 203 located at the intersection of the first trenches T1 and the second trenches T2; the sidewalls of each first semiconductor layer 203 are exposed in the first trenches T1 and the second trenches T2, and extend along a direction perpendicular to the surface of the active layer; the first direction and the second direction are parallel to the surface of the active layer;

[0103] A second semiconductor layer 202 is formed on the sidewalls and top surface of the first semiconductor layer 203.

[0104] Please refer to Figure 3a An active layer 101 is provided; the material of the active layer 101 may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc. The active layer 101 may be doped with certain impurity ions as needed, and the impurity ions may be N-type or P-type impurity ions. In practical applications, the active layer 101 can be formed by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0105] In some embodiments, the active layer 101 may be formed on the substrate 100, depending on the actual needs of the device. The material of the substrate 100 may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.; the substrate 100 may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). In other embodiments, the active layer 101 may also be formed on other functional thin film layers.

[0106] In some embodiments, the active layer 101 may be formed on the substrate 100 by an epitaxial growth process (EGP). The material of the substrate 100 may include silicon (Si), and the material of the active layer 101 may include silicon germanium (SiGe). It should be noted that the active layer 101 and the first semiconductor layer 203 described below are made of the same material but with different morphologies; that is, the active layer 101 material remaining after removing a portion of the active layer 101 material forms the first semiconductor layer 203.

[0107] Next, please refer to Figure 3bThe active layer 101 is partially etched to form multiple first trenches T1 extending along a first direction and multiple second trenches T2 extending along a second direction, as well as multiple first semiconductor layers 203 located at the intersection of the first trenches T1 and the second trenches T2; the sidewalls of each first semiconductor layer 203 are exposed in the first trenches T1 and the second trenches T2 and extend along a direction perpendicular to the surface of the active layer; the first direction and the second direction are parallel to the surface of the active layer.

[0108] In practical applications, dry etching methods, such as ion milling, plasma etching, reactive ion etching, and laser ablation, can be used to etch the active layer 101 along its surface portion, forming the first trench T1 extending in a first direction and arranged parallel to each other in a second direction, and the second trench T2 extending in the second direction and arranged parallel to each other in the first direction, within the active layer 101. It is understood that, as Figure 3b As shown, the first trench T1 separates two adjacent rows of first semiconductor layers AT1 and AT2 along the second direction, and the second trench T2 separates two adjacent rows of first semiconductor layers AT1 and AT2 along the first direction. In the top view plane (XY plane), the first trench T1 and the second trench T2 divide the active layer into a plurality of first semiconductor layers 203 arranged in an array along the first and second directions.

[0109] In some embodiments, the first trench T1 and the second trench T2 may be formed by one or more patterning processes. These processes include, but are not limited to, double-patterning technology (DPT), quadruple-patterning technology (QPT), extreme ultraviolet lithography (EUV), or any combination thereof.

[0110] In some embodiments, the first trench T1 and the second trench T2 have a first depth H1 and a second depth H2 respectively along the extension direction of the channel C, wherein the first depth H1 is different from the second depth H2.

[0111] In practical applications, such as Figure 3bAs shown, the first depth H1 can be understood as the dimension from the surface of the active layer 101 along a third direction to the bottom of the first trench T1, and the second depth H2 can be understood as the dimension from the surface of the active layer 101 along a third direction to the bottom of the second trench T2. In subsequent processes, bit lines can be formed in the first trench T1 and word lines can be formed in the second trench T2. In this case, the first depth H1 can be greater than the second depth H2. That is, the plurality of first semiconductor layers 203 have a first thickness H1 in the first trench T1 and a second thickness H2 in the second trench, and the first thickness H1 can be greater than the second thickness H2.

[0112] It is understandable that when the first depth H1 in the first trench T1 is greater than the second depth H2 in the second trench T2, a bit line BL can be formed in the first trench T1 first, and a word line WL can be formed in the second trench T2, so that the bit line BL and the word line WL can be staggered in the third direction (for the specific formation process, please refer to the relevant content on buried bit lines below).

[0113] In practical applications, the cross-sectional shape of each of the first semiconductor layers 203 can be selectively formed into one of the following shapes through specific processes: circular; elliptical; rectangular. It should be noted that the cross-section is a top-view plane (XY plane).

[0114] Please refer to Figure 3c In some embodiments, the method further includes:

[0115] A first semiconductor layer 203 with a rectangular cross-sectional shape is formed in the active layer 101;

[0116] Through an oxidation process, the cross-sectional shape of the first semiconductor layer 203 is changed from rectangular to elliptical.

[0117] In practical applications, dry etching methods, such as ion milling, plasma etching, reactive ion etching, and laser ablation, can be used to etch the active layer 101 along the surface portion of the active layer to form the structure described above. Figure 3b The first semiconductor layer 203 shown has a rectangular cross-sectional shape, meaning it is cuboid in shape; as shown... Figure 3c As shown, the first semiconductor layer 203, which is rectangular in shape, is then passivated by an oxidation process to form the shape described above. Figure 3cThe first semiconductor layer 203 is shown in a cylindrical shape. This allows for further miniaturization of the first semiconductor layer 203, reducing existing process challenges. Simultaneously, the cylindrical shape of the first semiconductor layer 203 provides a stable structure for the subsequent formation of transistors (TRs), helping to reduce transistor defects and leakage, and achieving better transistor performance.

[0118] Please refer to Figure 3d A second semiconductor layer 202 is formed on the sidewalls and top surface of the first semiconductor layer 203. The second semiconductor layer 202 can be formed by one or more deposition processes. These processes include, but are not limited to, PVD, CVD, ALD, or any combination thereof. For example, the second semiconductor layer 202 can be formed by atomic layer deposition.

[0119] In some embodiments, the second semiconductor layer 202 can be formed on the first semiconductor layer 203 by an epitaxial growth process. In practical applications, when the material composition of the first semiconductor layer 203 and the material composition of the second semiconductor layer 202 are different, if the second semiconductor layer 202 is formed on the first semiconductor layer 203 by an epitaxial growth process, a transition region with material composition mismatch is formed between the first semiconductor layer 203 and the second semiconductor layer 202. At this time, strain is introduced into the transition region, which is equivalent to the first semiconductor layer 203 applying strain to the second semiconductor layer 202 through the transition region with material composition mismatch.

[0120] In some embodiments, the lattice constant of the first element contained in the first semiconductor layer 203 is different from the lattice constant of the second element contained in the second semiconductor layer 202.

[0121] In some embodiments, the material of the first semiconductor layer 203 includes silicon germanium, and the material of the second semiconductor layer 202 includes silicon.

[0122] In practical applications, the material of the second semiconductor layer 202 may include silicon (Si), and the material of the first semiconductor layer 203 may include silicon-germanium (SiGe). Since the materials of the second semiconductor layer 202 and the first semiconductor layer 203 are different, the second semiconductor layer 202 is formed on the first semiconductor layer 203 through an epitaxial growth process. The second semiconductor layer 202 can introduce strain into the channel C. Specifically, because the lattice constant of germanium in the first semiconductor layer 203 is greater than that of silicon in the second semiconductor layer 202, at the interface between the silicon-germanium and silicon materials, the silicon with the smaller lattice constant experiences strain from the silicon with the larger lattice constant. In other words, the second semiconductor layer 202 is strained, increasing its electron mobility. Simultaneously, the silicon material surrounding the silicon-germanium material can reduce the adverse effects of the instability of germanium oxide on the channel. For example, germanium dioxide (GeO2) dissolves in water; germanium monoxide solid (GeO(s)) sublimates at 700°C; germanium and germanium dioxide in germanium decompose into solid or gaseous germanium monoxide at approximately 400°C. The instability of germanium dioxide and germanium monoxide leads to more defects in the channel material, increases the channel resistivity, and affects the channel carrier mobility.

[0123] In some embodiments, the transistor TR is N-type and the strain is tensile strain; or, the transistor TR is P-type and the strain is compressive strain.

[0124] It is understandable that when the second semiconductor layer 202 has compressive / tensile strain, and the first semiconductor layer 203 adjacent to the second semiconductor layer 202 in the direction perpendicular to the extension direction of the second semiconductor layer 202 does not have strain, the first semiconductor layer 203 without strain can be subjected to compressive / tensile force by the first semiconductor layer 203 with compressive / tensile strain, thereby introducing the compressive / tensile strain into the first semiconductor layer 203.

[0125] It is understood that when the second semiconductor layer 202 has no strain, and the source and / or drain of the second semiconductor layer 202 have compressive / tensile strain in the extension direction of the second semiconductor layer 202, the second semiconductor layer 202 without strain can be subjected to tensile / compressive forces from the source and / or drain of the source and / or drain with compressive / tensile strain, thereby introducing tensile / compressive forces into the first semiconductor layer 203.

[0126] Here, tensile strain can be understood as a tendency for the size of the second semiconductor layer 202 to increase in the channel extension direction of the transistor TR; compressive strain can be understood as a tendency for the size of the second semiconductor layer 202 to decrease in the channel extension direction of the transistor TR. It is understood that, taking the example that the material of the second semiconductor layer 202 may include silicon, and the material of the first semiconductor layer 203 may include silicon-germanium, when the transistor TR is N-type, at the interface between the silicon-germanium material and the silicon material, the silicon with a smaller lattice constant experiences tensile strain from the silicon-germanium material with a larger lattice constant. In other words, the second semiconductor layer 202 is subjected to tensile strain, increasing the electron mobility μ of the N-type / P-type transistor TR. e / μ h When the transistor TR is P-type, and the source and / or drain material includes silicon and germanium, while the second semiconductor layer 202 material includes silicon, a material composition mismatch transition region is formed between the source and / or drain and the second semiconductor layer 202 in the channel C extension direction. This transition region introduces strain, equivalent to the source and / or drain applying compressive strain to the second semiconductor layer 202 through the material composition mismatch transition region. In other words, in a P-type transistor, strain can be introduced into the second semiconductor layer 202 by using a different material between the source and / or drain and the second semiconductor layer 202, thereby increasing the hole mobility μ of the P-type transistor TR. h .

[0127] In other embodiments, during the deposition of thin films, such as the first semiconductor layer 201 and the second semiconductor layer 202, strain can be introduced into the second semiconductor layer 202 by adjusting the deposition process parameters, such as rate, temperature, and pressure.

[0128] In a specific example, strain can be introduced by adjusting the density difference between thin films through adjusting the parameters of the deposition process. For instance, when an active layer 101 is deposited using conventional chemical vapor deposition (CVD) (which subsequently forms a first semiconductor layer 203 through etching), a second semiconductor layer 202 can be deposited on the first semiconductor layer 203 using plasma-enhanced chemical vapor deposition (PECVD), which has a higher deposition rate and lower temperature than conventional CVD. This results in a second semiconductor layer 202 with a lower density than the first semiconductor layer 203. In this case, the relatively less dense second semiconductor layer 202 is subjected to compressive force from the relatively denser first semiconductor layer 203, thus introducing compressive strain into the second semiconductor layer 202. Similarly, when a second semiconductor layer 202 is deposited on the first semiconductor layer 203 using low-pressure chemical vapor deposition (LPCVD), which has a lower deposition rate and lower pressure than conventional CVD,… A second semiconductor layer 202 with a higher density than the first semiconductor layer 203 can be obtained. The second semiconductor layer 202 with a higher relative density is subjected to a tensile force from the first semiconductor layer 203 with a lower relative density, thereby introducing tensile strain into the second semiconductor layer 202.

[0129] In other words, different deposition process parameters can be used for the first semiconductor layer and the second semiconductor layer to create a density difference between the first semiconductor layer 203 and the second semiconductor layer 202, generating an interaction force between the two layers and thus introducing strain into the second semiconductor layer 202. It should be noted that the same method of introducing strain into the second semiconductor layer 202 can also introduce strain into the first semiconductor layer 203.

[0130] Please refer to Figures 3e to 3j In some embodiments, after forming the channel C, the method further includes:

[0131] A first dielectric layer 201 is filled in the first trench T1 and the second trench T2 having the second semiconductor layer 202;

[0132] Partial etching of the first dielectric layer 201 forms a third trench T3, and filling the third trench T3 with insulating material forms a gate isolation structure 207.

[0133] Partial etching of the first dielectric layer 201 forms an exposed second semiconductor layer 202;

[0134] A gate oxide layer 204 is formed on the exposed second semiconductor layer 202;

[0135] A first conductive material and a second dielectric layer 206 are sequentially filled; the first conductive material is used to form the gate 205 of each transistor.

[0136] Please refer to Figure 3e A first dielectric layer 201 is filled in the first trench T1 and the second trench T2 having the second semiconductor layer 202. An insulating material can be deposited in the first trench T1 and the second trench T2 using PVD or CVD processes, and the insulating material is then subjected to chemical mechanical polishing (CMP) so that the surface of the insulating material is flush with the top surface of the trench C. In this embodiment, the insulating material includes, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, or any combination thereof.

[0137] Please refer to Figure 3f A third trench T3 is formed by partially etching the first dielectric layer 201. The width of the third trench T3 (which can be understood as the dimension along the X direction) is smaller than the width of the first trench T1 (which can be understood as the dimension along the X direction). In practical applications, dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation can be used to form the third trench T3. The third trench T3 has a third depth H3 in the third direction, and the third depth H3 and the second depth H2 (refer to the above) are also considered. Figure 3b The third trench T3 extends along the second direction and is arranged in parallel intervals along the first direction, dividing the first dielectric layer 201 into a plurality of first dielectric layers 201 that extend along the second direction and are arranged in parallel intervals along the first direction.

[0138] Next, as Figure 3g As shown, an insulating material is filled in the third trench T3 to form a gate isolation structure 207. In practical applications, the insulating material can be deposited in the third trench T3 using PVD or CVD processes, and then chemically and mechanically polished to make the surface of the insulating material flush with the surface of the first dielectric layer 201, thus forming the gate isolation structure 207. In this embodiment, the insulating material includes, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, or any combination thereof.

[0139] In some embodiments, the thickness of the isolation structure 207 in the third direction is comparable to the thickness of the channel C in the third direction. For example... Figure 3fAs shown, the isolation structure 207 has a third thickness H3 in the third direction, and the third thickness H3 is different from the second thickness H2 (refer to the above). Figure 3b )quite.

[0140] Please refer to Figure 3h The first dielectric layer 201 is partially etched to form an exposed second semiconductor layer 202. In practical applications, the fourth groove T4 on the sidewall of the exposed second semiconductor layer 202 can be formed using dry etching processes such as ion milling, plasma etching, reactive ion etching, and laser ablation.

[0141] In some embodiments, the fourth groove T4 does not penetrate the first dielectric layer 201 in the third direction, and the fourth groove T4 has a fourth depth H4 in the third direction, the fourth depth H4 being less than the second thickness H2 (refer to the above). Figure 3b ).

[0142] Please refer to Figure 3i A gate oxide layer 204 is formed on the exposed second semiconductor layer 202. The gate oxide layer 204 can be formed at least on the exposed sidewalls (i.e., the exposed sidewalls of the second semiconductor layer 202) of each channel C by in-situ oxidation of the second semiconductor layer 202, which has exposed sidewalls in the corresponding fourth trench T4. Here, the exposed sidewalls (i.e., the exposed sidewalls of the second semiconductor layer 202) of each channel C can be oxidized in-situ by heating or pressurizing to form the gate oxide layer 204. The material of the gate oxide layer 204 includes, but is not limited to, silicon dioxide.

[0143] In some embodiments, a gate oxide layer 204 may also be formed at least on the exposed sidewalls of each of the channels C (i.e., the exposed sidewalls of the second semiconductor layer 202) by an ALD process.

[0144] In some embodiments, the gate oxide layer 204 is disposed around the channel C. In practical applications, the gate oxide layer 204 is formed over the channel C, that is, the gate oxide layer 204 is formed around the second semiconductor layer 202.

[0145] Please refer to Figure 3jA first conductive material and a second dielectric layer 206 are sequentially filled; the first conductive material is used to form the gate 205 of each transistor. The first conductive material can be deposited in the fourth trench T4 having the gate oxide layer 204 by PVD or CVD process; then the fourth trench T4 having the gate oxide layer 204 and the first conductive material is formed by etch-back process; and the second dielectric layer 206 is deposited in the fourth trench T4 having the gate oxide layer 204 and the first conductive material.

[0146] In this embodiment, the first conductive material may be a metallic material or a semiconductor conductive material, such as copper, cobalt, tungsten, doped silicon, polycrystalline silicon, or any combination thereof; the material of the second dielectric layer 206 includes, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, silicon dioxide, or any combination thereof.

[0147] In some embodiments, the method further includes:

[0148] A gate 205 is formed covering at least one side of the transistor TR of the channel C;

[0149] The source S and drain D of the transistor TR are formed at both ends of the extension direction of the channel C.

[0150] Here, the formed semiconductor structure includes multiple transistors, and the multiple channels C corresponding to the multiple transistors are arranged in an array along a first direction X and a second direction Y; both the first direction X and the second direction Y are perpendicular to the extension direction of the channel C; wherein...

[0151] The gates of each transistor in each row of transistors AT1 / AT2 arranged along the first direction are physically connected to each other; the gates of two adjacent rows of transistors AT1 and AT2 arranged along the first direction are electrically isolated from each other.

[0152] It is understood that the manufacturing method of the transistor array described in the embodiments of this application is used to manufacture, but is not limited to, a specific number of transistors; it can also be a manufacturing method for manufacturing a single transistor. The transistor array in the embodiments of this application (described above) Figure 1b The manufacturing method of ) is as described above. Figure 3a to Figure 3j The steps are for understanding, and will not be repeated here.

[0153] It should be understood that, referring to the foregoing Figures 3a to 3j In the process of fabricating a single transistor, some steps can be omitted, such as... Figure 3i and Figure 3j The gate isolation structure 207 formed in the process is unnecessary. In the embodiments of this application, a single transistor (as described above) Figure 1a The manufacturing method is as described above. Figure 3a to Figure 3h The steps are for understanding, and will not be repeated here.

[0154] In some embodiments, please refer to Figure 3a , Figure 3c and Figure 3d The formation of the channel includes:

[0155] Active layer 101 is provided. Please refer to the above for details. Figure 3a The relevant descriptions in the text will not be repeated here.

[0156] The active layer 101 is partially etched to form a columnar first semiconductor layer 203; the first semiconductor layer 203 extends along a direction perpendicular to the surface of the active layer. A grid-like mask pattern can be formed in the active layer 101 using one or more patterning processes to create multiple openings arranged in an array along a first direction and a second direction. These openings are then etched to form a single first semiconductor layer 203. This process includes, but is not limited to, DPT, QPT, EUV processes, or any combination thereof. It is understood that the first trench T1 and the second trench T2 are formed simultaneously in the same patterning process, each having a first depth H1 and a second depth H2 along the extension direction of the channel C, and the first depth H1 and the second depth H2 may be different.

[0157] A second semiconductor layer 202 is formed on the sidewalls and top surface of the first semiconductor layer 203. For details, please refer to the above. Figure 3c and Figure 3d The relevant description of the formation of the second semiconductor layer 202 is not repeated here.

[0158] This application provides a memory. Figure 4 This is a three-dimensional structural diagram of a memory provided in an embodiment of this application.

[0159] Please refer to Figure 4 In some embodiments, the memory 30 includes:

[0160] Multiple storage units ( Figure 4 (not shown), arranged in an array along the first and second directions;

[0161] A transistor array 20 includes multiple semiconductor structures described in the embodiments of this application; the gates of each row of transistors AT1 / AT2 along the first direction are physically connected to each other, and the physically connected gates 205 form word lines WL; each memory cell is connected to the source S or drain D of a transistor in the transistor array 20; both the first direction and the second direction are perpendicular to the extension direction of the channel C of the transistor;

[0162] Multiple bit lines BL are arranged parallel to each other along the second direction, and each bit line BL is connected to the drain D or source S of a row of transistors arranged along the second direction in the transistor array 20.

[0163] In practical applications, the word line WL is connected to the gate 205 of each of the transistor arrays 20. The word line WL is used to provide a word line voltage and control the conduction or cutoff of the channel region in each transistor through the word line voltage. The bit line BL, extending along the first direction X, is connected to the drain D of each of the transistor arrays 20. The bit line BL is used to perform read or write operations on the memory cell when each transistor is turned on.

[0164] In this embodiment of the application, the materials of the word line WL and the bit line BL include, but are not limited to, tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicides, or any combination thereof.

[0165] It is understood that in the memory, if each memory cell is connected to the source S of a transistor in the transistor array 20, then each bit line BL is connected to the drain D of a row of transistors arranged along the second direction in the transistor array 20; or, if each memory cell is connected to the drain D of a transistor in the transistor array 20, then each bit line BL is connected to the source S of a row of transistors arranged along the second direction in the first transistor array 20.

[0166] In some embodiments, the memory provided in this application includes various types of memory. For example, NAND flash memory, NOR flash memory, DRAM, static random access memory (SRAM), phase-change memory (PCM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0167] In some embodiments, the memory includes DRAM, and the memory cell includes a capacitor. The capacitor includes a pillar-shaped second electrode, a dielectric covering the sidewalls and bottom of the second electrode, and a first electrode covering the dielectric. In practical applications, the second electrode may be connected to the source of a transistor in the transistor array, and the first electrode may be connected to a reference voltage, which may be ground or other voltages. The capacitor is used to store written data.

[0168] In some embodiments, the memory includes a resistive random access memory (RRAM), and the memory cell includes an adjustable resistor connected between the bit line BL and the source S of a transistor in the transistor array 20; or, the adjustable resistor is connected between the bit line BL and the drain D of a transistor in the transistor array 20, and the adjustable resistor is used to adjust the state of the stored data by the bit line voltage provided by the bit line BL.

[0169] It should be noted that only some common memories are listed here as examples, and the scope of protection of this application is not limited to these. Any memory containing transistors provided in the embodiments of this application is within the scope of protection of this application.

[0170] Figure 5 A schematic diagram illustrating the implementation flow of a semiconductor structure manufacturing method provided in this application embodiment; Figure 6 This is a three-dimensional structural diagram illustrating the manufacturing process of a memory provided in an embodiment of this application.

[0171] The following is combined Figure 5 and Figure 6 The manufacturing method of the memory provided in the embodiments of this application will be described in detail. Please refer to... Figure 5 In some embodiments, the manufacturing method includes:

[0172] Step 5001, forming multiple storage units ( Figure 6 (Not shown in the image), the plurality of storage cells are arranged in an array along a first direction and a second direction;

[0173] Step 5002: Forming a transistor array 20, which is manufactured by the semiconductor structure manufacturing method described in the embodiments of this application; the gates 205 of each row of transistors AT1 / AT2 in the transistor array 20 along the first direction are physically connected to each other, and the physically connected gates form word lines WL; each memory cell is connected to the source S or drain D of a transistor in the transistor array 20; both the first direction and the second direction are perpendicular to the extension direction of the channel C of the transistor;

[0174] Step 5003: Form multiple bit lines BL that are arranged in parallel and spaced along the second direction. Each bit line BL is connected to the drain D or source S of a row of transistors arranged along the second direction in the transistor array 20.

[0175] Step 5001 is executed to form multiple storage cells, which are arranged in an array along a first direction and a second direction.

[0176] In some embodiments, the plurality of memory cells include the capacitors, each capacitor including a first electrode, a dielectric layer, and a second electrode. In practical applications, the second electrode of the capacitor is connected to the source S of a transistor in the transistor array 20, the first electrode of the capacitor is grounded, and the capacitor is used to store written data.

[0177] Step 5002 is executed to form a transistor array 20, which is manufactured by the semiconductor structure manufacturing method described in the embodiments of this application; the gates 205 of each row of transistors AT1 / AT2 in the transistor array 20 along the first direction are physically connected to each other, and the physically connected gates form word lines WL; each memory cell is connected to the source S or drain D of a transistor in the transistor array 20; the first direction and the second direction are both perpendicular to the extension direction of the channel C of the transistor.

[0178] In practical applications, the gate oxide layer 204, the first dielectric layer 201, the gate isolation structure 207, and the second dielectric layer 206 are all made of insulating materials, and their materials can be the same or different.

[0179] Step 5003 is executed to form multiple bit lines BL that are arranged in parallel and spaced along the second direction. Each bit line BL is connected to the drain D or source S of a row of transistors arranged along the second direction in the transistor array 20.

[0180] In some embodiments, the method for forming a plurality of bit lines BL arranged side by side along the second direction, wherein the bit lines BL are embedded bit lines, includes:

[0181] Active layer 101 is provided. Please refer to the above for details. Figure 3a The relevant descriptions in the document will not be repeated here;

[0182] The active layer 101 is etched along a surface portion of the active layer to form a first trench T1 extending in a first direction and arranged parallel to each other in a second direction, and a second trench T2 extending in a second direction and arranged parallel to each other in the first direction; and the first trench T1 and the second trench T2 have a first depth H1 and a second depth H2 respectively along the extension direction of the channel C, wherein the first depth H1 is greater than the second depth H2.

[0183] The alloying process allows for the partial metallization of multiple first semiconductor layers 203 located below and within the first trench T1, forming a structure as shown below. Figure 6 The bit line BL shown is located in the third direction below the second trench T2 (in conjunction with...) Figure 4 This can be understood as the bit line BL being located below the channel C, to form an embedded bit line. In the embodiments of this application, the material of the bit line can be a metallic material or a semiconductor conductive material, such as copper, cobalt, tungsten, doped silicon, polycrystalline silicon, or any combination thereof.

[0184] The memory manufactured by the method of manufacturing the memory provided in this application is similar to the memory in the above embodiments. For technical features not disclosed in detail in the embodiments of this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0185] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0186] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0187] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes a plurality of transistors, each of the plurality of transistors comprising: A channel, the channel including a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer; the second semiconductor layer introduces strain in the channel; A gate, covering at least one side of the channel; The source and drain are located at opposite ends of the channel's extension direction, respectively. The first semiconductor layer is made of silicon-germanium, and the second semiconductor layer is made of silicon. The second semiconductor layer covers the sidewalls and top surface of the first semiconductor layer; The plurality of channels corresponding to the plurality of transistors are arranged in an array along a first direction and a second direction, both of which are perpendicular to the extension direction of the channel; The gates of each transistor in each row of transistors spaced apart along the first direction are physically connected to each other; the gates of two adjacent rows of transistors spaced apart along the first direction are electrically isolated from each other.

2. The semiconductor structure according to claim 1, characterized in that, The gate is disposed around the channel.

3. The semiconductor structure according to claim 1, characterized in that, The cross-sectional shape of the channel includes one of the following: Circular; Oval shape; rectangle.

4. The semiconductor structure according to claim 1, characterized in that, The transistor is N-type, and the strain is tensile strain; or, the transistor is P-type, and the strain is compressive strain.

5. A method for manufacturing a semiconductor structure, characterized in that, The semiconductor structure includes a plurality of transistors, and the manufacturing method includes: Multiple channels are formed; each channel includes a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer; the second semiconductor layer introduces strain into the channel; The first semiconductor layer is made of silicon-germanium, and the second semiconductor layer is made of silicon. The second semiconductor layer covers the sidewalls and top surface of the first semiconductor layer; The plurality of transistors correspond to the plurality of channels; forming the plurality of channels includes: Provide an active layer; The active layer is partially etched to form multiple first trenches extending along a first direction and multiple second trenches extending along a second direction, as well as multiple first semiconductor layers located at the intersection of the first trenches and the second trenches; the sidewalls of each first semiconductor layer are exposed in the first trenches and the second trenches and extend along a direction perpendicular to the surface of the active layer; the first direction and the second direction are parallel to the surface of the active layer; A second semiconductor layer is formed on the sidewalls and top surface of the first semiconductor layer.

6. The method according to claim 5, characterized in that, The method further includes: A first semiconductor layer with a rectangular cross-sectional shape is formed in the active layer; Through an oxidation process, the cross-sectional shape of the first semiconductor layer is changed from rectangular to elliptical.

7. The method according to claim 5, characterized in that, The first groove and the second groove have a first depth and a second depth respectively along the extension direction of the channel, and the first depth is different from the second depth.

8. The method according to claim 5, characterized in that, After forming the plurality of channels, the method further includes: A first dielectric layer is filled in the first trench and the second trench having the second semiconductor layer; Partial etching of the first dielectric layer forms a third trench, and filling the third trench with insulating material forms a gate isolation structure; Partial etching of the first dielectric layer forms an exposed second semiconductor layer; A gate oxide layer is formed on the exposed second semiconductor layer; A first conductive material and a second dielectric layer are sequentially filled; the first conductive material is used to form the gate of each transistor.

9. A memory, characterized in that, include: Multiple storage cells are arranged in an array along a first direction and a second direction; A transistor array comprising a plurality of semiconductor structures as described in any one of claims 1 to 4; the gates of each row of transistors arranged at intervals along the first direction in the transistor array are physically connected to each other, the physically connected gates forming word lines; each memory cell is connected to the source or drain of a transistor in the transistor array; both the first direction and the second direction are perpendicular to the extension direction of the channel of the transistor; Multiple bit lines are arranged parallel to each other along the second direction, and each bit line is connected to the drain or source of a row of transistors arranged at intervals along the second direction in the transistor array.

10. The memory according to claim 9, characterized in that, The memory includes: dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.

11. The memory according to claim 10, characterized in that, The memory includes: dynamic random access memory, and the memory cell includes: a capacitor; the capacitor includes a columnar second electrode, a dielectric covering the sidewalls and bottom of the second electrode, and a first electrode covering the dielectric.

12. A method for manufacturing a memory, characterized in that, The method includes: Multiple storage cells are formed, and the multiple storage cells are arranged in an array along a first direction and a second direction; A transistor array is formed, the transistor array being manufactured by the semiconductor structure manufacturing method according to any one of claims 5 to 8; the gates of each row of transistors arranged at intervals along the first direction in the transistor array are physically connected to each other, and the physically connected gates form word lines; each of the memory cells is connected to the source or drain of a transistor in the transistor array; both the first direction and the second direction are perpendicular to the extension direction of the channel of the transistor; Multiple bit lines are formed and arranged in parallel along the second direction, and each bit line is connected to the drain or source of a row of transistors arranged in the transistor array along the second direction.

Images