A vertical structure LED chip and its manufacturing method

Abstract

Embodiments of the present application belong to the technical field of LED chips, and relate to a vertical-structured LED chip, including a conductive substrate, an epitaxial structure layer, a P electrode, and a two-dimensional material layer; the epitaxial structure layer is disposed on the conductive substrate, and the epitaxial structure layer includes a P-type gallium nitride material layer; the P electrode is disposed on the epitaxial structure layer, and the P electrode forms an ohmic contact with the P-type gallium nitride material layer; the two-dimensional material layer is disposed on the epitaxial structure layer, and the two-dimensional material layer forms a heterostructure with the P-type gallium nitride material layer through van der Waals force. The present application also relates to a method for manufacturing an LED chip. The technical solution provided by the present application can reduce the size of the LED device and improve the light-emitting power of the LED device.

Description

Technical Field

[0001] The present application relates to the technical field of LED chips, and more specifically, to a vertical structure LED chip and a method for manufacturing an LED chip. Background Art

[0002] With the continuous expansion of the LED lighting market share, the application scenarios of LEDs are becoming increasingly broad. With the gradual development of visible light communication technology, LEDs are considered to be ideal light sources for visible light communication (VLC) systems because of their excellent optoelectronic properties and the physical characteristics of semiconductor devices with high-speed on-off blinking.

[0003] In order to improve the communication rate and call quality of the entire communication system, the modulation bandwidth of the LED is increased. Currently, the common method for increasing the modulation bandwidth of the LED is to reduce the size of the LED device. However, reducing the size of the LED device will cause the luminous power of the LED to decrease, making it impossible for the LED device to improve both communication quality and luminous power simultaneously. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of the present application is that existing LED devices cannot improve both communication quality and luminous power simultaneously.

[0005] To solve the above technical problem, the embodiments of the present application provide a vertical structure LED chip, which adopts the following technical solutions:

[0006] A vertical structure LED chip includes a conductive substrate, an epitaxial structure layer, a P electrode, and a two-dimensional material layer;

[0007] The epitaxial structure layer is disposed on the conductive substrate, and the epitaxial structure layer includes a P-type gallium nitride material layer;

[0008] The P electrode is disposed on the epitaxial structure layer, and the P electrode forms an ohmic contact with the P-type gallium nitride material layer;

[0009] The two-dimensional material layer is disposed on the epitaxial structure layer, and the two-dimensional material layer forms a heterostructure with the P-type gallium nitride material layer through van der Waals force.

[0010] Further, the LED chip further includes an N electrode. An N electrode step is formed on the side of the epitaxial structure layer facing the conductive substrate, and the N electrode is disposed in the N electrode step.

[0011] Further, the epitaxial structure layer further includes an N-type gallium nitride material layer and a multi-quantum well layer;

[0012] The N-type gallium nitride material layer is disposed on the conductive substrate;

[0013] The multiple quantum well layer is disposed on the N-type gallium nitride material layer;

[0014] The P-type gallium nitride material layer is disposed on the multiple quantum well layer.

[0015] Further, the multiple quantum well layer includes at least one InGaN / GaN combined layer, and the InGaN / GaN combined layer is composed of an InGaN well layer located below and a GaN well layer located above which are interconnected.

[0016] Further, the LED chip further includes a buffer layer, and the buffer layer is disposed between the conductive substrate and the N-type gallium nitride material layer.

[0017] Further, the material of the conductive substrate is selected from one of Si, ITO, Si, GaN, SiN, and SiC;

[0018] And / or, the material of the P electrode is selected from at least one of Ti, Cr, Ag, Au, and Pt;

[0019] And / or, the material of the N electrode is selected from at least one of Ni, Au, Sn, and Ti;

[0020] And / or, the material of the N-type gallium nitride material layer is a doped GaN material, wherein the doping method of the N-type gallium nitride material layer is N-type doping, and the doping material for N-type doping is one of Si or N;

[0021] And / or, the material of the P-type gallium nitride material layer is a doped GaN material, wherein the doping method of the P-type gallium nitride material layer is P-type doping, and the doping material for P-type doping is Mg;

[0022] And / or, the material of the two-dimensional material layer is an MXene material, wherein the MXene material is selected from at least one of Hf2C(OH)2, Zr2N(OH)2, and NbC2;

[0023] And / or, the material of the buffer layer is selected from at least one of AlN and AlGaN.

[0024] Further, the thickness range of the conductive substrate is 500 μm to 700 μm;

[0025] And / or, the thickness range of the P electrode is 500 to 700 nm;

[0026] And / or, the thickness range of the N electrode is 300 to 500 nm;

[0027] And / or, the thickness range of the N-type gallium nitride material layer is 200 - 300 nm;

[0028] And / or, the thickness range of the P-type gallium nitride material layer is 200 - 300 nm;

[0029] And / or, the thickness range of the multi-quantum well layer is 21 - 33 nm;

[0030] And / or, the thickness range of the two-dimensional material layer is 5 - 10 nm;

[0031] And / or, the thickness range of the buffer layer is 5 - 10 μm.

[0032] Furthermore, the LED chip further includes a protective layer, and the protective layer is disposed on the P electrode.

[0033] To solve the above technical problems, an embodiment of the present application further provides a method for manufacturing an LED chip, which adopts the following technical solutions:

[0034] A method for manufacturing an LED chip, which is used to manufacture the vertical structure LED chip as described above, and is characterized by including the following steps:

[0035] Provide a substrate, and grow an epitaxial structure layer on the substrate;

[0036] Prepare a P electrode on the epitaxial structure layer, wherein the P electrode forms an ohmic contact with the P-type gallium nitride material layer;

[0037] Prepare a two-dimensional material layer on the epitaxial structure layer, wherein the two-dimensional material layer and the P-type gallium nitride material layer of the epitaxial structure layer form a heterostructure through van der Waals force, and the two-dimensional material layer at least partially covers the P electrode.

[0038] Furthermore, after preparing the P electrode on the epitaxial structure layer and before preparing the two-dimensional material layer on the epitaxial structure layer, the following steps are further included:

[0039] Remove the substrate;

[0040] Etch the bottom surface of the epitaxial structure layer to form an N electrode step;

[0041] Prepare an N electrode in the N electrode step;

[0042] Prepare a buffer layer on the bottom surface of the epitaxial structure layer, and the buffer layer completely covers the bottom surface of the epitaxial structure layer and the N electrode;

[0043] Prepare a conductive substrate on the buffer layer.

[0044] Compared with the prior art, the embodiments of the present application mainly have the following beneficial effects:

[0045] In the present invention, a two-dimensional material layer is prepared on the epitaxial structure layer, and the two-dimensional material layer forms a heterostructure with the P-type gallium nitride material layer on the uppermost layer of the epitaxial structure layer, enhancing the current expansion inside the LED chip, improving the uniformity of current distribution, and thus improving the light-emitting efficiency of the LED chip; in addition, the formation of a heterostructure between the two-dimensional material layer and the P-type gallium nitride material layer can also enhance the hole injection efficiency inside the LED chip, shorten the time required for the combination of holes and electrons, thereby reducing the carrier recombination lifetime, and further achieving the effect of reducing the RC time constant, achieving the effects of simultaneously increasing the light-emitting power and improving the communication quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the solution of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 is a schematic structural diagram of the LED chip according to the embodiment of the present application;

[0048] Figure 2 is a schematic structural diagram of the LED chip according to another embodiment of the present application;

[0049] Figure 3 is a flowchart of the method for manufacturing the LED chip according to the embodiment of the present application;

[0050] Figure 4 is a current-voltage characteristic curve graph of the LED chip according to the embodiment of the present application and a conventional LED chip;

[0051] Figure 5 is a light power-current characteristic curve graph of the LED chip according to the embodiment of the present application and a conventional LED chip.

[0052] REFERENCE NUMERALS:

[0053] 1, conductive substrate; 2, epitaxial structure layer; 21, N-type gallium nitride material layer; 22, multi-quantum well layer; 23, P-type gallium nitride material layer; 3, P electrode; 4, two-dimensional material layer; 5, N electrode; 6, buffer layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "comprising" and "having" and any variations thereof in the specification and claims of this application and the above drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the specification and claims of this application or the above drawings are used to distinguish different objects and not to describe a specific order.

[0055] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] Embodiment 1 of the vertical structure LED chip of this application

[0057] Please refer to Figure 1 As shown, the embodiment of this application provides a vertical structure LED chip, including: a conductive substrate 1, an epitaxial structure layer 2, a P electrode 3, and a two-dimensional material layer 4.

[0058] The epitaxial structure layer 2 is disposed on the conductive substrate 1. The epitaxial structure layer 2 includes a P-type gallium nitride material layer 23. In this embodiment, the epitaxial structure layer 2 further includes an N-type gallium nitride material layer 21 and a multi-quantum well layer 22. The N-type gallium nitride material layer 21 is disposed on the conductive substrate 1; the multi-quantum well layer 22 is disposed on the N-type gallium nitride material layer 21; the P-type gallium nitride material layer 23 is disposed on the multi-quantum well layer 22.

[0059] The P electrode is disposed on the epitaxial structure layer 2, and the P electrode 3 forms an ohmic contact with the P-type gallium nitride material layer 23.

[0060] The two-dimensional material layer 4 is disposed on the epitaxial structure layer 2. The two-dimensional material layer 4 forms a heterostructure with the P-type gallium nitride material layer 23 through van der Waals forces. In this embodiment, the two-dimensional material layer 4 at least partially covers the P electrode 3.

[0061] In the LED chip with a vertical structure provided by the embodiments of the present application, a two-dimensional material layer 4 is prepared on the epitaxial structure layer 2, and the two-dimensional material layer 4 forms a heterostructure with the uppermost P-type gallium nitride material layer 23 of the epitaxial structure layer 2, enhancing the current expansion inside the LED chip, improving the uniformity of current distribution, and thus improving the luminous efficiency of the LED chip; in addition, the formation of the heterostructure between the two-dimensional material layer 4 and the P-type gallium nitride material layer 23 can also enhance the hole injection efficiency inside the LED chip to shorten the time required for the combination of holes and electrons, thereby reducing the carrier recombination lifetime, and further achieving the effect of reducing the RC time constant, and achieving the effects of simultaneously improving the luminous power and improving the communication quality.

[0062] Please continue to refer to Figure 1 As shown, in some embodiments, an N electrode step is formed on the side of the epitaxial structure layer 2 facing the conductive substrate 1. In this embodiment, the epitaxial structure layer 2 is etched to form the N electrode step. The N electrode step penetrates the N-type gallium nitride material layer 21, and the bottom of the N electrode step extends deep into the multi-quantum well layer 22.

[0063] In some embodiments, the N-type gallium nitride material layer 21 is disposed on the conductive substrate 1, the multi-quantum well layer 22 is disposed on the N-type gallium nitride material layer 21, and the P-type gallium nitride material layer 23 is disposed on the multi-quantum well layer 22.

[0064] The multi-quantum well layer 22 includes at least one InGaN / GaN combination layer. The InGaN / GaN combination layer is composed of an InGaN well layer located below and a GaN well layer located above connected to each other. In this embodiment, the multi-quantum well layer 22 includes three InGaN / GaN combination layers. The upper surface of the N-type gallium nitride material layer 21 is connected to the lowermost InGaN well layer of the multi-quantum well layer 22, and the lower surface of the P-type gallium nitride material layer 23 is connected to the uppermost GaN well layer of the multi-quantum well layer 22. The N electrode 5 is disposed in the N electrode step, and the bottom of the N electrode 5 is in contact with one of the InGaN well layers. The side wall of the N electrode 5 and the multi-quantum well material are filled with N-type gallium nitride material.

[0065] By providing the multi-quantum well layer 22 in the embodiments of the present application, the capture probability of carriers is increased, thereby increasing the carrier recombination probability in the LED chip and increasing the luminous power of the LED chip. By forming an N electrode step on the side of the epitaxial structure layer facing the conductive substrate and disposing the N electrode in the N electrode step, the uniform distribution of the current inside the LED chip is optimized and the current expansion is improved.

[0066] In some embodiments, the epitaxial structure layer 2 further includes a buffer layer 6, and the buffer layer 6 is disposed between the conductive substrate 1 and the N-type gallium nitride material layer 21.

[0067] In the embodiment of the present application, by preparing the buffer layer 6 on the conductive substrate 1, the morphology of the conductive substrate 1 can be adjusted, so as to reduce the process complexity of preparing the epitaxial structure, and make the growth quality of the epitaxial structure layer 2 better. In addition, the mismatch stress between the epitaxial structure layer 2 and the conductive substrate 1 can be reduced.

[0068] In some embodiments, the material of the conductive substrate 1 is selected from one of Si, ITO, Si, GaN, SiN, and SiC. Among them, the thickness range of the conductive substrate 1 is 500-700 μm, for example: 500 μm, 550 μm, 600 μm, 650 μm, 700 μm. In this embodiment, the material of the conductive substrate 1 is preferably Si, and the thickness is 500 μm.

[0069] In some embodiments, the material of the buffer layer 6 is selected from at least one of AlN and AlGaN. Among them, the thickness range of the buffer layer 6 is 5-10 μm, for example: 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm. In this embodiment, the material of the buffer layer 6 is preferably Al, and the thickness is 7 μm.

[0070] In some embodiments, the material of the N-type gallium nitride material layer 21 is doped GaN material. Among them, the doping method of the N-type gallium nitride material layer 21 is N-type doping, and the doping material for N-type doping is one of Si or N. The thickness range of the N-type gallium nitride material layer 21 is 200-300 nm, for example: 200 nm, 250 nm, 300 nm. In this embodiment, the material of the N-type gallium nitride material layer 21 is Si-doped GaN material, and the thickness is 300 nm.

[0071] In some embodiments, the multiple quantum well layer 22 includes three layers of InGaN / GaN composite layers. Among them, the thickness range of the InGaN well layer is 2-4 nm, for example: 2 nm, 3 nm, 4 nm; the thickness range of the GaN well layer is 5-7 nm, for example: 5 nm, 6 nm, 7 nm; the thickness of the multiple quantum well layer 22 is 21-33 nm, for example: 21 nm, 24 nm, 27 nm, 30 nm, 33 nm. In this embodiment, the thickness of the InGaN well layer is 2 nm, the thickness of the GaN well layer is 5 nm, and the thickness of the multiple quantum well layer 22 is 21 nm.

[0072] In some embodiments, the material of the P-type gallium nitride material layer 23 is doped GaN material. Among them, the doping method of the P-type gallium nitride material layer 23 is P-type doping, and the doping material for P-type doping is Mg. The thickness range of the P-type gallium nitride material layer 23 is 200 - 300 μm, for example: 200 μm, 250 μm, 300 μm. In this embodiment, the material of the P-type gallium nitride material layer 23 is Mg-doped GaN material, and the thickness is 300 nm.

[0073] In some embodiments, the material of the P electrode 3 is selected from at least one of Ti, Cr, Ag, Au, and Pt. Among them, the thickness range of the P electrode 3 is 500 - 700 nm, for example: 500 nm, 550 nm, 600 nm, 650 nm, 700 nm. In this embodiment, the material of the P electrode 3 is Ag, and the thickness is 500 nm.

[0074] In some embodiments, the material of the two-dimensional material layer 4 is MXene material. Among them, the MXene material is selected from at least one of 2 Hf 2 C(OH) 2 、Zr 2 N(OH) 2 、NbC 2 Among them, the thickness range of the two-dimensional material layer 4 is 5 - 10 nm, for example: 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm. In this embodiment, the material of the two-dimensional material layer 4 is NbC

[0075] In some embodiments, the material of the N electrode 5 is selected from at least one of Ni, Au, Sn, and Ti. Among them, the thickness range of the N electrode 5 is 300 - 500 nm, for example: 300 nm, 310 nm, 350 nm, 400 nm, 450 nm, 500 nm. In this embodiment, the material of the N electrode 5 is a Ti, Cr alloy, and the thickness is 310 nm.

[0076] Embodiment 2 of the vertical structure LED chip of the present application

[0077] Please refer to Figure 1 、 Figure 2 As shown, the embodiment of the present application provides a vertical structure LED chip, including: a conductive substrate 1, a buffer layer 6, at least one epitaxial structure layer 2, a P electrode 3, a two-dimensional material layer 4, and at least one N electrode 5. The conductive substrate 1, the buffer layer 6, one epitaxial structure layer 2, the P electrode 3, the two-dimensional material layer 4, and one N electrode 5 are combined to form a vertical structure LED chip, and multiple vertically structured LED chips arranged in a parallel array are formed on the conductive substrate.

[0078] In some embodiments, the buffer layer 6 is disposed on the conductive substrate 1; a plurality of the epitaxial structure layers 2 are spaced apart on the buffer layer 6, and an insulating layer is formed between two adjacent epitaxial structure layers 2. In this embodiment, the material of the insulating layer is silicon dioxide (SiO 2 ); The P electrode 3 is disposed on the epitaxial structure layer 2 and is ohmically connected to the plurality of epitaxial structure layers 2 respectively; the two-dimensional material layer 4 is disposed on the epitaxial structure layer 2 and forms a heterostructure with the plurality of epitaxial structure layers 2 respectively through van der Waals force, and at least a part of the two-dimensional material layer 4 covers the P electrode 3.

[0079] The vertical structure LED chip provided by the embodiment of the present application improves the light output power of the LED chip and the applicability of the LED chip to different scenarios by setting multiple groups of epitaxial structure layers 2 arranged in parallel. In addition, through the heterostructure formed by the two-dimensional material layer 4 and the plurality of epitaxial structure layers 2, the current expansion inside each epitaxial structure layer 2 is enhanced, and the uniformity of current spreading is improved, thereby improving the overall luminous efficiency of the LED chip; In addition, the heterostructure formed by the two-dimensional material layer 4 and the epitaxial structure layer 2 can also enhance the hole injection efficiency inside the LED chip, so as to shorten the time required for the combination of holes and electrons, thereby reducing the carrier recombination lifetime, and further achieving the effect of reducing the RC time constant, achieving the effect of simultaneously improving the luminous power and improving the communication quality.

[0080] In some embodiments, an N electrode step is etched on one side of each epitaxial structure layer 2 connected to the buffer layer 6. In this embodiment, the epitaxial structure layer 2 includes an N-type gallium nitride material layer 21, a multi-quantum well layer 22, and a P-type gallium nitride material layer 23 stacked. The N electrode step penetrates the N-type gallium nitride material layer 21 and the bottom of the N electrode step extends into the multi-quantum well layer 22. A plurality of the N electrodes 5 are correspondingly disposed in the N electrode step, and an N-type gallium nitride material is filled between the side wall of the N electrode 5 and the multi-quantum well material.

[0081] The embodiment of the present application increases the capture probability of carriers by setting the multi-quantum well layer 22, thereby increasing the carrier recombination probability in the LED chip and increasing the luminous power of the LED chip.

[0082] Embodiment of the preparation method of the LED chip of the present application

[0083] Please refer to Figure 3 As shown, the embodiment of the present application provides a preparation method of an LED chip for preparing the LED chip as described above, including the following steps:

[0084] Step S100, providing a substrate and growing an epitaxial structure layer on the substrate.

[0085] In this embodiment, the material of the substrate is selected from one of Si, SiC, and GaN.

[0086] In some embodiments, in step S100, before growing the epitaxial structure layer on the substrate, the following steps are further included:

[0087] A buffer layer is grown on the substrate by metalorganic chemical vapor deposition (MOCVD method), and the material of the buffer layer is selected from at least one of AlN and AlGaN.

[0088] In this embodiment, step S100 of providing a substrate and growing an epitaxial structure layer on the substrate specifically includes the following steps:

[0089] A Si-doped GaN material is grown on the buffer layer by metalorganic chemical vapor deposition to form an N-type gallium nitride material layer. In this embodiment, during the process of growing the N-type gallium nitride material layer by metalorganic chemical vapor deposition, trimethylgallium (TMGa) is used as the gallium source, ammonia (NH 3 ) is used as the nitrogen source, and epitaxial growth is carried out in the reaction atmosphere of silane (SiH 4 ).

[0090] An InGaN well layer and a GaN well layer are sequentially grown on the N-type gallium nitride material layer by metalorganic chemical vapor deposition to form a multi-quantum well layer. In this embodiment, when growing the InGaN well layer, the ambient temperature is controlled at 880 °C, and when growing the GaN well layer, the ambient temperature is controlled at 1080 °C. During the process of growing the multi-quantum well layer by metalorganic chemical vapor deposition, trimethylgallium (TMGa) is used as the gallium source, trimethylindium (TMIn) is used as the indium source, and ammonia (NH 3 ) is used as the nitrogen source for epitaxial growth.

[0091] A Mg-doped GaN material is grown on the multi-quantum well layer by metalorganic chemical vapor deposition to form a P-type gallium nitride material layer. In this embodiment, during the process of growing the P-type gallium nitride material layer by metalorganic chemical vapor deposition, trimethylgallium (TMGa) is used as the gallium source, trimethylindium (TMIn) is used as the indium source, and bis(cyclopentadienyl)magnesium (Mg(C 5 H 5 ) 2 ) is used as the magnesium source for epitaxial growth.

[0092] In this embodiment, the material of the N-type gallium nitride material layer is Si-doped GaN material, and the thickness is 300 nm; the thickness of the multi-quantum well is 21 nm; the material of the P-type gallium nitride material layer is Mg-doped GaN material, and the thickness is 300 nm.

[0093] Step S200: fabricate a P electrode on the epitaxial structure layer, wherein the P electrode forms an ohmic contact with the P-type gallium nitride material layer.

[0094] In some embodiments, step S200 of fabricating a P electrode on the epitaxial structure layer specifically includes the following steps:

[0095] Deposit a P contact mirror metal on the P-type gallium nitride material layer through an electron beam evaporation device to form a P electrode.

[0096] In this embodiment, the metal evaporation rate of the P electrode deposited by the electron beam evaporation device is 15 Å / s, the material of the P electrode is Ag, and the thickness is 500 nm.

[0097] In some embodiments, after step S200, the following steps are further included:

[0098] Deposit a protective layer on the P electrode through an electron beam evaporation device, wherein the metal evaporation rate of the protective layer deposited by the electron beam evaporation device is 15 Å / s.

[0099] In some embodiments, after step S200, the step of fabricating an N electrode is further included, specifically including the following steps:

[0100] Remove the substrate.

[0101] In this embodiment, the substrate of the device fabricated in step S200 is mechanically polished and then immersed in a mixed acidic solution to corrode and remove the substrate.

[0102] Use inductively coupled plasma (ICP) etching to remove the buffer layer of the device after removing the substrate to expose the bottom surface of the epitaxial structure layer.

[0103] Etch the bottom surface of the epitaxial structure layer to form an N electrode step.

[0104] In some embodiments, after removing the substrate and before etching the bottom surface of the epitaxial structure layer, the following steps are further included:

[0105] Use inductively coupled plasma (ICP) etching method to etch the epitaxial structure layer to form a plurality of independent units, and an isolation region with the same interval is formed between two adjacent independent units.

[0106] Deposit an insulating material in the isolation region by plasma enhanced chemical vapor deposition (PECVD) method. In this embodiment, the insulating material is SiO 2 .

[0107] By forming multiple independent units, multiple LED chips in a side-by-side array are formed on the buffer layer, improving device performance.

[0108] In this embodiment, the bottom surface of the epitaxial structure layer is etched to form an N-electrode step, specifically including the following steps:

[0109] Each independent unit is processed by photolithography to form an N-electrode step within each independent unit.

[0110] An N-electrode is prepared within the N-electrode step.

[0111] In this embodiment, the preparation of the N-electrode within the N-electrode step includes the following steps:

[0112] An N-type metal is deposited within the N-electrode step by an electron beam evaporation device to form an N-electrode.

[0113] In this embodiment, the metal evaporation rate of the N-electrode deposited by the electron beam evaporation device is 15 Å / s, the material of the N-electrode is a Ti, Cr alloy, and the thickness is 310 nm.

[0114] A buffer layer is prepared on the bottom surface of the epitaxial structure layer, and the buffer layer completely covers the multiple independent units.

[0115] In this embodiment, the preparation of the buffer layer on the bottom surface of the epitaxial structure layer specifically includes the following steps:

[0116] A buffer layer is grown on the bottom surface of the epitaxial structure layer by metalorganic chemical vapor deposition (MOCVD method). Among them, the material of the buffer layer is preferably Al, and the thickness is 7 μm.

[0117] A conductive substrate is prepared on the buffer layer.

[0118] In this embodiment, the material of the conductive substrate is preferably a conductive silicon substrate, and the thickness is 500 μm.

[0119] Step S300, a two-dimensional material layer is prepared on the epitaxial structure layer, wherein the two-dimensional material layer and the P-type gallium nitride material layer of the epitaxial structure layer form a heterostructure through van der Waals forces.

[0120] In some embodiments, the step S300 of preparing a two-dimensional material layer on the epitaxial structure layer includes the following steps:

[0121] The epitaxial structure layer is cleaned.

[0122] In this embodiment, an acetone solution is used to clean the P-electrode of the device prepared in S200 and the epitaxial structure layer.

[0123] A two-dimensional material solution is formed on the epitaxial structure layer to form a liquid film.

[0124] In this embodiment, NbC 2 solution is dropped onto the P electrode and the epitaxial structure layer, and is evenly spread by spin coating to form a liquid film.

[0125] The liquid film is dried at a set temperature to form a two-dimensional material layer.

[0126] In this embodiment, the device carrying the liquid film is dried at a temperature of 75 °C to 80 °C for 30 min to form a two-dimensional material layer. In this embodiment, the material of the two-dimensional material layer is NbC2, and the thickness is 10 nm.

[0127] The LED chip prepared by the preparation method of the embodiment of the present application improves the light output power of the LED chip and the applicability of the LED chip to different scenarios by arranging multiple groups of epitaxial structure layers arranged in parallel. In addition, through the heterostructure formed by the two-dimensional material layer and multiple epitaxial structure layers, the current expansion inside each epitaxial structure layer is enhanced, and the uniformity of current spreading is improved, thereby improving the overall light emission efficiency of the LED chip; in addition, the heterostructure formed by the two-dimensional material layer and the epitaxial structure layer can also enhance the hole injection efficiency inside the LED chip to shorten the time required for holes and electrons to combine, thereby reducing the carrier recombination lifetime, and further achieving the effect of reducing the RC time constant, achieving the effect of simultaneously improving the light emission power and improving the communication quality.

[0128] The above scheme is further described below in conjunction with specific implementation examples. The preferred embodiments of the present invention are described in detail as follows:

[0129] Example 1

[0130] ⑴ Provide a substrate, wherein the material of the substrate is Si.

[0131] ⑵ Under the condition of 1100 °C, a buffer layer is epitaxially grown on the substrate by metalorganic chemical vapor deposition.

[0132] ⑶ Under the condition of 880 °C, trimethylgallium (TMGa) is used as the gallium source, ammonia (NH 3 ) is used as the nitrogen source, and in the reaction atmosphere of silane (Si H 4 ), an N-type gallium nitride material layer is epitaxially grown on the buffer layer by metalorganic chemical vapor deposition. Among them, the material of the N-type gallium nitride material layer is Si-doped GaN material, and the thickness is 300 nm.

[0133] ⑷ Trimethylgallium (TMGa) is used as the gallium source, trimethylindium (TM In) is used as the indium source, ammonia (NH3 ) As a nitrogen source, an InGaN well layer and a GaN well layer are sequentially grown on the N-type gallium nitride material layer by metal-organic chemical vapor deposition to form a multi-quantum well layer. When growing the InGaN well layer, the ambient temperature is controlled at 880 °C, and when growing the GaN well layer, the ambient temperature is controlled at 1080 °C. Among them, the thickness of the multi-quantum well is 21 nm.

[0134] ⑸ Trimethylgallium (TMGa) is used as the gallium source, trimethylindium (TMIn) is used as the indium source, and bis(cyclopentadienyl)magnesium (Mg(C 5 H 5 ) 2 ) is used as the magnesium source to epitaxially grow a P-type gallium nitride material layer on the multi-quantum well layer. Among them, the material of the P-type gallium nitride material layer is Mg-doped GaN material, and the thickness is 300 nm.

[0135] ⑹ A P-contact mirror metal is deposited on the P-type gallium nitride material layer by an electron beam evaporation device at a metal evaporation rate of 15 Å / s to form a P electrode. Among them, the material of the P electrode is Ag, and the thickness is 500 nm.

[0136] ⑺ The substrate of the device after the P electrode is prepared is mechanically polished and then immersed in a mixed acidic solution of hydrofluoric acid, glacial acetic acid, and nitric acid until the substrate completely disappears.

[0137] ⑻ The buffer layer of the device after the substrate is removed is removed by inductively coupled plasma (ICP) etching to expose the bottom surface of the epitaxial structure layer.

[0138] ⑼ The epitaxial structure layer is etched by inductively coupled plasma (ICP) etching method to form a plurality of independent units, and SiO 2 is deposited in the isolation region between adjacent two independent units by plasma-enhanced chemical vapor deposition (PECVD) method.

[0139] ⑽ Each independent unit is processed by photolithography to form an N electrode step in each independent unit.

[0140] ⑾ An N-type metal is deposited in the N electrode step by an electron beam evaporation device to form an N electrode. Among them, the material of the N electrode is a Ti, Cr alloy, and the thickness is 310 nm.

[0141] ⑿ A buffer layer is grown on the bottom surface of the epitaxial structure layer by metal-organic chemical vapor deposition (MOCVD method). Among them, the material of the buffer layer is preferably Al, and the thickness is 7 μm.

[0142] ⒀Prepare a conductive substrate on the buffer layer, wherein the material of the conductive substrate is preferably a conductive silicon substrate with a thickness of 500 μm

[0143] ⒁Clean the P electrode and the epitaxial structure layer of the device with an acetone solution.

[0144] ⒂Drop the NbC2 solution onto the P electrode and the epitaxial structure layer, and spread it evenly by spin coating to form a liquid film. Dry it at a temperature of 75 °C to 80 °C for 30 min to form a two-dimensional material layer to form an LED chip.

[0145] Comparative Example 1

[0146] The difference between Comparative Example 1 and Example 1 is that step ⒂ is absent, and the LED chip prepared in Comparative Example 1 has no two-dimensional material layer.

[0147] Analysis of test results:

[0148] The LED chips prepared by the preparation method of Example 1 and the LED chips prepared by the preparation method of Comparative Example 1 were respectively subjected to performance tests under the conditions of room temperature (25 °C) and atmospheric pressure. The test results are as Figure 4 、 Figure 5 shown.

[0149] Please refer to Figure 4 shown. Under the conditions of room temperature (25 °C) and atmospheric pressure, when the LED chip is started and the same current is output, the voltage measured by the LED chip of Example 1 is less than the voltage measured by the LED chip of Comparative Example 1. Therefore, according to Figure 4 's current-voltage characteristic curve, it can be considered that the LED chip of Example 1 has a higher photoelectric conversion efficiency.

[0150] Please refer to Figure 5 shown, wherein the optical output power refers to the ability of a light-emitting body to convert the absorbed energy into light energy when excited. Therefore, according to Figure 5 's optical power vs. current characteristic curve, it can be considered that under the condition of the same output current, the LED chip of Example 1 has a higher optical output power, and the LED chip of Example 1 can improve the luminous power.

[0151] In summary, the LED chip prepared in Example 1 can improve the luminous efficiency, improve the luminous power, and play a role in reducing the size of the LED chip, thereby improving the communication quality.

[0152] Obviously, the embodiments described above are only a part of the embodiments of this application, rather than all of them. The preferred embodiments of this application are shown in the accompanying drawings, but they do not limit the patent scope of this application. This application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosed content of this application more thorough and comprehensive. Although this application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing specific embodiments, or perform equivalent replacements on some of the technical features. Any equivalent structure that makes use of the content of this application's specification and the accompanying drawings, directly or indirectly applied in other related technical fields, is similarly within the scope of patent protection of this application.

Claims

1. A vertical-structured LED chip, characterized in that, it includes a conductive substrate, an epitaxial structure layer, a P electrode, an N electrode and a two-dimensional material layer; the epitaxial structure layer is disposed on the conductive substrate, and the epitaxial structure layer includes a P-type gallium nitride material layer, an N-type gallium nitride material layer and a multi-quantum well layer; the N-type gallium nitride material layer is disposed on the conductive substrate; the multi-quantum well layer is disposed on the N-type gallium nitride material layer; the P-type gallium nitride material layer is disposed on the multi-quantum well layer; wherein, an N electrode step is formed on a side of the epitaxial structure layer facing the conductive substrate; the P electrode is disposed on the epitaxial structure layer, and the P electrode forms an ohmic contact with the P-type gallium nitride material layer; the N electrode is disposed within the N electrode step; The two-dimensional material layer is disposed on the epitaxial structure layer. The two-dimensional material layer forms a heterostructure with the P-type gallium nitride material layer through van der Waals force. Among them, the material of the two-dimensional material layer is an MXene material. Among them, the MXene material is selected from Hf 2 C(OH) 2 , Zr 2 N(OH) 2 , NbC 2 at least one of them.

2. The vertical-structured LED chip according to claim 1, characterized in that, the multi-quantum well layer includes at least one InGaN / GaN combination layer, and the InGaN / GaN combination layer is composed of an InGaN well layer located below and a GaN well layer located above which are connected to each other.

3. The vertical-structured LED chip according to claim 2, characterized in that, the LED chip further includes a buffer layer, and the buffer layer is disposed between the conductive substrate and the N-type gallium nitride material layer.

4. The vertical-structured LED chip according to claim 3, characterized in that, the material of the conductive substrate is selected from one of Si, ITO, Si, GaN, SiN, and SiC; and / or, the material of the P electrode is selected from at least one of Ti, Cr, Ag, Au, and Pt; and / or, the material of the N electrode is selected from at least one of Ni, Au, Sn, and Ti; and / or, the material of the N-type gallium nitride material layer is a doped GaN material, wherein the doping method of the N-type gallium nitride material layer is N-type doping, and the doping material for N-type doping is one of Si or N; and / or, the material of the P-type gallium nitride material layer is a doped GaN material, wherein the doping method of the P-type gallium nitride material layer is P-type doping, and the doping material for P-type doping is Mg; and / or, the material of the buffer layer is selected from at least one of AlN and AlGaN.

5. The vertical-structured LED chip according to claim 3, characterized in that, the thickness range of the conductive substrate is 500 μm to 700 μm; and / or, the thickness range of the P electrode is 500 to 700 nm; and / or, the thickness range of the N electrode is 300 to 500 nm; and / or, the thickness range of the N-type gallium nitride material layer is 200 to 300 nm; and / or, the thickness range of the P-type gallium nitride material layer is 200 to 300 nm; and / or, the thickness range of the multi-quantum well layer is 21 to 33 nm; and / or, the thickness range of the two-dimensional material layer is 5 to 10 nm; and / or, the thickness range of the buffer layer is 5 to 10 μm.

6. The vertical-structured LED chip according to claim 1, characterized in that, The LED chip further includes a protective layer disposed on the P electrode.

7. A method for manufacturing an LED chip, which is used to manufacture the vertical structure LED chip according to any one of claims 1 to 6, characterized in that it includes the following steps: providing a substrate and growing an epitaxial structure layer on the substrate; fabricating a P electrode on the epitaxial structure layer, wherein the P electrode forms an ohmic contact with the P-type gallium nitride material layer; fabricating a two-dimensional material layer on the epitaxial structure layer, wherein the two-dimensional material layer and the P-type gallium nitride material layer of the epitaxial structure layer form a heterostructure through van der Waals force, and at least part of the two-dimensional material layer covers the P electrode.

8. According to the method for manufacturing an LED chip as claimed in claim 7, characterized in that after fabricating the P electrode on the epitaxial structure layer and before fabricating the two-dimensional material layer on the epitaxial structure layer, the following steps are further included: removing the substrate; etching the bottom surface of the epitaxial structure layer to form an N electrode step; fabricating an N electrode in the N electrode step; fabricating a buffer layer on the bottom surface of the epitaxial structure layer, and the buffer layer completely covers the bottom surface of the epitaxial structure layer and the N electrode; fabricating a conductive substrate on the buffer layer.

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