DIO message transmission method based on FPGA

Abstract

The present invention relates to the technical field of power system protection automation, and provides a DIO message transmission method based on FPGA, comprising: connecting a DIO module to an FPGA through a synchronous bus and a communication bus; the FPGA sends a synchronous pulse signal to synchronize the data of the DIO module with that of the FPGA; the FPGA and the CPU process data through interrupts, and process multiple DIO messages each time; after receiving the interrupt, the CPU reads a heartbeat message and multiple DIO messages through the LocalBus bus for processing; after the CPU compares and selects multiple DIO messages, the data transmission of the DIO message is realized, and the CPU completes the opening action. According to the scheme of the present invention, in order to realize the synchronization of multiple DIO modules, the FPGA sends a synchronization signal through the synchronous bus to ensure the synchronization error between the DIO modules, thereby improving the time accuracy of the DIO message communication. As a main communication device, the FPGA communicates with multiple DIO modules, and improves the communication reliability of the DIO message through multiple data retransmissions and a redundant check mechanism, thereby avoiding device malfunction events caused by communication errors.

Description

Technical Field

[0001] The present invention relates to the technical field of power system protection automation, and in particular to a DIO message transmission method based on FPGA. Background Art

[0002] In the power industry, DIO modules are a general term for input and output modules, which are used to collect input quantities and realize output quantities and tripping. When designing DIO module communication, traditional relay protection devices mainly use low-speed universal buses such as SPI bus or CAN bus to communicate with processors, which have disadvantages such as low communication rate, poor synchronization, and inconvenient expansion. Summary of the invention

[0003] The purpose of the present invention is to solve at least one technical problem in the background technology and provide a DIO message transmission method based on FPGA.

[0004] To achieve the above object, the present invention provides a DIO message transmission method based on FPGA, comprising:

[0005] Connect the DIO module and FPGA via the synchronization bus and the communication bus;

[0006] FPGA sends a synchronization pulse signal to synchronize the data between the DIO module and the FPGA;

[0007] The FPGA and CPU process data through interrupts, processing multiple DIO messages each time;

[0008] When the receive interrupt arrives, the CPU reads the heartbeat message and multiple DIO messages through the LocalBus bus for processing;

[0009] After the CPU compares and selects multiple DIO messages, the data transmission of the DIO messages is realized and the CPU completes the output action.

[0010] According to one aspect of the present invention, the CPU compares three DIO messages through a three-choose-two mechanism, selects two of the DIO messages, and implements DIO message data transmission.

[0011] According to one aspect of the present invention, the synchronous bus transmits a pulse signal with a period of 100 us.

[0012] According to one aspect of the present invention, the communication interval of the communication bus is 100 us.

[0013] According to one aspect of the present invention, the LocalBus bus is a parallel source synchronous communication bus.

[0014] According to one aspect of the present invention, the DIO module realizes time synchronization with the FPGA chip by means of external interrupt triggering, and the synchronization accuracy is 100ns.

[0015] According to one aspect of the present invention, the communication bus supports full-duplex communication of uplink data and downlink data, and the communication bus is composed of a clock, a chip select and a data line, wherein the frequency of the clock is ≤100 MHz.

[0016] According to one aspect of the present invention, the uplink data and the downlink data are valid when the chip select signal is 0, the uplink data includes a heartbeat message and data sent by the DIO module; the downlink data includes a heartbeat message and data received by the DIO module.

[0017] According to one aspect of the present invention, data exchange is achieved between the DIO module and the CPU through the heartbeat message, and the heartbeat message includes a sequence number, a monitoring state, a time stamp and CRC8.

[0018] According to one aspect of the present invention, the DIO message includes a sequence number, a message number, data of multiple DIO modules and CRC8, a total of 100 bytes of data.

[0019] According to one solution of the present invention, the FPGA chip serves as the main control device 1, which is connected to the DIO module through a synchronization bus and a communication bus. Through synchronization pulses, synchronization with multiple DIO modules is achieved, and the synchronization accuracy is not less than 100ns; the communication interval of the communication bus is 100us, and data interaction with multiple DIO modules is carried out in high real-time.

[0020] According to one solution of the present invention, the CPU chip serves as the main control device 2 and is connected to the FPGA chip via the Localbus bus. The LocalBus bus is a parallel source synchronous communication bus with the characteristics of high bandwidth and low latency. When triggered by an external interrupt, it reads the data of the DIO module at high speed to complete the data collection of the input quantity.

[0021] According to one solution of the present invention, the synchronous bus is a pulse signal with a period of 100us, and the DIO module realizes time synchronization with the FPGA chip through an external interrupt trigger. The communication bus consists of a clock, a chip select, and a data line, wherein the clock frequency supports up to 100MHz, realizing full-duplex communication of uplink data and downlink data.

[0022] According to one solution of the present invention, the DIO message contains a sequence number, message number, DIO module 1 data to DIO module 16 data and CRC8, a total of 100 bytes of data, to realize the acquisition of input quantity and the export and tripping of output quantity. In order to further improve the reliability, the DIO message is sent three times within the communication cycle of 100us, in which the message numbers are different. After receiving the DIO message, the FPGA uses the three-choose-two mechanism to prevent malfunction caused by data errors, which greatly improves the reliability of the relay protection device.

[0023] According to the solution of the present invention, in order to achieve synchronization of multiple DIO modules, the present invention sends synchronization signals through the synchronization bus by the FPGA, which ensures the synchronization error within 100ns between the DIO modules and improves the time accuracy of the DIO message communication. In addition, the FPGA, as the main communication device, communicates with multiple DIO modules in a high real-time manner according to the communication interval of the period of 100us, and improves the communication reliability of the DIO message of the relay protection device through multiple data retransmission and redundant verification mechanisms, avoids device malfunction events caused by communication errors, reduces economic losses, and improves social benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flowchart schematically showing a DIO message transmission method based on FPGA according to an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a DIO message transmission mechanism based on FPGA according to an embodiment of the present invention is schematically shown;

[0026] Figure 3 A timing diagram schematically showing a DIO message according to an embodiment of the present invention;

[0027] Figure 4 A diagram schematically showing a heartbeat message format according to an embodiment of the present invention;

[0028] Figure 5 A diagram schematically showing a DIO message format according to an embodiment of the present invention;

[0029] Figure 6 Schematically showing a DIO message data flow chart according to an embodiment of the present invention;

[0030] Figure 7 A DIO message transmission diagram according to an embodiment of the present invention is schematically shown. DETAILED DESCRIPTION

[0031] The content of the present invention will now be discussed with reference to exemplary embodiments. It should be understood that the embodiments discussed are only to enable those skilled in the art to better understand and thus implement the content of the present invention, rather than implying any limitation on the scope of the present invention.

[0032] As used herein, the term “including” and variations thereof are to be interpreted as open-ended terms meaning “including, but not limited to.” The term “based on” is to be interpreted as “based, at least in part, on.” The terms “one embodiment” and “an embodiment” are to be interpreted as “at least one embodiment.”

[0033] Figure 1 A flowchart schematically showing a DIO message transmission method based on FPGA according to an embodiment of the present invention; Figure 2 The schematic diagram shows a schematic block diagram of a DIO message transmission mechanism based on FPGA according to an embodiment of the present invention. Figure 1 and Figure 2 As shown, according to one embodiment of the present invention, the high-reliability DIO message transmission mechanism based on FPGA includes: multiple DIO modules, FPGA, CPU, synchronization bus, communication bus, LocalBus bus, etc. Based on this, the DIO message transmission method based on FPGA according to the present invention includes the following steps:

[0034] a. Connect the DIO module to the FPGA through the synchronization bus and the communication bus;

[0035] b. FPGA sends a synchronization pulse signal to synchronize the data between the DIO module and the FPGA;

[0036] c. FPGA and CPU process data through interrupts, processing multiple DIO messages each time;

[0037] d. After the receiving interrupt arrives, the CPU reads the heartbeat message and multiple DIO messages through the LocalBus bus for processing;

[0038] e. After the CPU compares and selects multiple DIO messages, the data transmission of the DIO messages is realized and the CPU completes the output action.

[0039] In this embodiment, the DIO module is a hardware module, which includes an MCU small processor and a CPLD device, and communicates with the CPU through DIO messages; the DIO messages represent the contents of input and output messages.

[0040] According to the above scheme of the present invention, the present invention adopts FPGA device to communicate with DIO module, takes advantage of FPGA device itself, has advantages of good scalability, high synchronization accuracy, high communication rate, etc. It meets the application in the power field, reduces the risk of malfunction of traditional relay protection device, reduces economic loss, and improves social benefits.

[0041] Further, Figure 3 A timing diagram schematically showing a DIO message according to an embodiment of the present invention; Figure 4 A diagram schematically showing a heartbeat message format according to an embodiment of the present invention; Figure 5 A diagram schematically showing a DIO message format according to an embodiment of the present invention; Figure 6 Schematically showing a DIO message data flow chart according to an embodiment of the present invention; Figure 7 A DIO message transmission diagram according to an embodiment of the present invention is schematically shown. Figure 3-Figure 7 As shown, in this embodiment, the CPU uses a three-choose-two mechanism, that is, compares three DIO messages and selects two of them for transmission, thereby achieving high-reliability DIO message data transmission.

[0042] In this embodiment, the synchronous bus transmits a pulse signal with a period of 100us. The communication interval of the communication bus is 100us. The LocalBus is a parallel source synchronous communication bus.

[0043] In this embodiment, the DIO module achieves time synchronization with the FPGA chip by means of external interrupt triggering, and the synchronization accuracy is 100ns.

[0044] In this implementation, the communication bus supports full-duplex communication of uplink data and downlink data, and the communication bus is composed of a clock, a chip select, and a data line, wherein the frequency of the clock is ≤100 MHz.

[0045] In this implementation manner, the uplink data and the downlink data are valid when the chip select signal is 0, the uplink data includes a heartbeat message and data sent by the DIO module; the downlink data includes a heartbeat message and data received by the DIO module.

[0046] In this embodiment, data exchange is achieved between the DIO module and the CPU through a heartbeat message, and the heartbeat message includes a sequence number, a monitoring state, a time stamp and CRC8.

[0047] In this embodiment, the DIO message includes a sequence number, a message number, data of multiple DIO modules and CRC8, a total of 100 bytes of data.

[0048] According to the above scheme of the present invention, it needs to be further explained that, in the present invention, multiple DIO modules can realize the collection of input signals of relay protection devices, as well as realize the export of output quantities and tripping and other actions. In the present invention, the communication mechanism supports the extended communication of up to 16 DIO modules.

[0049] Furthermore, in the present invention, the FPGA chip serves as the main control device 1, which is connected to the DIO module through a synchronization bus and a communication bus. Through synchronization pulses, synchronization with multiple DIO modules is achieved, and the synchronization accuracy is not less than 100ns; the communication interval of the communication bus is 100us, and data interaction with multiple DIO modules is carried out in high real-time.

[0050] Furthermore, in the present invention, the CPU chip serves as the main control device 2, and is connected to the FPGA chip through the Localbus bus. The LocalBus bus is a parallel source synchronous communication bus with the characteristics of high bandwidth and low latency. When triggered by an external interrupt, it reads the data of the DIO module at high speed to complete the data collection of the input quantity.

[0051] Furthermore, in the present invention, the synchronous bus is a pulse signal with a period of 100us, and the DIO module realizes time synchronization with the FPGA chip through an external interrupt triggering method.

[0052] Furthermore, in the present invention, the communication bus is composed of a clock, a chip select, and a data line, wherein the clock frequency supports a maximum of 100 MHz, thereby achieving full-duplex communication of uplink data and downlink data.

[0053] Furthermore, in the present invention, the DIO message includes a sequence number, a message number, DIO module 1 data to DIO module 16 data and CRC8, a total of 100 bytes of data, to realize the acquisition of the input quantity and the export and tripping of the output quantity. In order to further improve the reliability, the DIO message is sent three times within a communication cycle of 100us, wherein the message numbers are different. After receiving the DIO message, the FPGA uses a three-choose-two mechanism to prevent malfunction caused by data errors, thereby greatly improving the reliability of the relay protection device.

[0054] According to the above scheme of the present invention, the present invention improves the reliability of DIO message transmission through data redundant transmission and three-choose-two mechanism, meets the application in the power field, reduces the risk of false operation of traditional relay protection devices, reduces economic losses, and improves social benefits.

[0055] Specifically, in order to achieve synchronization of multiple DIO modules, the present invention uses FPGA to send synchronization signals through a synchronization bus, thereby ensuring a synchronization error within 100ns between DIO modules and improving the time accuracy of DIO message communication. In addition, FPGA, as a main communication device, communicates with multiple DIO modules in a high real-time manner according to a communication interval of 100us, and through multiple data retransmissions and a redundant check mechanism (the above step e), improves the communication reliability of the DIO message of the relay protection device, avoids device malfunctions caused by communication errors, reduces economic losses, and improves social benefits.

[0056] Those of ordinary skill in the art will appreciate that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0057] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and equipment can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0058] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0059] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0060] In addition, each functional module in the embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0061] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the energy-saving signal sending / receiving method of each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0062] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

[0063] It should be understood that the size of the serial numbers of each step in the content of the invention and the embodiments of the present invention does not absolutely mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A DIO message transmission method based on FPGA, characterized in that: include: Connect multiple DIO modules to FPGA through synchronization bus and communication bus respectively; FPGA sends a synchronization pulse signal to synchronize the data between the DIO module and the FPGA; The FPGA and CPU process data through interrupts, processing multiple DIO messages sent by multiple DIO modules each time; When the CPU receives an interrupt, it reads the heartbeat message and multiple DIO messages through the LocalBus bus for processing; After the CPU compares and selects multiple DIO messages, the data transmission of the DIO messages is realized and the CPU completes the output action; The CPU compares the three DIO messages through a two-out-of-three mechanism, selects two of the DIO messages, and implements DIO message data transmission.

2. The FPGA-based DIO message transmission method according to claim 1, characterized in that: The synchronous bus transmits a pulse signal with a period of 100us.

3. The FPGA-based DIO message transmission method according to claim 1, characterized in that: The communication interval of the communication bus is 100us.

4. The FPGA-based DIO message transmission method according to claim 1, characterized in that: The LocalBus bus is a parallel source synchronous communication bus.

5. The DIO message transmission method based on FPGA according to claim 1, characterized in that: The DIO module achieves time synchronization with the FPGA chip by means of external interrupt triggering, with a synchronization accuracy of 100ns.

6. The FPGA-based DIO message transmission method according to claim 1, characterized in that: The communication bus supports full-duplex communication of uplink data and downlink data, and the communication bus consists of a clock, a chip select and a data line, wherein the frequency of the clock is ≤100 MHz.

7. The FPGA-based DIO message transmission method according to claim 6, characterized in that: The uplink data and the downlink data are valid when the chip select signal is 0, the uplink data includes a heartbeat message and data sent by the DIO module; the downlink data includes a heartbeat message and data received by the DIO module.

8. The FPGA-based DIO message transmission method according to claim 1, characterized in that: The DIO module and the CPU implement data exchange through the heartbeat message, and the heartbeat message includes a sequence number, a monitoring state, a time stamp and CRC8.

9. The FPGA-based DIO message transmission method according to any one of claims 1 to 8, characterized in that: The DIO message includes a sequence number, message number, data of multiple DIO modules and CRC8, a total of 100 bytes of data.

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