An inter-chip communication link detection apparatus and method

Abstract

The application relates to the chip technical field and discloses an interconnection chip communication link detection device and method.The device comprises a first data sending module, a first sending processing module, a first receiving processing module and a first data checking module.The first data sending module is used for generating a first pseudo-random binary sequence signal according to system bandwidth; the first sending processing module is used for sending the first pseudo-random binary sequence signal through a first serial-parallel conversion transceiver link; the first receiving processing module is used for receiving and forwarding the first pseudo-random binary sequence signal; the first data checking module is used for checking the first pseudo-random binary sequence signal according to a second pseudo-random binary sequence signal generated according to system bandwidth and obtaining a checking result; and the first error code statistical module is used for determining the correct data amount and the error data amount according to the checking result to determine the error code rate of the first serial-parallel conversion transceiver link.The application solves the problem that when the system bandwidth is improved, the logic of the serial-parallel conversion transceiver link of the interconnection chip detected by using the pseudo-random binary sequence signal needs to be readjusted.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically to an interconnect chip communication link detection device and method. Background Technology

[0002] In recent years, with the rapid development of integrated circuit technology and the continuous improvement of data communication transmission performance requirements, multiprocessor technology has received increasing attention. Interconnect chips are used to connect different processors, providing a data channel for information exchange between multiple processors. Interconnect chips maintain the consistency of global system data access and play a crucial role in ensuring the stability and reliability of data communication.

[0003] The external physical communication link of the interconnect chip adopts a high-speed serial-to-parallel converter (SPCC) link. The transmission performance of the high-speed SPCC transceiver link is the key to measuring the overall bandwidth of the interconnect chip. A pseudo-random binary sequence is a binary code sequence containing only 0s and 1s. It can be predetermined and repeatedly generated and copied, and it also has random statistical properties. Therefore, it is often used to detect the bit error rate of the high-speed SPCC transceiver link.

[0004] Currently, interconnect chips are generally customized for fixed systems. Since the bandwidth of interconnect chips is limited by the system bandwidth, the bandwidth of interconnect chips is relatively fixed. When the system bandwidth increases, the architecture of existing interconnect chips needs to be restructured and upgraded accordingly. Consequently, the high-speed serial-to-parallel converter transceiver link of the interconnect chip also needs to be re-detected, and the logic for detecting the high-speed serial-to-parallel converter transceiver link using pseudo-random binary sequences also needs to be readjusted. This lack of versatility increases development costs and affects development efficiency. Summary of the Invention

[0005] In view of this, the present invention provides an interconnect chip communication link detection device and method to solve the problem that the logic of detecting the serial-to-parallel conversion transceiver link of the interconnect chip using pseudo-random binary sequence signals needs to be readjusted when the system bandwidth is increased.

[0006] In a first aspect, the present invention provides an interconnect chip communication link detection device, comprising the following modules:

[0007] The first data transmission module is used to generate a first pseudo-random binary sequence signal according to the system bandwidth, and to send the first pseudo-random binary sequence signal to the first transmission processing module.

[0008] The first transmitting processing module is used to transmit a first pseudo-random binary sequence signal to the first receiving processing module through the first serial-to-parallel converter transceiver link;

[0009] The first receiving and processing module is used to receive the first pseudo-random binary sequence signal and to forward the first pseudo-random binary sequence signal to the first data verification module.

[0010] The first data verification module is used to verify the first pseudo-random binary sequence signal by verifying the second pseudo-random binary sequence signal generated according to the system bandwidth, and to obtain the verification result; the first data verification module is also used to send the verification result to the first bit error statistics module.

[0011] The first bit error statistics module is used to determine the amount of correct data and the amount of erroneous data based on the verification results, and to determine the bit error rate of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data.

[0012] The first data transmission module and the first transmission processing module are mounted on the first interconnect chip, while the first receiving processing module, the first data verification module, and the first error statistics module are mounted on the second interconnect chip.

[0013] This device solves the problem that when system bandwidth increases, the architecture of existing interconnect chips needs to be reconstructed and upgraded accordingly, and the serial-to-parallel conversion transceiver links of interconnect chips also need to be re-detected. The logic for detecting serial-to-parallel conversion transceiver links using pseudo-random binary sequence signals also needs to be readjusted. This increases versatility, reduces development costs, and improves development efficiency.

[0014] In one optional implementation, the first data transmission module of this device includes multiple parallel linear feedback shift register (PLF) generation modules. The first data transmission module is used to select a corresponding number of PLF generation modules according to the system bandwidth. The corresponding number of PLF generation modules generate pseudo-random binary sequence signals and output values. The input value of the first PLF generation module among the corresponding number of PLF generation modules is derived from an initial value and the output values ​​of the other PLF generation modules. The input values ​​of the other PLF generation modules among the corresponding number of PLF generation modules are the output values ​​of the previous PLF generation module. The pseudo-random binary sequence signals generated by the corresponding number of PLF generation modules are combined to form a first pseudo-random binary sequence signal.

[0015] Based on the system bandwidth, a corresponding number of parallel linear feedback shift register (LPF) generation modules are selected. The pseudo-random binary sequence signals generated by these modules are combined to form a first pseudo-random binary sequence signal. This ensures that even with increased system bandwidth, a first pseudo-random binary sequence signal compatible with the system bandwidth can still be generated. The input value of the first LPF generation module is derived from the initial value and the output values ​​of all other LPF generation modules. The input values ​​of all other LPF generation modules are the output values ​​of the previous LPF generation module, thus forming a loop that continuously and efficiently generates the first pseudo-random binary sequence signal.

[0016] In one optional implementation, the first data verification module of the device is used to determine that the first pseudo-random binary sequence signal is correct data if the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal are the same.

[0017] By comparing the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal, it is possible to easily and efficiently verify whether the first pseudo-random binary sequence signal is correct or incorrect data, thereby providing a basis for calculating the bit error rate of the first serial-to-parallel converter transceiver link.

[0018] In one optional implementation, the first data verification module of this device includes multiple parallel linear feedback shift register (PLF) generation modules. The first data verification module is used to select a corresponding number of PLF generation modules according to the system bandwidth. The corresponding number of PLF generation modules generate pseudo-random binary sequence signals and output values. The input value of the first PLF generation module among the corresponding number of PLF generation modules is a part of the first pseudo-random binary sequence signal. The input values ​​of the other PLF generation modules among the corresponding number of PLF generation modules are the output values ​​of the previous PLF generation module. The pseudo-random binary sequence signals generated by the corresponding number of PLF generation modules are combined to form a second pseudo-random binary sequence signal.

[0019] Based on the system bandwidth, a corresponding number of parallel linear feedback shift register (LPF) generation modules are selected. The pseudo-random binary sequence signals generated by these modules are combined to form a second pseudo-random binary sequence signal. This ensures that even with increased system bandwidth, a second pseudo-random binary sequence signal can be generated that is compatible with the system bandwidth. The input value of the first LPF generation module in the corresponding number of LPFs is a portion of the first pseudo-random binary sequence signal. The input values ​​of the other LPF generation modules are the output values ​​of the previous LPF generation module. This allows for the efficient generation of the corresponding second pseudo-random binary sequence signal based on the first pseudo-random binary sequence signal.

[0020] In an optional implementation, the first data verification module of this device further includes multiple parallel linear feedback shift register (PLF) generation modules. The first data verification module is used to select a corresponding number of PLF generation modules according to the system bandwidth. The corresponding number of PLF generation modules generate pseudo-random binary sequence signals and output values. The input value of the first PLF generation module among the corresponding number of PLF generation modules is the output value of the last PLF generation module when the second pseudo-random binary sequence signal is generated at the current time. The input values ​​of the PLF generation modules other than the first one among the corresponding number of PLF generation modules are the output values ​​of the previous PLF generation module. The pseudo-random binary sequence signals generated by the corresponding number of PLF generation modules are combined to form a third pseudo-random binary sequence signal. The third pseudo-random binary sequence signal is used to verify the first pseudo-random binary sequence signal generated at the next time.

[0021] Based on the system bandwidth, a corresponding number of parallel linear feedback shift register (PLC) generation modules are selected. The pseudo-random binary sequence signals generated by these modules are combined to form a third pseudo-random binary sequence signal. This ensures that even with increased system bandwidth, a third pseudo-random binary sequence signal can be generated that is compatible with the system bandwidth. The input value of the first PLC generation module in the corresponding number of PLCs is the output value of the last PLC generation module when the second pseudo-random binary sequence signal is generated at the current time. The input values ​​of the other PLC generation modules are the output values ​​of the previous PLC generation module. Thus, based on the output value of the last PLC generation module when the second pseudo-random binary sequence signal is generated at the current time, the corresponding third pseudo-random binary sequence signal can be generated efficiently.

[0022] In one optional implementation, the first data verification module of the device is used to determine that the first pseudo-random binary sequence signal generated in the next moment is lost data, based on the fact that the first pseudo-random binary sequence signal generated in the next moment and the second pseudo-random binary sequence signal generated in the next moment are the same, and the first pseudo-random binary sequence signal generated in the next moment and the third pseudo-random binary sequence signal are different.

[0023] By comparing the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal, as well as comparing the first pseudo-random binary sequence signal and the third pseudo-random binary sequence signal, it is possible to simply and efficiently verify whether the first pseudo-random binary sequence signal is missing data.

[0024] In one optional implementation, the first transmission processing module of the device selects the corresponding channel in the first serial transceiver link according to the bit width of the first pseudo-random binary sequence signal.

[0025] The interconnect chip communication link consists of different channel bindings. The first transmission processing module of this device can select the appropriate channel in the transceiver link according to the bit width of the first pseudo-random binary sequence signal.

[0026] In one optional implementation, the device further includes the following modules:

[0027] The first register configuration module, located in the first interconnect chip, is used to configure the system bandwidth, which is used to generate the first pseudo-random binary sequence signal.

[0028] The system bandwidth can be flexibly adjusted through the first register configuration module of this device for use when generating the first pseudo-random binary sequence signal during the detection process.

[0029] In one optional implementation, the device further includes the following modules:

[0030] The second register configuration module, located in the second interconnect chip, is used to configure the system bandwidth, which is used to generate the second pseudo-random binary sequence signal.

[0031] The second register configuration module of this device allows for flexible adjustment of the system bandwidth for use when generating a second pseudo-random binary sequence signal during the detection process.

[0032] In one alternative implementation, the first multiplexer of the device is disposed on the first interconnect chip and is used to select the first pseudo-random binary sequence signal and the first input data according to the first pseudo-random test enable signal.

[0033] The first multiplexer of this device can select the first pseudo-random binary sequence signal and the first input data according to the first pseudo-random test enable signal.

[0034] In one alternative implementation, the second multiplexer of the device is disposed on the second interconnect chip and is used to select the first pseudo-random binary sequence signal and the first input data according to the second pseudo-random test enable signal.

[0035] The second multiplexer of this device can select the first pseudo-random binary sequence signal and the first input data according to the second pseudo-random test enable signal.

[0036] In one optional implementation, the first register configuration module of the device is further configured to configure a first pseudo-random test enable signal, which is used to control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

[0037] The first register configuration module of this device configures the first pseudo-random test enable signal, which can control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

[0038] In one optional implementation, the first register configuration module of the device is further configured to configure a second pseudo-random test enable signal, which is used to control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

[0039] By configuring the second pseudo-random test enable signal through the first register configuration module of this device, the second multiplexer can be controlled to select the first pseudo-random binary sequence signal and the first input data.

[0040] In one optional implementation, the device further includes the following modules:

[0041] The second data transmission module is used to generate a fourth pseudo-random binary sequence signal according to the system bandwidth, and to send the fourth pseudo-random binary sequence signal to the second transmission processing module.

[0042] The second transmission processing module is used to transmit a fourth pseudo-random binary sequence signal to the second receiving processing module through the second serial-to-parallel converter transceiver link.

[0043] The second receiving and processing module is used to receive the fourth pseudo-random binary sequence signal and to forward the fourth pseudo-random binary sequence signal to the second data verification module.

[0044] The second data verification module is used to verify the fourth pseudo-random binary sequence signal by verifying the fifth pseudo-random binary sequence signal generated according to the system bandwidth, and to obtain the verification result; the second data verification module is also used to send the verification result to the second bit error statistics module.

[0045] The second bit error statistics module is used to determine the amount of correct data and the amount of erroneous data based on the verification results, and to determine the bit error rate of the second serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data.

[0046] The second data transmission module and the second transmission processing module are located on the second interconnect chip, while the second receiving processing module, the second data verification module, and the second error statistics module are located on the first interconnect chip.

[0047] This device can detect the first serial-to-parallel converter transceiver link by sending a first pseudo-random binary sequence signal from the first serial-to-parallel converter transceiver link to the second interconnect chip, and it can also detect the second serial-to-parallel converter transceiver link by sending a fourth pseudo-random binary sequence signal from the second serial-to-parallel converter transceiver link to the first interconnect chip.

[0048] Secondly, the present invention provides a method for detecting communication links in interconnect chips, comprising the following steps:

[0049] The first data transmission module generates a first pseudo-random binary sequence signal based on the system bandwidth and sends the first pseudo-random binary sequence signal to the first transmission processing module.

[0050] The first pseudo-random binary sequence signal is transmitted to the first receiving processing module through the first serial-to-parallel converter transceiver link via the first transmitting processing module.

[0051] The first receiving and processing module receives the first pseudo-random binary sequence signal and forwards it to the first data verification module.

[0052] The first data verification module verifies the first pseudo-random binary sequence signal based on the second pseudo-random binary sequence signal generated by the system bandwidth, obtains the verification result, and sends the verification result to the first bit error statistics module.

[0053] The first bit error statistics module determines the amount of correct data and the amount of erroneous data based on the verification results, and then determines the bit error rate of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data.

[0054] The first data transmission module and the first transmission processing module are mounted on the first interconnect chip, while the first receiving processing module, the first data verification module, and the first error statistics module are mounted on the second interconnect chip.

[0055] This method solves the problem that when system bandwidth increases, the architecture of existing interconnect chips needs to be reconstructed and upgraded accordingly, and the serial-to-parallel conversion transceiver links of interconnect chips also need to be re-detected. The logic for detecting serial-to-parallel conversion transceiver links using pseudo-random binary sequence signals also needs to be readjusted. This method increases versatility, reduces development costs, and improves development efficiency. Attached Figure Description

[0056] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0057] Figure 1 This is a structural block diagram of an interconnect chip communication link detection device according to an embodiment of the present invention;

[0058] Figure 2 This is a structural block diagram of another interconnect chip communication link detection device according to an embodiment of the present invention;

[0059] Figure 3 This is a structural block diagram of another interconnect chip communication link detection device according to an embodiment of the present invention;

[0060] Figure 4 This is a structural diagram of an interconnect chip communication link device according to an embodiment of the present invention;

[0061] Figure 5 This is a structural diagram of the first data transmission module in the interconnect chip communication link device according to an embodiment of the present invention;

[0062] Figure 6 This is a schematic diagram of the principle of a serial linear feedback shift register according to an embodiment of the present invention;

[0063] Figure 7 This is a structural diagram of the first data verification module in the interconnect chip communication link device according to an embodiment of the present invention;

[0064] Figure 8 This is a schematic diagram of state transition in the first data verification module of the interconnect chip communication link device according to an embodiment of the present invention;

[0065] Figure 9This is a flowchart illustrating the interconnect chip communication link detection method according to an embodiment of the present invention. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] In recent years, with the rapid development of integrated circuit technology and the continuous improvement of data communication transmission performance requirements, multiprocessor technology has received increasing attention. Interconnect chips are used to connect different processors, providing a data channel for information exchange between multiple processors. Interconnect chips maintain the consistency of global system data access and play a crucial role in ensuring the stability and reliability of data communication.

[0068] The external physical communication link of the interconnect chip adopts a serial-to-parallel converter (SPC) link. The transmission performance of the SPC link is a key indicator of the overall bandwidth of the interconnect chip. A pseudo-random binary sequence is a binary code sequence containing only 0s and 1s. It can be predetermined and repeatedly generated and copied, and it also has random statistical properties. Therefore, it is often used to detect the bit error rate of the SPC link.

[0069] Currently, interconnect chips are generally customized for fixed systems. Since the bandwidth of interconnect chips is limited by the system bandwidth, the bandwidth of interconnect chips is relatively fixed. When the system bandwidth increases, the architecture of existing interconnect chips needs to be restructured and upgraded accordingly. Consequently, the serial-to-parallel conversion transceiver link of the interconnect chip also needs to be re-detected, and the logic of using pseudo-random binary sequence signals to detect the serial-to-parallel conversion transceiver link also needs to be readjusted. This lack of versatility increases development costs and affects development efficiency.

[0070] This invention provides an interconnect chip communication link detection device, which solves the problem that the logic for detecting the serial-to-parallel conversion transceiver link of the interconnect chip needs to be readjusted when the system bandwidth is increased. This improves versatility, reduces development costs, and increases development efficiency.

[0071] As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0072] This embodiment provides an interconnect chip communication link detection device, which can be used for the aforementioned interconnect chip. Figure 1 This is a structural block diagram of interconnect chip communication link detection according to an embodiment of the present invention, such as... Figure 1 As shown, the device includes the following modules:

[0073] The first data transmission module 101 is used to generate a first pseudo-random binary sequence signal according to the system bandwidth, and to transmit the first pseudo-random binary sequence signal to the first transmission processing module.

[0074] An interconnect chip system is formed by the first interconnect chip and the second interconnect chip. The data transmission bandwidth of the entire interconnect chip system is referred to as the system bandwidth. The first data transmission module generates a corresponding first pseudo-random binary sequence signal according to the system bandwidth and sends the first pseudo-random binary sequence signal to the first transmission processing module. The bit width of the first pseudo-random binary sequence signal is the same as the bit width of the system bandwidth.

[0075] The first transmitting processing module 102 is used to transmit a first pseudo-random binary sequence signal to the first receiving processing module through the first serial-to-parallel converter transceiver link.

[0076] After receiving the first pseudo-random binary sequence signal, the first transmitting processing module transmits the first pseudo-random binary sequence signal to the first receiving processing module through the first serial-to-parallel converter transceiver link.

[0077] The first receiving and processing module 103 is used to receive the first pseudo-random binary sequence signal and to forward the first pseudo-random binary sequence signal to the first data verification module.

[0078] After receiving the first pseudo-random binary sequence signal, the first receiving and processing module forwards the first pseudo-random binary sequence signal to the first data verification module.

[0079] The first data verification module 104 is used to verify the first pseudo-random binary sequence signal by verifying the second pseudo-random binary sequence signal generated according to the system bandwidth, and to obtain the verification result; and to send the verification result to the first error statistics module.

[0080] After receiving the first pseudo-random binary sequence signal, the first data verification module generates a corresponding second pseudo-random binary sequence based on the system bandwidth. The bit width of the second pseudo-random binary sequence signal is the same as the bit width of the system bandwidth. The first data verification module verifies the first pseudo-random binary sequence signal using the second pseudo-random binary sequence signal, obtaining a verification result indicating whether the first pseudo-random binary sequence signal is correct or incorrect. Finally, the first data verification module sends the verification result to the first bit error rate statistics module.

[0081] The first bit error statistics module 105 is used to determine the amount of correct data and the amount of erroneous data based on the verification results, so as to determine the bit error rate of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data.

[0082] After receiving the verification result, the first error statistics module determines the amount of correct data and the amount of erroneous data based on the verification result. The bit error rate of the first serial-to-parallel converter transceiver link can be determined by the amount of correct data and the amount of erroneous data.

[0083] The first data transmission module and the first transmission processing module are mounted on the first interconnect chip, while the first receiving processing module, the first data verification module, and the first error statistics module are mounted on the second interconnect chip.

[0084] The interconnect chip communication link detection device provided in this embodiment generates a corresponding first pseudo-random binary sequence signal and a corresponding second pseudo-random binary sequence signal based on the system bandwidth. The first pseudo-random binary sequence signal is verified by the second pseudo-random binary sequence signal. Based on the verification result, the bit error rate of the first serial-to-parallel converter transceiver link can be determined. The bit error rate of the first serial-to-parallel converter transceiver link can be used to determine the bandwidth transmission performance of the overall interconnect chip system.

[0085] In some optional embodiments, the first data transmission module 101 of the above-described device includes multiple parallel linear feedback shift register (PLF) generation modules. The first data transmission module is used to select a corresponding number of PLF generation modules according to the system bandwidth. The corresponding number of PLF generation modules generate pseudo-random binary sequence signals and output values. The input value of the first PLF generation module among the corresponding number of PLF generation modules is derived from an initial value and the output values ​​of the other PLF generation modules. The input values ​​of the other PLF generation modules among the corresponding number of PLF generation modules are the output values ​​of the previous PLF generation module. The pseudo-random binary sequence signals generated by the corresponding number of PLF generation modules are combined to form a first pseudo-random binary sequence signal.

[0086] Based on the system bandwidth, a corresponding number of parallel linear feedback shift register (LPF) generation modules are selected. The pseudo-random binary sequence signals generated by these modules are combined to form a first pseudo-random binary sequence signal. This ensures that even with increased system bandwidth, a first pseudo-random binary sequence signal compatible with the system bandwidth can still be generated. The input value of the first LPF generation module is derived from the initial value and the output values ​​of all other LPF generation modules. The input values ​​of all other LPF generation modules are the output values ​​of the previous LPF generation module, thus forming a loop that continuously and efficiently generates the first pseudo-random binary sequence signal.

[0087] In some optional embodiments, the first data verification module 103 of the above-described device is used to determine that the first pseudo-random binary sequence signal is correct data based on the fact that the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal are the same.

[0088] If the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal are the same, then the first pseudo-random binary sequence signal is correct data; if the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal are different, then the first pseudo-random binary sequence signal is incorrect data.

[0089] By comparing the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal, it is possible to easily and efficiently verify whether the first pseudo-random binary sequence signal is correct or incorrect data, thereby providing a basis for calculating the bit error rate of the first serial-to-parallel converter transceiver link.

[0090] In some optional embodiments, the first data verification module 103 of the above-described device includes multiple parallel linear feedback shift register (PLF) generation modules. The first data verification module is used to select a corresponding number of PLF generation modules according to the system bandwidth. The corresponding number of PLF generation modules generate pseudo-random binary sequence signals and output values. The input value of the first PLF generation module among the corresponding number of PLF generation modules is a part of the first pseudo-random binary sequence signal. The input values ​​of the other PLF generation modules among the corresponding number of PLF generation modules are the output values ​​of the previous PLF generation module. The pseudo-random binary sequence signals generated by the corresponding number of PLF generation modules are combined to form a second pseudo-random binary sequence signal.

[0091] Based on the system bandwidth, a corresponding number of parallel linear feedback shift register (LPF) generation modules are selected. The pseudo-random binary sequence signals generated by these modules are combined to form a second pseudo-random binary sequence signal. This ensures that even with increased system bandwidth, a second pseudo-random binary sequence signal can be generated that is compatible with the system bandwidth. The input value of the first LPF generation module in the corresponding number of LPFs is a portion of the first pseudo-random binary sequence signal. The input values ​​of the other LPF generation modules are the output values ​​of the previous LPF generation module. This allows for the efficient generation of the corresponding second pseudo-random binary sequence signal based on the first pseudo-random binary sequence signal.

[0092] In some optional embodiments, the first data verification module 103 of the above-described device further includes multiple parallel linear feedback shift register generation modules. The first data verification module is used to select a corresponding number of parallel linear feedback shift register generation modules according to the system bandwidth. The corresponding number of parallel linear feedback shift registers generate pseudo-random binary sequence signals and output values. The input value of the first parallel linear feedback shift register generation module in the corresponding number of parallel linear feedback shift registers is the output value of the last parallel linear feedback shift register generation module when the second pseudo-random binary sequence signal is generated at the current time. The input values ​​of the parallel linear feedback shift register generation modules other than the first in the corresponding number of parallel linear feedback shift registers are the output values ​​of the previous parallel linear feedback shift register generation module. The pseudo-random binary sequence signals generated by the corresponding number of parallel linear feedback shift register generation modules are combined to form a third pseudo-random binary sequence signal. The third pseudo-random binary sequence signal is used to verify the first pseudo-random binary sequence signal generated at the next time.

[0093] Based on the system bandwidth, a corresponding number of parallel linear feedback shift register (PLC) generation modules are selected. The pseudo-random binary sequence signals generated by these modules are combined to form a third pseudo-random binary sequence signal. This ensures that even with increased system bandwidth, a third pseudo-random binary sequence signal can be generated that is compatible with the system bandwidth. The input value of the first PLC generation module in the corresponding number of PLCs is the output value of the last PLC generation module when the second pseudo-random binary sequence signal is generated at the current time. The input values ​​of the other PLC generation modules are the output values ​​of the previous PLC generation module. Thus, based on the output value of the last PLC generation module when the second pseudo-random binary sequence signal is generated at the current time, the corresponding third pseudo-random binary sequence signal can be generated efficiently.

[0094] In some optional embodiments, the first data verification module 103 of the above-described device is used to determine that the first pseudo-random binary sequence signal generated in the next moment is lost data, based on the fact that the first pseudo-random binary sequence signal generated in the next moment and the second pseudo-random binary sequence signal generated in the next moment are the same, and the first pseudo-random binary sequence signal generated in the next moment and the third pseudo-random binary sequence signal are different.

[0095] If the first pseudo-random binary sequence signal generated at the next moment is the same as the second pseudo-random binary sequence signal generated at the next moment, and the first pseudo-random binary sequence signal generated at the next moment is different from the third pseudo-random binary sequence signal, then it can be determined that the first pseudo-random binary sequence signal generated at the next moment is the lost data. This way, it is possible to simply and efficiently verify whether the first pseudo-random binary sequence signal is the lost data.

[0096] In some alternative implementations, the first transmission processing module 102 of the above-described device selects the corresponding channel in the first serial and transceiver link according to the bit width of the first pseudo-random binary sequence signal.

[0097] The serial-to-parallel converter transceiver link consists of different channel bindings. The first transmission processing module of this device can select the appropriate channel in the first serial-to-parallel converter transceiver link according to the bit width of the first pseudo-random binary sequence signal.

[0098] This embodiment provides an interconnect chip communication link detection device, which can be used for the aforementioned interconnect chip. Figure 2 This is a structural block diagram of interconnect chip communication link detection according to an embodiment of the present invention, such as... Figure 2 As shown, the device includes the following modules:

[0099] The first data transmission module 201 is used to generate a first pseudo-random binary sequence signal based on the system bandwidth, and to transmit the first pseudo-random binary sequence signal to the first transmission processing module. For details, please refer to [link to relevant documentation]. Figure 1 The module 101 of the illustrated embodiment will not be described in detail here.

[0100] The first transmitting processing module 202 is used to transmit a first pseudo-random binary sequence signal to the first receiving processing module via the first serial-to-parallel converter transceiver link. For details, please refer to [link to details]. Figure 1 The module 102 of the illustrated embodiment will not be described in detail here.

[0101] The first receiving and processing module 203 is used to receive a first pseudo-random binary sequence signal and to forward the first pseudo-random binary sequence signal to the first data verification module. For details, please refer to [link to relevant documentation]. Figure 1 The module 103 of the illustrated embodiment will not be described in detail here.

[0102] The first data verification module 204 is used to verify the first pseudo-random binary sequence signal by verifying it with the second pseudo-random binary sequence signal generated based on the system bandwidth, and to obtain a verification result; and to send the verification result to the first error statistics module. For details, please refer to [link to relevant documentation]. Figure 1 The module 104 of the illustrated embodiment will not be described in detail here.

[0103] The first bit error rate (BER) statistics module 205 is used to determine the amount of correct data and the amount of erroneous data based on the verification results, and then determine the BER of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data. For details, please refer to [link to details]. Figure 1 The module 105 of the illustrated embodiment will not be described in detail here.

[0104] The first register configuration module 206 is used to configure the system bandwidth, which is used to generate the first pseudo-random binary sequence signal.

[0105] The system bandwidth is configured through the second register configuration module for use by the first data transmission module when generating the second pseudo-random binary sequence signal.

[0106] The second register configuration module 207 is used to configure the system bandwidth, which is used to generate the second pseudo-random binary sequence signal.

[0107] The system bandwidth is configured through the second register configuration module for use by the first data verification module when generating the second pseudo-random binary sequence signal.

[0108] The first data transmission module, the first transmission processing module, and the first register configuration module are located on the first interconnect chip, while the first reception processing module, the first data verification module, the first bit error statistics module, and the second register configuration module are located on the second interconnect chip.

[0109] The interconnect chip communication link detection device provided in this embodiment can flexibly adjust the system bandwidth for use when generating the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal during the detection process.

[0110] In one alternative implementation, the first multiplexer of the above-described device is disposed on the first interconnect chip and is used to select the first pseudo-random binary sequence signal and the first input data according to the first pseudo-random test enable signal.

[0111] The first register configuration module of this device configures the first pseudo-random test enable signal, which can control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

[0112] In one alternative embodiment, the second multiplexer of the above-described device is disposed on the second interconnect chip and is used to select the first pseudo-random binary sequence signal and the first input data according to the second pseudo-random test enable signal.

[0113] By configuring the second pseudo-random test enable signal through the first register configuration module of this device, the second multiplexer can be controlled to select the first pseudo-random binary sequence signal and the first input data.

[0114] In an optional implementation, the first register configuration module 206 of the above-mentioned device is further configured to configure a first pseudo-random test enable signal, which is used to control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

[0115] The first register configuration module of this device configures the first pseudo-random test enable signal, which can control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

[0116] In an optional implementation, the first register configuration module 207 of the above-mentioned device is further configured to configure a second pseudo-random test enable signal, which is used to control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

[0117] By configuring the second pseudo-random test enable signal through the first register configuration module of this device, the second multiplexer can be controlled to select the first pseudo-random binary sequence signal and the first input data.

[0118] This embodiment provides an interconnect chip communication link detection device, which can be used for the aforementioned interconnect chip. Figure 3 This is a structural block diagram of interconnect chip communication link detection according to an embodiment of the present invention, such as... Figure 3 As shown, the device includes the following modules:

[0119] The first data transmission module 301 is used to generate a first pseudo-random binary sequence signal based on the system bandwidth, and to transmit the first pseudo-random binary sequence signal to the first transmission processing module. For details, please refer to [link to relevant documentation]. Figure 1 The module 101 of the illustrated embodiment will not be described in detail here.

[0120] The first transmitting processing module 302 is used to transmit a first pseudo-random binary sequence signal to the first receiving processing module via the first serial-to-parallel converter transceiver link. For details, please refer to [link to details]. Figure 1 The module 102 of the illustrated embodiment will not be described in detail here.

[0121] The first receiving and processing module 303 is used to receive a first pseudo-random binary sequence signal and to forward the first pseudo-random binary sequence signal to the first data verification module. For details, please refer to [link to relevant documentation]. Figure 1 The module 103 of the illustrated embodiment will not be described in detail here.

[0122] The first data verification module 304 is used to verify the first pseudo-random binary sequence signal by verifying it with the second pseudo-random binary sequence signal generated based on the system bandwidth, and to obtain a verification result; and to send the verification result to the first error statistics module. For details, please refer to [link to relevant documentation]. Figure 1 The module 104 of the illustrated embodiment will not be described in detail here.

[0123] The first bit error rate (BER) statistics module 305 is used to determine the amount of correct data and the amount of erroneous data based on the verification results, and then determine the BER of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data. For details, please refer to [link to relevant documentation]. Figure 1 The module 105 of the illustrated embodiment will not be described in detail here.

[0124] The second data transmission module 306 is used to generate a fourth pseudo-random binary sequence signal according to the system bandwidth, and to transmit the fourth pseudo-random binary sequence signal to the second transmission processing module.

[0125] The second data transmission module generates a corresponding fourth pseudo-random binary sequence signal based on the system bandwidth and sends the fourth pseudo-random binary sequence signal to the second transmission processing module, wherein the bit width of the second pseudo-random binary sequence signal is the same as the bit width of the system bandwidth.

[0126] The second transmitting processing module 307 is used to transmit a fourth pseudo-random binary sequence signal to the second receiving processing module through the second serial-to-parallel converter transceiver link.

[0127] After receiving the fourth pseudo-random binary sequence signal, the second transmitting processing module transmits the fourth pseudo-random binary sequence signal to the second receiving processing module through the second serial-to-parallel converter transceiver link.

[0128] The second receiving and processing module 308 is used to receive the fourth pseudo-random binary sequence signal and to forward the fourth pseudo-random binary sequence signal to the second data verification module.

[0129] After receiving the fourth pseudo-random binary sequence signal, the second receiving and processing module forwards the fourth pseudo-random binary sequence signal to the second data verification module.

[0130] The second data verification module 309 is used to verify the fourth pseudo-random binary sequence signal by verifying the fifth pseudo-random binary sequence signal generated according to the system bandwidth, and to obtain the verification result; the second data verification module is also used to send the verification result to the second error statistics module.

[0131] After receiving the fourth pseudo-random binary sequence signal, the second data verification module generates a corresponding fifth pseudo-random binary sequence based on the system bandwidth. The bit width of the fifth pseudo-random binary sequence signal is the same as the bit width of the system bandwidth. The second data verification module verifies the fourth pseudo-random binary sequence signal using the fifth pseudo-random binary sequence signal, obtaining a verification result indicating whether the fourth pseudo-random binary sequence signal is correct or incorrect. Finally, the second data verification module sends the verification result to the second error statistics module.

[0132] The second bit error statistics module 310 is used to determine the amount of correct data and the amount of erroneous data based on the verification results, so as to determine the bit error rate of the second serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data.

[0133] After receiving the verification result, the second error statistics module determines the amount of correct data and the amount of erroneous data based on the verification result. The bit error rate of the second serial-to-parallel converter transceiver link can be determined by the amount of correct data and the amount of erroneous data.

[0134] The first data transmission module, the first transmission processing module, the second reception processing module, the second data verification module, and the second error statistics module are disposed in the first interconnect chip, and the second data transmission module, the second transmission processing module, the first reception processing module, the first data verification module, and the first error statistics module are disposed in the second interconnect chip.

[0135] The interconnect chip communication link detection device provided in this embodiment can detect the first serial-to-parallel conversion transceiver link by sending a first pseudo-random binary sequence signal from the first serial-to-parallel conversion transceiver link to the second interconnect chip, and can also detect the second serial-to-parallel conversion transceiver link by sending a fourth pseudo-random binary sequence signal from the second serial-to-parallel conversion transceiver link to the first interconnect chip.

[0136] The following application scenarios can be described in detail in conjunction with the embodiments provided by the present invention.

[0137] Currently, interconnect chips are generally customized for fixed systems. Since the bandwidth of interconnect chips is limited by the system bandwidth, the bandwidth of interconnect chips is relatively fixed. When the system bandwidth increases, the architecture of existing interconnect chips needs to be restructured and upgraded accordingly. Consequently, the serial-to-parallel conversion transceiver link of the interconnect chip also needs to be re-detected, and the corresponding logic for detecting the serial-to-parallel conversion transceiver link using pseudo-random binary sequences also needs to be readjusted. This lack of versatility increases development costs and affects development efficiency.

[0138] To address the problems encountered in the aforementioned scenarios, an interconnect chip communication link detection device is provided. For example... Figure 4 As shown, this device includes six functional modules on the first interconnect chip and six on the second interconnect chip. These modules are: register configuration module, data transmission module, transmission processing module, reception processing module, data verification module, and bit error statistics module. Although they are on different interconnect chips, their structure and function are the same. They are distinguished by the terms "first" and "second".

[0139] Through the complete testing process, combined with Figure 4 The six functional modules mentioned above will be explained as follows:

[0140] The system bandwidth on the first register configuration module and the second register configuration module is configured via the configuration bus through the system software for use in subsequent testing.

[0141] The first data transmission module includes multiple parallel linear feedback shift register (LFSR) generation modules, such as... Figure 5 The parallel LFSR generation module 1, parallel LFSR generation module 2, ... parallel LFSR generation module N shown are selected according to the system bandwidth previously configured in the first register configuration module, and the corresponding number of parallel linear feedback shift register generation modules are selected.

[0142] The selected parallel linear feedback shift register generation module can generate pseudo-random binary sequence signals and output values, such as... Figure 5 The dout[30:0] on the LFSR generation module 1 shown is the output value generated by the parallel LFSR generation module 1, and the prbs31[23:0] on the LFSR generation module 1 is the pseudo-random binary sequence generated by the parallel LFSR generation module 1.

[0143] In the selected parallel linear feedback shift register generation modules, the input value of the first parallel linear feedback shift register generation module is derived from the initial value and the output values ​​of the other parallel linear feedback shift register generation modules, such as... Figure 5The input values ​​din[30:0] in the parallel LFSR generation module 1 shown are obtained by passing the initial value and the output values ​​of the parallel linear feedback shift register generation modules other than the first one through a control signal gating multiplexer (MUX). The input values ​​of the parallel linear feedback shift register generation modules other than the first one are the output values ​​of the previous parallel linear feedback shift register generation module, such as... Figure 5 The input value din[30:0] of the parallel LFSR generation module 2 is the output value dou[30:0] of the parallel LFSR generation module 1.

[0144] The pseudo-random binary sequence signals output by the selected parallel linear feedback shift register generation module are combined to form the first pseudo-random binary sequence signal. For example... Figure 5 As shown, the prbs31[23:0] generated by parallel LFSR generation module 1, the prbs31[23:0] generated by parallel LFSR generation module 2, ..., until the prbs31[23:0] generated by parallel LFSR generation module N are merged. The pseudo-random binary sequence output by each parallel linear feedback shift register generation module is 24 bits wide, resulting in a first pseudo-random binary sequence signal with a width of 24×N bits.

[0145] The serial linear feedback shift register module in the first transmitting module of this device is derived from the principle of the serial linear feedback shift register. This module uses a 31st-order original polynomial 1+x 28 +x 31 Its serial generation principle is as follows Figure 6 As shown, it consists of 31 registers and 1 XOR gate. Each clock cycle, it shifts right once to output one bit of pseudo-random data. 24 consecutive right shifts yield a 24-bit pseudo-random binary sequence. The state values ​​in the 31 registers after 24 shifts can be used as the initial input values ​​for the next parallel LFSR generation module. The derivation result using R0 as an example is shown in the following equation.

[0146]

[0147] in This represents the value of R0 after shifting by 24. This represents the initial input value before the shift; the values ​​of the remaining register bits can be derived similarly. The principle of the serial linear feedback shift register module in other modules of this device is the same, and will not be elaborated further.

[0148] The system software configures the first pseudo-random test enable signal on the first register configuration module via the configuration bus, so that the first pseudo-random binary sequence signal can be selected by the input data from the central processing unit and only output as the first pseudo-random binary sequence signal.

[0149] After receiving the first pseudo-random binary sequence signal, the first transmitting processing module selects the corresponding channel in the first serial-to-parallel converter transceiver link according to the bit width of the first pseudo-random binary sequence signal, and finally sends the first pseudo-random binary sequence signal to the first receiving processing module through the first serial-to-parallel converter transceiver link.

[0150] The system software configures the second pseudo-random test signal on the second register configuration module via the configuration bus, so that the first pseudo-random binary sequence signal sent by the first receiving and processing module is only output to the first data verification module after being selected by the second multiplexer.

[0151] The first data verification module includes multiple parallel linear feedback shift register generation modules, such as... Figure 7 The parallel LFSR generation module 1, parallel LFSR generation module 2, ..., parallel LFSR generation module N shown are selected according to the system bandwidth previously configured in the second register configuration module, and the corresponding number of parallel linear feedback shift register generation modules are selected.

[0152] The selected parallel linear feedback shift register generation module can generate pseudo-random binary sequence signals and output values, such as... Figure 7 The dout[30:0] on the LFSR generation module 1 shown is the output value generated by the parallel LFSR generation module 1, and the prbs31[23:0] on the LFSR generation module 1 is the pseudo-random binary sequence generated by the parallel LFSR generation module 1.

[0153] In the selected parallel linear feedback shift register generation modules, the input value of the first parallel linear feedback shift register generation module is the high 31 bits of the first pseudo-random binary sequence signal, such as... Figure 7 The high 31 bits of the received data are shown. The input values ​​of the parallel linear feedback shift register generation modules other than the first one are the output values ​​of the previous parallel linear feedback shift register generation module, such as... Figure 7 The input value din[30:0] of the parallel LFSR generation module 2 is the output value dou[30:0] of the parallel LFSR generation module 1.

[0154] The pseudo-random binary sequence signals output by the selected parallel linear feedback shift register generation module are combined to form a second pseudo-random binary sequence signal. For example... Figure 7As shown, by controlling signal 1, the prbs31[23:0] generated by parallel LFSR generation module 1, the prbs31[23:0] generated by parallel LFSR generation module 2, ..., until the prbs31[23:0] generated by parallel LFSR generation module N are merged. The pseudo-random binary sequence output by each parallel linear feedback shift register generation module is 24 bits wide, resulting in a second pseudo-random binary sequence signal with a width of 24×N bits, i.e. Figure 7 The calculated value corresponding to the current valid data is PRBS0.

[0155] The first data verification module verifies the first pseudo-random binary sequence signal using the second pseudo-random binary sequence signal. If the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal are the same, then the first pseudo-random binary sequence signal is correct data; if the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal are different, then the first pseudo-random binary sequence signal is incorrect data.

[0156] The first data verification module also includes multiple parallel linear feedback shift register generation modules, such as... Figure 7 The parallel LFSR generation module 1′, parallel LFSR generation module 2′, ..., parallel LFSR generation module N′ shown are selected according to the system bandwidth previously configured in the second register configuration module, and the corresponding number of parallel linear feedback shift register generation modules are selected.

[0157] The selected parallel linear feedback shift register generation module can generate pseudo-random binary sequence signals and output values, such as... Figure 7 The dout[30:0] on the LFSR generation module 1′ shown is the output value generated by the parallel LFSR generation module 1′, and the prbs31[23:0] on the LFSR generation module 1′ is the pseudo-random binary sequence generated by the parallel LFSR generation module 1′.

[0158] In the selected parallel linear feedback shift register generation modules, the input value of the first parallel linear feedback shift register generation module is the output value of the last parallel linear feedback shift register generation module when the second pseudo-random binary sequence signal is generated at the current time, such as... Figure 7 As shown, prbs31[23:0] generated by the parallel LFSR generation module N via control signal 3 is the input of the parallel LFSR generation module 1'. The input values ​​of the parallel linear feedback shift register generation modules other than the first one are the output values ​​of the previous parallel linear feedback shift register generation module, such as... Figure 7 The input value din[30:0] of the parallel LFSR generation module 2′ is the output value dou[30:0] of the parallel LFSR generation module 1′.

[0159] The pseudo-random binary sequence signals output by the selected parallel linear feedback shift register generation module are combined to form a third pseudo-random binary sequence signal. For example... Figure 7 As shown, by controlling signal 2, the prbs31[23:0] generated by parallel LFSR generation module 1′, the prbs31[23:0] generated by parallel LFSR generation module 2′, ..., until the prbs31[23:0] generated by parallel LFSR generation module N′ are merged. The pseudo-random binary sequence output by each parallel linear feedback shift register generation module is 24 bits wide, resulting in a third pseudo-random binary sequence signal with a width of 24×N bits, i.e. Figure 7 The next valid data value corresponding to PRBS is calculated in the middle.

[0160] The first data verification module verifies whether the first pseudo-random binary sequence signal generated at the next moment is lost data by using the third pseudo-random binary sequence signal. If the first pseudo-random binary sequence signal generated at the next moment is the same as the second pseudo-random binary sequence signal generated at the next moment, and the first pseudo-random binary sequence signal generated at the next moment is different from the third pseudo-random binary sequence signal, then the first pseudo-random binary sequence signal generated at the next moment is lost data.

[0161] During the above verification process, five states may occur: RECV (waiting to receive valid data), CHECK (checking if the currently received data is equal to the calculated PRBS data), CMP (comparing if the next received data is equal to the calculated PRBS data), WAIT (waiting for the next valid data to arrive), and JUDGE (determining if data has been lost). The specific transition process for these five states is as follows: Figure 8 As shown, Figure 8 The meanings of PRBS and PRBS0 in the text are the same as those in the text. Figure 7 Similarly, flit_valid represents the first pseudo-random binary sequence signal received at the current moment, and flit_buffer represents the buffer of flit_valid values.

[0162] When in the RECV state, if it keeps waiting for the flit_valid to arrive, it will remain in the RECV state indefinitely; when in the RECV state, if it receives the flit_valid, it will jump from the RECV state to the CHECK state.

[0163] When in the CHECK state, if PRBS0 is different from flit_buffer and no next flit_valid is received, the system will transition from the CHECK state to the RECV state. When in the CHECK state, if PRBS0 is different from flit_buffer and a next flit_valid is received, the system will remain in the CHECK state. When in the CHECK state, if PRBS0 is the same as flit_buffer and a next flit_valid is received, the system will transition from the CHECK state to the CMP state. When in the CHECK state, if PRBS0 is the same as flit_buffer and no next flit_valid is received, the system will transition from the CHECK state to the WAIT state.

[0164] When in the CMP state, if PRBS is different from flit_buffer, and PRBS0 is different from flit_buffer, and no next flit_valid is received, the system will transition from the CMP state to the RECV state. When in the CMP state, if PRBS is different from flit_buffer, and PRBS0 is different from flit_buffer, and a next flit_valid is received, the system will transition from the CMP state to the CHECK state. When in the CMP state, if PRBS is the same as flit_buffer and a next flit_valid is received, or if PRBS is different from flit_buffer and PRBS0 is the same as flit_buffer and a next flit_valid is received, the system will remain in the CMP state. When in the CMP state, if PRBS is the same as flit_buffer and no next flit_valid is received, or if PRBS is different from flit_buffer and PRBS0 is the same as flit_buffer and a next flit_valid is received, the system will transition from the CMP state to the WAIT state.

[0165] When in the WAIT state, if a next flit_valid is received and PRBS is different from flit_buffer, the system will transition from the WAIT state to the JUDGE state. When in the WAIT state, if no next flit_valid is received and PRBS is the same as flit_buffer, the system will remain in the WAIT state.

[0166] When in the JUDGE state, if PRBS0 is the same as flit_buffer and no next flit_valid is received, the system will transition from the JUDGE state to the RECV state. When in the JUDGE state, if PRBS0 is the same as flit_buffer and a next flit_valid is received, the system will transition from the JUDGE state to the CHECK state. When in the JUDGE state, if PRBS0 is different from flit_buffer and a next flit_valid is received, the system will transition from the JUDGE state to the CMP state. When in the JUDGE state, if PRBS0 is different from flit_buffer and no next flit_valid is received, the system will transition from the JUDGE state to the WAIT state.

[0167] The first bit error rate statistics module, after receiving the verification result from the first data verification module, counts the number of correct data, the number of incorrect data, and the number of lost data in the verification result, in order to determine the bit error rate of the first serial-to-parallel converter transceiver link.

[0168] According to an embodiment of the present invention, an embodiment of an interconnect chip communication link detection method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0169] This embodiment provides a method for detecting communication links in an interconnect chip, which can be used in the aforementioned interconnect chip. Figure 9 This is a flowchart of an interconnect chip communication link detection method according to an embodiment of the present invention, such as... Figure 9 As shown, the process includes the following steps:

[0170] Step S901: The first data transmission module generates a first pseudo-random binary sequence signal based on the system bandwidth and sends the first pseudo-random binary sequence signal to the first transmission processing module.

[0171] In step S902, the first pseudo-random binary sequence signal is transmitted to the first receiving processing module through the first serial-to-parallel converter transceiver link via the first transmitting processing module.

[0172] Step S903: Receive the first pseudo-random binary sequence signal through the first receiving and processing module, and forward the first pseudo-random binary sequence signal to the first data verification module.

[0173] In step S904, the first data verification module verifies the first pseudo-random binary sequence signal based on the second pseudo-random binary sequence signal generated by the system bandwidth, obtains the verification result, and sends the verification result to the first error statistics module.

[0174] Step S905: The first bit error statistics module determines the amount of correct data and the amount of erroneous data based on the verification results, and determines the bit error rate of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data.

[0175] The first data transmission module and the first transmission processing module are mounted on the first interconnect chip, while the first receiving processing module, the first data verification module, and the first error statistics module are mounted on the second interconnect chip.

[0176] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A device for detecting communication links in interconnect chips, characterized in that, The device includes: The first data transmission module is used to generate a first pseudo-random binary sequence signal according to the system bandwidth, and to send the first pseudo-random binary sequence signal to the first transmission processing module. The first transmitting processing module is used to transmit the first pseudo-random binary sequence signal to the first receiving processing module through the first serial-to-parallel converter transceiver link; The first receiving and processing module is configured to receive the first pseudo-random binary sequence signal and to forward the first pseudo-random binary sequence signal to the first data verification module. The first data verification module is used to verify the first pseudo-random binary sequence signal by verifying the first pseudo-random binary sequence signal based on the second pseudo-random binary sequence signal generated according to the system bandwidth, and to obtain a verification result; the first data verification module is also used to send the verification result to the first bit error statistics module; The first bit error statistics module is used to determine the amount of correct data and the amount of erroneous data based on the verification result, so as to determine the bit error rate of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data; The first data sending module and the first sending processing module are disposed on the first interconnect chip, and the first receiving processing module, the first data verification module and the first bit error statistics module are disposed on the second interconnect chip. The first data transmission module includes multiple parallel linear feedback shift register generation modules, and the first data transmission module is used to select a corresponding number of the parallel linear feedback shift register generation modules according to the system bandwidth. The corresponding number of parallel linear feedback shift registers generate pseudo-random binary sequence signals and output values; The input value of the first parallel linear feedback shift register generation module in the corresponding number of parallel linear feedback shift registers is derived from the initial value and the output values ​​of the parallel linear feedback shift register generation modules other than the first one; The input value of the parallel linear feedback shift register generation module, excluding the first one, in the corresponding number of parallel linear feedback shift registers is the output value of the previous parallel linear feedback shift register generation module. The pseudo-random binary sequence signals generated by the corresponding number of parallel linear feedback shift register generation modules are combined to form the first pseudo-random binary sequence signal.

2. The apparatus according to claim 1, characterized in that, The first data verification module is used to determine that the first pseudo-random binary sequence signal is correct data based on the fact that the first pseudo-random binary sequence signal and the second pseudo-random binary sequence signal are the same.

3. The apparatus according to claim 2, characterized in that, The first data verification module includes multiple parallel linear feedback shift register generation modules. The first data verification module is used to select a corresponding number of the parallel linear feedback shift register generation modules according to the system bandwidth. The corresponding number of parallel linear feedback shift registers generate pseudo-random binary sequence signals and output values; The input value of the first parallel linear feedback shift register generation module in the corresponding number of parallel linear feedback shift registers is a part of the first pseudo-random binary sequence signal; The input value of the parallel linear feedback shift register generation module (excluding the first one) in the corresponding number of parallel linear feedback shift registers is the output value of the previous parallel linear feedback shift register generation module. The pseudo-random binary sequence signals generated by the corresponding number of parallel linear feedback shift register generation modules are combined to form the second pseudo-random binary sequence signal.

4. The apparatus according to claim 3, characterized in that, The first data verification module further includes multiple parallel linear feedback shift register generation modules. The first data verification module is used to select a corresponding number of the parallel linear feedback shift register generation modules according to the system bandwidth. The corresponding number of parallel linear feedback shift registers generate pseudo-random binary sequence signals and output values; The input value of the first parallel linear feedback shift register generation module in the corresponding number of parallel linear feedback shift registers is the output value of the last parallel linear feedback shift register generation module when the second pseudo-random binary sequence signal is generated at the current time. The input value of the parallel linear feedback shift register generation module, excluding the first one, in the corresponding number of parallel linear feedback shift registers is the output value of the previous parallel linear feedback shift register generation module. The pseudo-random binary sequence signals generated by the corresponding number of parallel linear feedback shift register generation modules are combined to form a third pseudo-random binary sequence signal, which is used to verify the first pseudo-random binary sequence signal formed at the next moment.

5. The apparatus according to claim 4, characterized in that, The first data verification module is used to determine that the first pseudo-random binary sequence signal generated in the next moment is lost data if the first pseudo-random binary sequence signal generated in the next moment is the same as the second pseudo-random binary sequence signal generated in the next moment, and the first pseudo-random binary sequence signal generated in the next moment is different from the third pseudo-random binary sequence signal.

6. The apparatus according to claim 1, characterized in that, The first transmission processing module selects the corresponding channel in the first serial-to-parallel converter link according to the bit width of the first pseudo-random binary sequence signal.

7. The apparatus according to claim 1, characterized in that, The device further includes: The first register configuration module, located in the first interconnect chip, is used to configure the system bandwidth, which is used to generate the first pseudo-random binary sequence signal.

8. The apparatus according to claim 1, characterized in that, The device further includes: The second register configuration module, located in the second interconnect chip, is used to configure the system bandwidth, which is used to generate the second pseudo-random binary sequence signal.

9. The apparatus according to claim 7, characterized in that, The device further includes: A first multiplexer, disposed on the first interconnect chip, is used to select the first pseudo-random binary sequence signal and the first input data according to the first pseudo-random test enable signal.

10. The apparatus according to claim 7, characterized in that, The device further includes: A second multiplexer, located in the second interconnect chip, is used to select the first pseudo-random binary sequence signal and the first input data according to a second pseudo-random test enable signal.

11. The apparatus according to claim 9, characterized in that, The first register configuration module is further configured to configure the first pseudo-random test enable signal, which is used to control the first multiplexer to select the first pseudo-random binary sequence signal and the first input data.

12. The apparatus according to claim 10, characterized in that, The first register configuration module is further configured to configure the second pseudo-random test enable signal, which is used to control the second multiplexer to select the first pseudo-random binary sequence signal and the first input data.

13. The apparatus according to claim 1, characterized in that, The device further includes: The second data transmission module is used to generate a fourth pseudo-random binary sequence signal according to the system bandwidth, and to transmit the fourth pseudo-random binary sequence signal to the second transmission processing module. The second transmitting processing module is used to transmit the fourth pseudo-random binary sequence signal to the second receiving processing module through the second serial-to-parallel converter transceiver link; The second receiving and processing module is used to receive the fourth pseudo-random binary sequence signal and to forward the fourth pseudo-random binary sequence signal to the second data verification module. The second data verification module is used to verify the fourth pseudo-random binary sequence signal by verifying the fifth pseudo-random binary sequence signal generated according to the system bandwidth, and to obtain a verification result; the second data verification module is also used to send the verification result to the second error statistics module; The second bit error statistics module is used to determine the amount of correct data and the amount of erroneous data based on the verification result, so as to determine the bit error rate of the second serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data; The second data transmission module and the second transmission processing module are disposed on the second interconnect chip, and the second receiving processing module, the second data verification module and the second error statistics module are disposed on the first interconnect chip.

14. A method for detecting communication links in interconnect chips, characterized in that, The method includes: The first data transmission module generates a first pseudo-random binary sequence signal based on the system bandwidth and sends the first pseudo-random binary sequence signal to the first transmission processing module. The first pseudo-random binary sequence signal is transmitted to the first receiving processing module through the first serial-to-parallel converter transceiver link via the first transmitting processing module. The first receiving and processing module receives the first pseudo-random binary sequence signal and forwards the first pseudo-random binary sequence signal to the first data verification module. The first data verification module verifies the first pseudo-random binary sequence signal based on the second pseudo-random binary sequence signal generated by the system bandwidth, obtains the verification result, and sends the verification result to the first error statistics module. The first bit error statistics module determines the amount of correct data and the amount of erroneous data based on the verification results, and then determines the bit error rate of the first serial-to-parallel converter transceiver link based on the amount of correct data and the amount of erroneous data. The first data sending module and the first sending processing module are disposed on the first interconnect chip, and the first receiving processing module, the first data verification module and the first bit error statistics module are disposed on the second interconnect chip. The first data transmission module includes multiple parallel linear feedback shift register (PLF) generation modules. The first data transmission module selects a corresponding number of PLF generation modules based on the system bandwidth. The corresponding number of PLF generation modules generate pseudo-random binary sequence signals and output values. The input value of the first PLF generation module among the corresponding number of PLF generation modules is derived from an initial value and the output values ​​of all other PLF generation modules. The input value of each of the other PLF generation modules among the corresponding number of PLF generation modules is the output value of the previous PLF generation module. The pseudo-random binary sequence signals generated by the corresponding number of PLF generation modules are combined to form the first pseudo-random binary sequence signal.

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