Chip design method, device, electronic device and computer readable storage medium

Abstract

The present application provides a chip design method, device, electronic device and computer-readable storage medium, the method comprising: in the layout stage of the chip, performing timing conflict detection on the completed layout to detect the target setup path with the timing conflict; the target setup path is the path where the setup time with the timing conflict is located; increasing the setup time margin of the target setup path; based on the target setup path with the increased setup time margin, re-entering the layout stage of the chip. The scheme of the present application can improve the probability of conflict resolution between setup time and hold time, reduce the difficulty of conflict resolution between setup time and hold time, and reduce the risk of needing to reduce the chip operating frequency.

Description

Technical Field

[0001] The present application relates to the technical field of chip design, and in particular, to a chip design method, device, electronic device and computer-readable storage medium. Background Art

[0002] At present, EDA (Electronic Design Automation) tools and processes are all driven by setup time in the early stage of place (layout), and the conflicts between setup time and hold time in the circuit are checked when the hold time is repaired in the later stage. After the conflict between setup time and hold time is found, it is usually solved by damaging the setup time, satisfying the hold time first, and then restoring the setup time (that is, without considering whether repairing the hold time will cause setup time violations, repairing the path where the hold time is located, so that the hold time meets the design requirements, and then repairing the path where the setup time is located due to the hold time repair after the hold time is satisfied). However, in the later stage of physical design, too much unit optimization and routing disturbance may cause the setup time to be unrepairable or bring other timing problems. Once the setup time is unrepairable or other timing problems cannot be repaired, the conflict between setup time and hold time can only be solved by reducing the operating frequency of the chip to relax the non-conflict interval between setup time and hold time. However, lowering the chip's operating frequency will result in a decrease in chip performance and may even cause the chip to fail to meet specified specifications. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a chip design method, device, electronic device and computer-readable storage medium to improve the probability of resolving conflicts between setup time and hold time, reduce the difficulty of resolving conflicts between setup time and hold time, and reduce the risk of needing to reduce the chip operating frequency.

[0004] An embodiment of the present application provides a chip design method, comprising: in the layout stage of the chip, performing timing conflict detection on the completed layout to detect a target setup path with a timing conflict; the target setup path is a path where the setup time with the timing conflict is located; increasing the setup time margin of the target setup path; and re-entering the layout stage of the chip based on the target setup path with the increased setup time margin.

[0005] In the above implementation process, by performing timing conflict detection on the completed layout in the layout stage of the chip, and increasing the setup time margin for the target setup path with the timing conflict, when re-entering the layout stage of the chip and entering the subsequent timing detection and timing repair stage, since a timing conflict has been detected once in the layout stage of the chip, and the setup time margin of the target setup path with the timing conflict has been increased, when repairing the hold time, there is more setup time margin for the hold time to be repaired, thereby improving the probability of resolving the conflict between the setup time and the hold time, reducing the difficulty of resolving the conflict between the setup time and the hold time, and reducing the risk of needing to reduce the chip operating frequency.

[0006] Furthermore, before performing timing conflict detection on the completed layout, the method also includes: performing initial clock tree synthesis on the completed layout during the layout stage of the chip; correspondingly, performing timing conflict detection on the completed layout includes: performing timing conflict detection on the layout after clock tree synthesis.

[0007] In the above implementation, the initial clock tree synthesis is performed on the completed layout, thereby facilitating the subsequent timing detection.

[0008] Furthermore, after re-entering the chip layout stage, the method further includes: performing final clock tree synthesis on the re-layout circuit; and the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis is within a preset deviation range.

[0009] In the above implementation, by configuring the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis to be within a preset deviation range, the timing conflict detection result performed in the layout stage can be closer to the detection result when the timing conflict detection and repair are performed after the layout stage is actually completed, so that the establishment time margin of the target setup path added in the layout stage can better improve the probability of conflict resolution between setup time and hold time when actually repairing the timing conflict, reduce the difficulty of conflict resolution between setup time and hold time, and reduce the risk of needing to reduce the chip operating frequency.

[0010] Furthermore, the target setup path is a path where a setup time exists where a timing conflict exists and the timing conflict cannot be repaired.

[0011] In the above implementation, the setup time margin of the target setup path is increased only for the setup path that cannot be fixed due to the timing conflict. This reduces the amount of changes to the existing layout and reduces the risk of causing other timing problems.

[0012] Furthermore, the completed layout is detected for timing conflicts, including: detecting hold paths with timing conflicts in the layout; the hold paths are paths where the hold time is located; using a simulation tool to simulate and repair the timing conflicts of the hold paths to obtain a target hold path where the timing conflict cannot be repaired; and determining that the path where the setup time of the timing conflict with the target hold path is located is the target setup path.

[0013] In the above implementation, simulation tools are used to simulate and repair each hold path with timing conflicts, and then the target hold paths that cannot be repaired are found. These hold paths are likely to be the hold paths with timing conflicts that cannot be repaired that will be detected during the complete physical design process when timing conflicts are detected and repaired. Then, the setup time margin is increased in advance for the setup paths corresponding to these hold paths (i.e., the paths where the setup time of the target hold path timing conflicts is located) to resolve the timing conflicts during the simulation repair process. Then, when the timing conflicts are actually detected and repaired, the timing conflicts can be resolved with a high probability, thereby increasing the probability of resolving conflicts between setup time and hold time.

[0014] Furthermore, before re-entering the chip layout phase based on the target setup path that increases the setup time margin, the method further includes: restoring each of the hold paths to a state before performing timing conflict simulation repair.

[0015] In the above implementation process, by restoring each of the hold paths to the state before the timing conflict simulation repair, that is, restoring the original layout, when the timing conflict detection and repair are actually performed later, the relevant timing conflicts can be detected accordingly, so that corresponding repairs can be performed, thereby improving the repairability of the timing conflict and reducing the risk of introducing new problems.

[0016] Further, increasing the setup time margin of the target setup path includes: deleting redundant delay devices in the target setup path; and / or invoking an electronic design automation tool to optimize the target setup path.

[0017] It can be understood that in the layout stage of the chip, since the setup time is driven, the setup times in the layout all meet the design requirements and are not optimized too much, which leads to the possibility of optimization space on the path where the setup time is located (i.e., the setup path). In the above implementation, by deleting redundant delay devices on the target setup path and / or using EDA tools to optimize the target setup path, the setup time margin of the target setup path can be effectively increased, thereby increasing the probability of successful repair when actually performing timing conflict detection and repair.

[0018] An embodiment of the present application also provides a chip design device, including: a detection module, used to perform timing conflict detection on a completed layout during the layout stage of the chip to detect a target setup path with a timing conflict; the target setup path is a path where the setup time with the timing conflict is located; a repair module, used to increase the setup time margin of the target setup path; and a layout design module, used to re-enter the layout stage of the chip based on the target setup path with the setup time margin increased.

[0019] Furthermore, the chip design device also includes: a clock tree synthesis module, which is used to perform initial clock tree synthesis on the completed layout during the layout stage of the chip before the detection module performs timing conflict detection on the completed layout; correspondingly, the detection module is specifically used to perform timing conflict detection on the layout after clock tree synthesis.

[0020] Furthermore, the clock tree synthesis module is also used to perform final clock tree synthesis on the re-layout circuit after re-entering the chip layout stage; wherein the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis is within a preset deviation range.

[0021] Furthermore, the target setup path is a path where a setup time exists where a timing conflict exists and the timing conflict cannot be repaired.

[0022] Furthermore, the detection module is specifically used to: detect hold paths with timing conflicts in the layout; the hold paths are paths where the hold time is located; use simulation tools to simulate and repair the timing conflicts of each of the hold paths to obtain a target hold path where the timing conflict cannot be repaired; determine that the path where the setup time of the timing conflict with the target hold path is located is the target setup path.

[0023] Furthermore, the repair module is also used to restore each of the hold paths to a state before performing timing conflict simulation repair before re-entering the chip layout stage based on the target setup path that increases the setup time margin.

[0024] Furthermore, the repair module is specifically used to: delete redundant delay devices in the target setup path; and / or call an electronic design automation tool to optimize the target setup path.

[0025] An embodiment of the present application also provides an electronic device, including a processor and a memory; the processor is used to execute one or more programs stored in the memory to implement any of the above-mentioned chip design methods.

[0026] A computer-readable storage medium is also provided in an embodiment of the present application. The computer-readable storage medium stores one or more programs. The one or more programs can be executed by one or more processors to implement any of the above-mentioned chip design methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A schematic diagram of a circuit structure of a setup path and a hold path provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a chip design method provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of a chip design device provided in an embodiment of the present application;

[0031] Figure 4A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0033] The back-end design of a chip, also known as the physical design phase, usually includes the following processes:

[0034] Layout stage: Place the macro unit modules of the chip and determine the placement of various functional circuits in general, such as IP modules, RAM, I / O pins, etc. The layout stage can directly affect the final area of ​​the chip.

[0035] CTS (Clock Tree Synthesis) stage: Clock tree synthesis can be understood as the routing of the clock. Due to the global command role of the clock signal in the digital chip, its distribution should be symmetrically connected to each register unit, so that when the clock reaches each register from the same clock source, the clock delay difference is minimized.

[0036] The wiring stage includes laying out the wiring between various standard units (basic logic gate circuits).

[0037] Verification phase: including timing conflict detection and repair, etc.

[0038] Currently, EDA tools and physical design processes are all driven by setup time in the early layout stage. In the later verification stage, conflicts between setup time and hold time in the circuit are checked, and the hold time is repaired by adding or reducing delay devices on the hold path with timing conflicts.

[0039] like Figure 1 As shown, assuming that the hold path within the dashed line (hold path, Figure 1 The horizontal path in the middle (from the Hold path startpoint to the Hold path endpoint) has a timing violation (i.e., a hold time violation). This can usually be solved by inserting a delay unit anywhere in the hold path (such as the triangle unit marked by the dotted line between 2 and 3 in the figure). However, sometimes due to the limitations of the design and automatic layout and routing tools, when the delay unit is inserted, it will cause setup time violations for other paths passing through this point, such as Figure 1The vertical path in the diagram (i.e., the path from the setup path startpoint to the setup path endpoint in the diagram). If a similar situation occurs at each point on the hold path (causing a setup time violation at that point), then the hold path cannot be repaired, and the hold time is often repaired by reducing the chip's operating frequency to expand the setup-hold window (i.e., the non-conflicting interval between setup time and hold time).

[0040] Understandably, Figure 1 Each box represents a circuit unit in the circuit, such as a register, a trigger, etc. Numbers 1 to 8 in the figure represent the unit number in the hold path, A and B in the circuit unit represent the input terminal, Z represents the output terminal, D represents the data input terminal, and Q represents the output terminal.

[0041] However, from Figure 1 It can be seen that even if the vertical setup path is destroyed (increasing the delay), the increased delay can be compensated by reducing the delay of other devices in the vertical setup path (such as the marked logic-A, Logic-B, etc.), thereby repairing the setup time.

[0042] However, although the setup path can be optimized in the verification phase, the setup path is not optimized in the initial layout phase because the setup time is used in the layout phase. Once the optimization is performed in the verification phase, on the one hand, since the routing has already been completed, the large-scale setup path optimization will disrupt other routings and bring more timing uncertainty; on the other hand, since the layout has been completed, some optimizations will have no space and cannot be implemented due to the density of the area; on the other hand, due to the limitations of the design tools, the optimization ability of the tools will be weakened after routing, resulting in the inability to optimize satisfactory results. Usually, the conflict of setup hold at this moment is almost unsolvable and can only be solved by downclocking the chip (i.e., reducing the operating frequency).

[0043] In order to improve the probability of conflict resolution between setup time and hold time, reduce the difficulty of conflict resolution between setup time and hold time, and reduce the risk of needing to reduce the chip operating frequency, a chip design method is provided in an embodiment of the present application. Figure 2 As shown, Figure 2 A schematic diagram of a chip design method provided in an embodiment of the present application includes:

[0044] S201: During the chip layout phase, a timing conflict detection is performed on the completed layout to detect a target setup path with a timing conflict.

[0045] In the embodiment of the present application, the setup path refers to the path where the setup time is located, and the target setup path is the path where the setup time with a timing conflict is located.

[0046] It can be understood that, as mentioned above, before performing timing conflict detection, clock tree synthesis is usually required to generate a clock tree for the clock routing in the layout. For this reason, in an embodiment of the present application, before performing timing conflict detection on the completed layout, the completed layout can be subjected to an initial clock tree synthesis. It should be noted that, in an embodiment of the present application, real routing is not performed during the initial clock tree synthesis, but simulated routing. After re-entering the layout stage of the chip (i.e., re-entering the layout stage) in step S203, the final clock tree synthesis will be performed on the re-layout circuit, and then the timing conflict detection and repair in the final stage of physical design will be performed.

[0047] Since the subsequent timing conflict detection results depend on the results of clock tree synthesis, the closer the results of each clock tree synthesis are, the closer the final timing conflict detection results will be. For this reason, in some implementations of the embodiments of the present application, the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis can be configured within a preset deviation range. The preset deviation range can be set by engineers according to actual needs.

[0048] In order to make the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis within the preset deviation range, in an optional implementation, a large amount of sample data can be obtained in advance, the sample data includes a large number of program parameters of the clock tree synthesis used in different layouts, and the accuracy of the clock tree synthesis is marked, and the neural network model is trained using the sample data to obtain a trained neural network model. When using it, the required accuracy (the accuracy of the final clock tree synthesis can be entered) and the completed layout are input, and then the program parameters of the clock tree synthesis predicted by the neural network model can be obtained.

[0049] In another optional implementation, engineers and other professional technicians may collect a large amount of experimental data on clock tree synthesis, and then configure the program parameters of the initial clock tree synthesis based on experience or a large amount of experimental data, so as to ensure that the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis is within a preset deviation range as much as possible.

[0050] In an embodiment of the present application, by configuring the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis to be within a preset deviation range, the timing conflict detection result performed in the layout stage can be closer to the detection result when the timing conflict detection and repair are performed after the layout stage is actually completed, so that the establishment time margin of the target setup path added in the layout stage can better improve the probability of conflict resolution between setup time and hold time when actually repairing the timing conflict, reduce the difficulty of conflict resolution between setup time and hold time, and reduce the risk of needing to reduce the chip operating frequency.

[0051] In a feasible implementation of the embodiment of the present application, the path where the setup time with timing conflicts that cannot be repaired is located can be determined as the target setup path. In this way, the setup time margin can be increased only for the setup path where the timing conflicts cannot be repaired, which reduces the amount of changes to the existing layout and reduces the risk of causing other timing problems.

[0052] In the above feasible implementation, the hold paths with timing conflicts in the layout can be detected first (the hold paths are the paths where the hold time is located). The method of detecting the hold paths with timing conflicts can be implemented by various existing timing detection methods, which are not limited in the embodiments of the present application.

[0053] Then, the simulation tool can be used to simulate and repair the timing conflicts of the hold paths with timing conflicts, and obtain the target hold paths that cannot be repaired with the timing conflicts. It can be understood that the repair method of the timing conflicts is consistent with the existing repair method, which can be to try to add or reduce delay units in the hold paths one by one to repair them on the basis of ensuring the circuit function. The only difference is that in the final stage of the physical design stage, the hold paths are actually repaired, but in this step, the hold paths are simulated and repaired through simulation technology.

[0054] Finally, the path where the setup time conflicts with the target hold path is located can be determined as the target setup path. It can be understood that the timing conflict requires the participation of both the setup time and the hold time, so after determining the target hold path, the target setup path can be determined.

[0055] It can be understood that before detecting the hold paths with timing conflicts in the layout, you can also use the routing tool in the EDA to perform virtual routing on the circuit in the layout (that is, perform the routing operation but do not retain it as the final result). Then, perform timing conflict detection based on the circuit after virtual routing.

[0056] S202: Increase the setup time margin of the target setup path.

[0057] It is understandable that in the layout stage of the chip, since the setup time is used as the driver, the setup times in the layout all meet the design requirements and are not optimized too much. This leads to the possibility of optimization space on the path where the setup time is located (i.e., the setup path). For example Figure 1 The logic-A, Logic-B, etc. marked in can be optimized.

[0058] To this end, in a feasible implementation of the embodiment of the present application, redundant delay devices in the target setup path may be deleted to increase the setup time margin of the target setup path.

[0059] In another feasible implementation of the embodiment of the present application, an EDA tool can be called to optimize the target setup path. In this case, the optimization capability of the EDA tool itself can be used, and during the optimization process, since the optimization is still in the layout stage, there is no need to consider the limitations of routing and area density, so that the optimization capability of the EDA tool can be fully utilized to obtain the optimal layout after optimizing the setup path.

[0060] It can be understood that in the embodiments of the present application, for the detected timing conflict, especially the timing conflict that cannot be repaired by adjusting the hold path, the possibility of repairing the timing conflict can be increased by increasing the setup time margin of the target setup path and expanding the setup-hold window.

[0061] For this reason, in the embodiment of the present application, the amount of increase in the setup time margin needs to be based on whether the timing conflict can be repaired. For this reason, in the first feasible implementation method described above, the redundant delay devices in the target setup path can be deleted one by one to detect whether the timing conflict has been repaired. Deletion can be stopped after the repair. In the second feasible implementation method described above, the target setup path with the timing conflict can be specified in the EDA tool, and the timing requirements can be configured to automatically optimize the target setup path through the EDA tool.

[0062] In another feasible implementation of the embodiment of the present application, the above two feasible implementations can also be combined for processing. For example, the redundant delay devices in the target setup path can be deleted first, and after deleting all the redundant delay devices in the target setup path, if the timing conflict still cannot be fixed, the EDA tool is called to optimize the target setup path.

[0063] S203: Re-entering the chip layout phase based on the target setup path with increased setup time margin.

[0064] In the embodiment of the present application, the above method can be performed after completing a version of chip layout. Since increasing the setup time margin will optimize the target setup path, in step S203, the optimization of the target setup path can be retained on the basis of the original layout, thereby completing the new layout. In addition, in other optional implementations of the embodiment of the present application, step S203 can also be based on retaining the optimization of the target setup path, and re-calling the EDA tool for layout.

[0065] In the embodiment of the present application, before re-entering the layout stage of the chip based on the target setup path with increased setup time margin, each hold path can also be restored to the state before the timing conflict simulation repair. For example, for hold path A, when the simulation repair is performed, a delay device A1 is added, and A1 needs to be deleted.

[0066] In addition, the clock tree obtained by the initial clock tree synthesis can be deleted before re-entering the chip layout stage based on the target setup path with increased setup time margin.

[0067] In addition, the simulated winding part can also be deleted.

[0068] In this way, all parts except the target setup path to be optimized can be restored to the original layout, so that when the timing conflict detection and repair are actually performed later, the relevant timing conflicts can be detected accordingly, so that corresponding repairs can be performed, thereby improving the repairability of the timing conflicts and reducing the risk of introducing new problems.

[0069] After the re-layout is completed, the final clock tree synthesis will be performed on the re-laid circuit, and then the EAD routing tool will be used for routing, and then it will enter the verification stage for timing conflict detection and repair.

[0070] At this point, since the existing timing conflicts have been detected in the layout stage, and for the timing conflicts that cannot be fixed by adjusting the hold path, the setup time margin of the corresponding setup path is also increased, so theoretically all timing conflicts detected at this time can be fixed, so that the conflict between setup time and hold time can be resolved without downclocking the chip.

[0071] Based on the same inventive concept, the present embodiment also provides a chip design device 300. Figure 3 As shown, Figure 3 Shows the use of Figure 2The chip design device of the method shown. It should be understood that the specific functions of the device 300 can be referred to the description above, and the detailed description is appropriately omitted here to avoid repetition. The device 300 includes at least one software function module that can be stored in a memory in the form of software or firmware or fixed in the operating system of the device 300. Specifically:

[0072] See also Figure 3 As shown, the device 300 includes:

[0073] The detection module 301 is used to perform timing conflict detection on the completed layout in the layout stage of the chip to detect the target setup path with timing conflict; the target setup path is the path where the setup time with timing conflict is located;

[0074] A repair module 302, used to increase the establishment time margin of the target setup path;

[0075] The layout design module 303 is used to re-enter the layout phase of the chip based on the target setup path with the setup time margin increased.

[0076] In a feasible implementation of the embodiment of the present application, the apparatus 300 further includes a clock tree synthesis module, which is used to perform initial clock tree synthesis on the completed layout during the layout stage of the chip before the detection module 301 performs timing conflict detection on the completed layout;

[0077] The detection module 301 is specifically used to perform timing conflict detection on the layout after clock tree synthesis.

[0078] In an embodiment of the present application, the clock tree synthesis module is also used to perform final clock tree synthesis on the re-layout circuit after re-entering the chip layout stage; wherein the deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis is within a preset deviation range.

[0079] In a feasible implementation of the embodiment of the present application, the target setup path is a path where a setup time exists where a timing conflict exists and the timing conflict cannot be repaired.

[0080] In this feasible implementation manner, the detection module 301 is specifically used for: detecting hold paths with timing conflicts in the layout; the hold paths are paths where the hold time is located; using a simulation tool to simulate and repair the timing conflicts of each of the hold paths to obtain a target hold path where the timing conflict cannot be repaired; and determining that the path where the setup time of the timing conflict with the target hold path is located is the target setup path.

[0081] In this feasible implementation manner, the repair module 302 is also used to restore each of the hold paths to the state before performing the timing conflict simulation repair before re-entering the chip layout stage based on the target setup path that increases the setup time margin.

[0082] In a feasible implementation of the embodiment of the present application, the repair module 302 is specifically used for:

[0083] Deleting redundant delay devices in the target setup path;

[0084] and / or,

[0085] An electronic design automation tool is called to optimize the target setup path.

[0086] It should be understood that, for the sake of brevity, some of the contents described in the first embodiment will not be repeated in this embodiment.

[0087] Based on the same inventive concept, the present application also provides an electronic device, see Figure 4 As shown, it includes a processor 401 and a memory 402. Among them:

[0088] The processor 401 is used to execute one or more programs stored in the memory 402 to implement the above chip design method.

[0089] It is understood that the processor 401 may be a processor core or a processor chip, or other circuits capable of program configuration and operation. The memory 402 may be a RAM (Random Access Memory), a ROM (Read-Only Memory), a flash memory, a hard disk, etc., but is not limited thereto.

[0090] It is understandable. Figure 4 The structure shown is for illustration only. The electronic device may also include Figure 4 More or fewer components as shown, or with Figure 4 For example, it may also have an internal communication bus for realizing communication between the processor 701 and the memory 702; for another example, it may also have an external communication interface, such as a USB (Universal Serial Bus) interface, a CAN (Controller Area Network) bus interface, etc.; for another example, it may also have an information display component such as a display screen, but this is not a limitation.

[0091] Based on the same inventive concept, this embodiment also provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more programs for implementing the above steps are stored, and the one or more programs can be executed by one or more processors to implement the above chip design method. No further details will be given here.

[0092] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0093] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0094] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0095] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0096] As used herein, a plurality refers to two or more than two.

[0097] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip design method, characterized in that: include: During the chip layout phase, the completed layout is tested for timing conflicts to detect target setup paths with timing conflicts. The target setup path is a path where a setup time exists that has a timing conflict and cannot be repaired; Increasing the setup time margin of the target setup path; re-entering the chip layout phase based on the target setup path that increases the setup time margin; Perform timing violation detection on the completed layout, including: Detecting hold paths with timing conflicts in the layout; the hold paths are paths where the hold time is located; using a simulation tool to simulate and repair the timing conflicts of the hold paths to obtain target hold paths where the timing conflicts cannot be repaired; determining the path where the setup time of the timing conflicts with the target hold paths is located as the target setup path; Before re-entering the chip layout phase based on increasing the target setup path with the setup time margin, the method further includes: restoring each of the hold paths to a state before performing timing conflict simulation repair.

2. The method according to claim 1, characterized in that Before performing timing conflict detection on the completed layout, the method further includes: During the layout phase of the chip, performing initial clock tree synthesis on the completed layout; Correspondingly, the timing conflict detection for the completed layout includes: Perform timing violation detection on the layout after clock tree synthesis.

3. The method according to claim 2, characterized in that After re-entering the layout stage of the chip, the method further includes: performing final clock tree synthesis on the re-layout circuit; The deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis is within a preset deviation range.

4. The method according to any one of claims 1 to 3, characterized in that: Increasing the setup time margin of the target setup path includes: Deleting redundant delay devices in the target setup path; and / or, An electronic design automation tool is called to optimize the target setup path.

5. A chip design device, characterized in that: include: The detection module is used to perform timing conflict detection on the completed layout during the chip layout stage to detect the target setup path with timing conflict; The target setup path is a path where a setup time exists that has a timing conflict and cannot be repaired; A repair module, used to increase the establishment time margin of the target setup path; A layout design module, configured to re-enter a layout phase of a chip based on the target setup path that increases the setup time margin; The detection module is specifically used to: detect the hold paths with timing conflicts in the layout; the hold paths are paths where the hold time is located; use a simulation tool to simulate and repair the timing conflicts of each of the hold paths to obtain a target hold path where the timing conflicts cannot be repaired; determine that the path where the setup time of the timing conflict with the target hold path is located is the target setup path; The repair module is also used to restore each of the hold paths to a state before performing timing conflict simulation repair before re-entering the chip layout stage based on the target setup path that increases the setup time margin.

6. The chip design device according to claim 5, characterized in that: The chip design device further includes: A clock tree synthesis module, used for performing an initial clock tree synthesis on the completed layout during the layout stage of the chip before the detection module performs a timing conflict detection on the completed layout; Correspondingly, the detection module is specifically used to perform timing conflict detection on the layout after clock tree synthesis.

7. The chip design device according to claim 6, characterized in that: The clock tree synthesis module is also used to perform final clock tree synthesis on the re-layout circuit after re-entering the layout stage of the chip; The deviation between the accuracy of the initial clock tree synthesis and the accuracy of the final clock tree synthesis is within a preset deviation range.

8. An electronic device, characterized in that: include: Processor and memory; The processor is used to execute one or more programs stored in the memory to implement the chip design method as described in any one of claims 1-4.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip design method as described in any one of claims 1-4.

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