Radiation-hardened pre-discharge type sense amplifier and control method thereof

Abstract

The application belongs to the field of non-volatile new type storage, and particularly relates to an anti-radiation reinforced pre-discharge type sensitive amplifier and a control method thereof, and aims to solve the problem that the existing storage unit peripheral circuit based on MOS tubes is still sensitive to space radiation effect. The application comprises: a pre-discharge part connected to a charge sensing part through a first sensing branch and a second sensing branch; the charge sensing part comprises PMOS tubes PM0 and PM1 and is connected to V DD ; a first end of a first feedback branch is connected to PM0, a second end is connected to PM1, a third end is connected to the first sensing branch, and a fourth end is connected to the second sensing branch; the first sensing branch is connected to the second sensing branch through a second feedback branch; and the second sensing branch is connected to the first sensing branch through a third feedback branch. The application accelerates the discharge time of the sensing branch where the data unit and the contrast unit are located by setting three feedback branches for the amplifier, and stably increases the voltage difference between the zeroth output node V0 and the first output node V1.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of non-volatile new type storage, and particularly relates to an anti-radiation reinforced pre-discharge type sensitive amplifier and a control method thereof. BACKGROUND

[0002] New type storage is to realize storage based on non-charge storage principle by using new materials. New type storage based on resistance storage has shown excellent performance and has been paid more and more attention, such as phase change memory (PCRAM), magnetic memory (MRAM), resistive random access memory (RRAM) and ferroelectric memory (FRAM). The common feature of these new type storage is non-volatility, that is, the data is effective after power failure, and they have similar storage principle: high and low resistance states are used to realize storage. Compared with traditional storage, the biggest advantage of new type storage is that it uses new materials as storage unit and uses new storage technology to replace the traditional charge storage mode, and has the natural anti-radiation characteristic, which is more suitable for the application development in the field of spaceflight. However, the circuit based on MOS tube outside the storage unit is still sensitive to space radiation effect, and needs to be designed for anti-radiation reinforcement to meet the high reliability requirement of space application storage.

[0003] The sensitive amplifier is one of the modules in the read circuit of new type storage, which is used to judge the high and low resistance states of the data unit and the reference unit, that is, to judge whether the stored data is "0" or "1", and to amplify and output the judgment result. The high-performance sensitive amplifier needs to have higher resistance state discrimination ability, faster operation speed, lower power consumption, and needs to have anti-radiation ability in order to adapt to the application field of aviation and spaceflight. SUMMARY

[0004] In order to solve the above problems in the prior art, that is, the problem that the circuit based on MOS tube outside the existing storage unit is still sensitive to space radiation effect, the application provides an anti-radiation reinforced pre-discharge type sensitive amplifier, which comprises:

[0005] a pre-discharge part, a first sensing branch, a second sensing branch, a charging sensing part, a first feedback branch, a second feedback branch and a third feedback branch;

[0006] The pre-discharge part is connected to the charging sensing part through the first sensing branch and the second sensing branch;

[0007] The charging sensing part includes PMOS tubes PM0 and PM1; the charging sensing part is connected to V DD ;

[0008] The first end of the first feedback branch is connected to PM0, the second end of the first feedback branch is connected to PM1, the third end of the first feedback branch is connected to the first sensing branch, and the fourth end of the first feedback branch is connected to the second sensing branch;

[0009] The first sensing branch is connected to the second sensing branch through the second feedback branch;

[0010] The second sensing branch is connected to the first sensing branch through the third feedback branch.

[0011] In some preferred embodiments, the first sensing branch and the second sensing branch specifically include:

[0012] The first sensing branch, from the pre-discharge part to the charging sensing part, includes the second connection node ND2, the resistor R0, the first output node V0, the zeroth connection node ND0, the fourth connection node ND4, and the third end of the first feedback branch;

[0013] The second sensing branch, from the pre-discharge part to the charging sensing part, includes the third connection node ND3, the resistor R1, the second output node V1, the first connection node ND1, the fifth connection node, and the fourth end of the first feedback branch.

[0014] In some preferred embodiments, the pre-discharge part specifically includes:

[0015] The pre-discharge part includes NMOS tubes NM0, NM1, NM2, and NM3, wherein the sources of NM0, NM1, NM2, and NM3 are grounded, the drain of NM2, the gate of NM2, and the drain of NM0 are connected to the second connection node ND2, the drain of NM3, the gate of NM3, and the drain of NM1 are connected to the third connection node ND3;

[0016] The second connection node ND2 is connected to the first sensing branch;

[0017] The third connection node ND3 is connected to the second sensing branch;

[0018] The gate of NM0 and the gate of NM1 are connected to the first clock signal end CLK.

[0019] In some preferred embodiments, the first feedback branch specifically includes:

[0020] The third input end AND gate OR0 and the first three-input OR gate OR1;

[0021] The three inputs of the first three-input AND gate OR0 are connected with the first clock signal end CLK, the column selection signal SELcol and the first connection node ND1 respectively, and the output of the first three-input AND gate OR0 is connected with the gate of PM0.

[0022] The three inputs of the first three-input AND gate OR1 are connected with the first clock signal end CLK, the column selection signal SELcol and the first connection node ND0 respectively, and the output of the first three-input AND gate OR1 is connected with the gate of PM1.

[0023] In some preferred embodiments, the second feedback branch specifically comprises:

[0024] The zero NAND gate NAND0, the zero inverter INV0 and the NMOS tube NM4.

[0025] The gate of NM4 is connected with the output of the zero inverter INV0, the source of NM4 is grounded, and the drain of NM4 is connected with the first connection node ND0.

[0026] The input of the zero inverter INV0 is connected with the output of the zero NAND gate NAND0.

[0027] The inputs of the zero NAND gate are connected with the first connection node ND1 and the second clock signal end / CLK respectively.

[0028] In some preferred embodiments, the third feedback branch specifically comprises:

[0029] The first NAND gate NAND1, the first inverter INV1 and the NMOS tube NM5.

[0030] The gate of NM5 is connected with the output of the first inverter INV1, the source of NM5 is grounded, and the drain of NM5 is connected with the first connection node ND1.

[0031] The input of the first inverter INV1 is connected with the output of the first NAND gate NAND1.

[0032] The inputs of the first NAND gate are connected with the fourth feedback node and the second clock signal end / CLK respectively.

[0033] Another aspect of the present application provides a control method of the anti-radiation reinforced pre-discharge type sensitive amplifier, which is based on the above-mentioned anti-radiation reinforced pre-discharge type sensitive amplifier and comprises the following steps:

[0034] According to the set instruction signal, the level of the column selection signal SELcol and the level of the clock signal are controlled, so that the sensitive amplifier is controlled to perform the pre-discharge stage or the sensing stage.

[0035] After the pre-discharge phase, the current pulse charges the zeroth connection node ND0 and the first connection node ND1 through PM0 and PM1, and the inductive, amplification of the signal difference and input to the subsequent circuit are completed by the different charging speeds of the zeroth connection node ND0 and the first connection node ND1 and the potential of the first output node V0 being 1 and the potential of the second output node V1 being 0 or the potential of the first output node V0 being 0 and the potential of the second output node V1 being 1.

[0036] In some preferred embodiments, the pre-discharge phase specifically includes:

[0037] The level of the column selection signal SELcol is low 0, the level of the first clock signal end CLK is high 1, and the level of the second clock signal end / CLK is low 0;

[0038] The NMOS tubes NM0 and NM1 of the pre-discharge part are turned on;

[0039] The potential of the second connection node ND2 and the potential of the third connection node ND3 are discharged to 0;

[0040] The level of the first end of the first feedback branch and the level of the second end of the first feedback branch are 1;

[0041] The PMOS tubes PM0 and PM1 are turned off, and the potential of the zeroth connection node ND0 and the potential of the first connection node ND1 are discharged to 0;

[0042] NM4 and NM5 are turned off, and the second feedback branch and the third feedback branch are not conductive;

[0043] No current passes through the resistors R0 and R1 in the pre-discharge phase, and the potential of the first output node V0 and the potential of the second output node V1 are 0.

[0044] In some preferred embodiments, the sensing phase specifically includes:

[0045] The level of the column selection signal SELcol is low 0, the level of the first clock signal end CLK is low 0, and the level of the second clock signal end / CLK is high 1;

[0046] The potential of the zeroth connection node ND0 and the potential of the first connection node ND1 are discharged to 0;

[0047] The level of the first end of the first feedback branch and the level of the second end of the first feedback branch are 0;

[0048] The PMOS tubes PM0 and PM1 are turned on to charge the zeroth connection node ND0 and the first connection node ND1;

[0049] By comparing the resistance value of the resistance R0 and the resistance R1, according to the comparison result, the first output node V0 and the second output node V1 output the set level.

[0050] In some preferred embodiments, the comparison of the resistance value of the resistance R0 and the resistance R1, according to the comparison result, the first output node V0 and the second output node V1 output the set level, specifically includes:

[0051] When the resistance value of the resistance R0 is higher than the resistance value of the resistance R1, the potential rising speed of the zero connection node ND0 is faster than the potential rising speed of the first connection node ND1;

[0052] When the potential of the zero connection node ND0 is higher than the threshold value of the low level output of the first NAND gate NAND1, the first inverter INV1 outputs a high level, the NM5 is opened, the third feedback branch is turned on, and the potential of the first connection node ND1 is discharged to 0;

[0053] The first three-input OR gate OR1 in the first feedback branch outputs a high level, the PM1 is closed, the charging of the first connection node ND1 is stopped, and the potential of the first connection node is maintained at 0;

[0054] The potential of the zero connection node ND0 is pulled up to 1 through the PM0;

[0055] The potential of the first output node V0 is 1, and the potential of the second output node V1 is 0;

[0056] When the resistance value of the resistance R0 is lower than the resistance value of the resistance R1, the potential rising speed of the first connection node ND1 is faster than the potential rising speed of the zero connection node ND0;

[0057] When the potential of the first connection node ND1 is higher than the threshold value of the low level output of the zero NAND gate NAND0, the zero inverter INV0 outputs a high level, the NM4 is opened, the second feedback branch is turned on, and the potential of the zero connection node ND0 is discharged to 0;

[0058] The zero three-input OR gate OR0 in the first feedback branch outputs a high level, the PM0 is closed, the charging of the zero connection node ND0 is stopped, and the potential of the zero connection node ND0 is maintained at 0;

[0059] The potential of the first connection node is pulled up to 1 through the PM1, the potential of the first output node V0 is 0, and the potential of the second output node V1 is 1.

[0060] The beneficial effects of the present application:

[0061] (1) The application accelerates the discharge time of the sensing branch where the data unit (R0 or R1) and the comparison unit (R1 or R0) are located by setting three feedback branches for the amplifier, thereby stabilizing and increasing the voltage difference between the zeroth output node V0 and the first output node V1.

[0062] (2) The application has the repair capability for single-node flip caused by space single event effect by setting three feedback branches for the amplifier, thereby improving the read operation speed and reliability.

[0063] (3) The anti-radiation reinforced pre-discharge type sensitive amplifier proposed in the application increases the tolerance of the read circuit to PVT deviation by using a symmetrical circuit structure, improves the sensing speed of the sensitive amplifier, and has an anti-radiation reinforcement effect on the single particle sensitive points ND0 and ND1, thereby reducing the area, power consumption and time overhead compared with the existing reinforcement scheme, and having the advantages of low power consumption, high reliability, anti-radiation and long service life, and can be used as a new type of space-grade memory read circuit design.

[0064] (4) The application adopts a hierarchical sensing operation mode, designs three feedback branches for auxiliary sensing and amplification, and accelerates the charging and discharging speed of the two sensing branches. According to the storage architecture design and the driving capability of the read circuit, the read operation can be performed on one storage subarray or a plurality of data units, and whether multi-modular redundancy anti-radiation reinforcement is needed can be determined according to the actual situation.

[0065] (5) The application adopts a pre-discharge operation mode, thereby reducing the operating current and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0066] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments made with reference to the accompanying drawings:

[0067] Figure 1 is a structural schematic diagram of an anti-radiation reinforced pre-discharge type sensitive amplifier in an embodiment of the application;

[0068] Figure 2 is a circuit schematic diagram of an anti-radiation reinforced pre-discharge type sensitive amplifier and its feedback branch in an embodiment of the application. DETAILED DESCRIPTION

[0069] The application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, in order to facilitate description, only the parts related to the application are shown in the drawings.

[0070] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0071] In order to more clearly describe the anti-radiation reinforced pre-discharge type sensitive amplifier of the present application, the following will be described in combination with Figure 1 and Figure 2 The various circuit components in the embodiments of the present application will be described in detail.

[0072] The anti-radiation reinforced pre-discharge type sensitive amplifier of the first embodiment of the present application includes a pre-discharge part, a first sensing branch, a second sensing branch, a charging sensing part, a first feedback branch, a second feedback branch and a third feedback branch; the various circuit components are described in detail as follows:

[0073] The pre-discharge part is connected to the charging sensing part through the first sensing branch and the second sensing branch.

[0074] In the present embodiment, the pre-discharge part specifically includes:

[0075] The pre-discharge part includes NMOS tubes NM0, NM1, NM2 and NM3, wherein the sources of NM0, NM1, NM2 and NM3 are grounded, the drain of NM2, the gate of NM2 and the drain of NM0 are connected to a second connection node ND2, the drain of NM3, the gate of NM3 and the drain of NM1 are connected to a third connection node ND3;

[0076] The second connection node ND2 is connected to the first sensing branch;

[0077] The third connection node ND3 is connected to the second sensing branch;

[0078] The gate of NM0 and the gate of NM1 are connected to a first clock signal end CLK.

[0079] In the present embodiment, the first sensing branch and the second sensing branch specifically include:

[0080] The first sensing branch, from the pre-discharge part to the charging sensing part, includes the second connection node ND2, a resistor R0, a first output node V0, a zeroth connection node ND0, a fourth connection node ND4 and a third end of the first feedback branch;

[0081] The second sensing branch, from the pre-discharge part to the charging sensing part, includes the third connection node ND3, a resistor R1, a second output node V1, a first connection node ND1, a fifth connection node ND5 and a fourth end of the first feedback branch.

[0082] The charging sensing part includes PMOS tubes PM0 and PM1; the charging sensing part is connected to VDD .

[0083] The first end of the first feedback branch is connected to PM0, the second end of the first feedback branch is connected to PM1, the third end of the first feedback branch is connected to the first sensing branch, and the fourth end of the first feedback branch is connected to the second sensing branch.

[0084] In the embodiment, the first feedback branch specifically comprises:

[0085] The third input end of the third input end AND gate OR0 is connected to the first clock signal end CLK, the column selection signal SELcol and the first connection node ND1, and the output end of the third input end AND gate OR0 is connected to the gate of PM0.

[0086] The third input end of the third input end AND gate OR0 is connected to the first clock signal end CLK, the column selection signal SELcol and the first connection node ND1, and the output end of the third input end AND gate OR0 is connected to the gate of PM0.

[0087] The third input end of the third input end AND gate OR1 is connected to the first clock signal end CLK, the column selection signal SELcol and the zeroth connection node ND0, and the output end of the third input end AND gate OR1 is connected to the gate of PM1.

[0088] The first sensing branch is connected to the second sensing branch through the second feedback branch.

[0089] In the embodiment, the second feedback branch specifically comprises:

[0090] The zeroth NAND gate NAND0, the zeroth inverter INV0 and the NMOS tube NM4.

[0091] The gate of NM4 is connected to the output end of the zeroth inverter INV0, the source of NM4 is grounded, and the drain of NM4 is connected to the zeroth connection node ND0.

[0092] The input end of the zeroth inverter INV0 is connected to the output end of the zeroth NAND gate NAND0.

[0093] The input end of the zeroth NAND gate is connected to the first connection node ND1 and the second clock signal end / CLK.

[0094] The second sensing branch is connected to the first sensing branch through the third feedback branch.

[0095] In the embodiment, the third feedback branch specifically comprises:

[0096] The first NAND gate NAND1, the first inverter INV1 and the NMOS tube NM5.

[0097] The gate of NM5 is connected to the output end of the first inverter INV1, the source of NM5 is grounded, and the drain of NM5 is connected to the first connection node ND1.

[0098] The input end of the first inverter INV1 is connected with the output end of the first NAND gate NAND1.

[0099] The input ends of the first NAND gate are respectively connected with the fourth feedback node and the second clock signal end / CLK.

[0100] The control method of the anti-radiation reinforced pre-discharge type sensitive amplifier of the second embodiment of the present application is based on the anti-radiation reinforced pre-discharge type sensitive amplifier described above, and the control method comprises:

[0101] The level of the column selection signal SELcol and the level of the clock signal are controlled according to the set instruction signal, so as to control the sensitive amplifier to perform the pre-discharge stage or the sensing stage.

[0102] In the present embodiment, the pre-discharge stage specifically comprises:

[0103] The level of the column selection signal SELcol is low level 0, the level of the first clock signal end CLK is high level 1, and the level of the second clock signal end / CLK is low level 0.

[0104] The NMOS tubes NM0 and NM1 of the pre-discharge part are turned on.

[0105] The potential of the second connection node ND2 and the potential of the third connection node ND3 are discharged to 0.

[0106] The level of the first end of the first feedback branch and the level of the second end of the first feedback branch are 1.

[0107] The PMOS tubes PM0 and PM1 are turned off, the potential of the zeroth connection node ND0 and the potential of the first connection node ND1 are discharged to 0.

[0108] The NM4 and NM5 are turned off, and the second feedback branch and the third feedback branch are not conducted.

[0109] In the pre-discharge stage, no current passes through the resistors R0 and R1, and the potentials of the first output node V0 and the second output node V1 are 0.

[0110] In the present embodiment, the sensing stage specifically comprises:

[0111] The level of the column selection signal SELcol is low level 0, the level of the first clock signal end CLK is low level 0, and the level of the second clock signal end / CLK is high level 1.

[0112] The potential of the zeroth connection node ND0 and the potential of the first connection node ND1 are discharged to 0.

[0113] The level of the first end of the first feedback branch and the level of the second end of the first feedback branch are 0;

[0114] The PMOS transistors PM0 and PM1 are turned on to charge the zeroth connection node ND0 and the first connection node ND1;

[0115] By comparing the resistance values of the resistors R0 and R1, the first output node V0 and the second output node V1 output the set level according to the comparison result. In this embodiment, for MRAM, RRAM, Flash and other non-volatile memories, data "0" and "1" are stored in the form of the relative resistance values of the resistors R0 and R1. For example, when R0>R1, the stored data is "0"; when R0

[0116] In this embodiment, the process of making the first output node V0 and the second output node V1 output the set level according to the comparison result by comparing the resistance values of the resistors R0 and R1 specifically includes:

[0117] When the resistance value of the resistor R0 is higher than that of the resistor R1, the potential of the zeroth connection node ND0 rises faster than that of the first connection node ND1;

[0118] When the potential of the zeroth connection node ND0 is higher than the threshold value of the low level output of the first NAND gate NAND1, the first inverter INV1 outputs a high level, the NM5 is turned on, the third feedback branch is turned on, and the potential of the first connection node ND1 is discharged to 0;

[0119] The first three-input OR gate OR1 in the first feedback branch outputs a high level, the PM1 is turned off, the charging of the first connection node ND1 is stopped, and the potential of the first connection node is maintained at 0;

[0120] The potential of the zeroth connection node ND0 is pulled up to 1 through the PM0;

[0121] The potential of the first output node V0 is 1, and the potential of the second output node V1 is 0;

[0122] When the resistance value of the resistor R0 is lower than that of the resistor R1, the potential of the first connection node ND1 rises faster than that of the zeroth connection node ND0;

[0123] When the potential of the first connection node ND1 is higher than the threshold value of the low level output of the zeroth NAND gate NAND0, the zeroth inverter INV0 outputs a high level, the NM4 is turned on, the second feedback branch is turned on, and the potential of the zeroth connection node ND0 is discharged to 0; in the actual circuit, the first connection node ND1 and the fifth connection node ND5 are the same node, and the zeroth connection node ND0 and the fourth connection node ND4 are the same node;

[0124] The third input end in the first feedback branch is connected with the high level output of the OR0 gate, the PM0 is closed, the charging of the zero connection node ND0 is stopped, and the level of the zero connection node ND0 is maintained at 0;

[0125] The potential of the first connection node is pulled up to 1 through the PM1, the potential of the first output node V0 is 0, and the potential of the second output node V1 is 1.

[0126] After the pre-discharge stage ends, the current pulse charges the zero connection node ND0 and the first connection node ND1 through the PM0 and the PM1, and the signal difference is completed by using the different charging speeds of the zero connection node ND0 and the first connection node ND1 and the potential of the first output node V0 being 1 and the potential of the second output node V1 being 0 or the potential of the first output node V0 being 0 and the potential of the second output node V1 being 1, and the output potential is input to the subsequent circuit. The three feedback branches in the embodiment can improve the single event upset resistance of the connection node and accelerate the connection node to reach the steady voltage.

[0127] Although the above embodiment describes each step in the above order, those skilled in the art can understand that, in order to achieve the effect of the embodiment, the different steps do not have to be executed in such an order, and they can be executed simultaneously (in parallel) or in a reversed order, and these simple changes are within the protection scope of the present application.

[0128] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related description of the system described above can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

[0129] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related description of the storage device and the processing device described above can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

[0130] Those skilled in the art should clearly understand that the modules and method steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of both. The programs corresponding to the software modules and method steps can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. In order to clearly illustrate the interchangeability of electronic hardware and software, the components and steps of each example have been described in the above description in general terms. Whether the functions are performed by electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0131] The terms "first", "second", and the like are used to distinguish similar objects, rather than to describe or indicate a particular order or sequence.

[0132] The term "comprising" or any other similar term is intended to encompass a non-exclusive inclusion, such that a process, method, article, or apparatus / device including a series of elements includes not only those elements expressly listed, but also other elements inherent in such process, method, article, or apparatus / device or latent in such process, method, article, or apparatus / device.

[0133] So far, the technical solutions of the present application have been described in combination with the preferred embodiments shown in the drawings, but those skilled in the art can easily understand that the protection scope of the present application is obviously not limited to these specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without departing from the principles of the present application, and the technical solutions after such changes or replacements will fall within the protection scope of the present application.

Claims

1. A radiation hardened pre-discharge type sensitive amplifier, characterized in that: The amplifier comprises: A pre-discharge portion, a first sensing branch, a second sensing branch, a charge sensing portion, a first feedback branch, a second feedback branch, and a third feedback branch; The pre-discharging part is connected to the charging sensing part through a first sensing branch and a second sensing branch; The charging sensing part includes PMOS tubes PM0 and PM1; the charging sensing part is connected to V DD ; A first end of the first feedback branch is connected to PM0, a second end of the first feedback branch is connected to PM1, a third end of the first feedback branch is connected to the first sensing branch, and a fourth end of the first feedback branch is connected to the second sensing branch; The first sensing branch is connected to the second sensing branch via the second feedback branch; The second sensing branch is connected to the first sensing branch via a third feedback branch; The first sensing branch and the second sensing branch specifically include: The first sensing branch, from the pre-discharging portion to the charging sensing portion, includes a second connection node ND2, a resistor R0, a first output node V0, a ​​zeroth connection node ND0, a fourth connection node ND4 and a third end of the first feedback branch; The second sensing branch, from the pre-discharging part to the charging sensing part, includes a third connection node ND3, a resistor R1, a second output node V1, a first connection node ND1, a fifth connection node ND5 and the fourth end of the first feedback branch.

2. The radiation hardened pre-discharge type sense amplifier according to claim 1, wherein: The pre-discharging part specifically includes: The pre-discharge portion includes NMOS transistors NM0, NM1, NM2, and NM3, wherein the sources of NM0, NM1, NM2, and NM3 are grounded, the drain of NM2, the gate of NM2, and the drain of NM0 are connected to the second connection node ND2, and the drain of NM3, the gate of NM3, and the drain of NM1 are connected to the third connection node ND3; The second connection node ND2 is connected to the first sensing branch; The third connection node ND3 is connected to the second sensing branch; The gate of NM0 and the gate of NM1 are connected to the first clock signal terminal CLK.

3. The radiation hardened pre-discharge type sense amplifier according to claim 2, wherein: The first feedback branch specifically includes: The zeroth three-input AND gate OR0 and the first three-input AND gate OR1; The three input terminals of the zero-third input terminal AND gate OR0 are respectively connected to the first clock signal terminal CLK, the column selection signal SELcol and the first connection node ND1, and the output terminal of the zero-third input terminal AND gate OR0 is connected to the gate of PM0; Three input terminals of the first three-input AND gate OR1 are respectively connected to the first clock signal terminal CLK, the column selection signal SELcol and the zeroth connection node ND0 , and an output terminal of the first three-input AND gate OR1 is connected to the gate of PM1 .

4. The radiation hardened pre-discharge type sense amplifier according to claim 2, wherein: The second feedback branch specifically includes: The zeroth NAND gate NAND0, the zeroth inverter INV0 and the NMOS tube NM4; The gate of NM4 is connected to the output end of the zeroth inverter INV0, the source of NM4 is grounded, and the drain of NM4 is connected to the zeroth connection node ND0; The input end of the zeroth inverter INV0 is connected to the output end of the zeroth NAND gate NAND0; Input terminals of the zeroth NAND gate are connected to the first connection node ND1 and the second clock signal terminal / CLK respectively.

5. The radiation hardened pre-discharge type sense amplifier according to claim 2, wherein: The third feedback branch specifically includes: A first NAND gate NAND1, a first inverter INV1 and an NMOS transistor NM5; The gate of NM5 is connected to the output terminal of the first inverter INV1, the source of NM5 is grounded, and the drain of NM5 is connected to the first connection node ND1; An input end of the first inverter INV1 is connected to an output end of the first NAND gate NAND1; Input terminals of the first NAND gate are connected to the fourth feedback node and the second clock signal terminal / CLK respectively.

6. A control method for a radiation hardened pre-discharge type sense amplifier, characterized in that: The method is implemented based on the radiation hardened pre-discharge type sense amplifier according to any one of claims 1 to 5, and the control method includes: According to the set command signal, the level of the column selection signal SELcol and the level of the clock signal are controlled, thereby controlling the sense amplifier to perform the pre-discharge stage or the sensing stage; After the pre-discharge stage, the current pulse charges the zeroth connection node ND0 and the first connection node ND1 through PM0 and PM1. By utilizing the different charging speeds of the zeroth connection node ND0 and the first connection node ND1 and the stable potential state when the potential of the first output node V0 is 1 and the potential of the second output node V1 is 0 or the potential of the first output node V0 is 0 and the potential of the second output node V1 is 1, the signal difference is sensed and amplified, and the potential of the output node is input into the subsequent circuit.

7. The control method of the radiation hardened pre-discharge type sense amplifier according to claim 6, characterized in that: The pre-discharge stage specifically includes: The level of the column selection signal SELcol is low level 0, the level of the first clock signal terminal CLK is high level 1, and the level of the second clock signal terminal / CLK is low level 0; The NMOS tubes NM0 and NM1 of the pre-discharge part are turned on; The potential of the second connection node ND2 and the potential of the third connection node ND3 are discharged to 0; The level of the first end of the first feedback branch and the level of the second end of the first feedback branch are 1; The PMOS transistors PM0 and PM1 are turned off, and the potential of the zeroth connection node ND0 and the potential of the first connection node ND1 are discharged to 0; NM4 and NM5 are turned off, and the second feedback branch and the third feedback branch are not conducting; In the pre-discharge stage, no current flows through the resistor R0 and the resistor R1 , and the potentials of the first output node V0 and the second output node V1 are zero.

8. The control method of the radiation hardened pre-discharge type sense amplifier according to claim 6, characterized in that: The sensing stage specifically includes: The level of the column selection signal SELcol is low level 0, the level of the first clock signal terminal CLK is low level 0, and the level of the second clock signal terminal / CLK is high level 1; The potential of the zeroth connection node ND0 and the potential of the first connection node ND1 are discharged to 0; The level of the first end of the first feedback branch and the level of the second end of the first feedback branch are 0; The PMOS transistors PM0 and PM1 are turned on to charge the zeroth connection node ND0 and the first connection node ND1; By comparing the resistance values ​​of the resistor R0 and the resistor R1 , the first output node V0 and the second output node V1 are made to output a set electrical level according to the comparison result.

9. The control method of the radiation hardened pre-discharge type sense amplifier according to claim 8, characterized in that: The step of comparing the resistance values ​​of the resistor R0 and the resistor R1 and causing the first output node V0 and the second output node V1 to output a set voltage level according to the comparison result specifically includes: When the resistance value of the resistor R0 is higher than the resistance value of the resistor R1, the potential of the zeroth connection node ND0 increases faster than the potential of the first connection node ND1. When the potential of the zeroth connection node ND0 is higher than the threshold of the low level output of the first NAND gate NAND1, the first inverter INV1 outputs a high level, NM5 is turned on, the third feedback branch is turned on, and the potential of the first connection node ND1 is discharged to 0; The first three-input AND gate OR1 in the first feedback branch outputs a high level, PM1 is turned off, and charging of the first connection node ND1 stops, so that the potential of the first connection node is maintained at 0; The potential of the zeroth connection node ND0 is pulled up to 1 through PM0; The potential of the first output node V0 is 1, and the potential of the second output node V1 is 0; When the resistance of the resistor R0 is lower than the resistance of the resistor R1, the potential of the first connection node ND1 increases faster than the potential of the zeroth connection node ND0. When the potential of the first connection node ND1 is higher than the threshold of the low level output of the zeroth NAND gate NAND0, the zeroth inverter INV0 outputs a high level, NM4 is turned on, the second feedback branch is turned on, and the potential of the zeroth connection node ND0 is discharged to 0; The zeroth third input terminal AND gate OR0 in the first feedback branch outputs a high level, PM0 is turned off, and the charging of the zeroth connection node ND0 is stopped, so that the level of the zeroth connection node ND0 is maintained at 0; The potential of the first connection node is pulled up to 1 by PM1, the potential of the first output node V0 is 0, and the potential of the second output node V1 is 1.

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