Semiconductor device with heat dissipation pipe in sidewall interconnect structure, method of manufacturing the same, and electronic device

Abstract

Disclosed are a semiconductor device with a heat dissipation pipe in a sidewall interconnection structure and a manufacturing method thereof, and an electronic device including the semiconductor device. According to embodiments, the semiconductor device can include a carrier substrate having a first region and a second region adjacent to each other, semiconductor devices on the first region, and an interconnection structure on the second region. The interconnection structure can include an electrically isolating layer, interconnection line layers and via layers alternately arranged in a vertical direction in the electrically isolating layer, wherein interconnection lines are arranged in the interconnection line layers, vias are arranged in the via layers, and components of at least a part of the semiconductor devices that need to be electrically connected are in contact with the interconnection lines and / or the vias at a corresponding height in the interconnection structure in a lateral direction through respective sidewalls and thus electrically connected, and a heat dissipation pipe in the electrically isolating layer, wherein the heat dissipation pipe includes a laterally extending portion.

Description

[0001] This application is a divisional application of invention patent application 202110181463.2 entitled “Semiconductor device with heat dissipation channel in sidewall interconnect structure and manufacturing method and electronic device thereof”, filed on February 9, 2021. Technical Field

[0002] This disclosure relates to the field of semiconductors, and more specifically, to a semiconductor device with heat dissipation channels in a sidewall interconnect structure, a method of manufacturing the same, and an electronic device including such a semiconductor device. Background Technology

[0003] As semiconductor devices continue to miniaturize, it becomes increasingly difficult to manufacture high-density interconnect structures because it is difficult to reduce their size laterally. Furthermore, to increase integration, multiple layers of devices can be stacked. There is a need to be able to flexibly configure interconnects for such stacked devices.

[0004] In addition, heat dissipation becomes a problem in high-density devices. Summary of the Invention

[0005] In view of this, the purpose of this disclosure is at least in part to provide a semiconductor device with heat dissipation channels in a sidewall interconnect structure, a method for manufacturing the same, and an electronic device including such a semiconductor device.

[0006] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnect structure on the second region. The interconnect structure may include: an electrically insulating layer; a conductive structure in the electrically insulating layer, wherein at least a portion of the semiconductor device requiring electrical connection is laterally contacted and thus electrically connected to the conductive structure at a corresponding height in the interconnect structure; and a heat dissipation channel in the electrically insulating layer.

[0007] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: disposing a device stack on a carrier substrate; forming an interconnect structure laterally adjacent to the device stack in a region on the carrier substrate adjacent to the device stack, the interconnect structure including an electrical isolation layer and a conductive structure therein, wherein, during the formation of the interconnect structure, the height of the conductive structure in the interconnect structure is controlled such that at least a portion of the components in the device stack requiring electrical connection are laterally contacted and thus electrically connected to the conductive structure at a corresponding height in the interconnect structure; and forming a heat dissipation channel in the electrical isolation layer.

[0008] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned semiconductor device.

[0009] According to embodiments of this disclosure, for semiconductor devices, particularly vertical semiconductor devices, laterally adjacent sidewall interconnect structures can be provided. This can reduce photolithography steps in the manufacturing process and lower manufacturing costs. Manufacturing process steps can be shared between stacked (vertical) semiconductor devices, thereby reducing manufacturing costs. Furthermore, the three-dimensional structure allows for more space for interconnects between devices, resulting in low resistance and high bandwidth. Due to the presence of the sidewall interconnect structures, the semiconductor devices can have lead terminals, thus allowing the fabrication of the semiconductor devices to be separated from the fabrication of the metallization stack, thereby obtaining chips similar to field-programmable gate arrays (FPGAs). Heat dissipation channels can be embedded in the sidewall interconnect structures to enhance heat dissipation performance. Attached Figure Description

[0010] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0011] Figures 1 to 37 The illustration schematically shows some stages in the process of manufacturing a semiconductor device, particularly its interconnect structures, according to embodiments of the present disclosure.

[0012] Figures 2(a) (showing the positions of lines AA′ and BB′), 2(b), 3(a), 4(a), 5(a), 12, 16(a) (showing the positions of lines CC′ and DD′), and 17(a) are top views.

[0013] Figure 1 , 2(c) 5(b), 6 to 11, and 13 to 15 are cross-sectional views along line AA′.

[0014] Figure 3(b) , 4(b) 5(c) is a cross-sectional view along line BB′.

[0015] Figure 16(b) , 17(b) Figures 18(a), 19, 20(a), 21 to 27, 28(a), 34(b), and 36(b) are cross-sectional views along line CC′.

[0016] Figure 16(c) , 17(c) 18(b), 20(b), 28(b), 29 to 33, 34(a), 35, 36(a), and 37 are cross-sectional views along line DD′.

[0017] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0018] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0020] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0021] According to embodiments of this disclosure, a semiconductor device with a sidewall interconnect structure is provided. Here, a "sidewall" interconnect structure refers to an interconnect structure formed laterally (e.g., generally parallel to the substrate surface) of the devices to be interconnected, and thus interconnected with the devices (components to be interconnected, such as source / drain layers or source / drain regions formed therein, gate electrodes, etc.) via the sidewalls of the devices. Due to differences in height and / or orientation of the components to be interconnected, conductive structures interconnected thereto can be formed on the sidewalls of these components respectively.

[0022] For example, in planar devices such as planar metal-oxide-semiconductor field-effect transistors (MOSFETs), the gate electrode is disposed above the active region, so the gate electrode and the active region (especially the source / drain regions therein) can be at different heights (relative to the substrate on which the device is formed). Thus, the source / drain regions can be connected to conductive structures (e.g., interconnects and / or vias) at a first height in the interconnect structure, and the gate electrode can be connected to conductive structures at a second height in the interconnect structure above the first height. Alternatively, the source / drain regions can be located on opposite sides of the gate electrode (referred to as the "first side" and the "second side"). Thus, the source / drain regions can be connected to corresponding conductive structures in the interconnect structure on the first side and / or the second side. Typically, on the first and second sides of the device, the sidewalls of the gate electrode are recessed inward relative to the sidewalls of the source / drain regions, so the gate electrode can be connected to corresponding conductive structures in the interconnect structure on another third and / or fourth side.

[0023] Similarly, in vertical devices, the source / drain layers, or the source / drain regions formed therein, and the gate electrodes are stacked in the vertical direction and can therefore be at different heights. Thus, interconnection with vertical devices can be achieved through conductive structures at different heights in the interconnect structure.

[0024] For example, a vertical device may have an active region disposed vertically (e.g., in a direction substantially perpendicular to the substrate surface) on a substrate, such as including a first source / drain layer, a channel layer, and a second source / drain layer stacked in a vertical direction. The channel layer may be a vertical nanosheet or nanowire. Source / drain regions may be formed in the first and second source / drain layers, and channel regions may be formed in the channel layer. The channel layer may include a single-crystal semiconductor material. Of course, the source / drain layers may also include a single-crystal semiconductor material. For example, they may both be formed by epitaxial growth. The vertical device may also include a gate electrode disposed on the outer periphery of the channel layer, the gate electrode may surround the outer periphery of the channel layer. Therefore, the device according to embodiments of the present disclosure may be a gate-all-around device. According to embodiments of the present disclosure, the gate electrode may be self-aligned to the channel layer. For example, at least a portion of the gate electrode near the channel layer may be substantially coplanar with the channel layer, for example, said portion of the gate electrode may be substantially coplanar with the upper surface and / or lower surface of the channel layer.

[0025] Devices can be stacked on top of each other to form device stacks, increasing integration density. Multiple device stacks can be disposed on a substrate. Interconnect structures can be formed between these device stacks, thereby electrically connecting devices that need to be interconnected within or between these device stacks. More specifically, where the interconnect structure is adjacent to the component that needs to be electrically connected, the conductive structure (sidewalls) in the interconnect structure is exposed, and the component (sidewalls) is also exposed, so that they can contact each other and thus be electrically connected. An observable interface can exist between the interconnect structure and the device. To achieve interconnection in all directions, the interconnect structure can surround each device stack. Of course, some device stacks may only have interconnect structures at the sidewalls where electrical connection is required.

[0026] For ease of layout, the device stacks can be arranged along a first direction and a second direction intersecting (e.g., perpendicular to) the first direction to form an array. Interconnect structures can then extend between the device stacks along the first and second directions, and thus can be adjacent to the device stacks in both directions.

[0027] Interconnect structures may include conductive structures such as interconnects and vias disposed in an electrically insulating layer (e.g., a dielectric layer). For example, an interconnect structure may include alternating interconnect layers and via layers. Interconnect layers contain interconnects to achieve interconnection within the same layer, while via layers contain vias to achieve interconnection between different layers. Interconnects may include a body portion extending within the respective interconnect layer and a barrier layer surrounding the body portion.

[0028] To enhance heat dissipation performance, heat dissipation channels can be formed within the electrical isolation layer. These channels can extend from the inside of the isolation layer to the outside, dissipating internal heat to the external environment. The channels can connect to an external coolant source, guiding coolant, such as gas or liquid, through them for more efficient heat dissipation. The channels can take various shapes. For example, they can be open at both ends, such as a U-shaped channel, facilitating coolant flow.

[0029] Such a semiconductor device can be fabricated as follows. For example, a device stack can be disposed on a carrier substrate, wherein multiple semiconductor device layers are stacked. Devices (parts requiring electrical connection) in the device stack can be exposed at the sidewalls of the stack. Interconnect structures laterally adjacent to the device stack can be formed in a region on the carrier substrate adjacent to the device stack, thereby interconnecting with the devices (parts requiring electrical connection) exposed at the sidewalls of the device stack.

[0030] The conductive structures in the interconnect structure can be formed in layers to connect to devices at different heights. For example, interconnects can be formed in the region. A dielectric material can be further formed to bury the interconnects, and vias can be formed in the dielectric material. By repeating this operation multiple times, an interconnect structure comprising multiple layers of interconnects and multiple layers of vias is formed. The height at which the interconnects and vias are located can be controlled by the formation height of the dielectric material.

[0031] Heat dissipation channels can be embedded in interconnect structures. These channels can be formed by first drilling holes and then cutting through them. The holes can be relatively small to facilitate closure. Vertically extending channels can be formed by etching directly downwards through the holes. Because the holes combined with the vertically extending channels have a large aspect ratio, the holes can be closed. Laterally extending channels can be formed by selectively etching a selectively etchable structure (e.g., a dummy conductive structure) below the holes. The holes can also form a "bottleneck" relative to the laterally extending channels, thus closing the holes as well.

[0032] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, and conductive materials for forming interconnects and vias) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation.

[0033] Figures 1 to 37 The illustrations schematically depict some stages in the process of manufacturing a semiconductor device, particularly an interconnect structure therein, according to embodiments of the present disclosure.

[0034] like Figure 1 As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SO1) substrates, and compound semiconductor substrates such as SiGe substrates. The following description uses a bulk Si substrate, such as a silicon wafer, as an example.

[0035] On substrate 1001, a sacrificial layer 10031 for defining an isolation layer, a first source / drain layer 10051 for defining a lower source / drain region, a channel defining layer 10071 for defining a channel portion, and a second source / drain layer 10091 for defining an upper source / drain region can be formed, for example, by epitaxial growth. The first source / drain layer 10051, the channel defining layer 10071, and the second source / drain layer 10091 subsequently define the active region of the device, and they can be referred to as the "device layer", denoted as L1 in the figure.

[0036] The sacrificial layer 10031 can then be replaced with an isolation layer for isolating the device from the substrate, the thickness of which can correspond to the desired thickness of the isolation layer, for example, about 10 nm to 20 nm. Depending on the circuit design, the sacrificial layer 10031 may also be omitted. The first source / drain layer 10051 and the second source / drain layer 10091 can then form source / drain regions by doping (or in-situ doping during growth), the thickness of which can be, for example, about 20 nm to 50 nm. The channel defining layer 10071 can define the gate length, the thickness of which can correspond to the desired gate length, for example, about 15 nm to 100 nm. Consider the following process where the sacrificial layer 10031 is replaced with an isolation layer, in which the thickness of the channel defining layer 10071 should be greater than the thickness of the sacrificial layer 10031, which will be further explained below.

[0037] Each layer grown on substrate 1001 can be a single-crystal semiconductor layer, and there can be etching selectivity between adjacent layers. For example, sacrificial layer 10031 may include SiGe (the atomic percentage of Ge is, for example, about 10%-30%, preferably 15%), first source / drain layer 10051 may include Si, channel defining layer 10071 may include SiGe (the atomic percentage of Ge is, for example, about 10%-30%, preferably 15%), and second source / drain layer 10091 may include Si.

[0038] To increase integration density, multiple device layers can be configured. For example, device layers L2 and L3 can be sequentially configured on device layer L1 via epitaxial growth, with each device layer separated by sacrificial layers 10032 and 10033 used to define isolation layers. Depending on the circuit design, some device layers may not have isolation layers. Similarly, device layer L2 may have a first source / drain layer 10052, a channel defining layer 10072, and a second source / drain layer 10092, and device layer L3 may have a first source / drain layer 10053, a channel defining layer 10073, and a second source / drain layer 10093. The corresponding layers in each device layer may have the same or similar thickness and / or material, or they may have different thicknesses and / or materials. In particular, the thickness of the channel defining layer in different device layers may be different, thereby adjusting the electrical characteristics of the resulting device. Here, for ease of description only, it is assumed that each device layer L1, L2, and L3 has the same configuration.

[0039] On these layers formed on the substrate 1001, a hard mask layer 1011 can be disposed to facilitate patterning. For example, the hard mask layer 1011 may include a nitride (e.g., silicon nitride) with a thickness of about 50 nm to 200 nm.

[0040] Next, active regions can be defined within these device layers.

[0041] For example, as shown in FIG2(a), photoresist 1013 can be formed on hard mask layer 1011 and patterned into the shape of an active region by photolithography. In the example of FIG2(a), photoresist 1013 is patterned as an array arranged along the x and y directions, with each element in the array being approximately rectangular (used to define the active region of a single device, which will be columnar), for example, a rectangle with the short side along the x direction and the long side along the y direction. Of course, this disclosure is not limited to this. Photoresist 1013 can be patterned into various suitable shapes. For example, as shown in FIG2(b), to avoid the columnar active region from collapsing during manufacturing, the elements in the array can be zigzag or meandering. Hereinafter, for convenience, the case shown in FIG2(a) will be described as an example.

[0042] The photoresist 1013, configured as an etching mask, sequentially etches the layers on the substrate 1001 using selective etching such as reactive ion etching (RIE). The RIE can be performed in a generally vertical direction (e.g., perpendicular to the substrate surface) and can stop at the surface of the substrate 1001. This leaves an array of pillars on the substrate 1001, as shown in Figure 2(c). Each pillar defines the active region of multiple (in this example, three) vertically stacked devices. In a top view, each pillar can be rectangular as shown in Figure 2(a), or zigzag or meandering as shown in Figure 2(b). The photoresist 1013 can then be removed.

[0043] Based on these active regions, the following device fabrication can be performed. Considering process requirements such as control of channel layer morphology, a shielding material can be formed around the pillar. During fabrication, one or more sides of the active region can be exposed for processing, while the other one or more sides are shielded by the shielding material. The shielding material can also support slender pillars during fabrication, especially in processes where sacrificial layers are replaced with isolation layers, to prevent collapse.

[0044] For example, such as Figure 3(a) and 3(b) As shown, a masking material (see 1017 in FIG. 4(a)) can be formed, for example, by deposition on substrate 1001. Considering etching selectivity (e.g., relative to a hard mask layer 1011, for example, nitride, and a subsequently formed position-retaining layer, for example, oxide (e.g., silicon oxide), the masking material 1017 can include SiC. The deposited masking material 1017 can be planarized, such as by chemical mechanical polishing (CMP), which can stop at the hard mask layer 1011. Thus, each pillar is surrounded by the masking material 1017.

[0045] Here, to control the length of the subsequently formed trench layer in the y-direction and the morphology of its ends in the y-direction, the opposite sides of the active region in the y-direction can be processed first. Therefore, these opposite sides need to be exposed. For this purpose, photoresist 1015 can be formed on the hard mask layer 1011 and the masking material 1017, and patterned to expose at least the opposite sides of each pillar in the y-direction. For example, the photoresist 1015 may include openings extending in the x-direction between each pillar. The photoresist 1015, patterned in this way, serves as an etching mask, and the masking material 1017 is etched by selective etching such as RIE. The RIE can be performed in a generally vertical direction and can stop at the surface of the substrate 1001. Thus, the sidewalls of each pillar in the y-direction are exposed (see FIG. 3(b)), while the sidewalls in the x-direction are at least partially (depending on the size of the openings in the photoresist 1015 in the y-direction) masked by the masking material 1017 (see FIG. 4(a)). Afterwards, the photoresist 1015 can be removed.

[0046] To form a self-aligned gate stack, the gap (which may be called the "gate gap") used to form the gate stack can be defined based on the channel defining layer. For example, as Figure 4(a) and 4(b) As shown, the exposed sidewalls of the channel defining layers 10071, 10072, and 10073 can be selectively etched to make them (relative to the upper and lower source / drain layers) relatively recessed. Atomic layer etching (ALE) can be used here to achieve good etching control. Thus, for each device layer L1, L2, and L3, a gap (i.e., a gate gap) is defined between the upper and lower source / drain layers, which was originally occupied by the channel defining layers, thereby self-aligning with the channel defining layers. The gate gaps on opposite sides of the channel defining layers in the y-direction can have approximately the same dimension (the height in the vertical direction corresponds to the thickness of the channel defining layers, and the width in the y-direction can be approximately equal to each other).

[0047] The etching formula can achieve substantially the same etching degree for each channel defining layer 10071, 10072, and 10073, so that after etching, the sidewalls of each channel defining layer 10071, 10072, and 10073 can still be substantially aligned or substantially coplanar in the vertical direction. In addition, the sacrificial layers 10031, 10032, and 10033, which are also SiGe as the channel defining layers, can also be etched to be relatively recessed, thus forming corresponding gaps (which can be called "isolation gaps").

[0048] To prevent residual material from affecting the formation of the gate stack during subsequent processing, a first position holding layer 1019 (also referred to as a "sacrificial gate") can be filled into the formed gate gaps. For example, the first position holding layer 1019, such as an oxide, can be filled into these gate gaps by deposition followed by etch-back (e.g., RIE). Similarly, isolation gaps are also filled with the first position holding layer 1019.

[0049] Then, the active region on opposite sides in the x-direction can be processed. Similarly, a masking material can first be formed and patterned to expose the sides to be processed. For example, as... Figure 5(a) , 5(b) As shown in 5(c), a masking material can be formed on the substrate 1001 by, for example, a deposition followed by planarization process. For the convenience of subsequent etching processes, the masking material formed here can include the same material, such as SiC, as the previous masking material 1017, and therefore can be integrally shown as 1017′ with the previous masking material 1017. In this way, the masking material 1017′ surrounds each pillar.

[0050] When exposing the opposite sides in the x-direction, the two sides can be treated separately, taking into account the support function required when replacing the isolation layer.

[0051] For example, a photoresist 1021 can be formed and patterned to expose one side of each pillar in the x-direction. For example, the photoresist 1021 may include openings extending in the y-direction between each pair of adjacent pillars. The photoresist 1021, patterned in this way, serves as an etching mask, and a masking material 1017' is etched by selective etching such as RIE. The RIE can be performed in a generally vertical direction and can stop at the surface of the substrate 1001. Thus, one sidewall of each pillar in the x-direction is exposed, while the sidewall in the y-direction is at least partially (depending on the size of the opening in the photoresist 1021 in the x-direction) and the other sidewall in the x-direction is masked by the masking material 1017'. The photoresist 1021 can then be removed.

[0052] For the currently exposed sidewalls of each column, it is possible to perform [further actions]. Figure 4(a) and 4(b) Similar processing is used to define the gate gap. For example, as... Figure 6 As shown, the exposed sidewalls of the channel defining layers 10071, 10072, and 10073 can be selectively etched to make them relatively recessed (relative to the upper and lower source / drain layers). Similarly, ALE (Alternating Edge Etching) can be used. This creates gate gaps that are self-aligned to the channel defining layers. Subsequently, a position-retention layer can be formed to fill these gate gaps.

[0053] Here, similarly, the sacrificial layers 10031, 10032, and 10033 will also be relatively recessed, thus forming an isolation gap. In the above combination... Figure 4(a) and 4(b) In the described process, the position-preserving layer also fills the isolation gaps, which will affect subsequent replacement of the sacrificial layer. To avoid the position-preserving layer filling the isolation gaps, the isolation gaps can be filled first.

[0054] For example, a filler layer 1023 can be formed by epitaxial growth. The growth thickness of the filler layer 1023 can be greater than half the thickness of each sacrificial layer 10031, 10032, 10033, thereby completely filling each isolation gap. However, the filler layer 1023 should not completely fill the gate gap (where a position holding layer, or sacrificial gate, should be formed). Therefore, on the one hand, as mentioned above, the thickness of the channel defining layer should be greater than the thickness of the sacrificial layer (the growth thickness of the filler layer 1023 can be less than half the thickness of the channel defining layer). On the other hand, when forming the gate gap, the etching depth of the channel defining layer is preferably greater than half the thickness of the sacrificial layer (the growth thickness of the filler layer 1023 can be less than the etching depth of the channel defining layer). Thus, the filler layer 1023 can fill each isolation gap without completely filling each gate gap, such as... Figure 6 As shown.

[0055] The material of the filler layer 1023 can have similar or substantially the same etching selectivity as the material of the sacrificial layer, so that it can be subsequently removed together with the same etching formulation. For example, the filler layer 1023 may comprise SiGe, with the atomic percentage of Ge being, for example, about 10%-40%.

[0056] After that, as Figure 7 As shown, a filler layer 1023 of a certain thickness can be removed by selective etching. For example, the removal thickness can be substantially equal to or slightly greater than the growth thickness of the filler layer 1023. Thus, the filler layer 1023 can be removed from the gate gap and remain in the isolation gap. ALE can be used to effectively control the removal thickness.

[0057] Then, as Figure 8 As shown, a second position retention layer 1019' can be formed as described above. The material of the second position retention layer 1019' can have similar or substantially the same etching selectivity as the material of the first position retention layer 1019, so that it can subsequently be removed together with the same etching formulation. For example, the second position retention layer 1019' can include an oxide.

[0058] In the above embodiments, the first position holding layer 1019 and the second position holding layer 1019′ are formed in different steps. This helps to control the length of the subsequently grown channel layer in the y-direction and the morphology of its ends in the y-direction. However, this disclosure is not limited thereto. The first position holding layer 1019 and the second position holding layer 1019′ can also be formed in the same steps, particularly when the channel layer is formed using the channel defining layer itself. For example, the opposite sides of each channel defining layer in the y-direction and one side in the x-direction (the other side in the x-direction can be masked by a masking material) can be selectively etched to make them relatively recessed, and the position holding layer is formed in the resulting gap.

[0059] Currently, each channel defining layer is surrounded by a masking material, a position holding layer, and a source / drain layer, while the sidewalls of the filler layer 1023 are exposed. The filler layer 1023 and the sacrificial layer exposed as a result of its removal can be removed by selective etching. The etching can stop at the masking material 1017′. In this way, the sacrificial layer is removed between the device layers (while the device layers are still held by the masking material 1017′). In the voids left by the removal of the sacrificial layer, a dielectric material can be filled to form an isolation layer by a process such as deposition (e.g., chemical vapor deposition, atomic layer deposition (ALD), etc.) followed by etching back (e.g., RIE). Suitable dielectric materials, such as oxides, nitrides, SiC, or combinations thereof, can be selected for various purposes, such as optimizing isolation reliability, leakage current, or capacitance. Thus, the device layers can be isolated from each other. Here, for ease of description only, the filling dielectric material may include SiC, and is therefore integrally shown as 1017″ along with the masking material 1017′.

[0060] Next, a channel layer can be formed.

[0061] For example, such as Figure 9 As shown, the position holding layer 1019' can be removed by selective etching. Here, the position holding layer 1019 can be retained because it is covered by the masking material 1017″. Thus, the gate gap occupied by the position holding layer 1019' is released. In the released gate gap, a semiconductor layer can be formed by selective epitaxial growth. This semiconductor layer can be grown along the surfaces of the channel defining layer and the source / drain layer. Hereinafter, for the sake of illustration and description only, the portion of the semiconductor layer located on the sidewall of the channel defining layer is shown separately and referred to as the channel layer 1025 (the channel portion will be mainly formed in this portion), while the portion of the semiconductor layer located on the surface of the source / drain layer can be shown integrally with the source / drain layer and referred to as the source / drain layer (where the source / drain region will be formed) (see See Figure 10(dashed line in the diagram). The channel layer 1025 may be formed on a sidewall of the channel defining layer in the x-direction (the sidewall originally covered by the position holding layer 1019'). The channel layers 1025 in each device layer may be substantially aligned or substantially coplanar in the vertical direction.

[0062] In this embodiment, to ensure that both sides of the channel layer 1025 have substantially the same gate length, the channel defining layer and the source / drain layer can be etched back to a certain thickness before the semiconductor layer is grown. The growth thickness of the semiconductor layer can be selected to be approximately equal to the etched-back thickness of the source / drain layer, so that the height of the gate gap after the semiconductor layer is grown can be substantially the same as the thickness of the channel defining layer. The material of the channel layer 1025 can be selected to achieve the desired device performance. For example, the channel layer 1025 can include the same material as the source / drain layer, such as Si, or it can include a different material, such as SiGe.

[0063] In this embodiment, a channel layer 1025 is additionally grown. This helps control the thickness of the channel layer 1025, and subsequent selective etching is also easier to control. Thus, precise control over both the channel layer thickness and the gate length can be achieved without the need for photolithography and selective ALE. However, this disclosure is not limited thereto. For example, the channel portion can be formed directly using the channel defining layer.

[0064] Next, we can process the other side of each cylinder in the x-direction.

[0065] For example, such as Figure 10 As shown, another masking material 1027 can be formed on substrate 1001 through a process such as deposition followed by planarization. The other masking material 1027 can fill the gaps between masking materials 1017″ on substrate 1001. To remove the masking material 1017″ and expose the side requiring processing, the other masking material 1027 can comprise a material with etching selectivity relative to the masking material 1017″, such as an oxide. The masking material 1017″ can then be selectively etched, such as by re-etching (RIE). The RIE can be performed in a generally vertical direction and can stop at substrate 1001. Therefore, except for the portion of the masking material 1017″ that is below the hard mask layer (forming an isolation layer, shown as 1017″′), the remaining portion of the masking material 1017″ can be removed. In this way, the other side of the channel defining layer is exposed in the x direction (although the masking material 1017″ is also removed on the other two sides in the y direction, the opposite sides of the channel layer 1025 in the y direction can be masked due to the presence of the position holding layer 1019).

[0066] The gate gap can also be defined on the side currently exposed in the x-direction. For example, as Figure 11As shown, channel defining layers 10071, 10072, and 10073 can be selectively etched. Similarly, ALE (Alternating Electrode Etching) can be used. Here, the etching of the channel defining layers can stop at channel layer 1025, leaving channel layer 1025 between the upper and lower source / drain layers. This forms the gate gap. The gate gaps on opposite sides of channel layer 1025 in the x-direction can have approximately the same dimensions (the height in the vertical direction corresponds to the thickness of the channel defining layer, and the width in the x-direction can be approximately equal to each other).

[0067] Without growing a separate channel layer 1025, but instead forming the channel portion using the channel defining layers 10071, 10072, and 10073 themselves, gate gaps can be similarly formed around the channel defining layers 10071, 10072, and 10073. For example, the channel defining layers 10071, 10072, and 10073 can be selectively etched, such as by ALE, leaving residual portions similar to the channel layer 1025.

[0068] Similarly, a third position holding layer 1027″ can be formed in the gate gap thus formed. For example, the third position holding layer 1027″ can be formed by depositing and then etching back (e.g., RIE) oxide. The RIE can be performed in a generally vertical direction and can stop at the surface of the substrate 1001.

[0069] like Figure 11 As shown, a plurality of pillars arranged in an array are formed on substrate 1001 (e.g., as shown in FIG. 2(a) or 2(b)). Multiple device layers are stacked in each pillar, and each device layer may include a first source / drain layer and a second source / drain layer, and a channel layer between them. Gate gaps are formed around the channel layers, and the gate gaps are occupied by a position holding layer. The gate gaps are self-aligned to the channel layers. The device layers are isolated from each other by isolation layers.

[0070] Currently, the sidewalls of each source / drain layer are exposed. These exposed sidewalls can be used to dope the source / drain layers to form source / drain regions.

[0071] exist Figure 11 In the illustrated embodiment, during the etch-back process when forming the third position holding layer 1027″, the hard mask layer 1011 serves as a mask. Thus, the opposing sidewalls of each source / drain layer in each of the x and y directions are exposed, allowing doping to occur through each of these sidewalls. According to another embodiment of this disclosure, as... Figure 12As shown, during the etching-back process when forming the third position holding layer 1027″, photoresist 1029 can also be formed. The photoresist 1029 can be patterned to block the relative sidewalls of each pillar in the y-direction. Thus, the formed third position holding layer 1027″ not only occupies the gate gap but also blocks the relative sidewalls of each pillar in the y-direction. In this way, doping can occur through the sidewalls of each source / drain layer in the x-direction, thereby suppressing changes in doping characteristics caused by the difference in width between the gate gaps on opposite sides in the x-direction and the gate gaps on opposite sides in the y-direction.

[0072] To perform doping, such as Figure 13 As shown, a dopant source layer can be formed on the surface of each pillar, for example, by deposition. The dopant source layer can be formed in a generally conformal manner. Here, the example of forming two types (n-type and p-type) devices is described, thus requiring both n-type and p-type doping. For example, an n-type dopant source layer 1031 can be formed first and patterned to cover the pillar in which the n-type device is to be formed. Then, a p-type dopant source layer 1035 can be formed. To prevent interdiffusion between the n-type dopant source layer 1031 and the p-type dopant source layer 1035, a diffusion barrier layer 1033 can be formed between them. For example, the diffusion barrier layer 1033 can be formed on the n-type dopant source layer 1031 and can be patterned together with the n-type dopant source layer 1031. The n-type dopant source layer 1031 can include an n-type dopant, such as a P or As-doped oxide, with a dopant concentration of about 0.1% to 10% and a thickness of about 1 nm to 10 nm. Similarly, the p-type doped source layer 1035 may include a p-type dopant, such as a B-doped oxide, with a dopant concentration of about 0.1% to 10% and a thickness of about 1 nm to 10 nm. The diffusion barrier layer 1033 may include a nitride with a thickness of about 2 nm to 10 nm.

[0073] Then, as Figure 14 As shown, dopant can be driven from the doped source layer into the source / drain layer through, for example, annealing, thereby forming source / drain regions in the source / drain layer. Here, n-type source / drain region S / D1 and p-type source / drain region S / D2 are shown. The substrate 1001 may also be doped. A position retention layer prevents dopant from directly entering the channel layer 1025. Of course, a small amount of dopant may be present in the channel layer 1025 near the end of the source / drain layer, having entered through the source / drain layer. Subsequently, the n-type doped source layer 1031, the p-type doped source layer 1035, and the diffusion barrier layer 1033 can be removed.

[0074] In this example, the source / drain layers in each pillar are doped with the same conductivity type. However, this disclosure is not limited to this. For example, with appropriate design of the dopant source layers, the source / drain layers in different device layers within each pillar can be doped with different conductivity types.

[0075] In this embodiment, the surfaces of the source / drain layers can be silicided to reduce contact resistance. For example, a metal such as NiPt can be formed on the surface of each pillar and annealed to react with Si in the source / drain layers, thereby generating a metal silicide such as NiPtSi. Unreacted metal can then be removed.

[0076] Subsequently, an alternative gate process can be performed to replace the position holding layer with a gate stack. For example, such as... Figure 15 As shown, the position retention layers 1019 and 1027″ can be removed by selective etching, thereby releasing the gate gap. The gate dielectric layer 1037 can be formed in a generally conformal manner by, for example, deposition or ALD. On the gate dielectric layer 1037, a gate conductor layer can be formed by, for example, deposition or ALD. Here, the gate conductor layer 10391, which is formed first in an n-type device, is described as an example. The deposited gate conductor layer 10391 can fill the gate gap. The portion of the gate conductor layer 10391 outside the gate gap can be removed by etching back, such as RIE, so that the gate conductor layer 10391 can remain in the gate gap. Then, a photoresist can be used, for example, The n-type device is covered, while the p-type device is exposed. The gate conductor layer 10391 formed in the gate gap of the p-type device can be removed by selective etching to release its gate gap. The gate conductor layer 10392 of the p-type device can be formed in the gate gap of the p-type device in a similar manner. The gate dielectric layer 1037 may include a high-k gate dielectric such as HfO2, and the gate conductor layers 10391 and 10392 may include metal gate conductors with corresponding work functions. Here, the n-type and p-type devices have the same gate dielectric layer 1037, but this disclosure is not limited thereto. For example, they may have different gate dielectric layers. Furthermore, the order in which the gate conductor layers are formed may be interchanged.

[0077] In this way, vertical devices are formed in each device layer of each pillar. Each vertical device may include a channel layer 1025 and a first source / drain layer and a second source / drain layer located above and below the channel layer 1025. A gate stack (a stack of gate dielectric layers and gate conductor layers) may surround and be self-aligned with the channel layer 1025. Each pillar may be referred to as a device stack. Between the device stacks, the substrate 1001 is recessed relative to each other, forming a trench.

[0078] Currently, the sidewalls of components requiring electrical connection in each device, such as the gate conductor layer (also known as the gate electrode) and the source / drain regions (or the silicide formed on their surfaces), are exposed. Therefore, interconnect structures can be formed that are laterally adjacent to each device to interconnect the devices in the stack. Since the interconnect structure is laterally adjacent to the devices and contacts the sidewalls of the components requiring electrical connection within the devices, it can be called a sidewall interconnect structure.

[0079] Furthermore, when forming the interconnect structure, to avoid unwanted short circuits, conductive structures at different heights can be connected to the device on different sides. For example, a first component of the device requiring electrical connection at a certain height can be connected to a conductive structure in the interconnect structure on a first side, while a second component adjacent to the first component in the vertical direction requiring electrical connection can be connected to a conductive structure in the interconnect structure on a second side different from the first side (e.g., opposite to the first side). Additionally, the sidewall of the first component on the second side can be covered by an isolation layer, and the sidewall of the second component on the first side can be covered by an isolation layer to prevent short circuits.

[0080] An embodiment of forming such an isolation layer will be described below.

[0081] For example, such as Figure 16(a) , 16(b) As shown in Figure 16(c), photoresist 1041 can be formed on substrate 1001 and patterned to shield one side of each device stack (the upper side in the y-direction in Figure 16(a)) while exposing the other side of each device stack (the lower side in the y-direction in Figure 16(a)). On the exposed side of each device stack, the gate conductor layer can be selectively etched to create a relative recess to a certain depth, for example, about 5 nm to 20 nm, to release some gate gaps. A self-aligned isolation layer can then be formed in these gate gaps. Afterward, photoresist 1041 can be removed.

[0082] Then, as Figure 17(a) , 17(b) As shown in Figure 17(c), photoresist 1043 can be formed on substrate 1001 and patterned to shield one side of each device stack (the lower side in the y-direction in Figure 17(a)) while exposing the other side of each device stack (the upper side in the y-direction in Figure 17(a)). On the exposed side of each device stack, the source / drain layers can be selectively etched to create a relative recess of a certain depth, for example, about 5nm-20nm (which can be the same depth as the previously released gate gap so that the subsequently filled isolation layer can have approximately the same thickness), to free up some space. A self-aligned isolation layer can then be formed in these spaces. Afterward, photoresist 1043 can be removed.

[0083] Therefore, in each device stack, the source / drain layers protrude relatively on one side, while the gate conductor layer protrudes relatively on the other side. Isolation layers can be formed within their respective relative recesses. For example, as... Figure 18(a) and 18(b) As shown, the isolation layer 1045 can be filled in these recesses through a deposition followed by etching back. Considering the etching selectivity with the subsequently formed interlayer dielectric layer, the isolation layer 1045 may include a dielectric material such as SiC. The isolation layers 1045 in different device layers may be substantially aligned or substantially coplanar in the vertical direction.

[0084] Next, the interconnect structure can be fabricated. When fabricating the interconnect lines in the interconnect structure, to avoid the difficulties of etching trenches and then filling them with conductive materials such as metals in conventional processes, according to embodiments of this disclosure, the conductive structure can be formed first, and then the dielectric material can be filled in.

[0085] For the current device stack-up, the bottom layer is the first source / drain layer, or source / drain region, of device layer L1. A conductive structure for this first source / drain layer can be formed first.

[0086] Considering the electrical isolation between the device and substrate 1001 and the height matching with the first source / drain layer, an electrical isolation layer of a certain thickness can be formed in the trenches between the device stacks. This allows the conductive structures subsequently formed on this electrical isolation layer to be at a height corresponding to the first source / drain layer, enabling lateral adjacency. Furthermore, it is desirable that the formed electrical isolation layer exposes the sidewalls of each device stack to avoid affecting the electrical contact with the sidewall interconnect structures.

[0087] For example, such an electrical isolation layer can be formed in the following manner. Figure 19 As shown, a preliminary insulating layer 1047 can be formed by depositing a dielectric material such as an oxide. To form the electrical insulating layer as described above, the preliminary insulating layer 1047 can be formed with a thicker lateral portion and a thinner vertical portion. This can be achieved, for example, by high-density plasma (HDP) deposition. Here, the thickness of the thicker portion of the preliminary insulating layer 1047 can be approximately 20 nm to 150 nm.

[0088] Then, as Figure 20(a) and 20(b) As shown, the pre-isolated isolation layer 1047 can be isotropically etched, and the etching thickness can remove the vertically extending portion of the pre-isolated isolation layer 1047, but leave its laterally extending portion. For example, the thickness of the left portion can be about 15nm-100nm. Thus, the pre-isolated isolation layer 1047 can be left in the trench between each isolation device (or a portion can be left on the top of each device stack, which will not affect the subsequent process), forming the electrical isolation layer 1047′.

[0089] Next, a conductive structure can be fabricated on the electrical isolation layer 1047′.

[0090] For example, such as Figure 21 As shown, a conductive barrier layer 1049 and a conductive host layer 1051 can be sequentially formed by deposition in a generally conformal manner. The conductive barrier layer 1049 prevents the conductive host layer 1051 from diffusing to the surroundings, and may include conductive nitrides such as TiN and TaN. The conductive host layer 1051 can be used to realize electrical connections between devices, and may include metals such as tungsten (W), cobalt (Co), rubidium (Ru), copper (Cu), aluminum (Al), and nickel (Ni). The formed conductive barrier layer 1049 and conductive host layer 1051 can contact and connect with the first source / drain layer of the lowest device in each device stack.

[0091] The conductive barrier layer 1049 and the conductive body layer 1051 can then be patterned as a conductive structure for the first source / drain layer of the lowest device in each device stack. In this example, to leave the portion of the conductive barrier layer 1049 and the conductive body layer 1051 at the bottom of the trench, a mask can be formed to cover this portion.

[0092] This type of mask can be achieved, for example, through the combination of the above. Figures 19 to 20(b) The described method is used.

[0093] Or, such as Figure 22 As shown, a mask layer 1053 and a patterning aid layer 1055 can be sequentially formed by deposition in a generally conformal manner. For example, considering etching selectivity, the mask layer 1053 may include an oxide with a thickness of about 1 nm to 5 nm; considering the convenience of local modification (changing etching selectivity), the patterning aid layer 1055 may include polycrystalline silicon or amorphous silicon with a thickness of about 5 nm to 20 nm. The etching selectivity (relative to the vertical extension) of the patterning aid layer 1055 can be changed by implanting impurities such as B into the horizontal extension 1055a of the patterning aid layer 1055 via ion implantation along the vertical direction and annealing, for example, at about 550 °C to about 900 °C. Then, as... Figure 23 As shown, the undoped portion of the patterning auxiliary layer 1055 can be removed by selective etching, such as wet etching using TMAH, leaving the doped portion 1055a. The doped portion 1055a can then be used as an etching mask to selectively etch the mask layer 1053 to obtain the desired mask shape. ALE can be used to effectively control the etching amount. Subsequently, the doped portion 1055a can be removed by selective etching such as RIE.

[0094] like Figure 24As shown, mask layer 1053 can be used as an etching mask to isotropically etch the conductive barrier layer 1049 and the conductive host layer 1051, so that they can remain at the bottom of the trench (and part of them remain on the top surface of each device stack, which will be removed in subsequent processes). Here, ALE can be used to achieve good etching control. Afterwards, mask layer 1053 can be removed by selective etching such as RIE.

[0095] In this example, the doped portion 1055a is removed before the conductive pattern is patterned. However, this disclosure is not limited thereto. For example, the doped portion 1055a may be removed after the conductive pattern is patterned.

[0096] The top surface of the conductive host layer 1051 is currently exposed. To prevent its diffusion, a barrier layer can be formed on its top surface. For example, such as... Figure 25 As shown, the conductive barrier layer 1057 can be formed by deposition in a generally conformal manner. The conductive barrier layer 1057 may comprise the same or different materials as the conductive barrier layer 1049. Then, the bonding described above can be utilized. Figures 22 to 24 The method described involves forming a mask layer 1059, such as an oxide layer, and isotropically etching a conductive barrier layer 1057 using the mask layer 1059, so that it remains at the bottom of the trench (and a portion remains on the top surface of each device stack, which will be removed in subsequent processes).

[0097] Next, the conductive main layer 1051, which is enclosed by conductive barrier layers 1049 and 1057, can be patterned. Pattern positioning can be aided by alignment marks on device layer L1. For example, as... Figure 26 As shown, a mask layer 1061 for patterning conductive structures can be formed within a trench. For example, the mask layer 1061 can be formed by spin-coating and etching back the photoresist to thin it for easier exposure, leaving the photoresist in the trench, and then patterning the photoresist (e.g., photolithography or electron beam exposure) with the aid of alignment marks on the device layer L1. The minimum gap Wt of each opening in the mask layer 1061 can remain substantially consistent. This contributes to the consistency of subsequent processes. To ensure this consistency, a portion of the conductive structure defined by the patterned photoresist can be a dummy conductive structure.

[0098] The mask layer 1061 can be used as an etching mask to selectively etch, such as RIE, the mask layer 1059, the conductive barrier layer 1057, the conductive host layer 1051, and the conductive barrier layer 1049 sequentially. RIE can be performed in a generally vertical direction and can stop at the electrical isolation layer 1047″ (or slightly into the electrical isolation layer 1047′ to ensure the cutting off of each conductive layer). This creates laterally extending conductive structures at the bottom of the trench at a height corresponding to the first source / drain layer of device layer L1. At least a portion of these conductive structures contacts and is thus electrically connected to the first source / drain layer of the lowest layer in each device stack. Furthermore, due to the etching step, residues from previous processes at the top surface of each device stack can be removed. Afterward, the mask layer 1061 can be removed.

[0099] Due to this etching, part of the sidewalls of the conductive host layer 1051 are exposed. To prevent diffusion, a conductive barrier layer can be formed on the sidewalls of the conductive host layer 1051. For example, such as... Figure 27 As shown, a conductive barrier layer 1063 can be formed by deposition in a generally conformal manner, and its lateral extensions can be removed by anisotropic etching, such as vertical RIE, leaving its vertical extensions, thereby forming a sidewall on the sidewall of the conductive host layer 1051. The conductive barrier layer 1063 may include the same or different material as the conductive barrier layers 1049 and 1057. To maintain consistency, the conductive barrier layers 1049, 1057, and 1063 may have the same material and substantially the same film thickness.

[0100] The conductive barrier layer 1063 in the form of a sidewall only needs to cover the conductive main layer 1051. Therefore, such as... Figure 28(a) and 28(b) As shown, a dielectric layer 1065 (e.g., oxide) can be filled within the trench, particularly between the gaps in the conductive structures. The dielectric layer 1065 can be formed by deposition followed by etching back. The thickness of the deposited dielectric layer 1065 can be greater than Wt / 2, thereby completely filling the gaps between the conductive structures.

[0101] Since the dielectric layer 1065 is located inside the trench, it is difficult to planarize it using methods such as CMP. To ensure that the top surface of the dielectric layer 1065 has a certain degree of flatness to facilitate subsequent photolithography, the conductive structure may include some dummy patterns (i.e., interconnects and / or vias that do not actually achieve electrical connections), so that the minimum gap can remain substantially consistent as described above. Additionally, the deposited film thickness can be greater than half of this minimum gap. To better control the flatness of the dielectric layer 1065, its deposition can be performed using atomic layer deposition (ALD), and its etching back can be performed using atomic layer etching (ALE).

[0102] Then, the exposed conductive barrier layer 1063 portion of the dielectric layer 1065 can be removed by selective etching, such as RIE. Thus, the conductive host layer 1051 is encapsulated by the conductive barrier layers 1049, 1057, and 1063. The resulting conductive structure has an interface or boundary with the device stack (e.g., components requiring connection, such as source / drain regions, gate electrodes, etc.) due to differences in materials, misalignment in vertical or horizontal positions, etc. Additionally, an interface or boundary may also exist between the dielectric layer 1065 and the device stack (e.g., interlayer dielectric layers therein). The dielectric layer 1065 also forms part of an electrically insulating layer, and is hereinafter referred to as the electrically insulating layer.

[0103] This forms a single conductive layer. Multiple conductive layers can be formed sequentially in the same or similar manner.

[0104] Next, a conductive structure can be formed, for example, for the gate conductor layer of the lowest device in the device stack. The conductive structure to be formed for the gate conductor layer should be located at a height corresponding to the gate conductor layer. Therefore, as... Figure 29 As shown, it can be achieved through, for example, the combination described above. Figures 19 to 20(b) The method involves depositing and then etching back a dielectric material, such as an oxide, to raise the top surface of the electrical isolation layer 1065 to a height corresponding to the gate conductor layer. The raised electrical isolation layer is labeled 1065′ in the figure. It should be noted that although the electrical isolation layer 1065′ is shown as a single unit here, interfaces or boundaries may exist between layers formed sequentially. Residue on the top surface of each device stack can also be thickened (this thickening is not shown in the figure for convenience).

[0105] Here, the height of the top surface of the electrical isolation layer 1065' is such that: on the one hand, the sidewalls of the first source / drain layer exposed in the trench are shielded to prevent the conductive structure subsequently formed on the top surface of the electrical isolation layer 1065' from contacting the first source / drain layer; on the other hand, the sidewalls of the gate conductor layer can be exposed in the trench, so that the conductive structure subsequently formed on the top surface of the electrical isolation layer 1065' can contact the gate conductor layer.

[0106] To enhance heat dissipation performance, heat dissipation channels can be formed within the electrical isolation layer. Here, a U-shaped heat dissipation channel is described as an example, but this disclosure is not limited to this shape. For example, the heat dissipation channel can also be formed in other shapes, such as a vertical straight line or an L-shape entering the electrical isolation layer.

[0107] like Figure 30 As shown, a hole H can be formed in the electrical isolation layer 1065' by etching, such as RIE. Subsequently, a laterally extending channel can be excavated in the electrical isolation layer through this hole H. In addition, the hole H can be formed to be relatively narrow so that it can be subsequently closed without substantially affecting the laterally extending channel.

[0108] like Figure 31 As shown, conductive structures accessible through via hole H can be removed by selective etching, such as wet etching. Specifically, the conductive barrier layers and conductive host layers within the conductive structures can be selectively etched. Due to the selective etching, the electrical isolation layer 1065′ remains largely unaffected, and thus, lateral extension channels corresponding to the etched conductive structures can be formed therein. That is, in the combination described above... Figures 21 to 28(b) When forming the conductive structure, a dummy conductive structure for defining a laterally extending channel can be formed. The hole H can be formed on the dummy conductive structure and can be narrower than the dummy conductive structure (and the resulting laterally extending channel) in the lateral direction.

[0109] Then, as Figure 32 As shown, a plug 1069 can be formed in the hole H to seal it. For example, plug material can be deposited by CVD, and the deposition thickness of the plug material can be controlled to be greater than half the width of the hole H, so that the plug material can completely fill the hole H. Furthermore, since the hole is relatively narrow relative to the lateral extension channel, it creates a bottleneck effect during deposition, inhibiting the insertion of plug material into the lateral extension channel, thus leaving the lateral extension channel essentially empty or with very little plug material. The plug material can be etch-selective relative to the electrical isolation layer 1065′, for example, a nitride. The deposited plug material can be selectively etched (e.g., the etching depth is approximately the same as the deposition thickness) to remain within the hole H, forming the plug 1069. For better control of the etching depth, ALE can be used.

[0110] This example shows only a single hole H and the resulting single lateral extension channel; however, this disclosure is not limited thereto. For example, multiple holes can be formed, and lateral extension channels can be formed through these holes respectively. As mentioned above, to ensure a certain degree of flatness, the widths of the holes H can be substantially the same.

[0111] Next, we can continue with the formation of the conductive structure.

[0112] like Figure 33 As shown, in the electrical isolation layer 1065', vias 1067 can be formed, for example, by etching holes and filling them with conductive barrier layers such as conductive nitrides and conductive materials such as metals. Vias 1067 enable electrical connections between upper and lower layers. One or more vias adjacent to the sidewalls of the device stack can directly contact the first source / drain layer.

[0113] In addition, such as Figure 34(a) and 34(b) As shown, it can be combined as described above. Figures 21 to 28(b)A conductive structure is formed on the electrically insulating layer 1065'. Then, the height of the electrically insulating layer 1065' is further increased. Here, the height of the top surface of the electrically insulating layer 1065' allows for: on the one hand, the sidewalls of the gate conductor layer exposed in the trench are shielded to prevent the conductive structure subsequently formed on the top surface of the electrically insulating layer 1065' from contacting the gate conductor layer; on the other hand, the sidewalls of the second source / drain layer can be exposed in the trench, so that the conductive structure subsequently formed on the top surface of the electrically insulating layer 1065' can contact the second source / drain layer. Similarly, vias can be formed in the electrically insulating layer 1065'.

[0114] like Figure 35 As shown, it can be combined as described above. Figure 30 As described above, holes are formed in the electrical isolation layer 1065', and a etch such as a RIE is made downward through the holes (e.g., along a generally vertical direction) to form vertically extending channels that communicate with opposite ends of the lateral extending channels. These channels are interconnected to form a heat dissipation channel P. Additionally, it can be combined as described above. Figure 32 As described above, a plug 1069' is formed in the hole. Here, since the vertically extending pipe is thin and deep, the plug 1069' can be formed at its top to close it, while its lower part can maintain a hollow structure.

[0115] In this way, such as Figure 36(a) and 36(b) As shown, conductive structures can be formed layer by layer to create interconnect structures. Here, for the first source / drain layer, gate conductor layer, and second source / drain layer in each device layer, corresponding conductive structures are formed at appropriate heights to achieve the desired interconnects. Figure 36(a) and 36(b) In the diagram, the electrical isolation layer between conductive structures in the interconnect structure is shown as 1065″. At least a portion of the interfaces or boundaries in each layer may be substantially coplanar, for example, substantially aligned in the vertical direction.

[0116] Alternatively, heat dissipation pipes P1 and P2 can be formed in the electrical isolation layer 1065″ as described above. In this example, heat dissipation pipes P1 and P2 have vertically extending pipes and transversely extending pipes extending between the vertically extending pipes. The number of transversely extending pipes between the vertically extending pipes is not limited to one, but can be more (for example, the figure shows that P1 has two transversely extending pipes). More or fewer heat dissipation pipes can be provided in the electrical isolation layer 1065″ as needed, and at least some heat dissipation pipes can have different dimensions, such as different depths, thicknesses, transversely extending pipe lengths, etc.

[0117] Vertical extension channels can also be formed by vertical etching after the electrical isolation layer 1065″ is completed. In the above embodiment, the vertical extension channels are formed in segments, which avoids the difficulty of etching deep and fine holes. After each segment of the vertical extension channel is formed, the top is sealed with a plug. When etching to form the next segment, the plug in the previous segment can also be etched away, thereby allowing the two segments to be connected.

[0118] The top ends of the formed heat dissipation pipes P1 and P2 can be plugged to prevent the heat dissipation pipes from being affected when the interlayer dielectric layer is subsequently formed.

[0119] Next, the lead-out terminals of the interconnect structure can be fabricated. For example, such as... Figure 37 As shown, an interlayer dielectric layer (shown integrally with the electrical isolation layer as 1065″′) can be formed, for example, by depositing and planarizing a dielectric material such as an oxide, and an interconnect structure 1071, such as an interconnect or a via, can be formed in the interlayer dielectric layer 1065″′. The interconnect structure 1071 can contact and be electrically connected to the interconnect structure previously formed in the trench.

[0120] Additionally, vertical channels can be formed in the interlayer dielectric layer 1065″′ by etching, such as RIE, to connect with the previously formed heat dissipation channels P1 and P2. These connected channels (still shown as P1 and P2 for convenience) form heat dissipation channels, such as... Figure 37 As shown by the dashed arrow in the diagram. According to an embodiment, coolant such as pressurized cold gas and / or liquid can be introduced from one end of the heat dissipation pipes P1 and P2 and led out from the other end, thus dissipating the heat emitted by the device more efficiently.

[0121] In the above embodiments, isolation layers are provided between adjacent device layers. However, this disclosure is not limited to this. For example, some device layers may be directly adjacent to each other, especially in the case of complementary metal-oxide-semiconductor (CMOS) processes.

[0122] The semiconductor device according to embodiments of this disclosure can be applied to various electronic devices. Therefore, this disclosure also provides an electronic device including the aforementioned semiconductor device. The electronic device may further include components such as a display screen and a wireless transceiver. Examples of such electronic devices include smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, and power banks.

[0123] According to embodiments of this disclosure, a method for manufacturing a system-on-a-chip (SoC) is also provided. This method may include the methods described above. Specifically, multiple devices may be integrated on the chip, at least some of which are manufactured according to the methods of this disclosure.

[0124] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0125] This disclosure relates to the following aspects.

[0126] 1. A semiconductor device, comprising:

[0127] A substrate having a first region and a second region adjacent to each other;

[0128] Semiconductor devices on the first region; and

[0129] The interconnect structure on the second region includes:

[0130] Electrical isolation layer;

[0131] The conductive structure in the electrical isolation layer, wherein at least a portion of the components in the semiconductor device requiring electrical connection are laterally contacted and thus electrically connected to the conductive structure at a corresponding height in the interconnect structure; and

[0132] The heat dissipation pipes in the electrical isolation layer.

[0133] 2. The semiconductor device according to aspect 1, wherein the heat dissipation conduit is in communication with the outside.

[0134] 3. The semiconductor device according to aspect 2, wherein the heat dissipation conduit is configured to guide gas and / or liquid flow therethrough.

[0135] 4. The semiconductor device according to aspect 1, wherein the carrier substrate further comprises a third region adjacent to the second region.

[0136] The semiconductor device further includes:

[0137] The semiconductor devices on the third region,

[0138] In this configuration, at least a portion of the semiconductor devices in the third region that require electrical connection are laterally contacted and thus electrically connected to the conductive structure at a corresponding height in the interconnect structure.

[0139] 5. The semiconductor device according to any one of aspects 1 to 4, wherein the heat dissipation conduit includes a first vertical extension portion, a second vertical extension portion, and a lateral extension portion connecting the first vertical extension portion and the second vertical extension portion to each other.

[0140] 6. The semiconductor device according to aspect 5, wherein the interconnect structure further includes a plug disposed on the lateral extension, the plug having etch selectivity relative to the electrical isolation layer.

[0141] 7. The semiconductor device according to aspect 6, wherein the plug is narrower in the lateral direction than the lateral extension portion.

[0142] 8. The semiconductor device according to aspect 5, wherein the heat dissipation conduit includes a plurality of lateral extensions connecting the first vertical extension and the second vertical extension to each other.

[0143] 9. The semiconductor device according to aspect 5, wherein a plurality of said heat dissipation channels are provided, wherein at least a portion of the heat dissipation channels have different dimensions.

[0144] 10. The semiconductor device according to aspect 9, wherein the dimension includes at least one of the depth of the heat dissipation channel, the diameter of the heat dissipation channel, and the length of the lateral extension.

[0145] 11. The semiconductor device according to any one of aspects 1 to 4, wherein the heat dissipation channel surrounds one or more conductive structures in the interconnect structure.

[0146] 12. The semiconductor device according to any one of aspects 1 to 4, wherein an interface exists between the component and the conductive structure.

[0147] 13. The semiconductor device according to any one of aspects 1 to 4, wherein there is an interface between the electrical isolation layer and the interlayer dielectric layer in the first region.

[0148] 14. The semiconductor device according to aspect 12 or 13, wherein at least a portion of the interfaces at different heights are substantially coplanar.

[0149] 15. The semiconductor device according to any one of aspects 1 to 4, wherein the interconnect structure further includes dummy conductive structures, wherein the minimum spacing between conductive structures and conductive structures, conductive structures and dummy conductive structures, and dummy conductive structures in the same layer remains substantially consistent in that layer.

[0150] 16. A method of manufacturing a semiconductor device, comprising:

[0151] Device stacks are disposed on a carrier substrate;

[0152] An interconnect structure is formed laterally adjacent to the device stack in a region on the carrier substrate adjacent to the device stack. The interconnect structure includes an electrically insulating layer and conductive structures within the electrically insulating layer. During the formation of the interconnect structure, the height of the conductive structures in the interconnect structure is controlled such that at least a portion of the components in the device stack requiring electrical connection are laterally contacted and thus electrically connected to the conductive structures at corresponding heights in the interconnect structure.

[0153] Heat dissipation channels are formed in the electrical isolation layer.

[0154] 17. The method according to aspect 16, wherein the heat dissipation pipe is formed as a pipe with openings at both ends.

[0155] 18. The method according to aspect 16, wherein forming the heat dissipation conduit comprises:

[0156] A first conductive structure is formed at a first height in the region, wherein the first height is such that the first conductive structure is at substantially the same height as the corresponding component;

[0157] A first dielectric material is formed in the region to bury the first conductive structure, wherein the top surface of the first dielectric material is at a second height, the second height such that the second conductive structure subsequently formed on the first dielectric material is at substantially the same height as the corresponding component;

[0158] A first opening of a first width is formed in the first dielectric material;

[0159] Through the first opening, a transverse channel with a second width greater than the first width is formed below the first opening by etching;

[0160] A first plug is formed in the first opening;

[0161] The second conductive structure is formed on the first dielectric material;

[0162] A second dielectric material is further formed in the region, wherein the top surface of the second dielectric material is at a third height;

[0163] A second opening is formed in the second dielectric material; and

[0164] Through the second opening, a vertical channel is formed by etching, connecting to the opposite ends of the transverse channel.

[0165] 19. The method according to aspect 18, wherein forming the first plug comprises:

[0166] A plug material with a thickness greater than half the first width is deposited to fill the first opening, but not substantially fill the lateral channel;

[0167] The plug material of a certain thickness is etched so that the plug material remains in the first opening to form the first plug.

[0168] 20. The method according to aspect 19, wherein the deposition comprises chemical vapor deposition and the etching comprises atomic layer etching.

[0169] 21. The method according to aspect 18, wherein the third height causes the third conductive structure subsequently formed on the second dielectric material to be at substantially the same height as the corresponding component, the method further comprising:

[0170] A second plug is formed in the second opening;

[0171] The third conductive structure is formed on the second dielectric material;

[0172] A third dielectric material is further formed in the region;

[0173] A third opening is formed in the third dielectric material; and

[0174] Through etching, the third opening is made to connect with the vertical channel.

[0175] 22. The method according to aspect 18, wherein forming the transverse channel comprises:

[0176] A portion of the first conductive structure is etched through the second opening.

[0177] 23. An electronic device comprising a semiconductor device as described in any one of aspects 1 to 15.

[0178] 24. The electronic device according to aspect 23, wherein the electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0179] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: A substrate having a first region and a second region adjacent to each other; Semiconductor devices in the first region; as well as The interconnect structure on the second region includes: Electrical isolation layer; The electrical isolation layer consists of interconnect layers and via layers arranged alternately in the vertical direction. The interconnect layers contain interconnects, and the via layers contain vias. At least a portion of the components in the semiconductor device that require electrical connection are in contact with and thus electrically connected to the interconnects and / or vias at corresponding heights in the interconnect structure in the lateral direction through their respective sidewalls. The heat dissipation conduit in the electrical isolation layer includes a first vertical extension, a second vertical extension, and a transverse extension connecting the first vertical extension and the second vertical extension; and A plug disposed on the lateral extension portion, the plug having etch selectivity relative to the electrical isolation layer. Wherein, a first component of the semiconductor device that needs to be electrically connected at a certain height is connected to a conductive structure in the interconnect structure on a first side, and a second component that needs to be electrically connected and is adjacent to the first component in the vertical direction is connected to a conductive structure in the interconnect structure on a second side different from the first side.

2. The semiconductor device according to claim 1, wherein, The heat dissipation pipe is connected to the outside.

3. The semiconductor device according to claim 2, wherein, The heat dissipation pipe is configured to guide gas and / or liquid flow through it.

4. The semiconductor device according to claim 1, wherein, The lateral extension is at substantially the same height as an interconnect layer in the interconnect structure.

5. The semiconductor device according to claim 4, wherein, The opposite ends of the lateral extension are defined by the sidewalls of the interconnects in the interconnect layer.

6. The semiconductor device according to claim 1, wherein, At least one interconnect line and / or at least a portion of a via in the interconnect structure is directly above the lateral extension.

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