A control method and system for modular parallel low-cost three-level inverters

Abstract

The present invention proposes a control method and system for a modular parallel low-cost three-level inverter, which connects the DC side neutral points of the parallel low-cost three-level inverters, and can eliminate the zero-sequence circulating current caused by the unbalanced midpoint voltage; the zero-sequence circulating current suppression and the balance of the midpoint voltage are both achieved by adjusting the duty cycle of the small vector, while suppressing the zero-sequence circulating current of the modular parallel low-cost three-level inverter system, ensuring the balance of the midpoint voltage, and improving the output current quality in both steady-state and dynamic conditions. The control method of the present invention is applicable to the operating conditions where the given currents of the parallel modules are equal or unequal and the operating conditions where the filter inductances of the inverters are equal or unequal.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic power conversion, and in particular relates to a control method and system for a modular parallel low-cost three-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] The three-level inverter has the advantages of low voltage stress and loss of switch tubes, low harmonic content, and good output waveform quality. It is widely used in photovoltaic power generation, composite energy storage, and power control. Among them, the diode clamped (Neutral-Point Clamped, NPC) and T-type (T-Type) three-level inverter are the two most commonly used circuit topologies, but both still have the limitation of a large number of switch tubes. Low-cost three-level inverters use fewer switch tubes to reduce system costs and maintain multi-level output functions, and have broad application prospects.

[0004] Modular parallel three-level inverters can improve system capacity, reliability and efficiency and shorten production cycle without increasing switch current stress. However, the parallel connection of common DC bus and AC bus leads to problems such as circulating current and midpoint voltage imbalance, among which zero-sequence circulating current (ZSCC) is the main component of circulating current.

[0005] The imbalance of zero-sequence circulating current and midpoint voltage causes serious distortion of the inverter output current, increases the voltage stress and loss of the switch tube, reduces system efficiency, and even damages the switch tube, seriously threatening the safety of system operation.

[0006] The inventors found that the existing zero-sequence circulating current suppression and neutral point voltage balance control methods are only applicable to T-type and NPC three-level inverter parallel systems; low-cost three-level inverter topology has limitations, the output state is limited, and the neutral vector cannot be generated. Therefore, the existing control method cannot be directly applied. Therefore, a control method suitable for low-cost three-level inverter parallel system needs to be studied urgently. Summary of the invention

[0007] In order to overcome the deficiencies of the above-mentioned prior art, the present invention provides a control method and system for a modular parallel low-cost three-level inverter. The zero-sequence circulating current suppression and the balance of the midpoint voltage are both achieved by adjusting the duty cycle of the small vector, which can effectively suppress the zero-sequence circulating current of the modular parallel low-cost three-level inverter, control the midpoint voltage balance, and significantly improve the output current waveform quality.

[0008] To achieve the above object, a first aspect of the present invention provides a control method for modular parallel low-cost three-level inverters, wherein the DC side neutral points of the parallel low-cost three-level inverters are connected to each other, and the control method comprises:

[0009] Determine the sector and region where the reference voltage vector is located, select the basic voltage vector to synthesize the reference voltage vector, and calculate the initial value of the duty cycle of the small vector;

[0010] Inputting the tracking error of the zero-sequence circulating current into a zero-sequence circulating current controller based on finite time regulation to obtain a correction value of the first allocation factor of the small vector duty cycle;

[0011] The DC side capacitor voltage deviation of the low-cost three-level inverter is input into a midpoint voltage balance controller based on proportional regulation to obtain a second allocation factor correction value of a small vector duty cycle;

[0012] Correcting the small vector duty cycle according to the first allocation factor correction value of the small vector duty cycle, the second allocation factor correction value of the small vector duty cycle and the initial value of the small vector duty cycle;

[0013] A switching sequence is designed according to the corrected small vector duty cycle, the sector and the region where the reference voltage vector is located, and a corresponding PWM drive signal is generated according to the designed switching sequence to control the on and off of the switch tube.

[0014] A second aspect of the present invention provides a control system for modular parallel low-cost three-level inverters, wherein the DC side neutral points of the parallel low-cost three-level inverters are connected to each other, comprising:

[0015] A small vector duty cycle initial value calculation module is configured to: determine the sector and region where the reference voltage vector is located, select a basic voltage vector to synthesize the reference voltage vector, and calculate the small vector duty cycle initial value;

[0016] A small vector duty cycle first allocation factor correction value determination module is configured to: input the tracking error of the zero-sequence circulating current into a zero-sequence circulating current controller based on finite time regulation to obtain a small vector duty cycle first allocation factor correction value;

[0017] A small vector duty cycle second allocation factor correction value determination module is configured to: input a DC side capacitor voltage deviation of the low-cost three-level inverter into a midpoint voltage balance controller based on proportional regulation to obtain a small vector duty cycle second allocation factor correction value;

[0018] A small vector duty cycle correction module is configured to correct the small vector duty cycle according to a first allocation factor correction value of the small vector duty cycle, a second allocation factor correction value of the small vector duty cycle and the initial value of the small vector duty cycle;

[0019] PWM drive control module: designs a switching sequence according to the corrected small vector duty cycle, the sector and region where the reference voltage vector is located, generates a corresponding PWM drive signal according to the designed switching sequence, and controls the opening and closing of the switch tube.

[0020] The third aspect of the present invention provides a computer device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, a control method for a modular parallel low-cost three-level inverter is executed.

[0021] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, a control method for a modular parallel low-cost three-level inverter is executed.

[0022] One or more of the above technical solutions have the following beneficial effects:

[0023] In the present invention, the neutral points of the DC sides of the low-cost three-level inverters connected in parallel are connected, which can eliminate the zero-sequence circulating current caused by the imbalance of the midpoint voltage; the zero-sequence circulating current suppression and the balance of the midpoint voltage are both achieved by adjusting the duty cycle of the small vector, while suppressing the zero-sequence circulating current of the modular parallel low-cost three-level inverter system, and ensuring the balance of the midpoint voltage, and can improve the output current quality in both steady-state and dynamic conditions. The control method of the present invention is applicable to the operating conditions where the given currents of the parallel modules are equal or unequal and the operating conditions where the filter inductances of the inverters are equal or unequal.

[0024] In the present invention, the zero-sequence circulating current controller based on finite time regulation has better zero-sequence circulating current suppression capability and stronger anti-interference capability than the traditional PI regulator.

[0025] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0027] Figure 1 This is a circuit topology diagram of a modular parallel low-cost three-level inverter in Embodiment 1 of the present invention;

[0028] Figure 2A spatial vector diagram of a low-cost three-level inverter in Embodiment 1 of the present invention;

[0029] Figure 3 is a block diagram of a control method in Embodiment 1 of the present invention;

[0030] Figure 4 This is a schematic diagram of a new switch sequence in sector 1 and area A of the control method of embodiment 1 of the present invention;

[0031] Figure 5 It is the simulation waveform diagram of the "traditional PI regulator + traditional switch sequence" method when the given current amplitude is equal;

[0032] Figure 6 It is a simulation waveform diagram of the control method of the first embodiment of the present invention when the given current amplitudes are equal;

[0033] Figure 7 It is a simulation waveform diagram of the control method of the first embodiment of the present invention when the given current amplitudes are equal;

[0034] Figure 8 It is the simulation waveform diagram of the "traditional PI regulator + traditional switch sequence" method when the given current amplitudes are not equal;

[0035] Fig. 9 It is a simulation waveform diagram of the control method of the first embodiment of the present invention when the given current amplitudes are not equal;

[0036] Fig.10 It is a simulation waveform diagram of the control method of the first embodiment of the present invention when the given current amplitudes are not equal;

[0037] Fig.11 This is a simulation waveform diagram of the control method of Embodiment 1 of the present invention when the given current amplitude of the first inverter increases from 30A to 40A in a step manner;

[0038] Fig.12 This is a simulation waveform diagram of the control method of Embodiment 1 of the present invention when the given current amplitude of the second inverter increases from 20A to 30A in a step-wise manner. DETAILED DESCRIPTION

[0039] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0040] It should be noted that the terms used herein are for describing specific embodiments only and are not intended to be limiting of exemplary embodiments according to the present invention.

[0041] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0042] Embodiment 1

[0043] The system structure of modular parallel low-cost three-level inverter is as follows Figure 1 As shown in the figure, it is composed of two identical low-cost three-level inverters connected in parallel. Each low-cost three-level inverter includes ten switch tubes, and the number of switch tubes is further reduced compared with the traditional T-type three-level inverter. The DC side of the low-cost three-level inverter uses a filter capacitor, and the output end of the three-phase bridge arm is connected to the grid through a filter inductor to transmit high-quality electric energy to the grid. The input and output ends of different low-cost three-level inverters are connected together to achieve system expansion and improve system efficiency and reliability.

[0044] The system generally adopts a vector control scheme based on grid voltage orientation. The phase-locked loop (PLL) is used to detect the grid voltage phase angle, and the current loop is used to achieve fast and accurate tracking and control of the grid-connected current.

[0045] Specifically, the first low-cost three-level inverter includes two DC link capacitors (C 11 , C 21 ), ten switch tubes (S 11 , S 21 , …, S 101 ) and the output side filter. The connection point between the two DC side capacitors is the DC side neutral point, i.e., point O1. 11 , S 21 , S 31 , S 41 Four switch tubes are connected in series to form a common switch unit. 51 , S 61 The first group of independent switch units is formed by connecting them in series, S 71 , S 81 By connecting in series to form a second group of independent switch units, S 91 , S 101 The third group of independent switch units is formed by connecting in series. 11 The emitter is connected to S 21 , S 51 , S 71 , S 91 The collector of S 41 The collector is connected to S 31 , S 61 , S 81 , S 101 The emitter of S 11 The collector of dc The positive electrode, S 41 The emitter is connected to Vdc The negative electrode; S 21 The emitter, S 31 The collector of is connected to the neutral point of the DC side, i.e., point O1; the inductor L1 is used as the output side filter (R1 is its equivalent series resistance), i.e., the three groups of inductors L1 are connected to S 51 The output terminal and S 61 A1 point between the input terminals, S 71 The output terminal and S 81 Point B1 between the input terminals, S 91 The output terminal and S 101 Point C1 between the input terminals.

[0046] The second low-cost three-level inverter includes two DC link capacitors (C 12 , C 22 ), ten switch tubes (S 12 , S 22 , …, S 102 ), output side filter. Among them, the connection point between the two DC side capacitors is the DC side neutral point, that is, point O2. 12 , S 22 , S 32 , S 42 Four switch tubes are connected in series to form a common switch unit. 52 , S 62 The first group of independent switch units is formed by connecting them in series, S 72 , S 82 By connecting in series to form a second group of independent switch units, S 92 , S 102 The third group of independent switch units is formed by connecting in series. 12 The emitter is connected to S 22 , S 52 , S 72 , S 92 The collector of S 42 The collector is connected to S 32 , S 62 , S 82 , S 102 The emitter of S 12 The collector of dc The positive electrode, S 42 The emitter is connected to V dc The negative electrode; S 22 The emitter, S 32 The collector of is connected to the neutral point of the DC side, i.e., point O2; the inductor L2 is used as the output side filter (R2 is its equivalent series resistance), i.e., the three groups of inductors L2 are connected to S 52 The emitter and S 61 A2 point between collectors, S 72The emitter and S 82 Point B2 between the collectors, S 92 The emitter and S 102 C2 points between the emitter.

[0047] The DC side neutral point O1 of the first low-cost three-level inverter is connected to the DC side neutral point O2 of the second low-cost three-level inverter, and the output side of the first low-cost three-level inverter is connected to the output side of the second low-cost three-level inverter. The turning on and off of each switch tube is realized based on the space vector modulation (SVM) method.

[0048] The switch tube refers to an insulated-gate bipolar transistor (IGBT); the switch tube may also be implemented by transistors in other forms, which may be selected according to the actual needs of technicians in this field.

[0049] This embodiment provides a control method for modular parallel low-cost three-level inverters, wherein the DC side neutral points of the parallel low-cost three-level inverters are connected to each other, and the control method includes:

[0050] Determine the sector and region where the reference voltage vector is located, select the basic voltage vector to synthesize the reference voltage vector, and calculate the initial value of the duty cycle of the small vector;

[0051] Inputting the tracking error of the zero-sequence circulating current into a zero-sequence circulating current controller based on finite time regulation to obtain a correction value of the first allocation factor of the small vector duty cycle;

[0052] The DC side capacitor voltage deviation of the low-cost three-level inverter is input into a midpoint voltage balance controller based on proportional regulation to obtain a second allocation factor correction value of a small vector duty cycle;

[0053] Correcting the small vector duty cycle according to the first allocation factor correction value of the small vector duty cycle, the second allocation factor correction value of the small vector duty cycle and the initial value of the small vector duty cycle;

[0054] A switching sequence is designed according to the corrected small vector duty cycle, the sector and the region where the reference voltage vector is located, and a corresponding PWM drive signal is generated according to the designed switching sequence to control the on and off of the switch tube.

[0055] The low-cost three-level inverter has three switching states: [P], [O] and [N]. When the midpoint voltage is balanced, select the DC power supply V dc Negative electrode (see Figure 1 ) as a reference, when the switch state is [P], the bridge arm output voltage is V dc; When the switch state is [O], the bridge arm output voltage is V dc / 2; when the switch state is [N], the bridge arm output voltage is 0.

[0056] The space vector diagram of a low-cost three-level inverter is shown in Figure 2. Figure 2 As shown in FIG. 1 , the entire space vector diagram is divided into six sectors (i.e., sector 1 to sector 6), and each sector is further divided into two small areas (i.e., area A and area B), the outer area is defined as area A, and the inner area is defined as area B. The basic voltage vectors, switch states, and turned-on switches are shown in Table 1. It can be seen that the basic voltage vectors of the low-cost three-level inverter include large vectors, small vectors, and zero vectors.

[0057] Table 1 Basic voltage vectors, switch states and enabled switch tubes of low-cost three-level inverter

[0058]

[0059]

[0060] The sector and region where the reference voltage vector is located are determined based on its amplitude and phase angle.

[0061] Without loss of generality, take sector 1 and region A as an example to illustrate the basic voltage vector selection and duty cycle calculation method. When the reference voltage vector is located in sector 1 and region A, select the large vector V L1 [PNN], large vector V L2 [PPN], small vector V S1 [POO] / [ONN] and small vector V S2 [PPO] / [OON] synthesizes the reference voltage vector. According to the volt-second balance principle, we can get:

[0062]

[0063] Among them, d L1 d L2 d S1 and d S2 are the duty cycles of large vector [PNN], large vector [PPN], small vector [POO] / [ONN] and small vector [PPO] / [OON], respectively. ref is the reference voltage vector.

[0064] When the four basic voltage vectors synthesize the reference voltage vector, the duty cycle of each basic voltage vector cannot be calculated directly, so an indirect calculation method is used to solve the duty cycle of the basic voltage vector. The expressions of large vector [PNN], large vector [PPN], small vector [POO] / [ONN], and small vector [PPO] / [OON] are:

[0065]

[0066] Substituting the expressions of each basic voltage vector into the volt-second balance equation and simplifying it, we can obtain:

[0067]

[0068] Where m and θ are the modulation index and the phase angle of the reference voltage vector, respectively.

[0069] Small Vector V S1 and the small vector V S2 The sum of the duty cycles is:

[0070]

[0071] Introducing small vector duty cycle allocation factor D S1 and d S2 Respectively expressed as:

[0072]

[0073] Consider the duty cycle d L1 and d L2 Constraints 0 <d L1 <1,0 <d L2 <1, further get the distribution factor The constraints are:

[0074]

[0075] Considering small vector duty cycle allocation factor The limiting condition of , the minimum and maximum values ​​are:

[0076]

[0077]

[0078] Select the allocation factor The upper limit and lower limit The average value of is:

[0079]

[0080] Substituting the allocation factor given by equation (9) into the above expression of duty cycle, the initial value of each basic voltage vector duty cycle can be obtained, where the initial value of the small vector duty cycle is:

[0081]

[0082] Among them, d s1p ds1n d s2p and d s2n They represent the duty cycles of the basic voltage vectors [POO], [ONN], [PPO] and [OON] respectively.

[0083] The zero-sequence circulating current of the jth (j=1,2) inverter is defined as the sum of its three-phase output currents, that is:

[0084] i zj =i aj +i bj +i cj (11)

[0085] In order to eliminate the zero-sequence circulating current caused by the unbalanced midpoint voltage, the DC side neutral points of each inverter are connected together.

[0086] To achieve unity power factor operation, the q-axis current setpoint of each inverter is set to 0, that is:

[0087]

[0088] Figure 3 The control block diagram of the method of the present invention includes zero-sequence circulating current suppression, midpoint voltage balance control, small vector duty cycle allocation factor update and switch sequence design.

[0089] 1. Constructing a zero-sequence circulating current mathematical model

[0090] Select the negative pole N of the DC power supply as a reference. According to Kirchhoff's voltage law, the mathematical model of the jth inverter is:

[0091]

[0092] Among them, L j , R j are the filter inductance and equivalent resistance of the jth inverter, u xj 、i xj (x=a, b, c) are the output voltage and output current of the inverter respectively, e x is the grid voltage, u ON It is the voltage between the neutral point of the grid and the negative pole of the DC power supply.

[0093] Adding the above formula together, we get:

[0094]

[0095] Among them, u zj Represents the zero-sequence voltage of the jth inverter.

[0096] When two inverters are connected in parallel, the zero-sequence circulating currents have equal amplitudes and opposite directions, and we have:

[0097]

[0098] Under the condition of midpoint voltage balance, u zj The expression in sector 1, area A is:

[0099]

[0100] Among them, d zj represents the zero-sequence duty cycle of the jth inverter, d L1j d L2j d S1pj d S1nj d S2pj and d S2nj They represent the duty cycles of the basic voltage vectors [PNN], [PPN], [POO], [ONN], [PPO] and [OON] of the j-th inverter respectively.

[0101] The relationship between the zero-sequence circulating current and the zero-sequence duty cycle of the modular parallel low-cost three-level inverter is:

[0102]

[0103] The tracking error e = i z2_ref -i z2 As the input of the zero-sequence circulating current controller, its output y is used as the first allocation factor correction value of the small vector duty cycle of the first inverter and the second inverter, that is:

[0104]

[0105] Among them, d s12 It represents the duty cycle of the small vector [POO] / [ONN] in the second inverter.

[0106] In summary, the zero-sequence duty ratios of the first and second inverters in sector 1 and region A can be expressed as:

[0107]

[0108]

[0109] By using the first allocation factor to correct the small vector duty cycle, the relationship between the zero-sequence circulating current and the zero-sequence duty cycle of the modular parallel low-cost three-level inverter can be further expressed as:

[0110]

[0111] 2. Design of zero-sequence circulating current controller and system stability analysis

[0112] The invention is designed based on a zero-sequence circulating current suppression scheme of a simplified finite-time regulator, which has better zero-sequence circulating current suppression capability and stronger anti-interference capability than a traditional PI regulator.

[0113] The error dynamic equation can be expressed as:

[0114]

[0115] According to the finite time control theory, the simplified zero-sequence circulating current controller is designed as:

[0116]

[0117] Among them, sign(·) is the sign function, α1∈[0,1],

[0118] Substituting formula (23) into formula (22), we can obtain:

[0119]

[0120] Given the Lyapunov function:

[0121]

[0122] Derivate equation (25), substitute equation (24) into the derivative, and consider the restriction of k1:

[0123]

[0124] According to the finite-time stability theory, it can be obtained that the tracking error of the control variable y converges to zero in a finite time.

[0125] In order to achieve the decoupling of zero-sequence circulating current suppression and neutral point voltage balance control, the output of the zero-sequence circulating current controller is applied to the two inverters respectively. The duty cycle of each basic voltage vector in sector 1 and area A can be expressed as:

[0126]

[0127]

[0128] Among them, d s1j and d s2j They represent the duty cycles of the small vector [POO] / [ONN] and the small vector [PPO] / [OON] in the j-th inverter respectively.

[0129] 3. Design of midpoint voltage balance controller

[0130] Sampling the first inverter DC side capacitor C 11 and C 21The voltage at both ends is used to calculate the deviation of the voltage of the two capacitors and send it to the proportional regulator to obtain the second distribution factor correction value y of the small vector duty cycle np ,Right now:

[0131] y np =k np (V C1 -V C2 ) (29)

[0132] Among them, V C1 and V C2 They are respectively the capacitor C 11 and C 21 The voltage across the terminals, k np is the coefficient of the proportional regulator.

[0133] The second distribution factor correction value obtained by the midpoint voltage controller is further distributed to the duty ratios of the P-type and N-type small vectors to achieve midpoint balance control, that is:

[0134]

[0135] 4. Small vector duty cycle correction

[0136] For the modular parallel low-cost three-level inverter system, zero-sequence circulating current suppression and midpoint voltage balance control are both achieved by adjusting the duty cycle of the small vector, that is:

[0137]

[0138]

[0139] In order to ensure that the duty cycle of the small vector is greater than 0, the total adjustment amount of the first allocation factor and the second allocation factor should be limited to between -1 and 1, and the proportional coefficients α and β are introduced so that:

[0140]

[0141] Among them, α+β<1.

[0142] In summary, the small vector duty cycle allocation factors of each inverter in sector 1 and area A are updated as follows:

[0143]

[0144]

[0145] Based on the updated duty cycle of the basic vector and the sector and region where the reference voltage vector is located, a switching sequence is designed and converted into a PWM drive signal for the switch tube to control the operation of the modular parallel low-cost three-level inverter system.

[0146] 5. New switch sequence design

[0147] The instantaneous zero-sequence voltage (IZSV) of the basic voltage vector is defined as:

[0148]

[0149] The instantaneous zero-sequence voltage of each basic voltage vector is shown in Table 2. It can be seen that: the small vectors are redundant, and the P-type and N-type small vectors generate the same line voltage, but the corresponding instantaneous zero-sequence voltages are different.

[0150] Table 2 IZSV of basic voltage vector of low-cost three-level inverter

[0151]

[0152]

[0153] The averaged zero-sequence voltage (AZSV) is defined as the average value of the zero-sequence voltage in a switching cycle. When the space vector modulation method is used, the difference in the average zero-sequence voltage of each inverter induces zero-sequence circulating current. By adjusting the duty cycle of the small vector, the AZSV of the two inverters can be made the same, thereby achieving zero-sequence circulating current suppression.

[0154] The traditional switching sequence design method uses a large vector as the starting vector of the switching sequence. The reference voltage vector undergoes sector switching, which causes a zero-sequence circulating current spike. The reason for this is that the IZSV of the starting large vector is different. To this end, the method of the present invention designs a new switching sequence (see Figure 4 ) to eliminate the zero-sequence circulating current spike caused by sector switching. Specifically, a nine-segment or eleven-segment switching sequence is designed to improve the output waveform quality. The switching sequence specifically includes:

[0155] When the reference voltage vector is located in region A within sector 1, the designed switching sequence is as follows:

[0156] [ONN]-[OON]-[PNN]-[PPN]-[POO]-[PPO]-[POO]-[PPN]-[PNN]-[OON]-[ONN];

[0157] When the reference voltage vector is located in region B within sector 1, the designed switching sequence is as follows:

[0158] [ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN];

[0159] When the reference voltage vector is located in region A within sector 2, the designed switching sequence is as follows:

[0160] [NON]-[OON]-[NPN]-[PPN]-[OPO]-[PPO]-[OPO]-[PPN]-[NPN]-[OON]-[NON];

[0161] When the reference voltage vector is located in region B within sector 2, the designed switching sequence is as follows:

[0162] [NON]-[OON]-[OOO]-[OPO]-[PPO]-[OPO]-[OOO]-[OON]-[NON];

[0163] When the reference voltage vector is located in region A within sector 3, the switching sequence is designed as follows:

[0164] [NON]-[NOO]-[NPN]-[NPP]-[OPO]-[OPP]-[OPO]-[NPP]-[NPN]-[NOO]-[NON];

[0165] When the reference voltage vector is located in region B within sector 3, the designed switching sequence is as follows:

[0166] [NON]-[NOO]-[OOO]-[OPO]-[OPP]-[OPO]-[OOO]-[NOO]-[NON];

[0167] When the reference voltage vector is located in region A within sector 4, the switching sequence is designed as follows:

[0168] [NNO]-[NOO]-[NNP]-[NPP]-[OOP]-[OPP]-[OOP]-[NPP]-[NNP]-[NOO]-[NNO];

[0169] When the reference voltage vector is located in region B within sector 4, the switching sequence is designed as follows:

[0170] [NNO]-[NOO]-[OOO]-[OOP]-[OPP]-[OOP]-[OOO]-[NOO]-[NNO];

[0171] When the reference voltage vector is located in region A within sector 5, the switching sequence is designed as follows:

[0172] [NNO]-[ONO]-[NNP]-[PNP]-[OOP]-[POP]-[OOP]-[PNP]-[NNP]-[ONO]-[NNO];

[0173] When the reference voltage vector is located in region B within sector 5, the designed switching sequence is as follows:

[0174] [NNO]-[ONO]-[OOO]-[OOP]-[POP]-[OOP]-[OOO]-[ONO]-[NNO];

[0175] When the reference voltage vector is located in region A within sector 6, the switching sequence is designed as follows:

[0176] [ONN]-[ONO]-[PNN]-[PNP]-[POO]-[OPO]-[POO]-[PNP]-[PNN]-[OON]-[ONN];

[0177] When the reference voltage vector is located in region B within sector 6, the switching sequence is designed as follows:

[0178] [ONN]-[ONO]-[OOO]-[POO]-[POP]-[POO]-[OOO]-[ONO]-[ONN].

[0179] When the reference voltage vector switches sectors, the IZSV of the starting small vector in the above switching sequence is the same, and in each switching cycle, IZSV has the same change rule (i.e., V dc / 6→V dc / 3→2V dc / 3→5V dc / 6→2V dc / 3→V dc / 3→V dc / 6). Therefore, the new switching sequence can effectively eliminate the zero-sequence circulating current spike.

[0180] In order to improve the utilization rate of DC voltage, the system usually runs in a high modulation mode, that is, the reference voltage vector is located in the area A of each sector. Therefore, only the simulation waveform when the modulation is 0.8 is given.

[0181] Figure 5 The simulation waveform of the “traditional PI regulator + traditional switching sequence” method when the given current amplitude is equal, including the three-phase output current of the first inverter (i a1 、i b1 、i c1 )、zero sequence circulating current(i z1 ) and the three-phase output current of the second inverter (i a2 、i b2 、i c2 ). Since the zero-sequence circulating currents of the first and second inverters are equal in amplitude and opposite in direction, only the zero-sequence circulating current of the first inverter is given. At this time, THD i1 and THD i2They are 2.73% and 1.88% respectively, but there is a zero-sequence circulating current spike with an amplitude as high as 3A.

[0182] Figure 6 and Figure 7 The simulation waveform diagram of the method of the present invention when the given current amplitude is equal, including the line voltage (V ab1 )、Three-phase output current (i a1 、i b1 、i c1 )、zero sequence circulating current(i z1 ), capacitor voltage (V C1 、V C2 ), the line voltage of the second inverter (V ab2 )、Three-phase output current (i a2 、i b2 、i c2 ). At this time, the voltages of the two capacitors on the DC side are equal, and the method of the present invention realizes the midpoint voltage balance control. The line voltage of each inverter is a five-level waveform, and THD V1 and THD V2 They are 58.27% and 58.36% respectively. Figure 5 and Figure 6 It can be seen that compared with the "traditional PI regulator + traditional switch sequence" method, the method of the present invention can eliminate the zero-sequence circulating current spike, THD i1 and THD i2 They are reduced to 2.45% and 1.84% respectively, and the quality of the output current waveform is significantly improved.

[0183] Figure 8 The simulation waveform of the “traditional PI regulator + traditional switching sequence” method when the given current amplitude is unequal, including the three-phase output current of the first inverter (i a1 、i b1 、i c1 )、zero sequence circulating current(i z1 ) and the three-phase output current of the second inverter (i a2 、i b2 、i c2 ). At this time, THD i1 and THD i2 They are 2.71% and 3.62% respectively, but there is still a zero-sequence circulating current spike with an amplitude of 3A.

[0184] Fig. 9 and Fig.10 The simulation waveform diagram of the method of the present invention when the given current is not equal, including the line voltage (V ab1 )、Three-phase output current (i a1 、i b1 、i c1)、zero sequence circulating current(i z1 ), capacitor voltage (V C1 、V C2 ) and the line voltage of the second inverter (V ab2 )、Three-phase output current (i a2 、i b2 、i c2 ). At this time, the voltages of the two capacitors on the DC side are equal, and the method of the present invention realizes the midpoint voltage balance control. The line voltage of each inverter is a five-level waveform, and THD V1 and THD V2 They are 58.41% and 58.74% respectively. Figure 7 and Figure 8 It can be seen that compared with the "traditional PI regulator + traditional switch sequence" method, the method of the present invention can eliminate the zero-sequence circulating current spike, THD i1 and THD i2 The method of the present invention is applicable to the working conditions of equal and unequal given current amplitudes, and has obvious advantages.

[0185] Fig.11 The simulation waveform diagram of the method of the present invention when the given currents are not equal and the given current amplitude of the first inverter increases stepwise, including the three-phase output current (i a1 、i b1 、i c1 )、zero sequence circulating current(i z1 ) and the three-phase output current of the second inverter (i a2 、i b2 、i c2 ). When t = 0.34s, the given current amplitude of the second inverter increases from 30A to 40A in a step, and the zero-sequence circulating current has no obvious change, and the inverter parallel system operates normally.

[0186] Fig.12 The simulation waveform diagram of the method of the present invention when the given currents are not equal and the given current amplitude of the second inverter increases in a step, including the three-phase output current (i a1 、i b1 、i c1 )、zero sequence circulating current(i z1 ) and the three-phase output current of the second inverter (i a2 、i b2 、i c2 ). When t=0.34s, the given current amplitude of the second inverter increases from 20A to 30A in a stepwise manner, and the zero-sequence circulating current has no obvious change, and the inverter works normally, that is, the method of the present invention is suitable for suppressing zero-sequence circulating current in dynamic conditions.

[0187] Embodiment 2

[0188] The purpose of this embodiment is to provide a control system for modular parallel low-cost three-level inverters, wherein the DC side neutral points of the parallel low-cost three-level inverters are connected to each other, including:

[0189] A small vector duty cycle initial value calculation module is configured to: determine the sector and region where the reference voltage vector is located, select a basic voltage vector to synthesize the reference voltage vector, and calculate the small vector duty cycle initial value;

[0190] A small vector duty cycle first allocation factor correction value determination module is configured to: input the tracking error of the zero-sequence circulating current into a zero-sequence circulating current controller based on finite time regulation to obtain a small vector duty cycle first allocation factor correction value;

[0191] A small vector duty cycle second allocation factor correction value determination module is configured to: input a DC side capacitor voltage deviation of the low-cost three-level inverter into a midpoint voltage balance controller based on proportional regulation to obtain a small vector duty cycle second allocation factor correction value;

[0192] A small vector duty cycle correction module is configured to correct the small vector duty cycle according to a first allocation factor correction value of the small vector duty cycle, a second allocation factor correction value of the small vector duty cycle and the initial value of the small vector duty cycle;

[0193] PWM drive control module: designs a switching sequence according to the corrected small vector duty cycle, the sector and region where the reference voltage vector is located, generates a corresponding PWM drive signal according to the designed switching sequence, and controls the opening and closing of the switch tube.

[0194] Embodiment 3

[0195] The purpose of this embodiment is to provide a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the program.

[0196] Embodiment 4

[0197] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are executed.

[0198] The steps involved in the apparatuses of the above embodiments 2, 3 and 4 correspond to the method embodiment 1, and the specific implementation methods can refer to the relevant description part of embodiment 1. The term "computer-readable storage medium" should be understood as a single medium or multiple media including one or more instruction sets; it should also be understood to include any medium that can store, encode or carry an instruction set for execution by a processor and enable the processor to execute any method in the present invention.

[0199] Those skilled in the art should understand that the modules or steps of the present invention described above can be implemented by a general-purpose computer device, or alternatively, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. The present invention is not limited to any specific combination of hardware and software.

[0200] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A control method for modular parallel low-cost three-level inverters, characterized in that: The DC side neutral points of two parallel three-level inverters are connected to each other, and the control method includes: Determine the sector and region where the reference voltage vector is located, select the basic voltage vector to synthesize the reference voltage vector, and calculate the initial value of the duty cycle of the small vector; The tracking error e of the zero-sequence circulating current is input into the zero-sequence circulating current controller based on finite time regulation to obtain the first allocation factor correction value of the small vector duty cycle, which is specifically: Among them, sign(■) is the sign function, α1∈[0,1], d s12 represents the duty cycle of the small vector [POO] / [ONN] in the second inverter, d S1p2 d S1n2 Respectively represent the first allocation factor correction value of the small vector duty cycle of the first inverter and the second inverter, d zj represents the zero-sequence duty cycle of the jth inverter, R j represents the equivalent resistance of the jth inverter, V dc is a DC power supply, i z2 is the zero-sequence circulating current of the second inverter; The deviation of the DC side capacitor voltage of one of the three-level inverters is multiplied by the proportional adjustment coefficient to obtain a correction value of the second allocation factor of the small vector duty cycle; The obtained small vector duty cycle second allocation factor correction value is allocated to the duty cycle of the P-type and N-type small vectors to achieve midpoint balance control, specifically: Among them, d S1pj d S1nj d S2pj and d S2nj represent the duty cycles of the basic voltage vectors [POO], [ONN], [PPO] and [OON] of the jth inverter respectively; d s1j and d s2j They represent the duty cycles of the small vector [POO] / [ONN] and the small vector [PPO] / [OON] in the j-th inverter respectively; According to the first allocation factor correction value of the small vector duty cycle, the second allocation factor correction value of the small vector duty cycle and the initial value of the small vector duty cycle, the small vector duty cycle is corrected, specifically: Among them, α and β are proportional coefficients; A switching sequence is designed according to the corrected small vector duty cycle, the sector and the region where the reference voltage vector is located, and a corresponding PWM drive signal is generated according to the designed switching sequence to control the on and off of the switch tube.

2. The control method of a modular parallel low-cost three-level inverter according to claim 1, characterized in that: The calculation of the initial value of the small vector duty cycle is as follows: Substitute the basic voltage vector expression and the phase angle of the reference voltage vector into the volt-second balance equation to obtain the sum of the duty cycles of the small vectors; The small vector duty cycle allocation factor is introduced, and the small vector duty cycle expression is obtained according to the sum of the small vector duty cycles; According to the constraint conditions of the large vector duty cycle and the limiting conditions of the small vector duty cycle allocation factor, the maximum value and the minimum value of the small vector duty cycle allocation factor are determined; Selecting the average of the maximum and minimum values ​​of the small vector duty cycle allocation factor as the small vector duty cycle allocation factor value; Substitute the obtained small vector duty cycle allocation factor value into the small vector duty cycle expression to obtain the small vector duty cycle initial value.

3. The control method of a modular parallel low-cost three-level inverter according to claim 1, characterized in that: The switching sequence of the design is specifically: When the reference voltage vector is located in the outer region A within sector 1, the switching sequence is designed as follows: [ONN]-[OON]-[PNN]-[PPN]-[POO]-[PPO]-[POO]-[PPN]-[PNN]-[OON]-[ON N]; When the reference voltage vector is located in the inner region B within sector 1, the switching sequence is designed as follows: [ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN]; When the reference voltage vector is located in the outer region A within sector 2, the switching sequence is designed as follows: [NON]-[OON]-[NPN]-[PPN]-[OPO]-[PPO]-[OPO]-[PPN]-[NPN]-[OON]-[NO N]; When the reference voltage vector is located in the inner region B within sector 2, the switching sequence is designed as follows: [NON]-[OON]-[OOO]-[OPO]-[PPO]-[OPO]-[OOO]-[OON]-[NON]; When the reference voltage vector is located in the outer region A within sector 3, the switching sequence is designed as follows: [NON]-[NOO]-[NPN]-[NPP]-[OPO]-[OPP]-[OPO]-[NPP]-[NPN]-[NOO]-[NO N]; When the reference voltage vector is located in the inner region B within sector 3, the switching sequence is designed as follows: [NON]-[NOO]-[OOO]-[OPO]-[OPP]-[OPO]-[OOO]-[NOO]-[NON]; When the reference voltage vector is located in the outer region A within sector 4, the switching sequence is designed as follows: [NNO]-[NOO]-[NNP]-[NPP]-[OOP]-[OPP]-[OOP]-[NPP]-[NNP]-[NOO]-[NN O]; When the reference voltage vector is located in the inner region B within sector 4, the switching sequence is designed as follows: [NNO]-[NOO]-[OOO]-[OOP]-[OPP]-[OOP]-[OOO]-[NOO]-[NNO]; When the reference voltage vector is located in the outer region A within sector 5, the switching sequence is designed as follows: [NNO]-[ONO]-[NNP]-[PNP]-[OOP]-[POP]-[OOP]-[PNP]-[NNP]-[ONO]-[NN O]; When the reference voltage vector is located in the inner region B within sector 5, the switching sequence is designed as follows: [NNO]-[ONO]-[OOO]-[OOP]-[POP]-[OOP]-[OOO]-[ONO]-[NNO]; When the reference voltage vector is located in the outer region A within sector 6, the switching sequence is designed as follows: [ONN]-[ONO]-[PNN]-[PNP]-[POO]-[OPO]-[POO]-[PNP]-[PNN]-[OON]-[ON N]; When the reference voltage vector is located in the inner region B within sector 6, the switching sequence is designed as follows: [ONN]-[ONO]-[OOO]-[POO]-[POP]-[POO]-[OOO]-[ONO]-[ONN].

4. The control method of a modular parallel low-cost three-level inverter according to claim 3, characterized in that: When the reference voltage is sector-switched, the instantaneous zero-sequence voltages of the starting small vectors in the switching sequence are the same, and in each switching cycle, the instantaneous zero-sequence voltages of the basic voltage vectors have the same variation rule.

5. A control system for modular parallel low-cost three-level inverters, characterized in that: The DC side neutral points of two parallel three-level inverters are connected to each other, including: A small vector duty cycle initial value calculation module is configured to: determine the sector and region where the reference voltage vector is located, select a basic voltage vector to synthesize the reference voltage vector, and calculate the small vector duty cycle initial value; The first allocation factor correction value determination module of the small vector duty cycle is configured to: input the tracking error e of the zero-sequence circulating current into the zero-sequence circulating current controller based on finite time regulation to obtain the first allocation factor correction value of the small vector duty cycle, specifically: Among them, sign(■) is the sign function, α1∈[0,1], d s12 represents the duty cycle of the small vector [POO] / [ONN] in the second inverter, d S1p2 d S1n2 Respectively represent the first allocation factor correction value of the small vector duty cycle of the first inverter and the second inverter, d zj represents the zero-sequence duty cycle of the jth inverter, R j represents the equivalent resistance of the jth inverter, V dc is a DC power supply; i z2 is the zero-sequence circulating current of the second inverter; A small vector duty cycle second allocation factor correction value determination module is configured to: multiply the deviation of the DC side capacitor voltage of one of the three-level inverters by the proportional adjustment coefficient to obtain a small vector duty cycle second allocation factor correction value; The obtained small vector duty cycle second allocation factor correction value is allocated to the duty cycle of the P-type and N-type small vectors to achieve midpoint balance control, specifically: Among them, d S1pj d S1nj d S2pj and d S2nj represent the duty cycles of the basic voltage vectors [POO], [ONN], [PPO] and [OON] of the jth inverter respectively; d s1j and d s2j They represent the duty cycles of the small vector [POO] / [ONN] and the small vector [PPO] / [OON] in the j-th inverter respectively; The small vector duty cycle correction module is configured to correct the small vector duty cycle according to the first allocation factor correction value of the small vector duty cycle, the second allocation factor correction value of the small vector duty cycle and the initial value of the small vector duty cycle, specifically: Among them, α and β are proportional coefficients; PWM drive control module: designs a switching sequence according to the corrected small vector duty cycle, the sector and region where the reference voltage vector is located, generates a corresponding PWM drive signal according to the designed switching sequence, and controls the opening and closing of the switch tube.

6. A computer device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, a control method for a modular parallel low-cost three-level inverter as described in any one of claims 1 to 4 is executed.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the control method of a modular parallel low-cost three-level inverter according to any one of claims 1 to 4 is executed.

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