Semiconductor structure and method of making the same, memory

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof and a memory, and relates to the technical field of semiconductor technology, and is used to solve the technical problem of difficulty in manufacturing a semiconductor structure. The semiconductor structure comprises a substrate and a conductive structure located above the substrate; the conductive structure comprises a plurality of first conductive structures and a plurality of second conductive structures arranged at intervals and extending in a first direction, and the lengths of the plurality of first conductive structures and the plurality of second conductive structures are both step-changed. The lengths of the plurality of first conductive structures and the plurality of second conductive structures are both step-changed, the first conductive structures and the second conductive structures form word lines, the word lines are easy to manufacture and convenient to lead out, and it is convenient to form other structures on the word lines to realize the electrical connection between the word lines and peripheral circuits.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] With the development of semiconductor technology, memory, especially dynamic random access memory (DRAM), is widely used in various electronic devices due to its high storage density and fast read / write speed.

[0003] Dynamic random access memory (DRAM) typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage on the word line controls the transistor's on and off states. The source / drain of the transistor is electrically connected to the bit line (BL), and the drain / source is electrically connected to the capacitor. Data information is output through the bit line.

[0004] To further reduce the size of the memory and increase its storage density, capacitors are usually placed horizontally to facilitate the fabrication of capacitors with a larger aspect ratio. However, the fabrication of such memory is quite difficult. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a semiconductor structure and its fabrication method, as well as a memory, to reduce the difficulty of fabricating semiconductor structures.

[0006] According to some embodiments, a first aspect of this disclosure provides a semiconductor structure comprising: a substrate and a conductive structure located above the substrate; the conductive structure includes a plurality of first conductive structures and second conductive structures extending in a first direction at intervals, wherein the lengths of the plurality of first conductive structures and the plurality of second conductive structures are all stepped.

[0007] In some possible embodiments, the substrate includes a device region and a first connection region and a second connection region respectively disposed on both sides of the device region; the first conductive structure is located above the device region and extends to the first connection region, and the second conductive structure is located above the device region and extends to the second connection region; the length of the first conductive structure located above the first connection region varies in a stepped manner, and the length of the second conductive structure located above the second connection region varies in a stepped manner.

[0008] In some possible embodiments, the length of the first conductive structure closer to the substrate is greater than the length of the first conductive structure farther from the substrate, so that the lengths of the plurality of first conductive structures vary in a step manner; the length of the second conductive structure closer to the substrate is greater than the length of the second conductive structure farther from the substrate, so that the lengths of the plurality of second conductive structures vary in a step manner.

[0009] In some possible embodiments, a plurality of the first conductive structures and a plurality of the second conductive structures are arranged alternately and at intervals along a second direction.

[0010] In some possible embodiments, the semiconductor structure further includes a plurality of spaced-apart contact plugs, the contact plugs including first contact plugs and second contact plugs; the plurality of first contact plugs correspond one-to-one with and are electrically connected to a plurality of first conductive structures; the plurality of second contact plugs correspond one-to-one with and are electrically connected to a plurality of second conductive structures.

[0011] In some possible embodiments, the plurality of first contact plugs and the plurality of second contact plugs extend along a second direction, and the lengths of the plurality of first contact plugs and the plurality of second contact plugs vary in a stepped manner.

[0012] In some possible embodiments, both the first contact plug and the second contact plug include a first conductive portion and a second conductive portion disposed on the first conductive portion, wherein the size of the first conductive portion is smaller than the size of the second conductive portion.

[0013] In some possible embodiments, each of the first conductive structures and each of the second conductive structures located above the device region surrounds a plurality of spaced-apart channel structures, and a dielectric layer is disposed between the first conductive structure and the channel structures, and between the second conductive structure and the channel structures.

[0014] In some possible embodiments, each of the first conductive structures located above the first connection region surrounds a first active layer, and a first insulating layer is disposed between the first conductive structure and the first active layer; each of the second conductive structures located above the second connection region surrounds a second active layer, and a second insulating layer is disposed between the second conductive structure and the second active layer.

[0015] In some possible embodiments, the first active layer corresponding to the same first conductive structure and the plurality of channel structures are disposed in the same layer, and the second active layer corresponding to the same second conductive structure and the plurality of channel structures are disposed in the same layer.

[0016] The semiconductor structure provided in this disclosure has at least the following advantages:

[0017] In the semiconductor structure provided in this embodiment, a plurality of first conductive structures and a plurality of second conductive structures are disposed above a substrate. Both the plurality of first conductive structures and the plurality of second conductive structures extend along a first direction, and are spaced apart from each other, from each other, and from each other to provide insulation. The lengths of the plurality of first conductive structures and the plurality of second conductive structures vary in a stepped manner. The first conductive structures and the second conductive structures form word lines. Word lines are easy to fabricate and easy to lead out, facilitating the formation of other structures on the word lines to achieve electrical connection between the word lines and peripheral circuits.

[0018] According to some embodiments, a second aspect of this disclosure provides a memory comprising: a substrate including a device region; a device layer located above the device region, the device layer including a plurality of spaced-apart channel structures; a word line structure including a plurality of spaced-apart word lines extending along a first direction, the lengths of the plurality of word lines varying in a stepped manner; and a bit line structure including a plurality of spaced-apart bit lines extending along a second direction; wherein the word lines penetrate the device layer and surround the channel structures, the bit lines penetrate the device layer and are electrically connected to the channel structures, and the channel structures are also electrically connected to a memory node.

[0019] In some possible embodiments, the substrate further includes a first connection region and a second connection region, the device region is located between the first connection region and the second connection region, and the lengths of the multiple word lines located above the first connection region and the multiple word lines located above the second connection region are stepped.

[0020] In some possible embodiments, each word line surrounds a plurality of channel structures spaced apart in the first direction, each bit line connects to one end of a plurality of channel structures spaced apart in the second direction, and the other end of the channel structures connects to the memory node.

[0021] In some possible embodiments, the substrate located in the device region is spaced apart from the substrates located in the first connection region and the second connection region.

[0022] The memory provided in the embodiments of this disclosure has at least the following advantages:

[0023] In the memory provided in this embodiment, a device layer is disposed above the device region of the substrate. The device layer includes multiple spaced-apart channel structures, multiple spaced-apart bit lines extending along a second direction, the bit lines penetrating the device layer and electrically connected to the channel structures, and the channel structures also electrically connected to the memory nodes; multiple spaced-apart word lines extending along a first direction, their lengths varying in a stepped manner, the word lines penetrating the device layer and electrically connected to the channel structures. By forming stepped word lines, the word lines are brought out, facilitating word line fabrication and the formation of other structures on the word lines to achieve electrical connection between the word lines and peripheral circuits.

[0024] According to some embodiments, a third aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0025] Provide substrate;

[0026] A conductive structure is formed on the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart and extend in a first direction. The lengths of the plurality of first conductive structures and the plurality of second conductive structures all vary in a stepped manner.

[0027] In some possible embodiments, the substrate includes a device region and a first connection region and a second connection region respectively disposed on both sides of the device region; the first conductive structure is located above the device region and extends to the first connection region, and the second conductive structure is located above the device region and extends to the second connection region; the length of the first conductive structure located above the first connection region varies in a stepped manner, and the length of the second conductive structure located above the second connection region varies in a stepped manner.

[0028] In some possible embodiments, a conductive structure is formed over the substrate, including:

[0029] A first stacked structure, a second stacked structure, and a third stacked structure are formed in the device region, the first connection region, and the second connection region of the substrate, respectively. The first stacked structure includes alternating stacked first sacrificial layers and device layers, the second stacked structure includes alternating stacked second sacrificial layers and first active layers, and the third stacked structure includes alternating stacked third sacrificial layers and second active layers. A plurality of first active layers correspond one-to-one with the device layers in the first part, and a plurality of second active layers correspond one-to-one with the device layers in the second part.

[0030] Remove the first sacrificial layer and a portion of the device layer to form a plurality of spaced-apart channel structures for each device layer;

[0031] Remove a portion of the first active layer and a portion of the second active layer that are far from the channel structure, so that the lengths of the remaining first active layer and second active layer both change in a stepped manner;

[0032] A first conductive structure is formed on the first active layer and the corresponding channel structure, and a second conductive structure is formed on the second active layer and the corresponding channel structure.

[0033] In some possible embodiments, a plurality of first active layers correspond to and are disposed on the same layer as the odd-numbered device layers, and a plurality of second active layers correspond to and are disposed on the same layer as the even-numbered device layers.

[0034] In some possible embodiments, before forming a first conductive structure on the first active layer and the corresponding channel structure, and before forming a second conductive structure on the second active layer and the corresponding channel structure, the method further includes:

[0035] Insulating materials are deposited on the first active layer, the second active layer, and the channel structure. The insulating material on the first active layer forms a first insulating layer, the insulating material on the channel structure forms a dielectric layer, and the insulating material on the second active layer forms a second insulating layer. The first insulating layer, the dielectric layer, and the second insulating layer are all spaced apart.

[0036] In some possible embodiments, after forming the conductive structure over the substrate, the method further includes:

[0037] Multiple contact plugs are formed at intervals. The contact plugs include first contact plugs and second contact plugs. The multiple first contact plugs correspond one-to-one with and are electrically connected to the multiple first conductive structures. The multiple second contact plugs correspond one-to-one with and are electrically connected to the multiple second conductive structures. The lengths of the multiple second contact plugs and the multiple second contact plugs all change in a stepped manner.

[0038] The method for fabricating a semiconductor structure provided in this disclosure has at least the following advantages:

[0039] In the semiconductor structure fabrication method provided in this disclosure, a conductive structure is formed above a substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that extend in a first direction at intervals. The lengths of the plurality of first conductive structures and the plurality of second conductive structures are all stepped. The first conductive structures and the second conductive structures form word lines. The word lines are easy to fabricate and easy to lead out, so as to facilitate the formation of other structures on the word lines to realize the electrical connection between the word lines and the peripheral circuits. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the semiconductor structure in one embodiment of the present disclosure;

[0042] Figure 2 This is an architectural diagram of a memory according to an embodiment of the present disclosure;

[0043] Figure 3 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0044] Figure 4 This is a schematic diagram of the structure after forming the first stacked structure, the second stacked structure and the third stacked structure in one embodiment of the present disclosure;

[0045] Figure 5 This is a schematic diagram of the structure after the first trench is formed in one embodiment of the present disclosure;

[0046] Figure 6 This is a schematic diagram of the structure after the channel structure is formed in one embodiment of the present disclosure;

[0047] Figure 7 This is a schematic diagram of the structure after removing a portion of the first active layer and a portion of the second active layer in one embodiment of this disclosure;

[0048] Figure 8 This is a schematic diagram of the structure after forming the first conductive structure and the second conductive structure in one embodiment of the present disclosure. Detailed Implementation

[0049] In related technologies, to further increase the storage capacity of memory, capacitors are typically placed horizontally, meaning their extension direction is parallel to the substrate, to facilitate capacitor fabrication. When capacitors are placed horizontally, the corresponding bit line and word line structures need to be rearranged, making memory fabrication more difficult.

[0050] In view of this, the present disclosure provides a semiconductor structure and its fabrication method, and a memory, by setting a plurality of first conductive structures and a plurality of second conductive structures above a substrate, wherein the lengths of the plurality of first conductive structures and the plurality of second conductive structures are all stepped, the first conductive structures and the second conductive structures form word lines, the word lines are easy to fabricate and easy to lead out, and it is easy to form other structures on the word lines to realize the electrical connection between the word lines and the peripheral circuits.

[0051] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0052] See Figure 1 The first aspect of this disclosure provides a semiconductor structure, which includes a substrate 10 and a conductive structure located above the substrate 10. The substrate 10 can be made of semiconductor material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium-on-insulator (GOI), silicon-on-insulator (SOI), or other materials known to those skilled in the art.

[0053] Continue reading Figure 1 The conductive structure includes a plurality of first conductive structures 50 and a plurality of second conductive structures 60 arranged at intervals. The plurality of first conductive structures 50 and the plurality of second conductive structures 60 extend along a first direction, and the lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 change in a stepped manner.

[0054] The aforementioned "multiple first conductive structures 50 and multiple second conductive structures 60 spaced apart" refers to the following: multiple first conductive structures 50 and multiple second conductive structures 60 are stacked along a second direction, with the multiple first conductive structures 50 spaced apart and the multiple second conductive structures 60 spaced apart, to ensure insulation between each first conductive structure 50 and each second conductive structure 60. The second direction may intersect with the first direction; preferably, the second direction is perpendicular to the first direction, so that the multiple first conductive structures 50 and multiple second conductive structures 60 are arranged more compactly. For example, the first direction is a direction parallel to the substrate 10. Figure 1 The X direction is shown), and the second direction is the direction perpendicular to the substrate 10. Figure 1 Y direction shown).

[0055] With this configuration, the lengths of the multiple first conductive structures 50 and the multiple second conductive structures 60 all vary in a stepped manner. The first conductive structures 50 and the second conductive structures 60 form word lines, so that each word line has a lead-out end. The word lines are easy to manufacture and easy to lead out, and it is easy to form other structures on the word lines to realize the electrical connection between the word lines and the peripheral circuits.

[0056] Specifically, the projections of the multiple first conductive structures 50 and the multiple second conductive structures 60 onto the substrate 10 have a partial overlap area. At least one first conductive structure 50 is located between the multiple second conductive structures 60, or at least one second conductive structure 60 is located between the multiple first conductive structures 50, to achieve a stacked arrangement of the multiple first conductive structures 50 and the multiple second conductive structures 60. This arrangement can make full use of the space above the substrate 10, and the leads of the first conductive structures 50 and the second conductive structures 60 are distributed relatively evenly.

[0057] Preferably, a plurality of first conductive structures 50 and a plurality of second conductive structures 60 are arranged alternately along a second direction. That is, a second conductive structure 60 is disposed between every two adjacent first conductive structures 50, or a first conductive structure 50 is disposed between every two adjacent second conductive structures 60. With this arrangement, the distance between two adjacent first conductive structures 50 and the distance between two adjacent second conductive structures 60 are approximately equal along the second direction, and the leads of the first conductive structures 50 and the leads of the second conductive structures 60 are more evenly distributed, making the first conductive structures 50 and the second conductive structures 60 nearly symmetrical, so as to make full use of the space above the substrate 10.

[0058] Continue reading Figure 1 Multiple first conductive structures 50 extend along a first direction, and the lengths of the multiple first conductive structures 50 vary in a stepped manner; multiple second conductive structures 60 extend along the first direction, and the lengths of the multiple second conductive structures 60 vary in a stepped manner. With this arrangement, each first conductive structure 50 and each second conductive structure 60 is partially exposed, and this portion can be used as a lead-out terminal for the first conductive structure 50 and each second conductive structure 60, thereby facilitating the lead-out of each first conductive structure 50 and each second conductive structure 60 for connection to external circuits.

[0059] In one possible implementation, the length of the first conductive structure 50 near the substrate 10 is greater than the length of the first conductive structure 50 away from the substrate 10, so that the lengths of the plurality of first conductive structures 50 vary in a step manner; the length of the second conductive structure 60 near the substrate 10 is greater than the length of the second conductive structure 60 away from the substrate 10, so that the lengths of the plurality of second conductive structures 60 vary in a step manner.

[0060] Specifically, along the direction away from the substrate 10, the lengths of the plurality of first conductive structures 50 decrease sequentially along the first direction, so that the portions of the plurality of first conductive structures 50 away from the second conductive structure 60 exhibit a stepped change, such as... Figure 1As shown, a step is formed at the left end of the plurality of first conductive structures 50. The lengths of the plurality of second conductive structures 60 decrease sequentially along the first direction, so that the portions of the plurality of second conductive structures 60 away from the first conductive structure 50 have a stepped change, such as... Figure 1 As shown, a step is formed at the right end of the plurality of second conductive structures 60. The ends of each first conductive structure 50 and each second conductive structure 60 that are far apart from each other are partially exposed. These ends are far away from the channel structure 23 in the middle of the substrate 10, which provides a large fabrication space and minimizes interference with the channel structure 23.

[0061] In some possible embodiments, the substrate 10 includes a device region and a first connection region and a second connection region respectively disposed on both sides of the device region. A semiconductor device, such as a transistor, is disposed on the device region. The first connection region and the second connection region are both used to lead out the semiconductor device in the device region so that the semiconductor device is electrically connected to the peripheral circuit.

[0062] The first connection area and the second connection area can be disposed on opposite sides of the device area. For example, the first connection area, the device area, and the second connection area are arranged sequentially along a first direction. The first direction is as follows: Figure 1 As shown in the horizontal direction (X direction), the first connecting region is as follows: Figure 1 As shown at point A, the device area is as follows Figure 1 As shown at point B, the second connecting region is as follows: Figure 1 As shown at point C, the first connection region is located on the left side of the device region, and the second connection region is located on the right side of the device region.

[0063] In some possible examples, the substrate 10 located in the device region, the substrate 10 located in the first connection region, and the substrate 10 located in the second connection region are integral, i.e., the substrate 10 located in the device region, the substrate 10 located in the first connection region, and the substrate 10 located in the second connection region are connected. In other possible examples, the substrate 10 located in the first connection region and / or the substrate 10 located in the second connection region are spaced apart from the substrate 10 located in the device region, i.e., at least one of the substrates 10 located in the first connection region and the substrate 10 located in the second connection region has a gap with the substrate 10 located in the device region. Preferably, the substrates 10 located in the first connection region, the substrate 10 located in the second connection region, and the substrate 10 located in the device region are all spaced apart to facilitate the provision of the substrate 10 and the subsequent formation of the desired structures on the substrate 10.

[0064] Based on the above embodiments, that is, based on the substrate 10 including a device region and a first connection region and a second connection region respectively disposed on both sides of the device region, in some possible implementations, the first conductive structure 50 is located above the device region and extends to the first connection region, and the second conductive structure 60 is located above the device region and extends to the second connection region; the length of the first conductive structure 50 located above the first connection region changes in a step, and the length of the second conductive structure 60 located above the second connection region changes in a step.

[0065] like Figure 1 As shown, a first conductive structure 50 is disposed above the device region and above the first connection region; a second conductive structure 60 is disposed above the device region and above the second connection region. The length of the first conductive structure 50 above the first connection region varies in a stepped manner, forming a first step, through which the first conductive structure 50 extends. The length of the second conductive structure 60 above the second connection region varies in a stepped manner, forming a second step, through which the second conductive structure 60 extends.

[0066] In some possible embodiments, the device region is provided with a plurality of spaced-apart channel structures 23, and each first conductive structure 50 and each second conductive structure 60 located above the device region surrounds the plurality of spaced-apart channel structures 23. A dielectric layer is provided between the first conductive structure 50 and the channel structure 23, and between the second conductive structure 60 and the channel structure 23.

[0067] like Figure 1 As shown, there can be multiple channel structures 23, which are arranged in an array. The multiple channel structures 23 are not only spaced apart along a first direction, but also spaced apart along a second direction, and each channel structure 23 extends along a third direction. The first and second directions intersect each other and are both perpendicular to the third direction. In this embodiment, the first and second directions are perpendicular to each other. This arrangement allows for a more compact and optimized arrangement of the channel structures 23, maximizing the number of channel structures 23 and increasing the storage density of the semiconductor structure. Of course, this embodiment does not limit the angle between the first and second directions; users can choose according to actual needs.

[0068] Specifically, a source and a drain are respectively disposed at both ends of the channel structure 23. The source, channel structure 23, and drain form an active pillar, which is stacked sequentially along a third direction. That is, the extension direction of the active pillar is the third direction, and the transistors subsequently formed are placed along the third direction, which is parallel to the substrate 10. The shape of the active pillar can be a cylinder, prism, cuboid, or other shape. This embodiment does not limit the shape of the active pillar, and users can choose according to actual needs.

[0069] Each first conductive structure 50 located above the device region surrounds a plurality of spaced-apart channel structures 23, and each second conductive structure 60 located above the device region surrounds a plurality of spaced-apart channel structures 23. Both the first conductive structure 50 and the second conductive structure 60 located above the device region form a gate. A dielectric layer (not shown in the figure) is disposed between the first conductive structure 50 and the channel structure 23, and a dielectric layer is disposed between the second conductive structure 60 and the channel structure 23. The gate, dielectric layer, and active pillar form a gate all around (GAA) transistor. Compared to planar transistors, GAA transistors have smaller feature sizes and can effectively improve the integration density of the semiconductor structure and increase the storage capacity while occupying the same substrate area 10.

[0070] Continue reading Figure 1 Each first conductive structure 50 located above the first connection region surrounds the first active layer 31, and a first insulating layer (not shown in the figure) is disposed between the first conductive structure 50 and the first active layer 31; each second conductive structure 60 located above the second connection region surrounds the second active layer 41, and a second insulating layer (not shown in the figure) is disposed between the second conductive structure 60 and the second active layer 41.

[0071] Each first conductive structure 50 located above the first connection region is used to lead out the corresponding gate above the device region; each second conductive structure 60 located above the second connection region is used to lead out the corresponding gate of the device region. That is, the gate of the transistor above the device region is led out through the first conductive structure 50 of the first connection region and the second conductive structure 60 of the second connection region respectively to connect to the peripheral circuit.

[0072] Specifically, each first conductive structure 50 located above the first connection region surrounds the first active layer 31. The first active layer 31 can serve as a support layer for the first conductive structure 50, facilitating the formation of the first conductive structure 50 thereon. A first insulating layer is disposed between the first conductive structure 50 and the first active layer 31. The material of the first insulating layer can be the same as that of the dielectric layer, so that the first insulating layer and the dielectric layer are formed simultaneously. This allows the first conductive structure 50 above the first connection region and the first conductive structure 50 above the device region to be formed simultaneously, simplifying the semiconductor structure fabrication process.

[0073] Each second conductive structure 60 located above the second connection region surrounds the second active layer 41. The second active layer 41 can serve as a support layer for the second conductive structure 60, facilitating the formation of the second conductive structure 60 thereon. A second insulating layer is disposed between the second conductive structure 60 and the second active layer 41. The material of the second insulating layer can be the same as that of the dielectric layer, allowing the second insulating layer and the dielectric layer to be formed simultaneously. This enables the second conductive structure 60 above the second connection region and the second conductive structure 60 above the device region to be formed simultaneously, simplifying the semiconductor structure fabrication process.

[0074] Furthermore, the first insulating layer, the second insulating layer, and the dielectric layer are made of the same material, thereby enabling the simultaneous formation of each first conductive structure 50 and each second conductive structure 60, further simplifying the semiconductor structure fabrication process. The first insulating layer, the second insulating layer, and the dielectric layer can be made of oxides, such as silicon oxide, hafnium oxide, or zirconium oxide.

[0075] In some possible embodiments, the first active layer 31 corresponding to the same first conductive structure 50 and the multiple channel structures 23 are disposed in the same layer, and the second active layer 41 corresponding to the same second conductive structure 60 and the multiple channel structures 23 are disposed in the same layer.

[0076] like Figure 1 As shown, each first conductive structure 50 located above the device region surrounds multiple spaced-apart channel structures 23, and each first conductive structure 50 located above the first connection region surrounds a first active layer 31. The first active layer 31 corresponding to the same first conductive structure 50 and the multiple channel structures 23 are disposed in the same layer, thereby optimizing the arrangement of the first conductive structures 50, reducing their space occupation, and resulting in more uniform thickness and better flatness of the first conductive structures 50.

[0077] Similarly, each second conductive structure 60 located above the device region surrounds multiple spaced-apart channel structures 23, and each second conductive structure 60 located above the second connection region surrounds the second active layer 41. The second active layer 41 corresponding to the same second conductive structure 60 and the multiple channel structures 23 are disposed in the same layer, thereby optimizing the arrangement of the second conductive structures 60, reducing their space occupation, and resulting in more uniform thickness and better flatness.

[0078] Continue reading Figure 1 The semiconductor structure also includes a plurality of spaced-apart contact plugs, including first contact plugs 70 and second contact plugs 80. Each of the first contact plugs 70 corresponds to and is electrically connected to a plurality of first conductive structures 50; each of the second contact plugs 80 corresponds to and is electrically connected to a plurality of second conductive structures 60. The multiple contact plugs are used to electrically connect the first conductive structures 50 and the second conductive structures 60 to peripheral circuits. The multiple contact plugs are spaced apart to ensure insulation and isolation between them, thereby avoiding mutual interference between the first conductive structures 50 or between the second conductive structures 60.

[0079] Specifically, the contact plugs include first contact plugs 70 and second contact plugs 80. The number of first contact plugs 70 is adapted to the number of first conductive structures 50, so that multiple first contact plugs 70 correspond one-to-one with multiple first conductive structures 50 and are electrically connected. This allows each first conductive structure 50 to be electrically connected to an external circuit, through which the external circuit controls the transistor corresponding to the first conductive structure 50. The number of second contact plugs 80 is adapted to the number of second conductive structures 60, so that multiple second contact plugs 80 correspond one-to-one with multiple second conductive structures 60 and are electrically connected. This allows each second conductive structure 60 to be electrically connected to an external circuit, through which the external circuit controls the transistor corresponding to the second conductive structure 60.

[0080] For example, each first conductive structure 50 and each second conductive structure 60 has a first surface and a second surface disposed opposite to each other, wherein the first surface is the side away from the substrate 10 and the second surface is the side closer to the substrate 10. A first contact plug 70 is in contact with the first surface of the first conductive structure 50, and a second contact plug 80 is in contact with the first surface of the second conductive structure 60.

[0081] like Figure 1As shown, multiple first contact plugs 70 and multiple second contact plugs 80 extend along a second direction, and the lengths of both the first contact plugs 70 and the second contact plugs 80 vary in a stepped manner. The multiple first contact plugs 70 and the multiple second contact plugs 80 can be arranged along a first direction. This arrangement reduces the space occupied by the multiple first contact plugs 70 and the multiple second contact plugs 80, which is beneficial for increasing the number of transistors and thus improving the storage density of the semiconductor structure. Preferably, the multiple first contact plugs 70 and the multiple second contact plugs 80 are located in the same row along the first direction to further reduce the space occupied by the multiple first contact plugs 70 and the multiple second contact plugs 80.

[0082] The lengths of the multiple first contact plugs 70 and the multiple second contact plugs 80 vary in a stepped manner, with the length direction being the second direction. This arrangement ensures that the lengths of the multiple first contact plugs 70 and the multiple second contact plugs 80 are approximately equal, and the paths between the peripheral circuit and the first conductive structure 50, as well as between the peripheral circuit and the second conductive structure 60, are approximately equal, thereby minimizing the differences in the operating states of the transistors in the device region.

[0083] Continue reading Figure 1 Both the first contact plug 70 and the second contact plug 80 include a first conductive portion and a second conductive portion disposed on the first conductive portion. The size of the first conductive portion is smaller than the size of the second conductive portion. The first conductive portion is the part closer to the substrate 10, and the second conductive portion is the part farther from the substrate 10; that is, the second conductive portion is located on the side of the first conductive portion away from the substrate 10. The first conductive portion of the first contact plug 70 is in contact with the first conductive structure 50, and the first conductive portion of the second contact plug 80 is in contact with the second conductive structure 60. The size of the first conductive portion can refer to its diameter or cross-sectional area, and the size of the second conductive portion can refer to its diameter or cross-sectional area. Figure 1 As shown, the orthogonal projection of the second conductive portion on the substrate 10 covers the orthogonal projection of the first conductive portion on the substrate 10.

[0084] Both the first and second conductive portions may include a core layer and an outer layer covering the sides and bottom of the core layer. The core layer may be an insulating layer, made of silicon nitride or silicon oxide. The outer layer may be a metal layer, made of tungsten or titanium nitride. This configuration reduces the thickness of the metal layer while maintaining the electrical performance of both the first and second conductive portions, thus saving costs.

[0085] In summary, in the semiconductor structure provided by this embodiment, a plurality of first conductive structures 50 and a plurality of second conductive structures 60 are disposed above the substrate 10. Both the plurality of first conductive structures 50 and the plurality of second conductive structures 60 extend along a first direction, and are spaced apart from each other, from each other, and from each other to provide insulation. The lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 vary in a stepped manner. The first conductive structures 50 and the second conductive structures 60 form word lines. Word lines are easy to fabricate and easy to lead out, facilitating the formation of other structures on the word lines to achieve electrical connection between the word lines and peripheral circuits.

[0086] See Figure 1 and Figure 2 This disclosure also provides a memory, which may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change random access memory (PRAM), or magneto-resistive random access memory (MRAM). This disclosure uses DRAM as an example for illustration.

[0087] like Figure 1 and Figure 2 As shown, the memory includes a substrate 10, a device layer, a word line structure 2, and a bit line structure 1. The substrate 10 can be made of a semiconductor substrate, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanium, germanium-on-insulator, or silicon-on-insulator.

[0088] The substrate 10 includes a device region, and a device layer is disposed above the device region. The device layer includes a plurality of spaced-apart channel structures 23. In some possible embodiments, the substrate 10 further includes a first connection region and a second connection region, with the device region located between the first connection region and the second connection region. The first connection region and the second connection region are used to lead out word line structures 2. Exemplarily, the first connection region, the device region, and the second connection region are arranged sequentially along a first direction. The substrate 10 located in the device region and the substrate 10 located in the first connection region and the second connection region are spaced apart to facilitate the provision of the substrate 10 and the formation of the desired structures on the substrate 10.

[0089] Multiple channel structures 23 can be arranged in an array, and the multiple channel structures 23 are not only spaced apart along the first direction, but also spaced apart along the second direction, and extend along the third direction; the first direction ( Figure 1 The X direction shown) and the second direction ( Figure 1 The Y-direction shown intersects with each other and is also perpendicular to a third direction (as shown). Figure 2 (As shown in the Z direction) perpendicular. This arrangement allows for a more compact and optimized arrangement of the channel structures 23, maximizing the number of channel structures 23 and increasing the storage density of the semiconductor structure.

[0090] A source and a drain are respectively disposed at both ends of the channel structure 23. The source, channel structure 23, and drain form an active pillar. The source, channel structure 23, and drain are stacked sequentially along a third direction, that is, the extension direction of the active pillar is the third direction. The shape of the active pillar can be a cylinder, prism, cuboid, or other shape. The third direction is parallel to the substrate 10, that is, the extension direction of the active pillar is parallel to the substrate 10.

[0091] Word line structure 2 includes multiple spaced word lines extending along a first direction. The lengths of the word lines vary in a stepped manner. The word lines penetrate the device layer and surround the channel structure 23. The word lines are used to control whether there is conduction between the source and drain. Bit line structure 1 includes multiple spaced bit lines extending along a second direction. The bit lines penetrate the device layer and are electrically connected to the channel structure 23, which is also electrically connected to the memory node. The bit lines are used to read data information from the memory node.

[0092] Specifically, each word line surrounds multiple channel structures 23 spaced apart in a first direction, and each bit line connects to one end of multiple channel structures 23 spaced apart in a second direction. The other end of the channel structure 23 is connected to a memory node. For example, one end of the channel structure 23 is the drain, which is in contact with the bit line; the other end of the channel structure 23 is the source, which is in contact with the memory node, which can be a capacitor 4.

[0093] In embodiments where the substrate 10 further includes a first connection region and a second connection region, the lengths of a plurality of word lines located above the first connection region vary in a stepped manner, and the lengths of a plurality of word lines located above the second connection region also vary in a stepped manner.

[0094] A portion of the word lines are located in the device region and extend to the first connection region, while the remaining word lines are located in the device region and extend to the second connection region. The word lines located in the device region serve as gates, and a dielectric layer is also disposed between the word lines and the channel structure 23. The gate, source, drain, channel structure 23, and dielectric layer form a transistor 3. This transistor 3 is a full-ring gate transistor. Compared to planar transistors, full-ring gate transistors have smaller feature sizes and can effectively improve the integration density of the semiconductor structure and increase the storage capacity while occupying the same substrate area 10.

[0095] The word lines above the first connection area have varying lengths in a stepped manner, creating a step along the second direction. The word lines above the second connection area also exhibit structural variations, creating a step along the second direction during writing. The portions of the word lines above the first and second connection areas serve as gate leads, facilitating connection to external circuitry.

[0096] In some possible examples, each word line above the first connection region surrounds a first active layer 31, which can serve as a support layer for the word line to facilitate its formation. A first insulating layer is disposed between the word line on the first connection region and the first active layer 31. Each word line above the second connection region surrounds a second active layer 41, which can serve as a support layer for the word line to facilitate its formation. A second insulating layer is disposed between the word line on the second connection region and the second active layer 41.

[0097] It should be noted that the memory also includes multiple support layers and isolation layers. The support layers are disposed between adjacent transistors 3 along the second direction, and the isolation layers fill the spaces between word lines. The support layers facilitate the stacking of transistors 3 in the second direction and provide electrical isolation between adjacent transistors 3. The isolation layers provide electrical isolation between adjacent transistors 3, preventing mutual interference.

[0098] In some possible embodiments, the memory further includes a plurality of spaced-apart contact plugs, each corresponding to and electrically connected to a word line to connect the word lines to peripheral circuitry. The contact plugs include a plurality of first contact plugs 70 located in a first connection region and a plurality of second contact plugs 80 located in a second connection region. Both the plurality of first contact plugs 70 and the plurality of second contact plugs 80 extend along a second direction, and the lengths of both the plurality of first contact plugs 70 and the plurality of second contact plugs 80 vary in a stepped manner. This arrangement ensures that the lengths of the plurality of first contact plugs 70 and the plurality of second contact plugs 80 are approximately equal, and the paths between the peripheral circuitry and each word line are approximately equal, thereby minimizing the differences in the operating states of the transistors in the device region.

[0099] In summary, in the memory provided by this embodiment, a device layer is disposed above the device region of the substrate 10. The device layer includes multiple spaced-apart channel structures 23, multiple bit lines spaced-apart and extending along a second direction, the bit lines penetrating the device layer and electrically connected to the channel structures 23, and the channel structures 23 are also electrically connected to the memory nodes; multiple word lines spaced-apart and extending along a first direction, their lengths varying in a stepped manner, the word lines penetrating the device layer and electrically connected to the channel structures 23. By forming stepped word lines, the word lines are brought out, facilitating the fabrication of the word lines and the formation of other structures on the word lines to achieve electrical connection between the word lines and peripheral circuits.

[0100] See Figure 3 This disclosure also provides a method for fabricating a semiconductor structure, the method comprising:

[0101] Step S10: Provide a substrate.

[0102] See Figure 4 The substrate 10 can be made of semiconductor substrate, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium-on-insulator, or silicon-on-insulator. In some possible embodiments, the substrate 10 includes a device region and a first connection region and a second connection region respectively disposed on both sides of the device region. A semiconductor device, such as a transistor, is disposed on the device region. Both the first and second connection regions are used to lead out the semiconductor device in the device region so that the semiconductor device is electrically connected to a peripheral circuit.

[0103] For example, the first connection region (such as Figure 4 As shown at point A in the middle), device area (such as...) Figure 4 (as shown at point B) and the second connection region (as shown at point B) Figure 4 As shown at point C, they are arranged sequentially along the first direction. The first direction is as follows: Figure 1 In the horizontal direction (X direction) shown, the first connection region is located on the left side of the device region, and the second connection region is located on the right side of the device region. The substrate 10 in the device region, the substrate 10 in the first connection region, and the substrate 10 in the second connection region can be a single unit or spaced apart. For example, at least one of the substrates 10 in the first connection region and the substrate 10 in the second connection region has a gap with the substrate 10 in the device region. Preferably, the substrates 10 in the first connection region, the substrate 10 in the second connection region, and the substrate 10 in the device region are all spaced apart to facilitate the provision of the substrates 10 and the formation of the desired structures on the substrates 10.

[0104] Step S20: A conductive structure is formed above the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart and extend in a first direction. The lengths of the plurality of first conductive structures and the plurality of second conductive structures are all stepped.

[0105] See Figures 5 to 8 Multiple first conductive structures 50 and multiple second conductive structures 60 are stacked along a second direction, with the first conductive structures 50 spaced apart and the second conductive structures 60 spaced apart, and the first conductive structures 50 and the second conductive structures 60 spaced apart to ensure insulation between each first conductive structure 50 and each second conductive structure 60. The second direction may intersect with the first direction; preferably, the second direction is perpendicular to the first direction to make the arrangement of the multiple first conductive structures 50 and the multiple second conductive structures 60 more compact. For example, the first direction is a direction parallel to the substrate 10. Figure 8 The X direction is shown), and the second direction is the direction perpendicular to the substrate 10. Figure 8 Y direction shown).

[0106] Multiple first conductive structures 50 and multiple second conductive structures 60 are arranged alternately along a second direction. That is, a second conductive structure 60 is disposed between every two adjacent first conductive structures 50, or a first conductive structure 50 is disposed between every two adjacent second conductive structures 60. With this arrangement, the distance between two adjacent first conductive structures 50 and the distance between two adjacent second conductive structures 60 are approximately equal along the second direction, and the leads of the first conductive structures 50 and the leads of the second conductive structures 60 are more evenly distributed, making the first conductive structures 50 and the second conductive structures 60 nearly symmetrical, so as to make full use of the space above the substrate 10.

[0107] Multiple first conductive structures 50 extend along a first direction, and the lengths of the multiple first conductive structures 50 vary in a stepped manner; multiple second conductive structures 60 extend along the first direction, and the lengths of the multiple second conductive structures 60 vary in a stepped manner. This arrangement exposes a portion of each first conductive structure 50 and each second conductive structure 60, facilitating their connection to external circuitry.

[0108] Specifically, the first conductive structure 50 is located above the device region and extends to the first connection region, and the second conductive structure 60 is located above the device region and extends to the second connection region. The length of the first conductive structure 50 above the first connection region changes in a stepped manner, and the length of the second conductive structure 60 above the second connection region also changes in a stepped manner. That is, the first conductive structure 50 is positioned above both the device region and the first connection region; the second conductive structure 60 is positioned above both the device region and the second connection region. The stepped length of the first conductive structure 50 above the first connection region forms a first step, and the first conductive structure 50 extends out through the step surface of the first step. The stepped length of the second conductive structure 60 above the second connection region forms a second step, and the second conductive structure 60 extends out through the step surface of the second step.

[0109] In one specific implementation, a conductive structure is formed above the substrate 10 (step S20), including:

[0110] Step S21: A first stacked structure, a second stacked structure, and a third stacked structure are formed in the device region, the first connection region, and the second connection region of the substrate, respectively. The first stacked structure includes a first sacrificial layer and a device layer that are alternately stacked. The second stacked structure includes a second sacrificial layer and a first active layer that are alternately stacked. The third stacked structure includes a third sacrificial layer and a second active layer that are alternately stacked. Multiple first active layers correspond one-to-one with the device layers in the first part, and multiple second active layers correspond one-to-one with the device layers in the second part.

[0111] like Figure 4 As shown, a first stacked structure 20 is formed in the device region of the substrate 10, a second stacked structure 30 is formed in the first interconnect region of the substrate 10, and a third stacked structure 40 is formed in the second interconnect region of the substrate 10. The first stacked structure 20 includes a plurality of first sacrificial layers 22 and a plurality of device layers 21, which are sequentially overlapped along a second direction. The second stacked structure 30 includes a plurality of second sacrificial layers 32 and a plurality of first active layers 31, which are sequentially overlapped along a second direction. The third stacked structure 40 includes a plurality of third sacrificial layers 42 and a plurality of second active layers 41, which are sequentially overlapped along a second direction.

[0112] In this configuration, multiple first active layers 31 correspond one-to-one with the device layers 21 in the first part, and multiple second active layers 41 correspond one-to-one with the device layers 21 in the second part. Preferably, the multiple first active layers 31 correspond to the device layers 21 in the odd-numbered layers and are arranged on the same layer, and the multiple second active layers 41 correspond to the device layers 21 in the even-numbered layers and are arranged on the same layer. With this arrangement, the distance between adjacent first active layers 31 along the second direction is approximately equal to the distance between adjacent second active layers 41 along the second direction, thereby making the structure above the first connection area and the structure above the second connection area more uniformly distributed and nearly symmetrical, making full use of space.

[0113] In some possible examples, the first sacrificial layer 22 is located on the outermost side of the first stacked structure 20 near the substrate 10, i.e., the first sacrificial layer 22 is located on the substrate 10. With this configuration, each device layer 21 can subsequently form a transistor 3, increasing the number of transistors 3 and thus improving the storage density of the semiconductor structure. Correspondingly, the second sacrificial layer 32 and the third sacrificial layer 42 are also located on the substrate 10.

[0114] The first active layer 31 is made of N-doped silicon, and the first sacrificial layer 22 is made of silicon germanide. The first active layer 31, the second active layer 41, and the third active layer are made of the same material, as are the first sacrificial layer 22, the second sacrificial layer 32, and the third sacrificial layer 42. The first active layer 31, the second active layer 41, the third active layer, the first sacrificial layer 22, the second sacrificial layer 32, and the third sacrificial layer 42 can all be formed by a deposition process.

[0115] Step S22: Remove the first sacrificial layer and part of the device layer so that each device layer forms multiple spaced channel structures.

[0116] See Figure 4 and Figure 5 Multiple channel structures 23 can be arranged in an array. These channel structures 23 are not only spaced apart along a first direction, but also spaced apart along a second direction, and extend along a third direction. The first and second directions intersect each other and are both perpendicular to the third direction. This arrangement allows for a more compact and optimized arrangement of the channel structures 23, maximizing the number of channel structures 23 and increasing the storage density of the semiconductor structure.

[0117] Device layer 21 also forms source and drain electrodes located at both ends of channel structure 23, respectively. The source, channel structure 23, and drain form an active pillar, which is stacked sequentially along a third direction, i.e., the extension direction of the active pillar is the third direction. The shape of the active pillar can be a cylinder, prism, cuboid, or other shape. The third direction is parallel to the substrate 10, i.e., the extension direction of the active pillar is parallel to the substrate 10.

[0118] See also some possible implementations. Figure 5 and Figure 6 The first sacrificial layer 22 and a portion of the device layer 21 are removed so that each device layer 21 forms a plurality of spaced-apart channel structures 23, including:

[0119] Multiple spaced-apart first trenches 24 extending in a third direction are formed in the first stacked structure 20. The first trenches 24 expose the substrate 10 and separate each device layer 21 into multiple spaced-apart active pillars, each active pillar including a channel structure 23. Specifically, as shown... Figure 5 As shown, a mask layer 90 is first formed on the first stacked structure 20, the second stacked structure 30, and the third stacked structure 40. The mask layer 90 on the first stacked structure 20 has a first pattern, which exposes a portion of the surface of the first stacked structure 20. The mask layer 90 can be photoresist. Then, using the mask layer 90 as a mask, the first stacked structure 20 is etched to form a first trench 24. After the first trench 24 is formed, the mask layer 90 on the first stacked structure 20 is removed.

[0120] After forming the first trench 24, the first sacrificial layer 22 is removed using the first trench 24, so that there is a gap between the active pillars arranged in different layers. Specifically, as shown in... Figure 6 As shown, the first sacrificial layer 22 exposed in the first trench 24 is etched using a selective wet etching process to completely remove the first sacrificial layer 22, while the second sacrificial layer 32 and the third sacrificial layer 42 are not removed or are only partially removed. After removing the first sacrificial layer 22, the mask layer 90 on the second stacked structure 30 and the third stacked structure 40 is then removed.

[0121] Step S23: Remove a portion of the first active layer and a portion of the second active layer that are far from the channel structure, so that the lengths of the remaining first and second active layers both change in a stepped manner.

[0122] See Figure 6 and Figure 7 The second sacrificial layer 32 and a portion of the first active layer 31 away from the trench structure 23 are removed. The remaining length of the first active layer 31 varies in a stepped manner, forming a step, to ensure that each first active layer 31 has a partially exposed surface, facilitating the formation of other structures on it. The third sacrificial layer 42 and a portion of the second active layer 41 away from the trench structure 23 are removed. The remaining length of the second active layer 41 varies in a stepped manner, forming a step, to ensure that each second active layer 41 has a partially exposed surface, facilitating the formation of other structures on it.

[0123] Step S24: A first conductive structure is formed on the first active layer and the corresponding channel structure, and a second conductive structure is formed on the second active layer and the corresponding channel structure.

[0124] See Figure 7 and Figure 8 After the first conductive layer and the second conductive layer are formed, the lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 both exhibit a stepped variation. Specifically, the length of the first conductive structure 50 closer to the substrate 10 is greater than the length of the first conductive structure 50 farther from the substrate 10, so that the lengths of the plurality of first conductive structures 50 exhibit a stepped variation; the length of the second conductive structure 60 closer to the substrate 10 is greater than the length of the second conductive structure 60 farther from the substrate 10, so that the lengths of the plurality of second conductive structures 60 exhibit a stepped variation.

[0125] In some possible embodiments, before forming a first conductive structure 50 on the first active layer 31 and the corresponding channel structure 23, and forming a second conductive structure 60 on the second active layer 41 and the corresponding channel structure 23 (step S24), the method further includes: depositing insulating material on the first active layer 31, the second active layer 41 and the channel structure 23, wherein the insulating material on the first active layer 31 forms a first insulating layer, the insulating material on the channel structure 23 forms a dielectric layer, and the insulating material on the second active layer 41 forms a second insulating layer, wherein the first insulating layer, the dielectric layer and the second insulating layer are all spaced apart.

[0126] In other words, before forming the first conductive structure 50 and the second conductive structure 60, a dielectric layer is first formed on the surface of the channel structure 23 to ensure that the channel structure 23 is insulated from both the first conductive structure 50 and the second conductive structure 60. At the same time, a first insulating layer is formed on the surface of the first active layer 31, and a second insulating layer is formed on the surface of the second active layer 41. The dielectric layer, the first insulating layer, and the second insulating layer are formed together to ensure the flatness of the first conductive structure 50 and the second conductive structure 60.

[0127] The surface of the channel structure 23 refers to its outer peripheral surface, and the dielectric layer surrounds the channel structure 23. The surface of the first active layer 31 can refer to its outer peripheral surface, or it can refer to the two opposing surfaces of the first active layer 31 along the second direction, and the surface facing the channel structure 23. That is, the first insulating layer at least covers the two opposing surfaces of the first active layer 31 along the second direction, and the surface facing the channel structure 23. The surface of the second active layer 41 can refer to its outer peripheral surface, or it can refer to the two opposing surfaces of the second active layer 41 along the second direction, and the surface facing the channel structure 23. That is, the second insulating layer at least covers the two opposing surfaces of the second active layer 41 along the second direction, and the surface facing the channel structure 23.

[0128] After forming the first insulating layer, the dielectric layer, and the second insulating layer, conductive materials are deposited on the first insulating layer, the dielectric layer, and the second insulating layer. The conductive materials located on the first insulating layer and part of the dielectric layer form the first conductive structure 50, and the conductive materials located on the second insulating layer and another part of the dielectric layer form the second conductive structure 60.

[0129] Specifically, the first conductive structure 50 and the second conductive structure 60 serve as word lines. Each first conductive structure 50 covers a corresponding first insulating layer and a dielectric layer disposed on the same layer as the first insulating layer, and fills the spaces between the dielectric layers and between the dielectric layer and the first insulating layer. Each second conductive structure 60 covers a corresponding second insulating layer and a dielectric layer disposed on the same layer as the second insulating layer, and fills the spaces between the dielectric layers and between the dielectric layer and the second insulating layer. The first conductive structure 50 and the second conductive structure 60 covering the dielectric layer form a gate, which is part of the word line. Both the first conductive structure 50 covering the first insulating layer and the second conductive structure 60 covering the second insulating layer serve as leads of the gate for connecting to peripheral circuits.

[0130] In some possible embodiments, after forming a conductive structure on the substrate 10, the method further includes forming a plurality of spaced contact plugs, the contact plugs including first contact plugs 70 and second contact plugs 80, the plurality of first contact plugs 70 corresponding one-to-one with and electrically connected to a plurality of first conductive structures 50, the plurality of second contact plugs 80 corresponding one-to-one with and electrically connected to a plurality of second conductive structures 60, and the lengths of the plurality of first contact plugs 70 and the plurality of second contact plugs 80 are all stepped.

[0131] Multiple contact plugs are used to electrically connect the first conductive structure 50 and the second conductive structure 60 to the peripheral circuit. The multiple contact plugs are spaced apart to ensure insulation and isolation between the multiple contact plugs, thereby avoiding mutual interference between the first conductive structure 50 or the second conductive structure 60.

[0132] The number of first contact plugs 70 is adapted to the number of first conductive structures 50, so that multiple first contact plugs 70 correspond one-to-one with multiple first conductive structures 50 and are electrically connected, thereby allowing each first conductive structure 50 to be electrically connected to an external circuit, through which the external circuit controls the transistor corresponding to the first conductive structure 50. The number of second contact plugs 80 is adapted to the number of second conductive structures 60, so that multiple second contact plugs 80 correspond one-to-one with multiple second conductive structures 60 and are electrically connected, thereby allowing each second conductive structure 60 to be electrically connected to an external circuit, through which the external circuit controls the transistor corresponding to the second conductive structure 60.

[0133] Multiple first contact plugs 70 and multiple second contact plugs 80 can be arranged along a first direction. This arrangement reduces the space occupied by the multiple first contact plugs 70 and multiple second contact plugs 80, which is beneficial for increasing the number of transistors and thus improving the storage density of the semiconductor structure. Preferably, the multiple first contact plugs 70 and multiple second contact plugs 80 are located in the same row along the first direction to further reduce the space occupied by the multiple first contact plugs 70 and multiple second contact plugs 80.

[0134] The lengths of the multiple first contact plugs 70 and the multiple second contact plugs 80 vary in a stepped manner, with the length direction being the second direction. This arrangement ensures that the lengths of the multiple first contact plugs 70 and the multiple second contact plugs 80 are approximately equal, and the paths between the peripheral circuit and the first conductive structure 50, as well as between the peripheral circuit and the second conductive structure 60, are approximately equal, thereby minimizing the differences in the operating states of the transistors in the device region.

[0135] Both the first contact plug 70 and the second contact plug 80 include a first conductive portion and a second conductive portion disposed on the first conductive portion, wherein the size of the first conductive portion is smaller than the size of the second conductive portion. The first conductive portion is the part closer to the substrate 10, and the second conductive portion is the part farther from the substrate 10; that is, the second conductive portion is located on the side of the first conductive portion away from the substrate 10. The size of the first conductive portion can refer to its diameter or cross-sectional area, and the size of the second conductive portion can refer to its diameter or cross-sectional area. Figure 1 As shown, the orthogonal projection of the second conductive portion on the substrate 10 covers the orthogonal projection of the first conductive portion on the substrate 10.

[0136] Both the first and second conductive portions may include a core layer and an outer layer covering the sides and bottom of the core layer. The core layer may be an insulating layer, made of silicon nitride or silicon oxide. The outer layer may be a metal layer, made of tungsten or titanium nitride. This configuration reduces the thickness of the metal layer while maintaining the electrical performance of both the first and second conductive portions, thus saving costs.

[0137] In summary, in the semiconductor structure fabrication method provided in this disclosure, a conductive structure is formed above the substrate 10. The conductive structure includes a plurality of first conductive structures 50 and second conductive structures 60 that are spaced apart and extend in a first direction. The lengths of the plurality of first conductive structures 50 and the plurality of second conductive structures 60 are all stepped. The first conductive structures 50 and the second conductive structures 60 form word lines. The word lines are easy to fabricate and easy to lead out, so as to facilitate the formation of other structures on the word lines to achieve electrical connection between the word lines and the peripheral circuits.

[0138] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and a conductive structure located above the substrate; The substrate includes a device region, and a first connection region and a second connection region respectively disposed on both sides of the device region; The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart and extend in a first direction, wherein the lengths of the plurality of first conductive structures and the plurality of second conductive structures are all stepped. The first conductive structure is located above the device region and extends to the first connection region, and the second conductive structure is located above the device region and extends to the second connection region; The length of the first conductive structure located above the first connection area varies in a step, and the length of the second conductive structure located above the second connection area varies in a step. Each of the first conductive structures and each of the second conductive structures located above the device region surrounds a plurality of spaced-apart channel structures, and a dielectric layer is disposed between the first conductive structure and the channel structure, and between the second conductive structure and the channel structure; Each of the first conductive structures located above the first connection region surrounds the first active layer, and a first insulating layer is disposed between the first conductive structure and the first active layer; Each of the second conductive structures located above the second connection area surrounds the second active layer, and a second insulating layer is disposed between the second conductive structure and the second active layer; The first active layer corresponding to the same first conductive structure and the multiple channel structures are disposed in the same layer; the second active layer corresponding to the same second conductive structure and the multiple channel structures are disposed in the same layer. The substrate located in the device region is spaced apart from the substrates located in the first connection region and the second connection region.

2. The semiconductor structure according to claim 1, characterized in that, The length of the first conductive structure closer to the substrate is greater than the length of the first conductive structure farther from the substrate, so that the lengths of the plurality of first conductive structures vary in a stepwise manner. The length of the second conductive structure closer to the substrate is greater than the length of the second conductive structure farther from the substrate, so that the lengths of the plurality of second conductive structures vary in a stepped manner.

3. The semiconductor structure according to claim 1, characterized in that, Multiple first conductive structures and multiple second conductive structures are arranged alternately and at intervals along a second direction.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The semiconductor structure also includes a plurality of spaced-apart contact plugs, the contact plugs including a first contact plug and a second contact plug; Each of the first contact plugs corresponds to and is electrically connected to a plurality of the first conductive structures; each of the second contact plugs corresponds to and is electrically connected to a plurality of the second conductive structures.

5. The semiconductor structure according to claim 4, characterized in that, The plurality of first contact plugs and the plurality of second contact plugs extend along the second direction, and the lengths of the plurality of first contact plugs and the plurality of second contact plugs vary in a stepped manner.

6. The semiconductor structure according to claim 4, characterized in that, Both the first contact plug and the second contact plug include a first conductive portion and a second conductive portion disposed on the first conductive portion, wherein the size of the first conductive portion is smaller than the size of the second conductive portion.

7. A memory, characterized in that, include: A substrate, the substrate including a device region; the substrate further including a first connection region and a second connection region, the device region being located between the first connection region and the second connection region; A device layer is located above the device region, and the device layer includes a plurality of spaced-apart channel structures; The character line structure includes a plurality of character lines spaced apart and extending along a first direction, the lengths of the plurality of character lines varying in a stepped manner; the lengths of the plurality of character lines located above the first connecting area vary in a stepped manner, and the lengths of the plurality of character lines located above the second connecting area vary in a stepped manner. Each of the word lines surrounds a plurality of channel structures spaced apart in the first direction, and a dielectric layer is disposed between each of the word lines and the channel structures; Each word line located above the first connection area surrounds the first active layer, and a first insulating layer is provided between each word line and the first active layer; Each word line located above the second connection area surrounds the second active layer, and a second insulating layer is provided between each word line and the second active layer; The first active layer corresponding to the same word line and the multiple channel structures are disposed on the same layer; the second active layer corresponding to the same word line and the multiple channel structures are disposed on the same layer. Bit line structure, the bit line structure including a plurality of bit lines spaced apart and extending along a second direction; The word line passes through the device layer and surrounds the channel structure; the bit line passes through the device layer and is electrically connected to the channel structure; and the channel structure is also electrically connected to the memory node. The substrate located in the device region is spaced apart from the substrates located in the first connection region and the second connection region.

8. The memory according to claim 7, characterized in that, Each bit line connects to one end of a plurality of channel structures spaced apart in the second direction, and the other end of the channel structure connects to the storage node.

9. A method for fabricating a semiconductor structure, used to form the semiconductor structure according to any one of claims 1-6, characterized in that, include: Provide substrate; A conductive structure is formed on the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart and extend in a first direction. The lengths of the plurality of first conductive structures and the plurality of second conductive structures all vary in a stepped manner.

10. The manufacturing method according to claim 9, characterized in that, The substrate includes a device region, and a first connection region and a second connection region respectively disposed on both sides of the device region; The first conductive structure is located above the device region and extends to the first connection region, and the second conductive structure is located above the device region and extends to the second connection region; the length of the first conductive structure located above the first connection region varies in a step, and the length of the second conductive structure located above the second connection region varies in a step.

11. The manufacturing method according to claim 10, characterized in that, A conductive structure is formed over the substrate, including: A first stacked structure, a second stacked structure, and a third stacked structure are formed in the device region, the first connection region, and the second connection region of the substrate, respectively. The first stacked structure includes alternating stacked first sacrificial layers and device layers, the second stacked structure includes alternating stacked second sacrificial layers and first active layers, and the third stacked structure includes alternating stacked third sacrificial layers and second active layers. A plurality of first active layers correspond one-to-one with the device layers in the first part, and a plurality of second active layers correspond one-to-one with the device layers in the second part. Remove the first sacrificial layer and a portion of the device layer to form a plurality of spaced-apart channel structures for each device layer; Remove a portion of the first active layer and a portion of the second active layer that are far from the channel structure, so that the lengths of the remaining first active layer and second active layer both change in a stepped manner; A first conductive structure is formed on the first active layer and the corresponding channel structure, and a second conductive structure is formed on the second active layer and the corresponding channel structure.

12. The manufacturing method according to claim 11, characterized in that, The plurality of first active layers correspond to the device layers of the odd-numbered layers and are disposed on the same layer, and the plurality of second active layers correspond to the device layers of the even-numbered layers and are disposed on the same layer.

13. The manufacturing method according to claim 11 or 12, characterized in that, Before forming a first conductive structure on the first active layer and the corresponding channel structure, and before forming a second conductive structure on the second active layer and the corresponding channel structure, the method further includes: Insulating materials are deposited on the first active layer, the second active layer, and the channel structure. The insulating material on the first active layer forms a first insulating layer, the insulating material on the channel structure forms a dielectric layer, and the insulating material on the second active layer forms a second insulating layer. The first insulating layer, the dielectric layer, and the second insulating layer are all spaced apart.

14. The manufacturing method according to any one of claims 9-12, characterized in that, After forming the conductive structure over the substrate, the method further includes: Multiple contact plugs are formed at intervals. The contact plugs include first contact plugs and second contact plugs. The multiple first contact plugs correspond one-to-one with and are electrically connected to the multiple first conductive structures. The multiple second contact plugs correspond one-to-one with and are electrically connected to the multiple second conductive structures. The lengths of the multiple second contact plugs and the multiple second contact plugs all change in a stepped manner.

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