Input bias current compensation circuit, bipolar input rail-to-rail op amp and chip

Abstract

The application relates to the chip technical field and discloses an input bias current compensation circuit, a bipolar input rail-to-rail operational amplifier and a chip. The circuit comprises a sampling circuit, a control circuit and a mirror circuit. The sampling circuit is used for sampling input bias currents of NPN input tubes and PNP input tubes in an input stage of a rail-to-rail operational amplifier. The control circuit is used for controlling the input bias current of the NPN input tube to be turned on and the input bias current of the PNP input tube to be turned off in a first common-mode input level range, and controlling the input bias current of the NPN input tube to be turned off and the input bias current of the PNP input tube to be turned on in a second common-mode input level range. The mirror circuit is used for providing NPN mirror currents of the input bias current of the NPN input tube and PNP mirror currents of the input bias current of the PNP input tube, and outputting superimposed currents of the NPN mirror currents and the PNP mirror currents. The application can adapt to the input bias current changes caused by different common-mode input ranges through segmented compensation.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically to an input bias current compensation circuit, a bipolar input rail-to-rail operational amplifier, and a chip. Background Technology

[0002] Operational amplifiers (op-amps) are a crucial component of analog signal chain chips, and many fields require amplification of weak, low-frequency signals. Examples include temperature acquisition in industrial control, low-frequency biological information acquisition, acquisition of signals from electrocardiograms, electromyograms, and electroencephalograms in medical centers, acquisition of human body information by smart wearable devices, and monitoring of the Earth's magnetic field. Typically, the physical signals acquired in these applications are very weak and low-frequency. Front-end sensors convert these physical signals into electrical signals, with amplitudes typically in the millivolt and microvolt ranges, and frequencies generally ranging from DC to several kilohertz. Due to the small amplitude and low frequency of these signals, amplifier offset and low-frequency noise can severely affect the amplification of such signals. Therefore, there is a significant practical demand for high-precision operational amplifiers (op-amps). A common solution for low-noise, low-offset op-amps is to use bipolar transistors (BJTs) instead of MOSFETs as the input stage of the op-amp. Compared to the infinite impedance of MOS transistors, which typically have an input bias current in the fA or pA range and do not require additional compensation, the limited input impedance of bipolar transistors results in a certain bias current, typically in the nA or even uA range. In this case, in order not to affect the transmission between signals, it is generally necessary to design a compensation for this input bias current.

[0003] For an ideal operational amplifier, according to the virtual open circuit principle, the input current IB+ = IB- = 0. However, the actual performance of components is not like this. Although these two currents are very small, they still exist. The average value of this current is called the input bias current. The existence of the bias current is because the input of an op-amp is generally a long-tailed differential input based on a bipolar junction transistor (BJT) or field-effect transistor (FET) structure: For BJTs, since the transistor operates in the amplification region, a certain bias current is required, thus requiring an input current, typically in the nA to uA range; for FETs, although the FET itself is a field-controlled device, there is still a certain leakage current, but the current is very small, typically in the fA or pA range. Therefore, for bipolar input structures (i.e., transistors / BJTs), an input bias current compensation circuit is generally required to reduce its input current. The main compensation schemes for the input bias current of bipolar inputs include the following three: First, increase the input impedance, which can be achieved by connecting a resistor in series with the base of the bipolar input. However, this introduces additional input noise, and the resistor value needs to be very large to be effective. Second, specialized components are used. While special semiconductor processes can achieve ultra-high beta in BJTs, reducing the input bias current to a few nA, these processes are costly and complex. Third, an input bias current compensation circuit is employed. The main principle of this circuit is to sample the input current and then replicate a current source to compensate for it. However, existing technologies for non-rail-to-rail structures provide a constant compensation current across the entire common-mode input range. Summary of the Invention

[0004] The purpose of this invention is to provide an input bias current compensation circuit, a bipolar input rail-to-rail operational amplifier, and a chip, which adapts to the input bias current changes caused by different common-mode input ranges through segmented compensation, thereby expanding the common-mode input range that the compensation current of the bipolar input rail-to-rail operational amplifier can adapt to.

[0005] To achieve the above objectives, a first aspect of the present invention provides an input bias current compensation circuit, comprising: a sampling circuit, the sampling circuit comprising: an NPN type sampling circuit for sampling the input bias current of an NPN input transistor in the input stage of a rail-to-rail operational amplifier, and a PNP type sampling circuit for sampling the input bias current of a PNP input transistor in the bipolar input stage; and a control circuit, the control circuit comprising: an NPN type compensation control circuit for controlling the conduction of the input bias current of the NPN input transistor within a first common-mode input level range, and controlling the cutoff of the input bias current of the NPN input transistor within a second common-mode input level range; and a PNP type compensation control circuit for controlling the cutoff of the input bias current of the PNP input transistor within the first common-mode input level range, and controlling the conduction of the input bias current of the PNP input transistor within the second common-mode input level range. The PNP input transistor has an input bias current, wherein any level within the first common-mode input level range is higher than any level within the second common-mode input level range; and a mirror circuit, the mirror circuit comprising: an NPN type compensation current mirror circuit for providing an NPN mirror current of the input bias current of the NPN input transistor output by the NPN type compensation control circuit; a PNP type compensation current mirror circuit for providing a PNP mirror current of the input bias current of the PNP input transistor output by the PNP type compensation control circuit; and an output circuit for outputting a superimposed current of the NPN mirror current and the PNP mirror current, wherein the ratio of the NPN mirror current to the input bias current of the NPN input transistor is the number of NPN input transistors, and the ratio of the PNP mirror current to the input bias current of the PNP input transistor is the number of PNP input transistors.

[0006] Preferably, the NPN type compensation control circuit includes: two NPN transistors for turning on or off the input bias current of the NPN input transistor; and a first diode for controlling the turn-on voltage threshold of the two NPN transistors, wherein the turn-on voltage threshold of the two NPN transistors is the lowest level within the first common-mode input level range; and the PNP type compensation control circuit includes: two PNP transistors for turning on or off the input bias current of the NPN input transistor; and a second diode for controlling the turn-on voltage threshold of the two PNP transistors, wherein the turn-on voltage threshold of the two PNP transistors is the highest level within the second common-mode input level range.

[0007] Preferably, both the first diode and the second diode comprise two diodes.

[0008] Preferably, the two NPN transistors are connected in series, the two PNP transistors are connected in series, and the two diodes are connected in series.

[0009] Preferably, the NPN type compensation control circuit includes: two NPN transistors for turning on or off the input bias current of the NPN input transistor; and a first MOSFET for controlling the turn-on voltage threshold of the two NPN transistors, wherein the turn-on voltage threshold of the two NPN transistors is the lowest level within the first common-mode input level range; and the PNP type compensation control circuit includes: two PNP transistors for turning on or off the input bias current of the NPN input transistor; and a second MOSFET for controlling the turn-on voltage threshold of the two PNP transistors, wherein the turn-on voltage threshold of the two PNP transistors is the highest level within the second common-mode input level range.

[0010] Preferably, both the first MOSFET and the second MOSFET include two MOSFETs, wherein the two MOSFETs are connected in the form of diodes.

[0011] Preferably, the two NPN transistors are connected in series, the two PNP transistors are connected in series, and the two MOSFETs are connected in series.

[0012] Preferably, the NPN type compensation current mirror circuit includes: three P-type MOSFETs, two of which form a current mirror structure with the other P-type MOSFET, wherein the ratio of the width-to-length ratio of the two P-type MOSFETs to the width-to-length ratio of the other P-type MOSFET is the number of NPN input transistors; and the PNP type compensation current mirror circuit includes: three N-type MOSFETs, two of which form a current mirror structure with the other N-type MOSFET, wherein the ratio of the width-to-length ratio of the two N-type MOSFETs to the width-to-length ratio of the other N-type MOSFET is the number of PNP input transistors.

[0013] Preferably, the NPN type sampling circuit includes: two first current sources and an NPN transistor, wherein the two first current sources are matched with the tail current source of the NPN input transistor in the input stage, and the NPN transistor is matched with the NPN input transistor; and the PNP type sampling circuit includes: two second current sources and a PNP transistor, wherein the two second current sources are matched with the tail current source of the PNP input transistor in the input stage, and the NPN transistor is matched with the NPN input transistor.

[0014] Through the above technical solution, this invention creatively samples the input bias currents of the NPN and PNP input transistors in the input stage of a rail-to-rail operational amplifier using a sampling circuit. Then, a control circuit controls the input bias current of the NPN input transistor to be turned on and the input bias current of the PNP input transistor to be turned off within a first common-mode input level range, and controls the input bias current of the NPN input transistor to be turned off and the input bias current of the PNP input transistor to be turned on within a second common-mode input level range. Finally, a mirror circuit replicates the input bias currents of the NPN and PNP input transistors and outputs the superimposed current of the NPN and PNP mirrored currents. Therefore, this invention adapts to changes in input bias current caused by different common-mode input ranges through segmented compensation, thereby expanding the common-mode input range adaptable to the compensation current of the bipolar input rail-to-rail operational amplifier.

[0015] A second aspect of the present invention provides a bipolar input rail-to-rail operational amplifier, the bipolar input rail-to-rail operational amplifier including the aforementioned input bias current compensation circuit.

[0016] For specific details and benefits of the bipolar input rail-to-rail operational amplifier provided in the embodiments of the present invention, please refer to the above description of the input bias current compensation circuit, which will not be repeated here.

[0017] A third aspect of the present invention provides a chip, the chip comprising the aforementioned input bias current compensation circuit and / or the aforementioned bipolar input rail-to-rail operational amplifier.

[0018] For specific details and benefits of the chip provided by this invention, please refer to the above description of the input bias current compensation circuit and / or bipolar input rail-to-rail operational amplifier, which will not be repeated here.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0021] Figure 1 This is a structural diagram of an input bias current compensation circuit provided in an embodiment of the present invention; and

[0022] Figure 2 This is a structural diagram of an input bias current compensation circuit provided in an embodiment of the present invention. Detailed Implementation

[0023] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0024] Before explaining and describing the specific embodiments of the present invention in detail, let's first introduce the bipolar input rail-to-rail operational amplifier and the main design concept of the present invention.

[0025] In rail-to-rail operation, the "rail" refers to the power supply rails, i.e., the supply voltages of the two power sources for the operational amplifier (op-amp). Rail-to-rail operation means that the input signal voltage can reach or approach these two power supply rails without distortion. To achieve a rail-to-rail input structure, complementary input pairs of transistors are generally used, and their transconductance is designed. Therefore, bipolar input rail-to-rail op-amps typically include both NPN and PNP types of devices, with the input bias currents of these two types in opposite directions.

[0026] During their research, the inventors discovered that at high input common-mode levels, only the NPN transistor is on, while the PNP transistor is off, resulting in a significant inward-flowing input bias current generated by the NPN transistor. Similarly, at low common-mode levels, only the PNP transistor is on, while the NPN transistor is off, again resulting in a significant inward-flowing input bias current generated by the PNP transistor. However, at intermediate common-mode levels, both the NPN and PNP transistors are on. Theoretically, when the β values ​​of the two devices are comparable, the currents they generate can cancel each other out, requiring no compensation. Therefore, input bias current compensation for rail-to-rail structures can be performed in segments. Compared to the constant compensation across the entire common-mode input range for non-rail-to-rail structures, segmented compensation is more complex.

[0027] Specifically, the present invention controls the generation of compensation current in the high or low input range by inserting a compensation control circuit on the sampling path, thereby adapting to the input bias current characteristics of the bipolar input rail-to-rail operational amplifier.

[0028] Figure 1 This is a structural diagram of an input bias current compensation circuit provided in an embodiment of the present invention. Figure 1 As shown, the input bias current compensation circuit may include: a sampling circuit 10, a control circuit 20, and a mirror circuit 30.

[0029] The sampling circuit 10, control circuit 20, and mirror circuit 30 will be explained and described below. The output of the sampling circuit 10 is connected to the input of the control circuit 20, and the output of the control circuit 20 is connected to the input of the mirror circuit 30, as follows: Figure 1 As shown.

[0030] First, the sampling circuit 10 may include: an NPN type sampling circuit 12 for sampling the input bias current of the NPN input transistor in the input stage of the rail-to-rail operational amplifier; and a PNP type sampling circuit 14 for sampling the input bias current of the PNP input transistor in the bipolar input stage.

[0031] Specifically, the sampling circuit 10 is used to sample the input bias current of the input transistor.

[0032] Secondly, the control circuit 20 may include: an NPN type compensation control circuit 22, used to control the input bias current of the NPN input transistor to be turned on within a first common-mode input level range, and to control the input bias current of the NPN input transistor to be turned off within a second common-mode input level range; and a PNP type compensation control circuit 24, used to control the input bias current of the PNP input transistor to be turned off within the first common-mode input level range, and to control the input bias current of the PNP input transistor to be turned on within the second common-mode input level range.

[0033] Wherein, any level within the first common-mode input level range (e.g., 9-10V) is higher than any level within the second common-mode input level range (e.g., 0-1V).

[0034] Specifically, the control circuit 20 controls the threshold value of the compensation current, allowing it to provide compensation or disable compensation within a specific common-mode input range. For example, in the high common-mode input level range (e.g., 9-10V), it turns on the input bias current of the NPN input transistor (providing compensation) and turns off the input bias current of the PNP input transistor (disabling compensation); in the low common-mode input level range (e.g., 0-1V), it turns off the input bias current of the NPN input transistor (disabling compensation) and turns on the input bias current of the PNP input transistor (providing compensation). That is, the control circuit 20 controls the threshold value of the first common-mode input level range (e.g., 9V, meaning the input bias current of the NPN input transistor can be turned on at values ​​higher than 9V) and the second common-mode input level range (e.g., 1V, meaning the input bias current of the PNP input transistor can be turned on at values ​​lower than 1V), allowing it to provide compensation or disable compensation within a specific common-mode input range.

[0035] Finally, the mirror circuit 30 may include: an NPN type compensation current mirror circuit 32, used to provide an NPN mirror current for the input bias current of the NPN input transistor output by the NPN type compensation control circuit; a PNP type compensation current mirror circuit 34, used to provide a PNP mirror current for the input bias current of the PNP input transistor output by the PNP type compensation control circuit; and an output circuit 36, used to output the superimposed current of the NPN mirror current and the PNP mirror current, wherein the ratio of the NPN mirror current to the input bias current of the NPN input transistor is the number of NPN input transistors, and the ratio of the PNP mirror current to the input bias current of the PNP input transistor is the number of PNP input transistors.

[0036] Specifically, since the sampling circuit samples the input bias current of one NPN / PNP input transistor, the mirror circuit 30 provides a certain current gain based on the number of input devices. The NPN mirror current and the PNP mirror current are then superimposed and directly connected to the input stage of the operational amplifier to form the final compensation current. In fact, within the high common-mode input level range, because the input bias current of the NPN input transistor is turned on (providing compensation) and the input bias current of the PNP input transistor is turned off (disabling compensation), the superimposed current is only the input bias current of the NPN input transistor. Within the low common-mode input level range, because the input bias current of the NPN input transistor is turned off (disabling compensation) and the input bias current of the PNP input transistor is turned on (providing compensation), the superimposed current is only the input bias current of the PNP input transistor.

[0037] The specific structures of the NPN type sampling circuit 12 and the PNP type sampling circuit 14 included in the sampling circuit 10 will be explained and described below.

[0038] In one embodiment, the NPN type sampling circuit 12 may include: two first current sources (e.g., Figure 2 I1, I2) and NPN transistors (e.g., Figure 2 (Q1 in the text).

[0039] Among them, the two first current sources (e.g., Figure 2 The I1 and I2 in the NPN transistor are matched with the tail current source of the NPN input transistor in the input stage, and the NPN transistor (e.g., Figure 2 Q1) in the NPN input tube is matched with the NPN input tube.

[0040] Specifically, when the bias current sources I1 and I2 of Q1 are set to the same current as the tail current source of the NPN input transistor, the bias state of Q1 will be consistent with that of the NPN input transistor. At this time, the sampled input bias current is also consistent with the input bias current of the input transistor.

[0041] The PNP type sampling circuit 14 may include: two second current sources (e.g., Figure 2 I3, I4) and PNP transistors (e.g., Figure 2 (Q2 in the text).

[0042] Among them, the two second current sources (e.g., Figure 2 The I3 and I4 in the input stage are matched with the tail current source of the PNP input transistor in the input stage, and the NPN transistor (e.g., Figure 2 The I3 and I4 in the NPN input transistors are matched with the NPN input transistors.

[0043] Specifically, when the bias current sources I3 and I4 of Q2 are set to the same current as the tail current source of the NPN input transistor, the bias state of Q2 will be consistent with that of the NPN input transistor. At this time, the sampled input bias current is also consistent with the input bias current of the input transistor.

[0044] The specific structures of the NPN type compensation control circuit 22 and the PNP type compensation control circuit 24 included in the control circuit 20 will be explained and described below.

[0045] In one embodiment, the NPN type compensation control circuit 22 includes: two NPN transistors (e.g., Figure 2 Q3 and Q4 are used to turn on or off the input bias current of the NPN input transistor; and a first diode (not shown) is used to control the two NPN transistors (e.g., ...). Figure 2 The on-state voltage thresholds of Q3 and Q4 in the model.

[0046] Among them, the two NPN transistors (e.g., Figure 2 The on-voltage threshold of Q3 and Q4 in the first common-mode input level range (e.g., 9-10V) is the lowest level (e.g., 9V).

[0047] The first diode (not shown) may include multiple diodes. In a preferred embodiment, the first diode may include two diodes, for example, the two diodes connected in series.

[0048] Among them, the two NPN transistors (e.g., Figure 2 Q3 and Q4 in the middle are connected in series.

[0049] Specifically, the conduction voltage thresholds (e.g., 9V) of Q3 and Q4 are controlled by setting the number and / or conduction voltage of the first diodes. In this embodiment, the common-mode input levels VP and VN of the two diodes can be set to be input through Q3 and Q4 respectively. When VP and VN are in the high common-mode input level range (e.g., 9-10V), Q3 and Q4 are turned on, and the diodes are turned on, thereby conducting the input bias current of the NPN input transistor. When VP and VN are in the low common-mode input level range (e.g., 0-1V), Q3 and Q4 are turned off, thereby cutting off the input bias current of the NPN input transistor.

[0050] The PNP type compensation control circuit 24 may include: two PNP transistors (e.g., Figure 2 Q5 and Q6 (not shown) are used to turn on or off the input bias current of the NPN input transistor; and a second diode (not shown) is used to control the two PNP transistors (e.g., ...). Figure 2 The on-state voltage thresholds of Q5 and Q6 in the model.

[0051] Among them, the two PNP transistors (e.g., Figure 2 The on-voltage threshold of Q5 and Q6 in the second common-mode input level range (e.g., 1V) is the highest level (e.g., 1V) within the second common-mode input level range (e.g., 0-1V).

[0052] The second diode (not shown) may include multiple diodes. In a preferred embodiment, the second diode may include two diodes, for example, the two diodes connected in series.

[0053] Among them, the two PNP transistors (e.g., Figure 2 Q5 and Q6 in the middle are connected in series.

[0054] Specifically, the turn-on voltage thresholds (e.g., 1V) of Q5 and Q6 are controlled by setting the number and / or turn-on voltage of the second diodes. Common-mode input levels VP and VN are input through Q5 and Q6, respectively. When VP and VN are in the high common-mode input level range (e.g., 9-10V), Q5 and Q6 are cut off, thereby cutting off the input bias current of the PNP input transistor. When VP and VN are in the low common-mode input level range (e.g., 0-1V), Q5 and Q6 are turned on, and the diodes conduct, thereby conducting the input bias current of the PNP input transistor.

[0055] In another embodiment, the NPN type compensation control circuit 22 may include: two NPN transistors (e.g., Figure 2 Q3 and Q4 in the transistor are used to turn on or off the input bias current of the NPN input transistor; and the first MOSFET (which can be a P-type MOSFET or an N-type MOSFET, for example, Figure 2M1 and M2 are used to control the two NPN transistors (e.g., Figure 2 The on-state voltage thresholds of Q3 and Q4 in the model.

[0056] Among them, the two NPN transistors (e.g., Figure 2 Q3 and Q4 in series connection

[0057] Among them, the two NPN transistors (e.g., Figure 2 The on-voltage threshold of Q3 and Q4 in the first common-mode input level range (e.g., 9-10V) is the lowest level (e.g., 9V).

[0058] Specifically, the first MOSFET includes two MOSFETs (e.g., Figure 2 M1 and M2), wherein the two MOS transistors (e.g., Figure 2 M1 and M2 are connected in the form of diodes, for example, the two MOS transistors (e.g., Figure 2 M1 and M2 are connected in series. The setting of M1 and M2 allows current to flow from Q3 to Q1.

[0059] Specifically, the turn-on voltage thresholds (e.g., 9V) of Q3 and Q4 are controlled by setting the number and / or turn-on voltage of the first MOSFET. In this embodiment, two MOSFETs can be used (e.g., ...). Figure 2 (M1 and M2 in the diagram). The common-mode input levels VP and VN are input through Q3 and Q4, respectively. When VP and VN are in the high common-mode input level range (e.g., 9-10V), Q3 and Q4 are turned on, and M1 and M2 are turned on, thereby conducting the input bias current of the NPN input transistor. When VP and VN are in the low common-mode input level range (e.g., 0-1V), Q3 and Q4 are turned off, thereby cutting off the input bias current of the NPN input transistor.

[0060] M1, M2, Q3, and Q4 constitute the compensation threshold control circuit for NPN input bias current sampling. Q3 and Q4 act as switches, and the threshold voltage for the base current (i.e., IB / input bias current) of M1 and M2, which are connected in diode form, is adjusted. Thus, the IB current path will only be opened when the common-mode input level is high enough.

[0061] The PNP type compensation control circuit 24 may include: two PNP transistors (e.g., Figure 2 Q5 and Q6 in the transistor are used to turn on or off the input bias current of the NPN input transistor; and a second MOSFET (which can be a P-type MOSFET or an N-type MOSFET, for example, Figure 2 M3 and M4 are used to control the two PNP transistors (e.g., Figure 2The on-state voltage thresholds of Q5 and Q6 in the model.

[0062] Among them, the two PNP transistors (e.g., Figure 2 Q5 and Q6 in the middle are connected in series.

[0063] Among them, the two PNP transistors (e.g., Figure 2 The on-voltage threshold of Q5 and Q6 in the second common-mode input level range (e.g., 1V) is the highest level (e.g., 1V) within the second common-mode input level range (e.g., 0-1V).

[0064] Specifically, the second MOSFET includes two MOSFETs (e.g., Figure 2 M3 and M4), wherein the two MOS transistors (e.g., Figure 2 M3 and M4 in the diagram are connected in the form of diodes. For example, the two MOS transistors (e.g., Figure 2 M3 and M4 are connected in series as diodes. The arrangement of M3 and M4 allows current to flow from Q2 to Q5.

[0065] Specifically, the turn-on voltage thresholds (e.g., 1V) of Q5 and Q6 are controlled by setting the number and / or turn-on voltage of the second MOSFETs. Common-mode input levels VP and VN are input through Q5 and Q6, respectively. When VP and VN are in the high common-mode input level range (e.g., 9-10V), Q5 and Q6 are turned off, thereby cutting off the input bias current of the PNP input transistor. When VP and VN are in the low common-mode input level range (e.g., 0-1V), Q5 and Q6 are turned on, and M3 and M4 are turned on, thereby turning on the input bias current of the PNP input transistor.

[0066] M3, M4, Q5, and Q6 constitute the compensation threshold control circuit for PNP input bias current sampling. Q5 and Q6 act as switches, and the threshold voltage for the base current (i.e., IB / input bias current) of M3 and M4, which are connected in diode form, is adjusted. Thus, the IB current path will only be opened when the common-mode input level is low enough.

[0067] The specific structures of the NPN type compensation current mirror circuit 32 and the PNP type compensation current mirror circuit 34 included in the mirror circuit 30 will be explained and described below.

[0068] In one embodiment, the NPN type current mirror circuit 32 may include: three P-type MOS transistors (e.g., Figure 2 M5, M6, and M7), and two of the three P-type MOS transistors (e.g., M5, M6, and M7). Figure 2 M6 and M7 in the diagram are both connected to another P-type MOSFET (e.g., Figure 2In the M5) form a current mirror structure, wherein the two P-type MOS transistors (e.g., Figure 2 The width-to-length ratio of M6 and M7 in the transistor is the same as that of the other P-type MOS transistor (e.g., Figure 2 The aspect ratio of M5 in the NPN input transistor is the number of the NPN input transistors.

[0069] When VP and VN are within the high common-mode input level range (e.g., 9-10V), Q3 and Q4 are turned on. At this time, the diodes on the Q3 and Q4 circuits are turned on, thereby conducting the input bias current of the NPN input transistor. Q5 and Q6 are turned off, thereby cutting off the input bias current of the PNP input transistor. At the same time, M5 conducts the input bias current of the NPN input transistor. Since M5 and M6 are mirror structures, and M5 and M7 are mirror structures, a certain multiple of the input bias current of the NPN input transistors responding to VP and VN can be output through M6 and M7 (i.e., the number of NPN input transistors).

[0070] The PNP type current mirror circuit 34 includes: three N-type MOS transistors (e.g., ...). Figure 2 M8, M9, and M10), and two of the three N-type MOS transistors (e.g., M8, M9, and M10). Figure 2 M9 and M10 in the diagram are both connected to another N-type MOSFET (e.g., Figure 2 In the M8) form a current mirror structure, wherein the two N-type MOS transistors (e.g., Figure 2 The width-to-length ratio of M9 and M10 in the transistor is the same as that of the other N-type MOS transistor (e.g., Figure 2 The aspect ratio of M8 in the PNP input tube is the number of the PNP input tubes.

[0071] When VP and VN are in the low common-mode input level range (e.g., 0-1V), Q3 and Q4 are cut off, thus cutting off the input bias current of the NPN input transistor; Q5 and Q6 are turned on, and the diodes on the Q5 and Q6 circuits are turned on, thus cutting off the input bias current of the NPN input transistor and turning on the input bias current of the PNP input transistor. Simultaneously, M8 turns on the input bias current of the PNP input transistor. Since M8 and M9 are mirror images, and M8 and M10 are mirror images, a certain multiple (i.e., the number of PNP input transistors) of the input bias current of the PNP input transistors responding to VP and VN can be output through M9 and M10 respectively.

[0072] Therefore, the compensation current mirror circuit composed of M5, M6, M7, M8, M9, and M10 superimposes the gain values ​​of the replicated NPN input bias sampling current and the PNP input bias sampling current, respectively, and supplies the superimposed current output (i.e., the final input compensation current) to the input terminal of the op-amp.

[0073] The final compensation current can be configured in three ways:

[0074] (1) When only the NPN input transistor is turned on (high common-mode input level range), the current in the current summing circuit is N1 times the sampling current IB of the NPN minus the sampling current of the PNP (at this time the sampling current of the PNP is 0). The output is a positive compensation current (N1*IB-0), where N1 is the number of NPN input transistors.

[0075] (2) When only the PNP input transistor is turned on (low common mode input level range), the current in the current summing circuit is N2 times the sampling current IB of the NPN (at this time the NPN current is 0) minus the sampling current on the PNP. At this time, the output is the reverse compensation current (0-N2*IB), where N2 is the number of PNP input transistors.

[0076] (3) When both NPN and PNP input transistors are turned on or off (within the middle common-mode input level range), the sampling currents of the upper and lower paths cancel each other out or are both 0, and the output sampling current is 0.

[0077] Therefore, this invention cleverly combines the input bias current compensation circuit of NPN type and PNP type through a dual extension of the traditional structure. By using current mirror interconnection, the direction of the compensation current is controllable, making it suitable for bipolar input rail-to-rail operational amplifier structures. Compared to existing compensation methods that can only satisfy the compensation of one type of device (NPN or PNP type) at a time, this invention is designed for the complementary rail-to-rail structure, adapting to the current characteristics of bipolar input rail-to-rail structures and expanding the common-mode input range adaptable to the operational amplifier's compensation current.

[0078] At intermediate common-mode levels (e.g., 1-9V), both NPN and PNP transistors conduct. Theoretically, when the β values ​​of the two devices are equivalent, the currents they generate can cancel each other out, requiring no compensation. Therefore, the common-mode input range that can accommodate the compensation current of the extended bipolar input rail-to-rail op-amp is 0-10V.

[0079] In summary, this invention creatively samples the input bias currents of the NPN and PNP input transistors in the input stage of a rail-to-rail operational amplifier using a sampling circuit. Then, a control circuit controls the input bias current of the NPN input transistor to be turned on and the input bias current of the PNP input transistor to be turned off within a first common-mode input level range, and controls the input bias current of the NPN input transistor to be turned off and the input bias current of the PNP input transistor to be turned on within a second common-mode input level range. Finally, a mirror circuit replicates the input bias currents of the NPN and PNP input transistors and outputs the superimposed current of the NPN and PNP mirrored currents. Therefore, this invention adapts to changes in input bias current caused by different common-mode input ranges through segmented compensation, thereby expanding the common-mode input range adaptable to the compensation current of a bipolar input rail-to-rail operational amplifier.

[0080] An embodiment of the present invention also provides a bipolar input rail-to-rail operational amplifier, wherein the bipolar input rail-to-rail operational amplifier includes the aforementioned input bias current compensation circuit.

[0081] For specific details and benefits of the bipolar input rail-to-rail operational amplifier provided in the embodiments of the present invention, please refer to the above description of the input bias current compensation circuit, which will not be repeated here.

[0082] An embodiment of the present invention also provides a chip, the chip including the aforementioned input bias current compensation circuit and / or the aforementioned bipolar input rail-to-rail operational amplifier.

[0083] For specific details and benefits of the chip provided by this invention, please refer to the above description of the input bias current compensation circuit and / or bipolar input rail-to-rail operational amplifier, which will not be repeated here.

[0084] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention.

[0085] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not describe the various possible combinations separately.

[0086] Furthermore, various different implementations of the present invention can be combined arbitrarily, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed in the present invention.

Claims

1. An input bias current compensation circuit, characterized in that, The input bias current compensation circuit includes: The sampling circuit includes: an NPN type sampling circuit for sampling the input bias current of the NPN input transistor in the input stage of the rail-to-rail operational amplifier, and a PNP type sampling circuit for sampling the input bias current of the PNP input transistor in the bipolar input stage. The control circuit includes: an NPN type compensation control circuit for controlling the input bias current of the NPN input transistor to be turned on within a first common-mode input level range and controlling the input bias current of the NPN input transistor to be turned off within a second common-mode input level range; and a PNP type compensation control circuit for controlling the input bias current of the PNP input transistor to be turned off within the first common-mode input level range and controlling the input bias current of the PNP input transistor to be turned on within the second common-mode input level range, wherein any level within the first common-mode input level range is higher than any level within the second common-mode input level range. The NPN type compensation control circuit includes: two NPN transistors for turning on or off the input bias current of the NPN input transistors; and a first diode for controlling the turn-on voltage threshold of the two NPN transistors, wherein the turn-on voltage threshold of the two NPN transistors is the lowest level within the first common-mode input level range. The PNP type compensation control circuit includes: two PNP transistors for turning on or off the input bias current of the NPN input transistor; and a second diode for controlling the turn-on voltage threshold of the two PNP transistors, wherein the turn-on voltage threshold of the two PNP transistors is the highest level within the second common-mode input level range; and A mirror circuit, comprising: an NPN type compensation current mirror circuit for providing an NPN mirror current of the input bias current of the NPN input transistor output by the NPN type compensation control circuit; a PNP type compensation current mirror circuit for providing a PNP mirror current of the input bias current of the PNP input transistor output by the PNP type compensation control circuit; and an output circuit for outputting a superimposed current of the NPN mirror current and the PNP mirror current, wherein the ratio of the NPN mirror current to the input bias current of the NPN input transistor is the number of NPN input transistors, and the ratio of the PNP mirror current to the input bias current of the PNP input transistor is the number of PNP input transistors.

2. The input bias current compensation circuit according to claim 1, characterized in that, Both the first diode and the second diode consist of two diodes.

3. The input bias current compensation circuit according to claim 2, characterized in that, The two NPN transistors are connected in series, the two PNP transistors are connected in series, and the two diodes are connected in series.

4. The input bias current compensation circuit according to claim 1, characterized in that, The NPN type compensation control circuit includes: two NPN transistors for turning on or off the input bias current of the NPN input transistors; and a first MOSFET for controlling the turn-on voltage thresholds of the two NPN transistors, wherein the turn-on voltage thresholds of the two NPN transistors are the lowest level within the first common-mode input level range. The PNP type compensation control circuit includes: two PNP transistors for turning on or off the input bias current of the NPN input transistor; and a second MOSFET for controlling the turn-on voltage threshold of the two PNP transistors, wherein the turn-on voltage threshold of the two PNP transistors is the highest level within the range of the second common-mode input level.

5. The input bias current compensation circuit according to claim 4, characterized in that, Both the first MOSFET and the second MOSFET include two MOSFETs, wherein the two MOSFETs are connected in the form of diodes.

6. The input bias current compensation circuit according to claim 5, characterized in that, The two NPN transistors are connected in series, the two PNP transistors are connected in series, and the two MOSFETs are connected in series.

7. The input bias current compensation circuit according to claim 1, characterized in that, The NPN type current mirror circuit includes three P-type MOSFETs, two of which form a current mirror structure with the third P-type MOSFET. The ratio of the width-to-length ratio of the two P-type MOSFETs to the width-to-length ratio of the third P-type MOSFET is equal to the number of NPN input transistors. The PNP type compensation current mirror circuit includes three N-type MOS transistors, two of which form a current mirror structure with the other N-type MOS transistor. The ratio of the width-to-length ratio of the two N-type MOS transistors to the width-to-length ratio of the other N-type MOS transistor is the number of PNP input transistors.

8. The input bias current compensation circuit according to claim 1, characterized in that, The NPN sampling circuit includes: two first current sources and an NPN transistor, wherein the two first current sources are matched with the tail current source of the NPN input transistor in the input stage, and the NPN transistor is matched with the NPN input transistor. The PNP type sampling circuit includes two second current sources and a PNP transistor, wherein the two second current sources are matched with the tail current source of the PNP input transistor in the input stage, and the NPN transistor is matched with the NPN input transistor.

9. A bipolar input rail-to-rail operational amplifier, characterized in that, The bipolar input rail-to-rail operational amplifier includes an input bias current compensation circuit according to any one of claims 1-8.

10. A chip, characterized in that, The chip includes an input bias current compensation circuit according to any one of claims 1-8 and / or a bipolar input rail-to-rail operational amplifier according to claim 9.

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