Decision feedback equalization circuit, data receiving circuit and memory

Abstract

The present disclosure provides a decision feedback equalization circuit, a data receiving circuit and a memory. The decision feedback equalization circuit includes: a first amplification equalization circuit, which is used to output a first data signal according to an input data signal, a first reference voltage signal and a tap signal; a second amplification equalization circuit, which is used to output a second data signal according to the input data signal, the second reference voltage signal and the tap signal; a selection sampling circuit, which is coupled to both the first amplification equalization circuit and the second amplification equalization circuit, and is used to select and sample the first data signal and the second data signal according to a selection signal and a sampling clock signal, and output a target data signal; wherein the first amplification equalization circuit and the second amplification equalization circuit are operated in accordance with the selection signal. Since the selection signal enables the first amplification equalization circuit and the second amplification equalization circuit to operate in accordance with the selection signal, the operating current of the amplification equalization circuit is reduced, thereby reducing the power consumption of the decision feedback equalization circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a decision feedback equalization circuit, a data receiving circuit and a memory. Background Art

[0002] At present, in the process of receiving input data signals, in order to solve the problem of Inter Symbol Interference (ISI), a decision feedback equalizer (DFE) circuit is often used to process the input data signals. However, the decision feedback equalizer circuit has the problem of high power consumption in the process of processing the input data signals. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a decision feedback equalization circuit, a data receiving circuit and a memory.

[0005] According to a first aspect of an embodiment of the present disclosure, a decision feedback equalization circuit is provided, the decision feedback equalization circuit comprising:

[0006] A first amplifying and equalizing circuit, configured to output a first data signal according to an input data signal, a first reference voltage signal and a tap signal;

[0007] A second amplifying and equalizing circuit, configured to output a second data signal according to the input data signal, a second reference voltage signal and the tap signal;

[0008] A selection sampling circuit, the selection sampling circuit is coupled to both the first amplification and equalization circuit and the second amplification and equalization circuit, and is used to select and sample the first data signal and the second data signal according to a selection signal and a sampling clock signal, and output a target data signal;

[0009] The first amplifying and equalizing circuit and the second amplifying and equalizing circuit selectively operate according to the selection signal.

[0010] According to some embodiments of the present disclosure, the first amplification and equalization circuit includes:

[0011] a first amplifier circuit, the first amplifier circuit is coupled to the selection sampling circuit and is used to amplify a first voltage difference signal between the input data signal and the first reference voltage signal;

[0012] a first equalizing circuit, the first equalizing circuit being coupled to the first amplifying circuit and the selective sampling circuit, and being configured to perform decision feedback equalization on the input data signal according to the tap signal and the amplified first voltage difference signal, and output the first data signal;

[0013] a first gating circuit, the first gating circuit being coupled to the first amplifying circuit and configured to control the first amplifying circuit to be turned on or off according to the selection signal; and / or,

[0014] The second amplification and equalization circuit comprises:

[0015] a second amplifier circuit, the second amplifier circuit is coupled to the selection sampling circuit and is used to amplify a second voltage difference signal between the input data signal and the second reference voltage signal;

[0016] a second equalizing circuit, the second equalizing circuit being coupled to the second amplifying circuit and the selection sampling circuit, and configured to perform decision feedback equalization on the input data signal according to the tap signal and the amplified second voltage difference signal, and output the second data signal;

[0017] A second gating circuit is coupled to the second amplifying circuit and is used to control the second amplifying circuit to be turned on or off according to the selection signal.

[0018] According to some embodiments of the present disclosure, the selection signal includes a first selection signal and a second selection signal; the first gating circuit includes:

[0019] a first gating transistor, wherein the first gating transistor is coupled between the first amplifying circuit and a common terminal, and a control terminal of the first gating transistor receives the first selection signal; and / or,

[0020] The second gating circuit comprises:

[0021] A second gating transistor is coupled between the second amplifying circuit and the common terminal, and a control terminal of the second gating transistor receives the second selection signal.

[0022] According to some embodiments of the present disclosure, the first amplification circuit includes:

[0023] a first input transistor, wherein a control terminal of the first input transistor receives the first reference voltage signal;

[0024] a second input transistor, wherein a control terminal of the second input transistor receives the input data signal;

[0025] A first resistor, the first resistor is coupled between a first terminal of the first input transistor and a power supply;

[0026] a second resistor, the second resistor being coupled between the first terminal of the second input transistor and the power supply;

[0027] Wherein, the second end of the first input transistor and the second end of the second input transistor are both coupled to the first gating circuit; and / or,

[0028] The second amplifier circuit comprises:

[0029] a third input transistor, wherein a control terminal of the third input transistor receives the second reference voltage signal;

[0030] a fourth input transistor, wherein a control terminal of the fourth input transistor receives the input data signal;

[0031] a third resistor, the third resistor being coupled between the first end of the third input transistor and the power supply;

[0032] a fourth resistor, the fourth resistor being coupled between the first end of the fourth input transistor and the power supply;

[0033] The second end of the third input transistor and the second end of the fourth input transistor are both coupled to the second gating circuit.

[0034] According to some embodiments of the present disclosure, the selection sampling circuit includes:

[0035] a data selection circuit, the data selection circuit being coupled to both the first amplifying and equalizing circuit and the second amplifying and equalizing circuit, and configured to select the first data signal or the second data signal according to the selection signal;

[0036] A sampling circuit is coupled to the data selection circuit and is used to sample the signal selected by the data selection circuit according to the sampling clock signal and output the target data signal.

[0037] According to some embodiments of the present disclosure, the data selection circuit includes multiple transmission gates, the input end of each transmission gate is coupled to an output end of the first amplification and equalization circuit or the second amplification and equalization circuit, the output end of each transmission gate is coupled to the sampling circuit, and the control end of each transmission gate is coupled to the selection signal.

[0038] A second aspect of the present disclosure provides a data receiving circuit, which includes a plurality of decision feedback equalization circuits as described above.

[0039] According to some embodiments of the present disclosure, the sampling phases of the sampling clock signals received by each decision feedback equalization circuit are different, and in the sampling phase order of the sampling clock signals, the phase differences of the sampling clock signals received by the decision feedback equalization circuits with adjacent sampling phases are the same.

[0040] According to some embodiments of the present disclosure, in the sampling phase order of the sampling clock signal, the selection signal received by each decision feedback equalization circuit includes the target data signal output by the decision feedback equalization circuit corresponding to the previous sampling phase; wherein the selection signal received by the decision feedback equalization circuit corresponding to the first sampling phase is the target data signal output by the decision feedback equalization circuit corresponding to the last sampling phase.

[0041] A third aspect of the present disclosure provides a memory, comprising the data receiving circuit as described above.

[0042] In the decision feedback equalization circuit, data receiving circuit and memory provided by the embodiments of the present disclosure, the decision feedback equalization circuit includes a first amplification equalization circuit, a second amplification equalization circuit and a selection sampling circuit. The input data signal is processed by the first amplification equalization circuit and the second amplification equalization circuit with the first reference voltage signal and the second reference voltage signal to avoid misprocessing the input data signal by a single reference voltage signal so as to improve the accuracy of the target data signal. The first data signal and the second data signal are selected and sampled by the selection sampling circuit, and the target data signal is output. Since the selection signal can enable the first amplification equalization circuit and the second amplification equalization circuit to operate selectively, the operating current of the first amplification equalization circuit or the second amplification equalization circuit is reduced, thereby reducing the power consumption of the decision feedback equalization circuit. At the same time, since the first amplification equalization circuit, the second amplification equalization circuit and the selection sampling circuit reuse the selection signal, the number of control signals is reduced, thereby reducing the complexity of the decision feedback equalization circuit structure.

[0043] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 It is a structural schematic diagram of a data receiving circuit;

[0046] Figure 2 is a structural schematic diagram of a decision feedback equalization circuit according to an exemplary embodiment;

[0047] Figure 3a is a schematic structural diagram of a first amplifying and equalizing circuit according to an exemplary embodiment;

[0048] Figure 3b is a structural schematic diagram of a second amplification and equalization circuit according to an exemplary embodiment;

[0049] Figure 4a is a structural schematic diagram of a first amplifying and equalizing circuit according to another exemplary embodiment;

[0050] Figure 4b is a structural schematic diagram of a second amplifying and equalizing circuit according to another exemplary embodiment;

[0051] Figure 5a is a structural schematic diagram of a first amplifying and equalizing circuit according to another exemplary embodiment;

[0052] Figure 5b is a structural schematic diagram of a second amplifying and equalizing circuit according to another exemplary embodiment;

[0053] Figure 6a is a structural schematic diagram of a first equalization circuit according to an exemplary embodiment;

[0054] Figure 6b is a structural schematic diagram of a second equalization circuit according to an exemplary embodiment;

[0055] Figure 7a is a structural schematic diagram of a selective sampling circuit according to an exemplary embodiment;

[0056] Figure 7b is a structural schematic diagram of a selective sampling circuit according to another exemplary embodiment;

[0057] Figure 8 is a structural schematic diagram of a data selection circuit according to an exemplary embodiment;

[0058] Fig. 9 is a structural schematic diagram of a decision feedback equalization circuit according to another exemplary embodiment;

[0059] Fig.10 is a working timing diagram of a decision feedback equalization circuit according to an exemplary embodiment;

[0060] Fig.11The diagram is a structural diagram of a data receiving circuit according to an exemplary embodiment.

[0061] In the figure: 10, first amplifying and balancing circuit; 11, first amplifying circuit; 12, first balancing circuit; 13, first gating circuit; 20, second amplifying and balancing circuit; 21, second amplifying circuit; 22, second balancing circuit; 23, second gating circuit; 30, sampling circuit selection; 31, data selection circuit; 32, sampling circuit; 121, first switching circuit; 122, first compensation circuit; 221, second switching circuit; 222, second compensation circuit; CMP, comparator; Latch, latch; Qs1, first gating transistor; Qs 2, second selection transistor; Qi1, first input transistor; Qi2, second input transistor; Qi3, third input transistor; Qi4, fourth input transistor; Qt1, first switch transistor; Qt2, second switch transistor; Qt3, third switch transistor; Qt4, fourth switch transistor; Qc1, first control transistor; Qc2, second control transistor; Qc3, third control transistor; Qc4, fourth control transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; TG, transmission gate TG1, first transmission gate; TG2, second transmission gate; TG3, third transmission gate; TG4, fourth transmission gate; VCC, power supply; GND, common terminal; Data, input data signal; Vref1, first reference voltage signal; Vref2, second reference voltage signal; Tap, tap signal; Cs, selection signal; Cs1, first selection signal; Cs2, second selection signal; Clk, sampling clock signal; Clk_0, first sampling clock signal; Clk_90, second sampling clock signal; Clk_180, third sampling clock signal Sampling clock signal; Clk_270, fourth sampling clock signal; Out, target data signal; Out_0, first target data signal; Out_90, second target data signal; Out_180, third target data signal; Out_270, fourth target data signal; Out_0(n-1), previous first target data signal; Out_90(n-1), previous second target data signal; Out_180(n-1), previous third target data signal; Out_270(n-1), previous fourth target data signal. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0063] At present, when the memory receives input data signals, there is an inter-symbol interference problem, which affects the quality of receiving the input data signals. In order to solve the inter-symbol interference problem, a decision feedback equalization circuit is often used to process the input data signal to improve the quality of signal transmission.

[0064] In related technologies, such as Figure 1 As shown, Figure 1 The structural schematic diagram of a data receiving circuit is shown. The data receiving circuit includes a plurality of decision feedback equalization circuits, each decision feedback equalization circuit includes a comparator CMP and a latch Latch, and the comparison signal output by each comparator CMP is input to the comparator CMP of the next level decision feedback equalization circuit. Among them, the comparison signal output by the comparator CMP of the last level decision feedback equalization circuit is input to the comparator CMP of the first level decision feedback equalization circuit. The comparator CMP includes a first comparison branch and a second comparison branch. The first comparison branch receives the input data signal Data, the first reference voltage signal Vref1 and the comparison signal of the previous level. The second comparison branch receives the input data signal Data, the second reference voltage signal Vref2 and the comparison signal of the previous level. The comparator CMP is used to compare the input data signal Data with the first reference voltage signal Vref1 and the second reference voltage signal Vref2 respectively, and then output the comparison signal of this level in combination with the comparison signal of the previous level. The latch Latch is coupled to the comparator CMP, and is used to latch the comparison signal and then output the target data signal Out. Among them, the target data signal Out output by each level of decision feedback equalization circuit is 1 bit data in the input data signal Data. Although the decision feedback equalization circuit can solve the problem of inter-symbol interference, in the process of outputting the comparison signal, the first comparison branch and the second comparison branch are both in operation. The simultaneous operation of the first comparison branch and the second comparison branch will cause a large current in the decision feedback equalization circuit, resulting in high power consumption of the decision feedback equalization circuit.

[0065] Based on this, the present disclosure provides a decision feedback equalization circuit. Since the target data signal output by the decision feedback equalization circuit is only related to the first data signal output by the first amplification equalization circuit or the second data signal output by the second amplification equalization circuit, the first amplification equalization circuit and the second amplification equalization circuit are selectively operated through a selection signal, and the amplification equalization circuit that is not related to the target data signal is turned off. Since one amplification equalization circuit is turned off, the operating current of the first amplification equalization circuit or the second amplification equalization circuit is reduced, thereby reducing the power consumption of the decision feedback equalization circuit.

[0066] In an exemplary embodiment of the present disclosure, a decision feedback equalization circuit is provided, such as Figure 2 As shown, the decision feedback equalization circuit includes a first amplification equalization circuit 10, a second amplification equalization circuit 20 and a selection sampling circuit 30. The first amplification equalization circuit 10 receives an input data signal Data, a first reference voltage signal Vref1 and a tap signal Tap, and is used to output a first data signal according to the input data signal Data, the first reference voltage signal Vref1 and the tap signal Tap. The second amplification equalization circuit 20 receives an input data signal Data, a second reference voltage signal Vref2 and a tap signal Tap, and is used to output a second data signal according to the input data signal Data, the second reference voltage signal Vref2 and the tap signal Tap. The selection sampling circuit 30 is coupled to both the first amplification equalization circuit 10 and the second amplification equalization circuit 20, and is used to select and sample the first data signal and the second data signal according to the selection signal Cs and the sampling clock signal Clk, and output the target data signal Out. Among them, the first amplification equalization circuit 10 and the second amplification equalization circuit 20 are operated one by one according to the selection signal Cs.

[0067] In this embodiment, the decision feedback equalization circuit includes a first amplification equalization circuit, a second amplification equalization circuit and a selection sampling circuit. The first amplification equalization circuit and the second amplification equalization circuit process the input data signal with the first reference voltage signal and the second reference voltage signal, thereby avoiding the single reference voltage signal from misprocessing the input data signal to improve the accuracy of the target data signal. The first data signal and the second data signal are selected and sampled by the selection sampling circuit, and the target data signal is output. Since the selection signal enables the first amplification equalization circuit and the second amplification equalization circuit to operate selectively, the operating current of the first amplification equalization circuit or the second amplification equalization circuit is reduced, thereby reducing the power consumption of the decision feedback equalization circuit. At the same time, since the first amplification equalization circuit, the second amplification equalization circuit and the selection sampling circuit reuse the selection signal, the number of control signals is reduced, thereby reducing the complexity of the decision feedback equalization circuit structure.

[0068] Exemplarily, the first data signal includes a first in-phase data signal and a first inverted data signal, and the first in-phase data signal and the first inverted data signal are complementary signals. The second data signal includes a second in-phase data signal and a second inverted data signal, and the second in-phase data signal and the second inverted data signal are complementary signals. In addition to outputting the target data signal Out, the sampling circuit 30 can also output a complementary signal of the target data signal Out.

[0069] In some exemplary embodiments provided in the present disclosure, Figure 3a As shown, Figure 3a A schematic diagram of the structure of a first amplifying and equalizing circuit provided according to an exemplary embodiment of the present disclosure is shown. The first amplifying and equalizing circuit 10 includes a first amplifying circuit 11, a first equalizing circuit 12 and a first gating circuit 13. The first amplifying circuit 11 is coupled to the selection sampling circuit 30, receives the input data signal Data and the first reference voltage signal Vref1, and is used to amplify the first voltage difference signal of the input data signal Data and the first reference voltage signal Vref1. The first equalizing circuit 12 is coupled to the first amplifying circuit 11 and the selection sampling circuit 30, receives the tap signal Tap and the first voltage difference signal, and is used to perform decision feedback equalization on the input data signal Data according to the tap signal Tap and the amplified first voltage difference signal to output the first data signal. The first gating circuit 13 is coupled to the first amplifying circuit 11, receives the selection signal Cs, and is used to control the first amplifying circuit 11 to be turned on or off according to the selection signal Cs.

[0070] In this embodiment, the first amplifying and equalizing circuit includes a first amplifying circuit, a first equalizing circuit and a first gating circuit. The first amplifying circuit amplifies the first voltage difference signal between the input data signal and the first reference voltage signal. The first equalizing circuit performs decision feedback equalization on the input data signal to solve the problem of inter-symbol interference. The first gating circuit controls the first amplifying circuit to be turned on or off, thereby reducing the power consumption of the first amplifying and equalizing circuit.

[0071] Exemplarily, the first voltage difference signal includes a first in-phase voltage difference signal and a first inverted voltage difference signal. When the first reference voltage signal Vref1 is less than the input data signal Data, the first in-phase voltage difference signal is greater than the first inverted voltage difference signal. When the first reference voltage signal Vref1 is greater than the input data signal Data, the first in-phase voltage difference signal is less than the first inverted voltage difference signal. The first equalization circuit 12 performs decision feedback equalization on the input data signal Data according to the amplified first in-phase voltage difference signal, the amplified first inverted voltage difference signal and the tap signal Tap, and outputs the first data signal.

[0072] In some exemplary embodiments provided in the present disclosure, Figure 3b As shown, Figure 3bA schematic diagram of the structure of a second amplifying and equalizing circuit provided according to an exemplary embodiment of the present disclosure is shown. The second amplifying and equalizing circuit 20 includes a second amplifying circuit 21, a second equalizing circuit 22, and a second gating circuit 23. The second amplifying circuit 21 is coupled to the selection sampling circuit 30, and is used to amplify the second voltage difference signal of the input data signal Data and the second reference voltage signal Vref2. The second equalizing circuit 22 is coupled to the second amplifying circuit 21 and the selection sampling circuit 30, and is used to perform decision feedback equalization on the input data signal Data according to the tap signal Tap and the amplified second voltage difference signal to output the second data signal. The second gating circuit 23 is coupled to the second amplifying circuit 21, and is used to control the second amplifying circuit 21 to be turned on or off according to the selection signal Cs.

[0073] In this embodiment, the second amplifying and equalizing circuit includes a second amplifying circuit, a second equalizing circuit and a second gating circuit. The second amplifying circuit amplifies the second voltage difference signal of the input data signal and the second reference voltage signal. The second equalizing circuit performs decision feedback equalization on the input data signal to solve the problem of inter-symbol interference. The second gating circuit controls the second amplifying circuit to be turned on or off, thereby reducing the power consumption of the second amplifying and equalizing circuit.

[0074] Exemplarily, the second voltage difference signal includes a second in-phase voltage difference signal and a second inverted voltage difference signal. When the second reference voltage signal Vref2 is less than the input data signal Data, the second in-phase voltage difference signal is greater than the second inverted voltage difference signal. When the second reference voltage signal Vref2 is greater than the input data signal Data, the second in-phase voltage difference signal is less than the second inverted voltage difference signal. The second equalization circuit 22 performs decision feedback equalization on the input data signal Data according to the amplified second in-phase voltage difference signal, the amplified second inverted voltage difference signal and the tap signal Tap, and outputs a second data signal.

[0075] In some exemplary embodiments provided in the present disclosure, Figure 4a As shown, Figure 4a The schematic diagram of the structure of the first amplifying and equalizing circuit provided according to an exemplary embodiment of the present disclosure is shown. The selection signal Cs includes a first selection signal Cs1. The first gating circuit 13 includes a first gating transistor Qs1. The first gating transistor Qs1 is coupled between the first amplifying circuit 11 and the common terminal GND, and the control terminal receives the first selection signal Cs1.

[0076] In this embodiment, the first gating circuit includes a first gating transistor. Only one transistor is needed to control the on or off of the first amplifying circuit, thereby reducing the complexity of the structure of the first gating circuit.

[0077] It can be understood that, in addition to using the first selection transistor Qs1 as the first selection circuit 13, other devices or combinations of devices having a switching function may also be used as the first selection circuit 13.

[0078] In some exemplary embodiments provided in the present disclosure, Figure 4b As shown, Figure 4b The schematic diagram of the structure of the second amplifying and equalizing circuit provided according to an exemplary embodiment of the present disclosure is shown. The selection signal Cs also includes a second selection signal Cs2, and the first selection signal Cs1 and the second selection signal Cs2 are complementary signals. The second gating circuit 23 includes a second gating transistor Qs2. The second gating transistor Qs2 is coupled between the second amplifying circuit 21 and the common terminal GND, and the control terminal receives the second selection signal Cs2.

[0079] In this embodiment, the second gating circuit includes a second gating transistor, and only one transistor is needed to control the conduction or disconnection of the second amplifier circuit, thereby reducing the complexity of the second gating circuit structure. At the same time, the conduction and disconnection of the first gating transistor are controlled by the first selection signal, and the conduction and disconnection of the second gating transistor are controlled by the second selection signal, and the first gating transistor and the second gating transistor are controlled by a set of complementary signals, thereby reducing the complexity of the selection signal generation and thus reducing the complexity of the decision feedback equalization circuit structure.

[0080] It can be understood that, in addition to using the second selection transistor Qs2 as the second selection circuit 23, other devices or combinations of devices having a switching function may also be used as the second selection circuit 23.

[0081] It is understandable that, in addition to using the first selection transistor Qs1 as the first selection circuit 13 and the second selection transistor Qs2 as the second selection circuit 23, a single-pole double-throw switch can also be used as the first selection circuit 13 and the second selection circuit 23.

[0082] In one embodiment, the first selection signal Cs1 includes the previous bit data of the target data signal Out, and the second selection signal Cs2 includes the previous bit data of the complementary signal of the target data signal Out. The previous bit data of the target data signal Out is relative to the current bit data of the target data signal Out. The previous bit data of the complementary signal of the target data signal Out is relative to the current bit data of the complementary signal of the target data signal Out.

[0083] In this embodiment, the previous bit of the target data signal is used as the first selection signal, and the previous bit of the complementary signal of the target data signal is used as the second selection signal. The first selection signal and the second selection signal can turn on and off the first selection transistor and the second selection transistor according to the need of input data signal transmission. The first selection transistor, the second selection transistor and the selection sampling circuit are controlled by the target data signal and its complementary signal, which reduces the complexity of the selection signal generation, thereby reducing the complexity of the decision feedback equalization circuit structure.

[0084] In some exemplary embodiments provided in the present disclosure, Figure 5a As shown, Figure 5a A structural schematic diagram of a first amplifying and balancing circuit provided according to an exemplary embodiment of the present disclosure is shown. The first amplifier circuit 11 includes a first input transistor Qi1, a second input transistor Qi2, a first resistor R1 and a second resistor R2. The control end of the first input transistor Qi1 receives a first reference voltage signal Vref1. The control end of the second input transistor Qi2 receives an input data signal Data. The first resistor R1 is coupled between the first end of the first input transistor Qi1 and the power supply VCC. The second resistor R2 is coupled between the first end of the second input transistor Qi2 and the power supply VCC. Among them, the second end of the first input transistor Qi1 and the second end of the second input transistor Qi2 are both coupled to the first gating circuit 13. That is, coupled to the first gating transistor Qs1. The signal between the first input transistor Qi1 and the first resistor R1 is an amplified first in-phase voltage difference signal, and the signal between the second input transistor Qi2 and the second resistor R2 is an amplified first inverse voltage difference signal.

[0085] In this embodiment, the first amplifier circuit includes a first input transistor, a second input transistor, a first resistor and a second resistor, and receives a first reference voltage signal and an input data signal through the first input transistor and the second input transistor to amplify a first voltage difference signal between the input data signal and the first reference voltage signal. The first amplifier circuit is formed by two transistors and two resistors, thereby reducing the complexity of the structure of the first amplifier circuit.

[0086] In some exemplary embodiments provided in the present disclosure, Figure 5b As shown, Figure 5bA structural schematic diagram of a second amplifying and balancing circuit provided according to an exemplary embodiment of the present disclosure is shown. The second amplifying circuit includes a third input transistor Qi3, a fourth input transistor Qi4, a third resistor R3 and a fourth resistor R4. The control end of the third input transistor Qi3 receives a second reference voltage signal Vref2. The control end of the fourth input transistor Qi4 receives an input data signal Data. The third resistor R3 is coupled between the first end of the third input transistor Qi3 and the power supply VCC. The fourth resistor R4 is coupled between the first end of the fourth input transistor Qi4 and the power supply VCC. Among them, the second end of the third input transistor Qi3 and the second end of the fourth input transistor Qi4 are both coupled to the second gating circuit 23. That is, coupled to the second gating transistor Qs2. The signal between the third input transistor Qi3 and the third resistor R3 is an amplified second in-phase voltage difference signal, and the signal between the fourth input transistor Qi4 and the fourth resistor R4 is an amplified second in-phase voltage difference signal.

[0087] In this embodiment, the second amplifier circuit includes a third input transistor, a fourth input transistor, a third resistor and a fourth resistor, and receives the second reference voltage signal and the input data signal through the third input transistor and the fourth input transistor to amplify the second voltage difference signal between the input data signal and the second reference voltage signal. The second amplifier circuit is formed by two transistors and two resistors, which reduces the complexity of the second amplifier circuit structure.

[0088] Exemplarily, the amplified first in-phase voltage difference signal is processed by the first equalizing circuit 12 to become the first in-phase data signal in the first data signal. The amplified first inverse voltage difference signal is processed by the first equalizing circuit 12 to become the first inverse data signal in the first data signal. The amplified second in-phase voltage difference signal is processed by the second equalizing circuit 22 to become the second in-phase data signal in the second data signal. The amplified second inverse voltage difference signal is processed by the second equalizing circuit 22 to become the second inverse data signal in the second data signal. The sampling circuit 30 selects and outputs the target data signal Out and its complementary signal according to the received first in-phase data signal and the first inverse data signal, or the second in-phase data signal and the second inverse data signal.

[0089] For example, Figure 6a As shown, Figure 6aThe structural schematic diagram of the first equalizing circuit provided according to an exemplary embodiment of the present disclosure is shown. The tap signal Tap includes a plurality of tap differential signals and a plurality of tap control signals. Each tap differential signal includes a complementary first tap differential signal and a second tap differential signal. The first equalizing circuit 12 includes a plurality of first tap adjustment circuits, each of which receives a tap differential signal, and different first tap adjustment circuits receive different tap differential signals. Each first tap adjustment circuit also receives a tap control signal, and different first tap adjustment circuits receive different tap control signals. Each first tap adjustment circuit includes a first switching circuit 121 and a first compensation circuit 122. The first switching circuit 121 includes a first switching transistor Qt1 and a second switching transistor Qt2. The first end of the first switching transistor Qt1 is coupled to an output end of the first amplifier circuit 11, and the control end receives a first tap differential signal in a tap differential signal. The first end of the second switching transistor Qt2 is coupled to another output end of the first amplifier circuit 11, and the control end receives a second tap differential signal in a corresponding tap differential signal. The first compensation circuit 122 includes a first control transistor group and a second control transistor group. Each first control transistor group includes a plurality of first control transistors Qc1 (one example is shown in the figure), each first control transistor Qc1 is coupled in parallel, the first end is coupled to the second end of the first switch transistor Qt1, the second end is coupled to the common end GND, and the control end receives a tap control signal. Each second control transistor group includes a plurality of second control transistors Qc2 (one example is shown in the figure), each second control transistor Qc2 is coupled in parallel, the first end is coupled to the second end of the second switch transistor Qt2, the second end is coupled to the common end GND, and the control end receives a tap control signal. The tap control signal is used to control the number of first control transistors Qc1 and second control transistors Qc2 that are turned on, and adjust the degree of influence of the corresponding tap differential signal on the input data signal Data, so as to perform decision feedback equalization on the input data signal Data. In each first tap adjustment circuit, the number of the first control transistors Qc1 and the number of the second control transistors Qc2 are the same, and the tap control signal in the first control transistor group is the same as the tap control signal in the second control transistor group.

[0090] For example, Figure 6b As shown, Figure 6bThe structural schematic diagram of the second equalizing circuit provided according to an exemplary embodiment of the present disclosure is shown. The second equalizing circuit 22 includes a plurality of second tap adjustment circuits, each of which receives a tap differential signal, and the tap differential signals received by different second tap adjustment circuits are different. Each second tap adjustment circuit also receives a tap control signal, and the tap control signals received by different second tap adjustment circuits are different. Each second tap adjustment circuit includes a second switch circuit 221 and a second compensation circuit 222. The second switch circuit 221 includes a third switch transistor Qt3 and a fourth switch transistor Qt4. The first end of the third switch transistor Qt3 is coupled to an output end of the second amplifier circuit 21, and the control end receives a first tap differential signal in a tap differential signal. The first end of the fourth switch transistor Qt4 is coupled to another output end of the second amplifier circuit 21, and the control end receives a second tap differential signal in a corresponding tap differential signal. The second compensation circuit 222 includes a third control transistor group and a fourth control transistor group. Each third control transistor group includes a plurality of third control transistors Qc3 (one example in the figure), each third control transistor Qc3 is coupled in parallel, the first end is coupled to the second end of the third switch transistor Qt3, the second end is coupled to the common end GND, and the control end receives the tap control signal. Each fourth control transistor group includes a plurality of fourth control transistors Qc4 (one example in the figure), each fourth control transistor Qc4 is coupled in parallel, the first end is coupled to the second end of the fourth switch transistor Qt4, the second end is coupled to the common end GND, and the control end receives the tap control signal. The tap control signal is used to control the number of the third control transistors Qc3 and the fourth control transistor Qc4 that are turned on, and adjust the degree of influence of the corresponding tap differential signal on the input data signal Data, so as to perform decision feedback equalization on the input data signal Data. Among them, in each second tap adjustment circuit, the number of the third control transistors Qc3 and the fourth control transistors Qc4 is the same, and the tap control signal in the third control transistor group is the same as the tap control signal in the fourth control transistor group.

[0091] Exemplarily, the tap control signal may be a control signal preset according to the circuit structure of the first switch circuit 121 and the second switch circuit 221 and the received tap differential signal.

[0092] In some exemplary embodiments provided in the present disclosure, Figure 7a As shown, Figure 7aThe schematic diagram of the structure of the selection sampling circuit provided according to an exemplary embodiment of the present disclosure is shown. The selection sampling circuit 30 includes a data selection circuit 31 and a sampling circuit 32. The data selection circuit 31 is coupled to both the first amplification and equalization circuit 10 and the second amplification and equalization circuit 20, receives a selection signal Cs, and is used to select the first data signal or the second data signal according to the selection signal Cs. The sampling circuit 32 is coupled to the data selection circuit 31, receives a sampling clock signal Clk, and is used to sample the signal selected by the data selection circuit 31 according to the sampling clock signal Clk, and outputs a target data signal Out.

[0093] In this embodiment, the sampling circuit includes a data selection circuit and a sampling circuit. The data selection circuit selects the first data signal or the second data signal, and the sampling circuit samples the signal selected by the data selection circuit to output the target data signal. Since one sampling circuit can perform sampling to output the target data signal, the number of sampling circuits required is small, which reduces the complexity of the decision feedback equalization circuit structure.

[0094] For example, Figure 7b As shown, Figure 7b The schematic diagram of the structure of the selection sampling circuit provided according to an exemplary embodiment of the present disclosure is shown. The selection sampling circuit 30 includes a data selection circuit 31 and two sampling circuits 32. One sampling circuit 32 is coupled to the first amplification and equalization circuit 10, receives the sampling clock signal Clk, and is used to sample the first data signal according to the sampling clock signal Clk. The other sampling circuit 32 is coupled to the second amplification and equalization circuit 20, receives the sampling clock signal Clk, and is used to sample the second data signal according to the sampling clock signal Clk. The data selection circuit 31 is coupled to both sampling circuits 32, receives the selection signal Cs, and is used to select the first data signal or the second data signal sampled by the sampling circuit 32 according to the selection signal Cs, and outputs the target data signal Out.

[0095] In some exemplary embodiments provided in the present disclosure, Figure 8 As shown, Figure 8 The structure diagram of the data selection circuit provided according to an exemplary embodiment of the present disclosure is shown. The data selection circuit 31 includes a plurality of transmission gates TG, the input end of each transmission gate TG is coupled to an output end of the first amplification and equalization circuit 10 or the second amplification and equalization circuit 20, the output end of each transmission gate TG is coupled to the sampling circuit 32, and the control end of each transmission gate TG is coupled to the selection signal Cs.

[0096] In this embodiment, the data selection circuit includes a plurality of transmission gates, and the transmission gates can be controlled by a selection signal to select the first data signal or the second data signal, thereby reducing the complexity of the data selection circuit structure. At the same time, since each transmission gate is coupled to the selection signal, the complexity of signal generation is reduced, thereby reducing the complexity of the decision feedback equalization circuit structure.

[0097] Exemplarily, the transmission gate TG includes an N-type transistor and a P-type transistor connected in parallel. One end of the N-type transistor and the P-type transistor coupled in parallel is the input end of the transmission gate TG, and the other end is the output end of the transmission gate TG. The control end of the P-type transistor is the first control end of the transmission gate TG, and the control end of the N-type transistor is the second control end of the transmission gate TG.

[0098] For example, Fig. 9 As shown, Fig. 9The structural schematic diagram of the decision feedback equalization circuit provided according to an exemplary embodiment of the present disclosure is shown. The decision feedback equalization circuit includes a first input transistor Qi1, a second input transistor Qi2, a third input transistor Qi3, a fourth input transistor Qi4, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, a first selection transistor Qs1, a second selection transistor Qs2, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4 and a sampling circuit 32. The control end of the first input transistor Qi1 receives a first reference voltage signal Vref1. The control end of the second input transistor Qi2 receives an input data signal Data. The first resistor R1 is coupled between the first end of the first input transistor Qi1 and the power supply VCC. The second resistor R2 is coupled between the first end of the second input transistor Qi2 and the power supply VCC. The first end of the first selection transistor Qs1 is coupled to the second end of the first input transistor Qi1 and the second input transistor Qi2, the second end is coupled to the common end GND, and the control end receives the first selection signal Cs1. The control end of the third input transistor Qi3 receives the second reference voltage signal Vref2. The control end of the fourth input transistor Qi4 receives the input data signal Data. The third resistor R3 is coupled between the first end of the third input transistor Qi3 and the power supply VCC. The fourth resistor R4 is coupled between the first end of the fourth input transistor Qi4 and the power supply VCC. The first end of the second selection transistor Qs2 is coupled to the second ends of the third input transistor Qi3 and the fourth input transistor Qi4, the second end is coupled to the common end GND, and the control end receives the second selection signal Cs2. The input end of the first transmission gate TG1 is coupled between the first input transistor Qi1 and the first resistor R1, the output end is coupled to the first input end of the sampling circuit 32, the first control end receives the second selection signal Cs2, and the second control end receives the first selection signal Cs1. The input end of the second transmission gate TG2 is coupled between the third input transistor Qi3 and the third resistor R3, the output end is coupled to the first input end of the sampling circuit 32, the first control end receives the first selection signal Cs1, and the second control end receives the second selection signal Cs2. The input terminal of the third transmission gate TG3 is coupled between the second input transistor Qi2 and the second resistor R2, the output terminal is coupled to the second input terminal of the sampling circuit 32, the first control terminal receives the second selection signal Cs2, and the second control terminal receives the first selection signal Cs1. The input terminal of the fourth transmission gate TG4 is coupled between the fourth input transistor Qi4 and the fourth resistor R4, the output terminal is coupled to the second input terminal of the sampling circuit 32, the first control terminal receives the first selection signal Cs1, and the second control terminal receives the second selection signal Cs2.

[0099] For example, Fig. 9 and Fig.10 As shown, Fig.10The working timing diagram of the decision feedback equalization circuit provided according to an exemplary embodiment of the present disclosure is shown. Before transmitting the D1 data, the decision feedback equalization circuit is in an initialization state. In the process of transmitting the input data signal Data, when transmitting the D1, D2, D7 and D9 data, the first selection transistor Qs1 turns on the first amplifier circuit 11, and the second selection transistor Qs2 turns off the second amplifier circuit 21. When transmitting the D3, D4, D5, D6 and D8 data, the first selection transistor Qs1 turns off the first amplifier circuit 11, and the second selection transistor Qs2 turns on the second amplifier circuit 21. Since only one amplifier circuit is turned on at the same time, the working current of the amplifier circuit is reduced, thereby reducing the power consumption of the decision feedback equalization circuit. Among them, Data1 is an ideal input data signal, Data2 is an actual input data signal, Vref1 is a first reference voltage signal, Vref2 is a second reference voltage signal, Clk is a sampling clock signal, Out1 is a first in-phase data signal in the first data signal, Out2 is a second in-phase data signal in the second data signal, and Out is a target data signal. The dotted line in Out1 indicates that the first amplifier circuit 11 is disconnected, and the dotted line in Out2 indicates that the second amplifier circuit 21 is disconnected.

[0100] The embodiment of the present disclosure further provides a data receiving circuit, which includes a plurality of decision feedback equalization circuits as in any of the above embodiments.

[0101] In some exemplary embodiments provided in the present disclosure, the sampling phases of the sampling clock signal Clk received by each decision feedback equalization circuit are different, and in the sampling phase order of the sampling clock signal Clk, the phase differences of the sampling clock signals Clk received by the decision feedback equalization circuits with adjacent sampling phases are the same.

[0102] In this embodiment, since each decision feedback equalization circuit can output the target data signal, when sampling and outputting the target data signal with different sampling phases, different decision feedback equalization circuits output different bit data in the target data signal, thereby increasing the number of bits of data transmission. Since the phase difference of the sampling clock signals received by adjacent decision feedback equalization circuits is the same, different bit data in the target data signal can be output to avoid omission, thereby improving the reliability of input data signal transmission.

[0103] Exemplarily, when the number of decision feedback equalization circuits in the data receiving circuit is 4, the phase difference of the sampling clock signal Clk received by the decision feedback equalization circuits with adjacent sampling phases is 90°. The sampling phase of the sampling clock signal Clk of the first decision feedback equalization circuit is 0°. The sampling phase of the sampling clock signal Clk of the second decision feedback equalization circuit is 90°. The sampling phase of the sampling clock signal Clk of the third decision feedback equalization circuit is 180°. The sampling phase of the sampling clock signal Clk of the fourth decision feedback equalization circuit is 270°.

[0104] It is understandable that, as the number of decision feedback equalization circuits in the data receiving circuit changes, the phase difference of the sampling clock signal Clk received by the decision feedback equalization circuits with adjacent sampling phases may also be 45°, etc., which is not limited here.

[0105] In some exemplary embodiments provided by the present disclosure, in the sampling phase sequence of the sampling clock signal Clk, the selection signal Cs received by each decision feedback equalization circuit includes the target data signal Out and its complementary signal output by the decision feedback equalization circuit corresponding to the previous sampling phase. Among them, the selection signal Cs received by the decision feedback equalization circuit corresponding to the first sampling phase is the target data signal Out and its complementary signal output by the decision feedback equalization circuit corresponding to the last sampling phase.

[0106] In this embodiment, by using the target data signal and its complementary signal output by the decision feedback equalization circuit corresponding to the previous sampling phase as the selection signal, there is no need to add a circuit for generating the selection signal, thereby reducing the complexity of the data receiving circuit structure.

[0107] Exemplarily, when the number of decision feedback equalization circuits in the data receiving circuit is 4, in the sampling phase order of the sampling clock signal Clk, the selection signal Cs received by the first decision feedback equalization circuit includes the target data signal Out output by the fourth decision feedback equalization circuit and its complementary signal. The selection signal Cs received by the second decision feedback equalization circuit includes the target data signal Out output by the first decision feedback equalization circuit and its complementary signal. The selection signal Cs received by the third decision feedback equalization circuit includes the target data signal Out output by the second decision feedback equalization circuit and its complementary signal. The selection signal Cs received by the fourth decision feedback equalization circuit includes the target data signal Out output by the third decision feedback equalization circuit and its complementary signal.

[0108] In some exemplary embodiments provided by the present disclosure, for a tap signal Tap of a decision feedback equalization circuit, it includes a target data signal Out and its complementary signal of the decision feedback equalization circuit that differ from the sampling phase of the sampling clock signal Clk of the decision feedback equalization circuit by one or more phase differences, and a target data signal Out and its complementary signal output by the decision feedback equalization circuit in the previous sampling clock cycle. According to the number of tap signals Tap in the decision feedback equalization circuit, the decision feedback equalization circuit can be divided into a 1-Tap decision feedback equalization circuit, a 2-Tap decision feedback equalization circuit, a 3-Tap decision feedback equalization circuit, a 4-Tap decision feedback equalization circuit, etc.

[0109] In this embodiment, by using the target data signal and its complementary signal as the tap signal, signal multiplexing is achieved, thereby reducing the complexity of the data receiving circuit structure. At the same time, using the target data signal and its complementary signal as the tap signal enables the first amplification and equalization circuit or the second amplification and equalization circuit to perform decision feedback equalization on the input data signal, thereby solving the inter-symbol interference problem and improving the reliability of the input data signal transmission.

[0110] For example, Fig.11 As shown, Fig.11The structural schematic diagram of a data receiving circuit provided according to an exemplary embodiment of the present disclosure is shown. The data receiving circuit includes a first decision feedback equalization circuit, a second decision feedback equalization circuit, a third decision feedback equalization circuit and a fourth decision feedback equalization circuit. The first decision feedback equalization circuit, the second decision feedback equalization circuit, the third decision feedback equalization circuit and the fourth decision feedback equalization circuit all include a first amplification equalization circuit 10, a second amplification equalization circuit 20, a data selection circuit 31 and a sampling circuit 32, and all receive an input data signal Data, a first reference voltage signal Vref1 and a second reference voltage signal Vref2. The first decision feedback equalization circuit receives a first sampling clock signal Clk_0. The second decision feedback equalization circuit receives a second sampling clock signal Clk_90. The third decision feedback equalization circuit receives a third sampling clock signal Clk_180. The fourth decision feedback equalization circuit receives a fourth sampling clock signal Clk_270. The first decision feedback equalization circuit outputs a first target data signal Out_0. The second decision feedback equalization circuit outputs a second target data signal Out_90. The third decision feedback equalization circuit outputs a third target data signal Out_180. The fourth decision feedback equalization circuit outputs a fourth target data signal Out_270. The tap signal Tap received by the first decision feedback equalization circuit includes the previous first target data signal Out_0(n-1), the second target data signal Out_90 and the third target data signal Out_180 output by the first decision feedback equalization circuit in the previous sampling clock cycle. The tap signal Tap received by the second decision feedback equalization circuit includes the previous second target data signal Out_90(n-1), the third target data signal Out_180 and the fourth target data signal Out_270 output by the second decision feedback equalization circuit in the previous sampling clock cycle. The tap signal Tap received by the third decision feedback equalization circuit includes the previous third target data signal Out_180(n-1), the first target data signal Out_0 and the fourth target data signal Out_270 output by the third decision feedback equalization circuit in the previous sampling clock cycle. The tap signal Tap received by the fourth decision feedback equalization circuit includes the previous fourth target data signal Out_270(n-1), the first target data signal Out_0 and the second target data signal Out_90 output by the fourth decision feedback equalization circuit in the previous sampling clock cycle. The selection signal Cs received by the first decision feedback equalization circuit includes the fourth target data signal Out_270. The selection signal Cs received by the second decision feedback equalization circuit includes the first target data signal Out_0. The selection signal Cs received by the third decision feedback equalization circuit includes the second target data signal Out_90. The selection signal Cs received by the fourth decision feedback equalization circuit includes the third target data signal Out_180.Among them, the first target data signal Out_0, the second target data signal Out_90, the third target data signal Out_180, the fourth target data signal Out_270, the previous first target data signal Out_0(n-1), the previous second target data signal Out_90(n-1), the previous third target data signal Out_180(n-1) and the previous fourth target data signal Out_270(n-1) also include their corresponding complementary signals. Since the selection signal Cs can enable the first amplification and equalization circuit 10 and the second amplification and equalization circuit 20 to operate one by one, the operating current of the four amplification and equalization circuits is reduced, thereby reducing the power consumption of the data receiving circuit. At the same time, since each decision feedback equalization circuit only includes one sampling circuit 32, four sampling circuits 32 are reduced, reducing the complexity of the data receiving circuit structure.

[0111] Exemplarily, when the number of decision feedback equalization circuits in the data receiving circuit is n, the operating current of the n amplification equalization circuits can be reduced to reduce power consumption, and the n sampling circuits 32 can be reduced to reduce the complexity of the data receiving circuit structure.

[0112] The embodiment of the present disclosure further provides a memory, which includes the data receiving circuit in any of the above embodiments.

[0113] The present disclosure is described with reference to flowcharts and / or block diagrams of methods, apparatuses (devices) and computer program products according to embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0114] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0116] In the present disclosure, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of more restrictions, the elements defined by the sentence "comprising..." do not exclude the presence of other identical elements in the article or device comprising the elements.

[0117] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0118] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the intent of the present disclosure also includes these modifications and variations.

Claims

1. A decision feedback equalization circuit, characterized in that: The decision feedback equalization circuit comprises: A first amplifying and equalizing circuit, configured to output a first data signal according to an input data signal, a first reference voltage signal and a tap signal; A second amplifying and equalizing circuit, configured to output a second data signal according to the input data signal, a second reference voltage signal and the tap signal; A selection sampling circuit, the selection sampling circuit is coupled to both the first amplification and equalization circuit and the second amplification and equalization circuit, and is used to select and sample the first data signal and the second data signal according to a selection signal and a sampling clock signal, and output a target data signal; Wherein, the first amplifying and equalizing circuit and the second amplifying and equalizing circuit selectively operate according to the selection signal; The first amplification and equalization circuit comprises: a first amplifier circuit, the first amplifier circuit is coupled to the selection sampling circuit and is used to amplify a first voltage difference signal between the input data signal and the first reference voltage signal; a first equalizing circuit, the first equalizing circuit being coupled to the first amplifying circuit and the selective sampling circuit, and being configured to perform decision feedback equalization on the input data signal according to the tap signal and the amplified first voltage difference signal, and output the first data signal; A first gating circuit, the first gating circuit is coupled to the first amplifying circuit and is used to control the first amplifying circuit to be turned on or off according to the selection signal; and / or, The second amplification and equalization circuit comprises: a second amplifier circuit, the second amplifier circuit is coupled to the selection sampling circuit and is used to amplify a second voltage difference signal between the input data signal and the second reference voltage signal; a second equalizing circuit, the second equalizing circuit being coupled to the second amplifying circuit and the selection sampling circuit, and configured to perform decision feedback equalization on the input data signal according to the tap signal and the amplified second voltage difference signal, and output the second data signal; A second gating circuit is coupled to the second amplifying circuit and is used for controlling the second amplifying circuit to be turned on or off according to the selection signal.

2. The decision feedback equalization circuit according to claim 1, characterized in that: The selection signal includes a first selection signal and a second selection signal; the first gating circuit includes: a first gating transistor, wherein the first gating transistor is coupled between the first amplifying circuit and a common terminal, and a control terminal of the first gating transistor receives the first selection signal; and / or, The second gating circuit comprises: A second gating transistor is coupled between the second amplifying circuit and the common terminal, and a control terminal of the second gating transistor receives the second selection signal.

3. The decision feedback equalization circuit according to claim 1, characterized in that: The first amplifying circuit comprises: a first input transistor, wherein a control terminal of the first input transistor receives the first reference voltage signal; a second input transistor, wherein a control terminal of the second input transistor receives the input data signal; A first resistor, wherein the first resistor is coupled between a first terminal of the first input transistor and a power supply; a second resistor, the second resistor being coupled between the first terminal of the second input transistor and the power supply; Wherein, the second end of the first input transistor and the second end of the second input transistor are both coupled to the first gating circuit; and / or, The second amplifier circuit comprises: a third input transistor, wherein a control terminal of the third input transistor receives the second reference voltage signal; a fourth input transistor, wherein a control terminal of the fourth input transistor receives the input data signal; a third resistor, the third resistor being coupled between the first end of the third input transistor and the power supply; a fourth resistor, the fourth resistor being coupled between the first end of the fourth input transistor and the power supply; The second end of the third input transistor and the second end of the fourth input transistor are both coupled to the second gating circuit.

4. The decision feedback equalization circuit according to claim 1, characterized in that: The selection sampling circuit comprises: a data selection circuit, the data selection circuit being coupled to both the first amplifying and equalizing circuit and the second amplifying and equalizing circuit, and configured to select the first data signal or the second data signal according to the selection signal; A sampling circuit is coupled to the data selection circuit and is used to sample the signal selected by the data selection circuit according to the sampling clock signal and output the target data signal.

5. The decision feedback equalization circuit according to claim 4, characterized in that: The data selection circuit includes multiple transmission gates, the input end of each transmission gate is coupled to an output end of the first amplification and equalization circuit or the second amplification and equalization circuit, the output end of each transmission gate is coupled to the sampling circuit, and the control end of each transmission gate is coupled to the selection signal.

6. A data receiving circuit, characterized in that: The data receiving circuit comprises a plurality of decision feedback equalization circuits as claimed in any one of claims 1 to 5.

7. The data receiving circuit according to claim 6, characterized in that: The sampling phases of the sampling clock signals received by the decision feedback equalization circuits are different. According to the sampling phase sequence of the sampling clock signals, the phase differences of the sampling clock signals received by the decision feedback equalization circuits with adjacent sampling phases are the same.

8. The data receiving circuit according to claim 7, characterized in that: According to the sampling phase sequence of the sampling clock signal, the selection signal received by each decision feedback equalization circuit includes the target data signal output by the decision feedback equalization circuit corresponding to the previous sampling phase; wherein the selection signal received by the decision feedback equalization circuit corresponding to the first sampling phase is the target data signal output by the decision feedback equalization circuit corresponding to the last sampling phase.

9. A memory, characterized in that: The memory includes the data receiving circuit according to any one of claims 6 to 8.

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