A wide input range micro-power linear voltage regulator circuit

Abstract

The application discloses a kind of wide input range micro-power consumption linear voltage regulator circuit, including power rail conversion module, band gap reference source, error amplifier, buffer, power output stage and transient enhancement module, the power rail conversion module is converted into low-voltage power supply by high-voltage power supply;Band gap reference source generates reference voltage independent of power supply voltage and temperature;Error amplifier compares the size of reference voltage and voltage feedback voltage of voltage dividing resistor, and amplifies the difference between them to control power tube gate voltage by feedback;Buffer isolates error amplifier output impedance and power tube input capacitance to move power tube input end pole to high frequency, in addition, responsible for the output low-voltage signal of error amplifier is converted into high-voltage signal for controlling power tube gate;Power output stage is responsible for providing output current for load while feeding back the change of output voltage;Transient enhancement improves the transient response capability of linear voltage regulator output load when heavy load is converted to light load.

Description

Technical Field

[0001] The present invention relates to the field of linear voltage regulators, and in particular to a wide input range micro-power consumption linear voltage regulator circuit. Background Art

[0002] As a key component of power management chips that provide stable power and protect the safety of electronic devices, LDO linear regulators are widely used due to their compact size, stable output, and low noise. With the advancement of science and technology, the demand for LDO linear regulators with a wide input range and ultra-low quiescent power consumption is increasing in the consumer electronics and new energy vehicle markets, particularly electric vehicles.

[0003] To achieve a wide input range, all branches can be designed with high-voltage transistors. However, given the same width-to-length ratio, the area of ​​high-voltage transistors is typically much larger than that of conventional low-voltage transistors, resulting in a waste of chip area. Another approach is to design some modules with low-voltage transistors. This requires adding a power rail conversion module to convert the high-voltage input into low-voltage power for the low-voltage modules. Figure 1 This is a common internal power rail conversion circuit schematic. Using the same negative feedback principle as an LDO, it can convert a widely varying input voltage into a stable low voltage independent of the power supply voltage, while also possessing a certain current drive capability. However, this structure requires an additional amplifier, which consumes additional power and hinders ultra-low power system design. Summary of the Invention

[0004] The purpose of the present invention is to provide a low-power linear voltage regulator circuit with a wide input range.

[0005] The technical solution of the present invention is:

[0006] A wide input range micro-power linear regulator circuit includes a power rail conversion module, a bandgap reference source, an error amplifier, a buffer, a power output stage, and a transient enhancement module, wherein:

[0007] The power rail conversion module converts the high voltage power supply V IN Converted into low voltage power supply V DDL ;

[0008] The bandgap reference generates a reference voltage V that is independent of the power supply voltage and temperature. ref ;

[0009] The error amplifier compares the reference voltage V ref The feedback voltage V fb The size of the power tube gate is controlled by amplifying the difference between them.

[0010] The buffer isolates the error amplifier output impedance and the power tube input capacitance, thereby moving the power tube input terminal pole to high frequency. It is also responsible for converting the error amplifier output low-voltage signal into a high-voltage signal to control the power tube gate.

[0011] The power output stage is responsible for providing output current to the load while feeding back changes in output voltage;

[0012] Transient enhancement improves the transient response capability of the linear regulator when the output load changes from heavy load to light load.

[0013] Preferably, the transient enhancement module, the bandgap reference source and the error amplifier all include low-voltage MOS tubes, which are powered by a low-voltage power supply V DDL Power supply; the buffer and power output stage both include high-voltage MOS tubes, which are powered by the high-voltage power supply V IN The power rail conversion module is composed of a single-tube high-voltage depletion-type NMOS tube DH1 in a source-follower structure.

[0014] Preferably, a series RC network is introduced at the output end of the error amplifier to compensate for the zero pole and reduce the influence of the error amplifier output pole on the phase margin.

[0015] Preferably, the buffer adopts a common source input structure, including a low voltage N MOS tube M1, high voltage N MOS tubes MH6, MH7, high voltage PMOS tubes MH4, MH5 and resistors R1, R2, R3; the gate of the N MOS tube M1 is connected to the output end of the error amplifier, the source is grounded, and the drain is connected to the source of the high voltage N MOS tubes MH6 and MH7 at the same time. The drains of MH6 and MH7 are connected to the high voltage power supply V through the resistor R1, high voltage PMOS tubes MH5 and MH4 connected in series in sequence. IN , resistors R2 and R3 are connected in parallel with high-voltage PMOS tubes MH5 and MH4 respectively.

[0016] Preferably, the buffer further includes an adaptive bias voltage structure, which includes low-voltage NMOS transistors M2, M5, and M6, low-voltage PMOS transistors M3 and M4, high-voltage PMOS transistor MH3, and resistors R4 and R5; wherein:

[0017] Resistor R4, MH3 tube, M3 tube, M2 tube, resistor R5 are connected in series to the high voltage power supply V IN The gate of MH3 is connected to the output stage of the power tube and the ground, and the load current is sampled through the MH3 tube; the gate of MH7 is connected to the common point of the M3 tube and the M2 tube, the gates of the M3 tube and the M4 tube are connected in common, the M4 tube is grounded through the series-connected M6 tube and M5 tube, and the gates of the M5 tube and the M6 ​​tube are connected to the bias voltage Vb1 and Vb2 respectively.

[0018] Preferably, the power tube output stage includes a high-voltage PMOS power tube MH1, a high-voltage PMOS current sampling tube MH2, a feedback resistor R f1 、R f2 , compensation resistor R C , compensation capacitor C C1 and the load capacitance C L ;in:

[0019] High-voltage PMOS power tube MH 1 and feedback resistor R f1 、R f2 Connect in series with the high voltage power supply V IN The source of the high-voltage PMOS current sampling tube MH2 is connected to the high-voltage power supply V IN , the gate of MH2 and the gate of power tube MH1 are connected to the gate of MH3 at the same time, and the drain of MH2 and the drain of MH1 are connected through the compensation resistor R C The drain of MH 1 is connected to the output terminal Vout, and the output terminal is connected to the load capacitor C L Ground; the drain of MH2 is also connected to the compensation capacitor C C1 Connect the feedback resistor R f1 、R f2 The middle sampling point of the feedback resistor R f1 、R f2 The feedback voltage Vfb is output at the middle sampling point.

[0020] Preferably, the transient enhancement circuit is composed of a comparator CO MP, low-voltage NMOS transistors M9, M10, M11, M12, low-voltage PMOS transistors M7, M8, and resistors R6, R7; wherein:

[0021] The output of the comparator COMP is connected to the gate of the low-voltage PMOS tube M7 and M8 respectively, and the source of M7 and M8 is connected to the low-voltage power supply V through the resistors R6 and R7 respectively. DDL The drains are grounded through low-voltage N MOS transistors M9 and M11 respectively. The low-voltage N MOS transistors M10 and M12 are connected to the common gates of M9 and M11 respectively. The drain of the low-voltage N MOS transistor M10 is connected to the output end of the error amplifier, and the drain of the low-voltage N MOS transistor M12 is connected to the output terminal Vout.

[0022] Preferably, the low-voltage NMOS transistors M1 and M2 are respectively connected in parallel with Zener diodes ZD1 and ZD2 to play a clamping protection role and prevent the M1 and M2 transistors from being broken down.

[0023] The advantages of the present invention are:

[0024] 1. In the present invention, the power rail conversion is realized by a single-tube high-voltage depletion-type NMOS transistor DH1 with a source-follower structure, which has the characteristics of simple structure and 100% current utilization.

[0025] 2. The buffer of this invention utilizes a low-power dynamic bias buffer structure, which reduces buffer power consumption under light loads while improving the buffer's bandwidth and transient response capability under heavy loads. The dynamically biased sampling tube utilizes a source-degenerate feedback structure to achieve logarithmic sampling of the load current, improving sampling sensitivity under light loads.

[0026] 3. The transient enhancement circuit of the present invention adopts a micro-power consumption dual-path feedback structure, one path of feedback increases the load capacitor discharge current to ground, and the other path of feedback reduces the power tube charging current. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0028] Figure 1 This is the schematic diagram of the traditional internal power rail conversion circuit;

[0029] Figure 2 This is a schematic diagram of the circuit of the wide input range micro-power linear regulator of the present invention;

[0030] Figure 3 This is the simulation result of converting the high-voltage power rail to the low-voltage power rail described in the present invention. DETAILED DESCRIPTION

[0031] like Figure 2 As shown in the figure, the wide input range micro-power linear regulator circuit of the present invention is mainly composed of power rail conversion, bandgap reference source, error amplifier, buffer, power output stage and transient enhancement modules. The power rail conversion module mainly converts the high voltage power supply into a low voltage power supply to power the core modules such as the error amplifier; the bandgap reference source mainly generates a reference voltage V that is independent of the power supply voltage and temperature. ref ;The error amplifier is responsible for comparing the reference voltage V ref The feedback voltage V fb The buffer is mainly used to isolate the output impedance of the error amplifier and the input capacitance of the power tube, thereby moving the input pole of the power tube to a high frequency. It is also responsible for converting the low-voltage output signal of the error amplifier into a high-voltage signal to control the gate of the power tube. The power output stage is mainly composed of the power tube and the feedback voltage divider resistor, which is responsible for providing output current to the load and feedbacking the change of output voltage. The transient enhancement plays a role in improving the transient response capability of the linear regulator when the output load changes from heavy load to light load.

[0032] Transient enhancement, bandgap reference, and error amplifier modules use a low voltage power supply V DDL For power supply, the circuit is composed of low-voltage MOS tubes; the buffer and power output stage use high-voltage power supply V IN To supply power, each branch of the circuit contains a high-voltage MOS tube. Input high-voltage power supply V IN With low voltage power supply V DDL The conversion between them is realized by power rail conversion. In the present invention, the power rail conversion is composed of a single-tube high-voltage depletion-type N MOS tube DH1 with a source follower structure.

[0033] Internal LDOs (Low-Drain Detectors) are typically used to convert power between multiple power rails. However, these LDOs consume additional current, making them unsuitable for μA-class ultra-low-power circuits. Given the inherently low internal power consumption of the linear regulator of the present invention, a single NMOS transistor in a source-follower configuration is sufficient to power the internal low-voltage circuits. Furthermore, to meet the wide input range requirement, the NMOS transistor DH1 is designed as a high-voltage depletion-mode transistor. The threshold voltage of a depletion-mode NMOS transistor is less than zero, enabling normal operation even with low input voltages. Figure 2 The DH1 tube in the middle works in the saturation region, so the low voltage power supply V DDL equal

[0034]

[0035] Where V BN1 is the gate bias voltage of DH 1 tube, generated by the self-bias voltage circuit which is independent of the power supply voltage; V th1 is the threshold voltage of DH 1 tube; μ n is the carrier mobility; C ox is the gate oxide capacitance; I is the source load current of DH 1 tube.

[0036] Figure 3 This is the simulation result of high voltage power supply to low voltage power supply. The horizontal axis is the input voltage, and the simulation condition source load current is 1mA. It can be seen from the figure that when V IN When the input voltage changes from 2.7V to 40V, V DDL The voltage is maintained at around 2.1V, achieving stability of the internal power supply within a wide input range.

[0037] In a micro-power linear regulator, the quiescent current of the error amplifier (EA) is only a few hundred nA, so the MOS tubes of the error amplifier all operate in the sub-threshold region, and the output impedance will be very large (10 8The EA output poles are relatively small (level), resulting in a smaller output pole. To minimize the impact of the EA output poles on the phase margin, a series RC pole-zero compensation network is introduced at the output. This compensation method utilizes multiple pole-zero pairs with relatively fixed distances to minimize the phase margin degradation at the error amplifier output. The series RC network can be a single series RC network or multiple series RC networks in parallel. Using multiple pole-zero compensation pairs, when a pole first affects the phase, a zero also has an opposite effect on the phase, thus minimizing phase degradation. The more pole-zero pairs there are, the less phase degradation there is.

[0038] The power tube MH1 of the linear voltage regulator of the present invention is a high-voltage PMOS tube, and its gate drive voltage is close to the high-voltage supply voltage V IN , and the error amplifier is powered by the internal low voltage rail V DDL Therefore, the error amplifier output EA_OUT cannot directly drive the power transistor gate. Furthermore, due to the large parasitic capacitance of the power transistor gate and the high static output impedance of the error amplifier, the pole formed by directly cascading the two is very small. Based on these considerations, the buffer in this project uses a common-source input structure and a diode-connected active load. This shifts the power transistor gate pole outside the loop bandwidth while also achieving a level shift function.

[0039] The buffer consists of a low-voltage NMOS transistor M1, high-voltage NMOS transistors MH6 and MH7, high-voltage PMOS transistors MH4 and MH5, and resistors R1, R2, and R3. The load selection resistor is connected in parallel with the diode, which has the characteristics of a dynamic load. When the load is very light, the MOS transistors all operate in the subthreshold region, and the output impedance of the diode-connected MOS transistor is 1 / g. m The output impedance of the buffer is approximately equal to R1+R2+R3, and the output pole can be easily moved outside the loop bandwidth. When the load current increases, the output impedance of the MOS tube connected to the diode is 1 / g. m Follow the decrease, when 1 / g m When the output impedance of the buffer is less than its parallel resistance, it is approximately equal to R1+1 / g m4 +1 / g m5 , which is inversely proportional to the load current, the output pole is dynamically pushed farther away, away from the loop bandwidth that follows the increasing load.

[0040] To ensure the buffer's output pole remains outside the loop bandwidth, a sufficiently low buffer output impedance is required. However, reducing the output impedance requires increasing the bias current, which does not meet the requirements of micropower design. Therefore, this linear regulator introduces an adaptive bias voltage structure for the buffer. The adaptive bias voltage structure consists of low-voltage NMOS transistors M2, M5, and M6, low-voltage PMOS transistors M3 and M4, high-voltage PMOS transistor MH3, and resistors R4 and R5. Vb1 and Vb2 are bias voltages.

[0041] The gate of MH3 is connected to the gate of power transistor MH1, and load current is sampled through MH3. When the load current is low, the current of MH3 is very small, the gate voltage of M2 is very low, and the current flowing through MH7 is equal to zero, reducing static power consumption. When the load current increases, the gate voltage of M2 increases, which increases the gate bias voltage of MH7. At the same time, the source voltage of MH7 is also pulled up, ensuring that MH1 operates in the saturation region under heavy loads. This increases the buffer bandwidth under heavy loads, thereby improving the transient response capability of the linear regulator when the load changes from low to high.

[0042] Because the width-to-length ratio of the MH3 transistor is much smaller than that of the power transistor MH1, the MH3 transistor uses source negative feedback to improve the current sampling ratio under light load conditions. This ensures that the sampled current is logarithmically related to the load current under light load conditions, improving the current sampling sensitivity under light load conditions.

[0043] ZD1 and ZD2 are Zener diodes that act as clamping protection to prevent M1 and M2 tubes from being broken down.

[0044] The power tube output stage consists of high-voltage PMOS power tube MH1, high-voltage PMOS current sampling tube MH2, feedback resistor R f1 、R f2 , compensation resistor R C , compensation capacitor C C1 and the load capacitance C L The load capacitance and load current of the linear regulator usually vary in a wide range, resulting in a wide range of changes in the pole of its output node. In order to ensure the loop stability under full load current and a wide range of capacitance loads, the linear regulator of the present invention adds an additional circuit at the output end, M H2, R C and C C1 A compensation current branch is formed, thereby introducing a compensation zero point at the output end that follows the change of the pole position. This zero point can realize the functions of load current tracking and load capacitance tracking.

[0045] analyze Figure 2 The small signal network characteristics of the medium power output stage can be obtained as the transfer function:

[0046]

[0047] Among them I OUT Indicates the output current of the power tube; R L1 Represents the output impedance of the power tube; β represents the ratio of the width-to-length ratio of MH2 to the width-to-length ratio of MH1.

[0048] Therefore, from formula (2), we can know that the zero-pole position of the power output stage is:

[0049]

[0050] From formula (4), we can see that the denominators of the compensation zero points z1 and z2 both include the output load capacitance C L , so the compensation zero point can achieve load capacitance tracking. As the load capacitance C L As the compensation zero point z1 moves from far away to the origin, z2 moves from the origin to the direction away from the origin. L When it is greater than a certain value, z1 and z2 become a pair of conjugate zeros, and their real parts change with C L Increase and gradually decrease.

[0051] Because the power tube output impedance is inversely proportional to the load current, pole p1 is directly proportional to the load current and inversely proportional to the load capacitance. Under light load, pole p1 is significantly less than 1Hz and is the primary pole for the entire system. Under heavy load, the power tube output impedance decreases dramatically, causing pole p1 to rapidly increase and become a secondary pole. The position of pole p2 remains relatively fixed.

[0052] One problem with micropower consumption is that when the load drops from a heavy load to 0mA, the linear regulator's output voltage overshoots. At this point, the leakage current to ground is only in the nanoamp range, resulting in a very long output voltage stabilization time. Therefore, an additional transient enhancement circuit is needed to improve the transient response when the load drops from a heavy load to a light load.

[0053] The transient enhancement circuit of the linear voltage regulator of the present invention consists of a comparator COMP, low-voltage NMOS transistors M9, M10, M11, and M12, low-voltage PMOS transistors M7 and M8, and resistors R6 and R7. It suppresses overshoot voltage by increasing the pull-down discharge current of the load capacitor while reducing the charging current of the power transistor.

[0054] Figure 2 When the amplitude changes from heavy load to light load, V OUT The voltage surges and increases, V FB The voltage increases synchronously, and the comparator outputs a low level, thereby increasing the bias current of M7 and M8. After the mirror copy, M12 tube provides a V OUT Pull-down discharge current from the terminal to ground, accelerating the load capacitance C LOn the other hand, the gate voltage of M1 is pulled down to the ground through the M10 tube, thereby shutting off the charging current of the power tube, effectively suppressing the overshoot voltage and improving the transient response.

[0055] The comparator in the transient enhancement module sets a positive system offset voltage. When the system is stable, V ref and V FB Equal, at this time the comparator outputs a high level, the bias current of M7 and M8 is zero, and there is no other current consumption except the comparator current. At this time, the overshoot suppression module does not affect the normal operation of the circuit.

[0056] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

[0057] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any modifications made based on the spirit of the main technical solution of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A wide input range micro-power linear regulator circuit, characterized in that: It includes a power rail conversion module, a bandgap reference source, an error amplifier, a buffer, a power output stage, and a transient enhancement module, among which: The power rail conversion module consists of a single high-voltage depletion-type NMOS transistor DH1 in a source-follower structure, which converts the high-voltage power supply VIN into a low-voltage power supply VDDL. The bandgap reference generates a reference voltage V that is independent of the power supply voltage and temperature. ref ; The error amplifier compares the reference voltage V ref The feedback voltage V fb The size of the power tube gate is controlled by amplifying the difference between them. The buffer isolates the error amplifier output impedance and the power tube input capacitance, thereby shifting the power tube input terminal pole to a higher frequency. It also converts the error amplifier's low-voltage output signal into a high-voltage signal to control the power tube gate. The buffer utilizes a micro-power dynamic bias buffer structure, which reduces buffer power consumption under light loads while improving the buffer's bandwidth and transient response capability under heavy loads. The dynamically biased sampling tube utilizes a source negative feedback structure to achieve logarithmic sampling of the load current, improving sampling sensitivity under light loads. The power output stage is responsible for providing output current to the load while feeding back changes in output voltage; The transient enhancement module adopts a micro-power dual-path feedback structure. One feedback path increases the load capacitor's ground discharge current, while the other feedback path reduces the power tube charging current, improving the linear regulator's transient response capability when the output load changes from heavy load to light load.

2. The wide input range micro-power linear regulator circuit according to claim 1, characterized in that: The transient enhancement module, bandgap reference source and error amplifier all include low-voltage MOS tubes, which are powered by a low-voltage power supply V DDL Power supply; the buffer and power output stage both include high-voltage MOS tubes, which are powered by the high-voltage power supply V IN The power rail conversion module is composed of a single-tube high-voltage depletion-type NMOS tube DH1 in a source-follower structure.

3. The wide input range micro-power linear regulator circuit according to claim 2, characterized in that: A series RC network is introduced into the output end of the error amplifier to compensate for the zero pole and reduce the influence of the error amplifier output pole on the phase margin.

4. The wide input range micro-power linear regulator circuit according to claim 3, characterized in that: The buffer adopts a common source input structure, including a low voltage NMOS transistor M1, high voltage NMOS transistors MH6, MH7, high voltage PMOS transistors MH4, MH5 and resistors R1, R2 and R3; the gate of the NMOS transistor M1 is connected to the output end of the error amplifier, the source is grounded, and the drain is connected to the sources of the high voltage NMOS transistors MH6 and MH7 at the same time. The drains of MH6 and MH7 are connected to the high voltage power supply V through the resistor R1, high voltage PMOS transistors MH5 and MH4 connected in series in sequence. IN , resistors R2 and R3 are connected in parallel with high-voltage PMOS tubes MH5 and MH4 respectively.

5. The wide input range micro-power linear regulator circuit according to claim 4, characterized in that: The buffer further includes an adaptive bias voltage structure, which includes low-voltage NMOS transistors M2, M5, and M6, low-voltage PMOS transistors M3 and M4, high-voltage PMOS transistor MH3, and resistors R4 and R5; wherein: Resistor R4, MH3 tube, M3 tube, M2 tube, resistor R5 are connected in series to the high voltage power supply V IN The gate of MH3 is connected to the output stage of the power tube and the ground, and the load current is sampled through the MH3 tube; the gate of MH7 is connected to the common point of the M3 tube and the M2 tube, the gates of the M3 tube and the M4 tube are connected in common, the M4 tube is grounded through the series-connected M6 tube and M5 tube, and the gates of the M5 tube and the M6 ​​tube are connected to the bias voltage Vb1 and Vb2 respectively.

6. The wide input range micro-power linear regulator circuit according to claim 5, characterized in that: The power tube output stage includes a high-voltage PMOS power tube MH1, a high-voltage PMOS current sampling tube MH2, a feedback resistor R f1 、R f2 , compensation resistor R C , compensation capacitor C C1 and the load capacitance C L ;in: High-voltage PMOS power tube MH 1 and feedback resistor R f1 、R f2 Connect in series with the high voltage power supply V IN The source of the high-voltage PMOS current sampling tube MH2 is connected to the high-voltage power supply V IN , the gate of MH2 and the gate of power tube MH1 are connected to the gate of MH3 at the same time, and the drain of MH2 and the drain of MH1 are connected through the compensation resistor R C The drain of MH 1 is connected to the output terminal Vout, and the output terminal is connected to the load capacitor C L Ground; the drain of MH2 is also connected to the compensation capacitor C C1 Connect the feedback resistor R f1 、R f2 The middle sampling point of the feedback resistor R f1 、R f2 The feedback voltage Vfb is output at the middle sampling point.

7. The wide input range micro-power linear regulator circuit according to claim 6, characterized in that: The transient enhancement module is composed of a comparator COMP, low-voltage NMOS transistors M9, M10, M11, M12, low-voltage PMOS transistors M7, M8, and resistors R6, R7; wherein: The output of the comparator COMP is connected to the gate of the low-voltage PMOS tube M7 and M8 respectively, and the source of M7 and M8 is connected to the low-voltage power supply V through the resistors R6 and R7 respectively. DDL The drains of M7 and M8 are grounded through low-voltage NMOS transistors M9 and M11 respectively. The low-voltage NMOS transistors M10 and M12 are connected to the common gates of M9 and M11 respectively. The drain of the low-voltage NMOS transistor M10 is connected to the output end of the error amplifier, and the drain of the low-voltage NMOS transistor M12 is connected to the output terminal Vout.

8. The wide input range micro-power linear regulator circuit according to claim 5, characterized in that: The low-voltage NMOS transistors M1 and M2 are respectively connected in parallel with Zener diodes ZD1 and ZD2 to play a clamping protection role and prevent the M1 and M2 transistors from being broken down.

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