Semiconductor apparatus performing training operation and method of operation thereof

Abstract

Embodiments of this disclosure relate to a semiconductor device for performing training operations and a method of operating the same. One semiconductor device includes: a data input circuit adapted to receive a training clock to provide a first data signal and a strobe signal according to a plurality of input control signals in a training mode; a delay circuit adapted to output a second data signal by delaying the first data signal according to a delay value corresponding to a corresponding setting code; a data alignment circuit adapted to output a third data signal by aligning the second data signal according to the strobe signal; a code generation circuit adapted to generate a preliminary code corresponding to the third data signal according to the training clock and to sequentially store the preliminary code as a setting code according to a code lock signal; and a lock detection circuit adapted to activate the code lock signal based on the training clock and the preliminary code.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0045553, filed on April 13, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to semiconductor design techniques, and more specifically, to a semiconductor device capable of performing write training operations during ZQ calibration operations. Background Technology

[0004] Generally, semiconductor devices can transmit and receive data synchronously with a clock. Semiconductor devices can use data strobe signals with the same period as the clock to transmit and receive data. For example, a memory device within a semiconductor device can receive data sent from the memory controller in response to a data strobe signal during a write operation, and output data to the memory controller synchronously with the data strobe signal during a read operation. Therefore, to improve the operational reliability of semiconductor devices, it is important to adjust the timing between the data strobe signal and the data. As the operating speed of semiconductor devices increases, the timing deviation between the data strobe signal and the data increases depending on various environments.

[0005] To address this issue, semiconductor devices can perform write training operations and / or read training operations to measure data latch margin, and control the deviation to be corrected by setting the delay value of the signal path of the data or data strobe signal based on the measurement results. Summary of the Invention

[0006] Embodiments of this disclosure relate to a semiconductor device and a method thereof capable of performing a write training operation that sequentially adjusts the delay value of the input path of a data signal according to the delay value of the input path of the data strobe signal.

[0007] Embodiments of this disclosure relate to a semiconductor device and a method of operation thereof, the semiconductor device being capable of performing a write training operation prior to a ZQ calibration operation based on a calibration command, the ZQ calibration operation being used to adjust the impedance of a group of resistors to be coupled to calibration pad ZQ to be substantially the same as that of an external resistor RZQ.

[0008] According to one embodiment of this disclosure, a semiconductor device includes: a data input circuit adapted to receive a training clock to provide a first data signal and a strobe signal in a training mode based on a plurality of input control signals; a delay circuit adapted to output a second data signal by delaying the first data signal according to a delay value corresponding to a corresponding setting code; a data alignment circuit adapted to output a third data signal by aligning the second data signal according to the strobe signal; a code generation circuit adapted to generate a preliminary code corresponding to the third data signal according to the training clock, and to sequentially store the preliminary code as a setting code according to a code lock signal; and a lock detection circuit adapted to activate the code lock signal based on the training clock and the preliminary code.

[0009] According to one embodiment of the present disclosure, a method of operating a semiconductor device includes: generating a calibration command during its power-on period; generating a training mode signal in response to the calibration command; performing a training operation based on the training mode signal, the training operation sequentially setting delay values ​​of corresponding delay lines coupled to corresponding data pads; generating a calibration mode signal after the training operation is completed; and performing a calibration operation based on the calibration mode signal.

[0010] According to one embodiment of the present disclosure, a semiconductor system includes: a controller adapted to provide an initialization command; and a semiconductor device adapted to: generate a calibration command according to the initialization command, generate a training mode signal in response to the calibration command, perform a training operation according to the training mode signal, the training operation sequentially setting delay values ​​of corresponding delay lines coupled to corresponding data pads, generate a calibration mode signal after completing the training operation, and perform a calibration operation according to the calibration mode signal.

[0011] According to one embodiment of this disclosure, a method of operating a semiconductor device includes: upon power-on, performing a calibration operation after sequentially setting delay values ​​for corresponding delay lines, wherein the sequential setting includes: delaying an internally generated training clock via selected delay lines; aligning the delay clock synchronously with the training clock; changing a pre-code synchronously with the training clock according to the logic level of the aligned clock; and adjusting the delay values ​​of the selected delay lines according to the pre-code, wherein the pre-code is changed until: the training clock is triggered a predetermined number of times, or the pre-code has one or more values, or a maximum or minimum value, within a stable range.

[0012] According to embodiments of the present invention, a semiconductor device can sequentially adjust the delay value of the input path of a data signal based on the delay value of the input path of the data strobe signal. Therefore, the phase difference between data signals can be reduced, and the timing margin can be increased, thereby satisfying the time specification tDQ2DQ between data signals and improving operational reliability.

[0013] According to embodiments of the present invention, a semiconductor device can perform training operations using internally generated signals without requiring externally provided control signals, thereby minimizing randomly generated deviations for each semiconductor device. In particular, the semiconductor device can automatically perform training operations before performing ZQ calibration operations based on calibration commands generated during power-on, thereby improving its operational efficiency.

[0014] These and other features and advantages of this disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0016] Figure 2 This is for describing an embodiment of the present invention. Figure 1 The timing diagram shows the training operation of the memory device.

[0017] Figure 3 This is a block diagram illustrating a memory device according to an embodiment of the present invention.

[0018] Figure 4 The illustration shows an embodiment of the present invention. Figure 3 The circuit diagram of the first data buffer.

[0019] Figure 5 The illustration shows an embodiment of the present invention. Figure 3 The configuration diagram of the delay circuit.

[0020] Figure 6 The illustration shows an embodiment of the present invention. Figure 5 The circuit diagram of the unit delay line.

[0021] Figure 7 The illustration shows an embodiment of the present invention. Figure 3 The circuit diagram of the data alignment circuit.

[0022] Figure 8 The illustration shows an embodiment of the present invention. Figure 3 Detailed block diagram of the training control circuit.

[0023] Figure 9 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the control signal generation circuit.

[0024] Figure 10 The illustration shows an embodiment of the present invention. Figure 8Detailed circuit diagram of the clock generation circuit.

[0025] Figure 11 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the code storage circuit.

[0026] Figure 12 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the locking detection circuit.

[0027] Figure 13 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the input control circuit.

[0028] Figure 14 This is a timing diagram used to describe the operation of a memory device according to an embodiment of the present invention.

[0029] Figure 15 and Figure 16 This is a flowchart describing the operation of a memory device according to an embodiment of the present invention. Detailed Implementation

[0030] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey the scope of the invention to those skilled in the art. Throughout this disclosure, and throughout the various drawings and embodiments of the invention, the same reference numerals refer to the same parts.

[0031] It should be noted that references to "one embodiment", "another embodiment", etc. do not necessarily imply only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment(s).

[0032] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the spirit and scope of the invention, the first element described below may also be referred to as the second or third element.

[0033] It will be further understood that the terms “comprising,” “including,” “contains,” and “includes”, when used in this specification, expressly indicate the presence of the stated element and do not exclude the presence or addition of one or more other elements. As used herein, the term “and / or” includes any and all combinations of one or more associated listed items.

[0034] As used herein, the singular form may also include the plural form, and vice versa, unless the context clearly indicates otherwise. Unless otherwise stated or clearly indicated from the context, the articles “a” and “an” used in this application and the appended claims should generally be interpreted as meaning “one or more”.

[0035] In the following embodiments, the memory device is described as an example of a semiconductor device. However, the proposed invention is not limited thereto and can be applied to various types of semiconductor devices.

[0036] Figure 1 This is a block diagram illustrating a memory system 10 according to an embodiment of the present invention.

[0037] refer to Figure 1 The memory system 10 may include a memory device 20 and a memory controller 30. Figure 1 The diagram illustrates the signals exchanged between the memory controller 30 and the memory device 20. The memory device 20 can exchange commands (CMD), addresses (ADD), or data (DQ) with the memory controller 30 via the data pad DQ_P in the form of data DQ<7:0> sent to the same data lines. Furthermore, the memory device 20 can exchange data strobe signals (DQS) with the memory controller 30 via the data strobe pad DQS_P. Additionally, the memory device 20 can receive chip enable signal CE#, address latch enable signal ALE, command latch enable signal CLE, write enable signal WE#, and read enable signal RE# via the control pad C_P.

[0038] The chip enable signal CE# can be a signal that indicates the operability of memory device 20 (i.e., memory chip) and is activated to a logic low level. The chip enable signal CE# can be selectively applied to memory chips coupled to the same channel. When the chip enable signal CE# is activated to a logic low level, it indicates that all operations within the memory chip are possible; when the chip enable signal CE# is deactivated to a logic high level, it indicates that the memory chip is in a standby state.

[0039] The command latch enable signal CLE can be used to receive the command CMD sent via the data pad DQ_P, and is activated to a logic high level when the command CMD is input to the memory device 20. The address latch enable signal ALE can be used to receive the address ADD sent via the data pad DQ_P, and is activated to a logic high level when the address ADD is input to the memory device 20.

[0040] The write enable signal WE# can be triggered when data DQ<7:0>, including command CMD and address ADD, is loaded into memory device 20, and the read enable signal RE# can be triggered when data DQ<7:0>, including data DQ, is loaded into memory controller 30. When the write enable signal WE# transitions from logic low to logic high, i.e., at the rising edge of the write enable signal WE#, command CMD and address ADD can be input into memory device 20. According to one embodiment, when the write enable signal WE# transitions from logic high to logic low, i.e., at the falling edge of the write enable signal WE#, command CMD and address ADD can be input into memory device 20.

[0041] The memory device 20 can receive data DQ<7:0> or output data DQ<7:0> to the memory controller 30 via data pads DQ_P. Each data pad DQ_P can have 8 bits when the data DQ<7:0> consists of 8 bits. However, the number of data pads DQ_P is not limited to 8 and can be extended to 16 or 32 in various embodiments.

[0042] During a write operation, memory device 20 can receive data DQ<7:0> synchronously with the data strobe signal DQS input via data strobe pad DQS_P through data strobe pad DQS_P. For example, in Double Data Rate (DDR) mode, memory device 20 can receive data DQ<7:0> at each rising and falling edge of the data strobe signal DQS. During a read operation, when data DQ<7:0> is output via data strobe pad DQ_P, memory device 20 can synchronously output the data strobe signal DQS via data strobe pad DQS_P. Therefore, memory device 20 can be a synchronous memory device that operates synchronously with the data strobe signal DQS.

[0043] The following will describe Figure 1 Write operations of the memory system 10.

[0044] During a write operation, the memory controller 30 may provide the memory device 20 with a write enable signal WE# that is triggered at predetermined intervals. The memory controller 30 may provide the memory device 20 with data DQ<7:0> including a command CMD indicating a write operation, along with a command latch enable signal CLE. When the command latch enable signal CLE goes high, the memory device 20 may receive the command CMD via the data pad DQ_P based on the rising edge of the write enable signal WE#.

[0045] Subsequently, the memory controller 30 can provide the data DQ<7:0>, including the address ADD, along with the address latch enable signal ALE. When the address latch enable signal ALE goes high, the memory device 20 can receive the address ADD via the data pad DQ_P based on the rising edge of the write enable signal WE#. Afterward, the memory controller 30 can provide the data DQ<7:0> along with the data strobe signal DQS. The memory device 20 can receive the data DQ<7:0> based on the data strobe signal DQS and store the data DQ<7:0> in the memory region specified by the address ADD.

[0046] Memory device 20 may include latching circuitry for latching data DQ<7:0> according to a data strobe signal DQS. In this case, because the data pads DQ_P and DQS_P are at different distances from the latching circuitry, the paths for the signals to travel from the data pads DQ_P and DQS_P to the latching circuitry are different. Due to these different paths, a phase difference (i.e., offset) occurs between each signal. (Reference) Figure 2 Each data DQ<7:0> can have a unit interval (UI) (i.e., an effective window) defined by a first edge (e.g., a rising edge) and a second edge (e.g., a falling edge). The memory device 20 can perform a write training operation that adjusts the amount of delay (or timing compensation) for each path such that the rising edge of the data strobe signal DQS is located at the center of the effective window of each data DQ<7:0>.

[0047] However, even if each path is ideally matched and arranged, deviations may occur randomly for each semiconductor device due to internal process variations, mismatches in internal wiring, internal power supply noise, etc. Therefore, there are limitations to correcting deviations by writing training operations.

[0048] In the following description, according to one embodiment of the invention, in order to minimize randomly occurring deviations for each semiconductor device and satisfy the time specification tDQ2DQ between data signals, a method for performing a write training operation to sequentially adjust the delay values ​​of the input paths of the data signals can be described. In the following embodiments, components related to the invention for performing the write operation will be primarily described.

[0049] Figure 3 This is a block diagram illustrating a memory device 100 according to an embodiment of the present invention.

[0050] refer to Figure 3The memory device 100 may include a data input circuit 110, a delay circuit 120, a data alignment circuit 130, a command / address (C / A) control circuit 140, a training control circuit 150, and an internal circuit 160.

[0051] Data input circuitry 110 may include multiple data buffers DB0 to DB7, each coupled to a plurality of data pads DQ_P, and a data strobe buffer DSB coupled to a data strobe pad DQS_P. In a normal mode, such as a write operation, the multiple data buffers DB0 to DB7 can receive data from an external device (e.g., ...) via the data pads DQ_P. Figure 1 The memory controller 30) provides data DQ<7:0> to provide the first data signal DIN<7:0>. In normal mode, the data strobe buffer DSB can receive the data strobe signal DQS provided from an external device via the data strobe pad DQS_P to provide it as the internal strobe signal IDQS. In training mode, data buffers DB0 to DB7 can receive the training clock TCLK according to multiple input control signals EN_DQ0 to EN_DQ7 to provide the first data signal DIN<7:0>. In training mode, the data strobe buffer DSB can receive the training clock TCLK to provide it as the internal strobe signal IDQS. Hereinafter, as an example, the case where eight data pads DQ_P are provided and the data input circuit 110 includes first to eighth data buffers DB0 to DB7 respectively coupled to the eight data pads DQ_P will be described. Figure 4 The document describes the detailed configuration and operation of the first to eighth data buffers, DB0 to DB7.

[0052] The delay circuit 120 can receive first to eighth setting codes CODE0<4:0> to CODE7<4:0> and output a second data signal DDIN<7:0> by delaying the first data signal DIN<7:0> according to the delay values ​​corresponding to the first to eighth setting codes CODE0<4:0> to CODE7<4:0> respectively. The delay circuit 120 may include first to eighth delay lines ( Figure 5 (121 to 128), each delay line receives the corresponding setting code from the first to eighth setting codes CODE0<4:0> to CODE7<4:0>, and delays the corresponding first data signal in the first data signal DIN<7:0> according to the delay value set by the corresponding setting code. (Refer to...) Figure 5 and Figure 6 This describes the detailed configuration and operation of the delay circuit 120.

[0053] The data alignment circuit 130 can output a third data signal IDATA<7:0> by aligning the second data signal DDIN<7:0> according to the internal strobe signal IDQS provided from the data strobe buffer DSB. Figure 7 The details of the configuration and operation of the data alignment circuit 130 are described in the text.

[0054] The C / A control circuit 140 can receive the chip enable signal CE#, address latch enable signal ALE, command latch enable signal CLE, write enable signal WE#, and read enable signal RE# via the control pad C_P, and can receive the first data signal DIN<7:0> from the first to eighth data buffers DB0 to DB7. When the chip enable signal CE# is activated to a logic low level and the command latch enable signal CLE becomes a logic high level, the C / A control circuit 140 can receive the first data signal DIN<7:0> as a command CMD at the rising edge of the write enable signal WE#, and generate write command WT, read command RD, calibration command ZQ_CMD, etc. by decoding the command CMD. For example, the C / A control circuit 140 can generate the calibration command ZQ_CMD based on the command CMD, which is the hexadecimal code "FFh" indicating the initialization operation during power-on. In addition, the C / A control circuit 140 can generate the clock CK based on the write enable signal WE#. When the chip enable signal CE# is activated to a logic low level and the address latch enable signal ALE becomes a logic high level, the C / A control circuit 140 can receive the first data signal DIN<7:0> as address ADD at the rising edge of the write enable signal WE#.

[0055] The training control circuit 150 can enter training mode in response to the calibration command ZQ_CMD. The training control circuit 150 can activate a training mode signal indicating entry into training mode. Figure 8 TR_EN). The training control circuit 150 can generate a signal based on the training mode signal TR_EN and the code lock signal (TR_EN). Figure 8 The first to eighth input control signals EN_DQ0 to EN_DQ7 are activated sequentially using CODE_LOCK, and a training completion signal can be generated after all of the first to eighth input control signals EN_DQ0 to EN_DQ7 have been activated. Figure 8 (TR_DONE). The training control circuit 150 can activate the training mode signal TR_EN based on the training completion signal TR_DONE, and activate the calibration mode signal CAL_EN for performing ZQ calibration operations.

[0056] Furthermore, the training control circuit 150 can generate a training clock TCLK triggered at a predetermined period based on the training mode signal TR_EN. The training control circuit 150 can also generate preparatory code corresponding to the third data signal IDATA<7:0> based on the training mode signal TR_EN. Figure 8 CODEA<4:0>), and can be locked according to the code signal ( Figure 8 The training control circuit 150 stores the preliminary codes CODEA<4:0> sequentially as the first to eighth set codes CODE0<4:0> to CODE7<4:0>. Furthermore, the training control circuit 150 can generate the code lock signal CODE_LOCK based on the training clock TCLK and the preliminary codes CODEA<4:0>. The training control circuit 150 can generate the code lock signal CODE_LOCK when the training clock TCLK is triggered a predetermined number of times, or when the preliminary codes CODEA<4:0> meet predetermined conditions. Figure 8 The detailed configuration and operation of the training control circuit 150 are described in the document.

[0057] Internal circuitry 160 may include multiple memory cells. Internal circuitry 160 may perform a write operation to write the third data signal IDATA<7:0> to the memory cell specified by address ADD in response to a write command WT, and may perform a read operation to read the third data signal IDATA<7:0> from the memory cell specified by address ADD in response to a read command RD.

[0058] Furthermore, the memory device 100 may also include a calibration circuit 170 that generates termination control code for adjusting the resistance or impedance of on-chip termination circuitry. The calibration circuit 170 can generate termination control code that varies depending on conditions (such as process, voltage, and temperature (PVT)) by performing a ZQ calibration operation that adjusts the impedance of the resistor group to be coupled to the calibration pad ZQ to be substantially the same as the external resistor RZQ. The calibration circuit 170 can perform the ZQ calibration operation according to the calibration mode signal CAL_EN and can generate a calibration completion signal CAL_DONE after generating the termination control code through the ZQ calibration operation. The training control circuit 150 can deactivate the calibration mode signal CAL_EN according to the calibration completion signal CAL_DONE.

[0059] although Figure 3Not shown, but the memory device 100 may also include a data output circuit for outputting data from the internal circuitry 160 to an external device via the data pad DQ_P during a read operation. The data output circuit may include a termination circuit for providing pull-up and / or pull-down impedance to the data pad DQ_P during a read or write operation based on a termination control code generated by the calibration circuitry 170.

[0060] After that, reference will be made Figures 4 to 8 To describe Figure 3 Detailed configuration of each circuit.

[0061] Figure 4 The illustration shows an embodiment of the present invention. Figure 3 The circuit diagram for the first data buffer DB0 is shown below. The remaining data buffers DB1 through DB7 can have substantially the same configuration as the first data buffer DB0.

[0062] refer to Figure 4 The first data buffer DB0 may include a first inverter INV1, first and second OR gates OR1 and OR2, and first to third buffer circuits 112, 114 and 116.

[0063] The first inverter INV1 generates the inverted input control signal EN_DQB0 by inverting the first input control signal EN_DQ0. The first OR gate OR1 generates the third bias signal NEN_DQ0 by performing a logical OR operation on the first input control signal EN_DQ0 and the first bias signal NBIAS. The second OR gate OR2 generates the fourth bias signal PEN_DQ0 by performing a logical OR operation on the inverted input control signal EN_DQB0 and the second bias signal PBIAS. For reference, in normal mode, the first bias signal NBIAS is activated to a logic high level, while the second bias signal PBIAS is activated to a logic low level.

[0064] The first buffer circuit 112 may include a first pull-up transistor P1, a second pull-up transistor P2, a first pull-down transistor N1, and a second pull-down transistor N2, which are connected in series between the power supply voltage (VDD) terminal and the ground voltage (VSS) terminal. The first pull-up transistor P1 and the second pull-down transistor N2 can receive data DQ through their gates. <0> The first pull-down transistor N1 can receive a first bias signal NBIAS through its gate, while the second pull-up transistor P2 can receive a second bias signal PBIAS through its gate. One end (e.g., the drain) of the second pull-up transistor P2 and the first pull-down transistor N1 can be coupled to the first node ND1. Using this configuration, in normal modes such as write operations, the first buffer circuit 112 can buffer the data DQ input through the data pad DQ_P. <0> The logic level is inverted to transmit the inverted logic level to the first node ND1.

[0065] In addition to receiving the training clock TCLK, the first input control signal EN_DQ0, and the inverting input control signal EN_DQB0, the second buffer circuit 114 may have substantially the same configuration as the first buffer circuit 112. When the first input control signal EN_DQ0 is activated in training mode, the second buffer circuit 114 can invert the logic level of the training clock TCLK to transmit the inverted logic level to the first node ND1.

[0066] Similarly, besides receiving the signal from the first node ND1, the third bias signal NEN_DQ0, and the fourth bias signal PEN_DQ0, the third buffer circuit 116 can have substantially the same configuration as the first buffer circuit 112. In both normal and training modes, the third buffer circuit 116 can invert the signal from the first node ND1 to use the inverted signal as the first data signal DIN. <0> And the output.

[0067] Using the above configuration, the first to eighth data buffers DB0 to DB7 can receive data DQ<7:0> in normal mode to provide the first data signal DIN<7:0>. The first to eighth data buffers DB0 to DB7 can receive the training clock TCLK according to the first to eighth input control signals EN_DQ0 to EN_DQ7 to provide the first data signal DIN<7:0> in training mode.

[0068] Figure 5 The illustration shows an embodiment of the present invention. Figure 3 The configuration diagram of the delay circuit 120. Figure 6 The illustration shows an embodiment of the present invention. Figure 5 The circuit diagram of the unit delay line DL.

[0069] refer to Figure 5The delay circuit 120 may include first to eighth delay lines 121 to 128. Each delay line receives a corresponding setting code from the first to eighth setting codes CODE0<4:0> to CODE7<4:0>, and delays the corresponding data signal of the first data signal DIN<7:0> according to the delay value set by the corresponding setting code. Each of the first to eighth delay lines 121 to 128 may be implemented using a digitally controlled delay line (DCDL) whose delay value is controlled according to a digital code.

[0070] For example, the first delay line 121 may include multiple unit delay lines DL coupled in series, which are used to delay the first data signal DIN. <0> And output the second data signal DDIN <0> Each unit delay line DL can receive the first setting code CODE0<4:0>, delay the signal at the input terminal by the unit delay value set by the first setting code CODE0<4:0>, and output the delayed signal to the output terminal. The first delay line 121 can have a delay value corresponding to the value obtained by multiplying the number of unit delay lines DL by the unit delay value.

[0071] refer to Figure 6 Each unit delay line DL may include a first inverter INV2, a second inverter INV3, first to fifth MOS capacitors M11 to M15, and sixth to tenth MOS capacitors M21 to M25.

[0072] The first inverter, INV2, inverts each bit of the corresponding setup code CODE<4:0> to generate the inverted setup code CODEB<4:0>. Figure 6 Although a first inverter INV2 is illustrated, the first inverter INV2 can be arranged in an amount corresponding to the number of bits of the setting code CODE<4:0>, and according to one embodiment, it can be arranged together on multiple unit delay lines DL.

[0073] The second inverter, INV3, can be coupled between the input terminal IN and the output terminal OUT, and can invert the signal at the input terminal IN to output the inverted signal to the output terminal OUT. The first to fifth MOS capacitors M11 to M15 can be implemented as PMOS transistors with their gates commonly connected to the output terminal OUT. The first to fifth MOS capacitors M11 to M15 can each receive the bits of the setting code CODE<4:0> through their respective drains and sources. The sixth to tenth MOS capacitors M21 to M25 can be implemented as NMOS transistors with their gates commonly connected to the output terminal OUT. The sixth to tenth MOS capacitors M21 to M25 can each receive the inverted bits of the setting code CODEB<4:0 through their respective drains and sources.

[0074] Using the above configuration, the first to eighth delay lines 121 to 128 can delay the first data signal DIN<7:0> according to the delay value set by the first to eighth setting codes CODE0<4:0> to CODE7<4:0> and output the second data signal DDIN<7:0>.

[0075] Figure 7 The illustration shows an embodiment of the present invention. Figure 3 The circuit diagram of the data alignment circuit 130.

[0076] refer to Figure 7 The data alignment circuit 130 may include bit-first to bit-eighth flip-flops 131 to 138 for receiving the second data signal DDIN<7:0> respectively. The bit-first to bit-eighth flip-flops 131 to 138 may latch the second data signal DDIN<7:0> according to an internal strobe signal IDQS to output a third data signal IDATA<7:0>. Therefore, the third data signal IDATA<7:0> may be aligned as parallel data according to the internal strobe signal IDQS.

[0077] Figure 8 The illustration shows an embodiment of the present invention. Figure 3 Detailed block diagram of the training control circuit 150.

[0078] refer to Figure 8 The training control circuit 150 may include a control signal generation circuit 210, a clock generation circuit 220, a data selection circuit 230, a code generation circuit 240, a lock detection circuit 250, an input control circuit 260, and a terminal control circuit 270.

[0079] The control signal generation circuit 210 can generate a training mode signal TR_EN in response to the calibration command ZQ_CMD. The control signal generation circuit 210 can also generate a calibration mode signal CAL_EN for performing calibration operations based on a training completion signal TR_DONE indicating the completion of the training operation. The control signal generation circuit 210 can deactivate the training mode signal TR_EN based on the training completion signal TR_DONE, and deactivate the calibration mode signal CAL_EN based on the calibration completion signal CAL_DONE indicating the completion of the calibration operation. The calibration mode signal CAL_EN can be provided to... Figure 3 The calibration circuit 170 will be used. Figure 9 The detailed configuration of the control signal generation circuit 210 is described in the text.

[0080] The clock generation circuit 220 can generate a training clock TCLK that is triggered at a predetermined period based on the training mode signal TR_EN. Figure 10The detailed configuration of the clock generation circuit 220 is described in the document.

[0081] The data selection circuit 230 can select one of the third data signals IDATA<7:0> based on the first to eighth input control signals EN_DQ0 to EN_DQ7, and output the selected signal as the target signal PD_OUT. The data selection circuit 230 can select the third data signal IDATA when the first input control signal EN_DQ0 is activated. <0> When the second input control signal EN_DQ1 is activated, the third data signal IDATA is selected. <1> The output target signal PD_OUT is used, and in this way, when the eighth input control signal EN_DQ7 is activated, the third data signal IDATA is selected. <7> .

[0082] In training mode, the code generation circuit 240 generates a preliminary code CODEA<4:0> corresponding to the target signal PD_OUT provided by the data selection circuit 230 according to the training clock TCLK, and stores the preliminary code CODEA<4:0> as the first to eighth setting codes CODE0<4:0> to CODE7<4:0> according to the code lock signal CODE_LOCK. Whenever the preliminary code CODEA<4:0> is updated, the code generation circuit 240 can synchronously store and output the first to eighth setting codes CODE0<4:0> to CODE7<4:0> with the training clock TCLK. Whenever the code lock signal CODE_LOCK is activated, the code generation circuit 240 can sequentially lock the stored first to eighth setting codes CODE0<4:0> to CODE7<4:0>, so that the stored code values ​​are fixed and no longer updated.

[0083] In detail, the code generation circuit 240 may include a pre-code generation circuit 242 and a code storage circuit 244.

[0084] The pre-code generation circuit 242 can be synchronized with the training clock TCLK and increment or decrement the code value of pre-code CODEA<4:0> by "+1" according to the target signal PD_OUT. When the code lock signal CODE_LOCK is activated, the pre-code generation circuit 242 can initialize the pre-code CODEA<4:0> to an initial value. The initial value can be set to an intermediate value of the pre-code CODEA<4:0> (i.e., 16h of "10000"). Preferably, the pre-code generation circuit 242 can be implemented using an up / down counter. Each time the training clock TCLK is triggered, the up / down counter can increment the code value of the pre-code CODEA<4:0> by "+1" from the previous value according to the logic high level target signal PD_OUT, and decrement the pre-code CODEA<4:0> by "+1" from the previous value according to the logic low level target signal PD_OUT.

[0085] Whenever the preparatory code CODEA<4:0> is updated, the code storage circuit 244 can store and output the preparatory code CODEA<4:0> as the first to eighth setup codes CODE0<4:0> to CODE7<4:0>, synchronized with the training clock TCLK. Whenever the code lock signal CODE_LOCK is activated, the code storage circuit 244 can sequentially lock the stored first to eighth setup codes CODE0<4:0> to CODE7<4:0>. Figure 11 The detailed configuration of the code storage circuit 244 is described in the text.

[0086] The lock detection circuit 250 can generate a code lock signal CODE_LOCK based on the training clock TCLK and the pre-set code CODEA<4:0>. The lock detection circuit 250 can activate the code lock signal CODE_LOCK when the training clock TCLK is triggered a predetermined number of times, when the pre-set code CODEA<4:0> reaches a target value by maintaining a fixed value within a predetermined range, or when the pre-set code CODEA<4:0> reaches its maximum or minimum value. Figure 12 The detailed configuration of the lock detection circuit 250 is described in the text.

[0087] The input control circuit 260 can generate first to eighth input control signals EN_DQ0 to EN_DQ7 that are activated sequentially based on the training mode signal TR_EN and the code lock signal CODE_LOCK. When the training mode signal TR_EN is activated, the input control circuit 260 can activate the first input control signal EN_DQ0, and then sequentially activate the second to eighth input control signals EN_DQ1 to EN_DQ7 whenever the code lock signal CODE_LOCK is activated. (See reference...) Figure 13Describe the detailed configuration of the input control circuit 260.

[0088] After all the first to eighth input control signals EN_DQ0 to EN_DQ7 are activated sequentially, the terminal control circuit 270 can generate the training completion signal TR_DONE according to the code lock signal CODE_LOCK. When the code lock signal CODE_LOCK is activated after the eighth input control signal EN_DQ7 is activated, the terminal control circuit 270 can activate the training completion signal TR_DONE.

[0089] The following will refer to Figures 9 to 13 To describe Figure 8 Detailed configuration of each circuit.

[0090] Figure 9 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the control signal generation circuit 210.

[0091] refer to Figure 9 The control signal generation circuit 210 may include a first signal generation section 212 and a second signal generation section 214.

[0092] The first signal generation section 212 can generate a training mode signal TR_EN that is activated according to the calibration command ZQ_CMD and deactivated according to the training completion signal TR_DONE. The first signal generator 212 can be implemented using a D flip-flop, which receives the power supply voltage VDD as the input signal D, receives the calibration command ZQ_CMD as the clock signal, receives the training completion signal TR_DONE as the reset signal RST, and outputs the training mode signal TR_EN as the output signal Q.

[0093] The second signal generation section 214 can generate a calibration mode signal CAL_EN that is activated based on the training completion signal TR_DONE and deactivated based on the calibration completion signal CAL_DONE. The second signal generation section 214 can be implemented using a D flip-flop, which receives the power supply voltage VDD as the input signal D, receives the training completion signal TR_DONE as the clock signal, receives the calibration completion signal CAL_DONE as the reset signal RST, and outputs the calibration mode signal CAL_EN as the output signal Q.

[0094] Figure 10 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of clock generation circuit 220.

[0095] refer to Figure 10The clock generation circuit 220 can be implemented using a ring oscillator. For example, the clock generation circuit 220 may include a NAND gate ND1, a first inverter chain ICH1, and a second inverter chain ICH2. Each of the first inverter chain ICH1 and the second inverter chain ICH2 may include an even number of inverters.

[0096] The NAND gate ND1 generates an enable signal C_EN by performing a logical NAND operation on the training mode signal TR_EN and the feedback clock FCLK output from the second inverter chain ICH2. The first inverter chain ICH1 can delay the enable signal C_EN to output the training clock TCLK. The second inverter chain ICH2 can delay the training clock TCLK to output the feedback clock FCLK.

[0097] Using the above configuration, the clock generation circuit 220 can generate a training clock TCLK that is triggered by a period determined by the number of inverters, based on the training mode signal TR_EN.

[0098] Figure 11 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the code storage circuit 244.

[0099] refer to Figure 11 The code storage circuit 244 may include first to eighth registers R1 to R8 for storing first to eighth setting codes CODE0<4:0> to CODE7<4:0> respectively.

[0100] Whenever the preparatory code CODEA<4:0> is updated, registers R1 to R8 (first to eighth registers) can store and output the preparatory code CODEA<4:0> as the first to eighth setup codes CODE0<4:0> to CODE7<4:0>, synchronized with the training clock TCLK. Whenever the code lock signal CODE_LOCK is activated, registers R1 to R8 can sequentially lock the stored first to eighth setup codes CODE0<4:0> to CODE7<4:0>, preventing them from being updated. For example, when the code lock signal CODE_LOCK is activated for the first time, register R1 can fix the code value of the stored first setup code CODE0<4:0>. When the code lock signal CODE_LOCK is activated for the second time, register R2 can fix the code value of the stored second setup code CODE1<4:0>. In this way, when the code lock signal CODE_LOCK is activated for the eighth time, the eighth register R8 can fix the stored value of the eighth setting code CODE7<4:0>.

[0101] Figure 12 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the locking detection circuit 250.

[0102] refer to Figure 12 The lock detection circuit 250 may include a timer detector 252, a bang-bang detector 254, a minimum / maximum (MIN / MAX) detector 256, and an output circuit 258.

[0103] Timer detector 252 generates a first lock signal T_DONE by detecting when the number of times the training clock TCLK is triggered reaches a predetermined number. For example, when the number of times the training clock TCLK is triggered reaches "32", timer detector 252 can generate a first lock signal T_DONE that is activated to a logic high level. Timer detector 252 may include clock counter 2522 and full count detector 2524. Clock counter 2522 generates a 5-bit count code CLK_CODE<4:0> by counting the number of times the training clock TCLK is triggered. Full count detector 2524 activates the first lock signal T_DONE by detecting when all bits of the count code CLK_CODE<4:0> become high bits. Full count detector 2524 can be implemented using logic gates for performing a logical AND operation on all bits of the count code CLK_CODE<4:0>.

[0104] The switch detector 254 generates a second lock signal BB_DONE by detecting when the preparatory code CODEA<4:0> changes between two fixed values ​​based on the training clock TCLK. The switch detector 254 can detect when the preparatory code CODEA<4:0> is stored four times consecutively each time the training clock TCLK is triggered, and the code values ​​change between two fixed values. For example, when the code value of the preparatory code CODEA<4:0> changes to "15h-16h-15h-16h", the switch detector 254 can generate a second lock signal BB_DONE activated to a logic high level. For reference, with the activation of the second lock signal BB_DONE, it can be determined that the code value of the preparatory code CODEA<4:0> has reached the target value. In this case, the code value "16h" of the preparatory code CODEA<4:0> can ultimately be stored in the corresponding register of the code storage circuit 244.

[0105] The MIN / MAX detector 256 can generate a third lock signal M_DONE by detecting when the preparatory code CODEA<4:0> reaches its maximum or minimum value. When the preparatory code CODEA<4:0> reaches its maximum value "11111" or its minimum value "00000", the MIN / MAX detector 256 can generate a third lock signal M_DONE that is activated to a logic high level.

[0106] When the first lock signal T_DONE, the second lock signal BB_DONE, or the third lock signal M_DONE is activated, the output circuit 258 can activate the code lock signal CODE_LOCK. The output circuit 258 can be implemented using logic gates (e.g., NOR gate NR1 and inverter INV5) to perform a logical AND operation on the first lock signal T_DONE, the second lock signal BB_DONE, and the third lock signal M_DONE.

[0107] Using the above configuration, when the number of times the training clock TCLK is triggered reaches a predetermined number, the pre-set code CODEA<4:0> is maintained at a fixed value within a predetermined range, or the pre-set code CODEA<4:0> reaches its maximum or minimum value, the lock detection circuit 250 can activate the code lock signal CODE_LOCK.

[0108] Figure 13 The illustration shows an embodiment of the present invention. Figure 8 Detailed circuit diagram of the input control circuit 260.

[0109] refer to Figure 13 The input control circuit 260 may include a first input controller 262 and a second input controller 264.

[0110] The first input controller 262 may include a first D flip-flop 2622, a first NAND gate ND2, and a first inverter INV6. The first D flip-flop 2622 can receive the ground voltage VSS as the input signal D, the code lock signal CODE_LOCK as the clock signal, and the training mode signal TR_EN as the set signal SET, and output the seed signal SEED as the output signal Q. When the training mode signal TR_EN is activated, the first D flip-flop 2622 can initialize the seed signal SEED to a logic high level. When the code lock signal CODE_LOCK is activated, the first D flip-flop 2622 can output the seed signal SEED to a logic low level. The first NAND gate ND2 and the first inverter INV6 can perform a logical AND operation on the seed signal SEED and the training mode signal TR_EN to output the first input control signal EN_DQ0. Using the above configuration, the first input control unit 262 can generate a first input control signal EN_DQ0, which is activated when the training mode signal TR_EN is activated, and deactivated once the code lock signal CODE_LOCK is activated.

[0111] The second input controller 264 may include second to eighth D flip-flops 2641 to 2647 coupled in series. The second D flip-flop 2641 may receive the first input control signal EN_DQ0 as an input signal D, and the second to eighth D flip-flops 2641 to 2647 may respectively output second to eighth input control signals EN_DQ1 to EN_DQ7. The second to eighth D flip-flops 2641 to 2647 may receive the code lock signal CODE_LOCK as a clock signal and the training mode signal TR_EN as a reset signal RST. When the training mode signal TR_EN is activated, the second to eighth D flip-flops 2641 to 2647 may initialize all of the second to eighth input control signals EN_DQ1 to EN_DQ7 to a logic low level. When the code lock signal CODE_LOCK is activated, the second to eighth D flip-flops 2641 to 2647 may sequentially change the first input control signal EN_DQ0 to output the first to eighth input control signals EN_DQ1 to EN_DQ7. Using the above configuration, whenever the code lock signal CODE_LOCK is activated after the first input control signal EN_DQ0 is activated, the second input control unit 264 can sequentially activate the second to eighth input control signals EN_DQ1 to EN_DQ7.

[0112] After that, reference will be made Figures 1 to 16 The operation of a memory device 100 according to an embodiment of the present invention is described.

[0113] Figure 14This is a timing diagram used to describe the operation of a memory device according to an embodiment of the present invention. Figure 15 and Figure 16 This is a flowchart describing the operation of a memory device according to an embodiment of the present invention.

[0114] refer to Figure 14 and Figure 15 During power-on (at S110), the memory controller 30 can provide a logic low-level chip enable signal CE# to the memory device 20, and provide data DQ<7:0> including the command CMD indicating an initialization operation “FFh”, together with a logic high-level command latch enable signal CLE. The C / A control circuit 140 of the memory device 20 can receive the data DQ<7:0> of “FFh” at the rising edge of the write enable signal WE#, and generate a calibration command ZQ_CMD based on the received data DQ<7:0> (at S120).

[0115] The control signal generation circuit 210 can activate the training mode signal TR_EN (at S130) in response to the calibration command ZQ_CMD. According to the training mode signal TR_EN, the memory device 100 can perform a training operation that sequentially sets the delay values ​​of the first to eighth delay lines 121 to 128 coupled to the data pad DQ_P (at S140).

[0116] For details, please refer to Figure 14 and Figure 16 When the training mode signal TR_EN is activated (at S1410), the input control circuit 260 activates the first input control signal EN_DQ0 (at S1420), and the clock generation circuit 220 can generate a training clock TCLK that is triggered at a predetermined period. The first data buffer DB0, one of the first to eighth data buffers DB0 to DB7, can receive the training clock TCLK according to the first input control signal EN_DQ0 to provide the first data signal DIN. <0> The data gating buffer DSB can receive the training clock TCLK to provide the internal gating signal IDQS. In this case, all remaining data buffers DB1 to DB7 can be deactivated according to the second to eighth input control signals EN_DQ1 to EN_DQ7.

[0117] Simultaneously, synchronized with the training clock TCLK, the code generation circuit 240 can output the preparatory code CODEA<4:0> set to an initial value (e.g., "16h") as the first to eighth setup codes CODE0<4:0> to CODE7<4:0>. The first to eighth delay lines 121 to 128 can output the second data signal DDIN<7:0> by delaying the first data signal DIN<7:0> by the corresponding delay values ​​of the first to eighth setup codes CODE0<4:0> to CODE7<4:0>. The data alignment circuit 130 can output the third data signal IDATA<7:0> by aligning the second data signal DDIN<7:0> according to the internal strobe signal IDQS. The data selection circuit 230 can select the third data signal IDATA from the third data signal IDATA<7:0> according to the first input control signal EN_DQ0. <0> and the selected data signal IDATA <0> It is output as the target signal PD_OUT.

[0118] Synchronized with the training clock TCLK, the preparatory code generation circuit 242 can increment the code value of the preparatory code CODEA<4:0> by "+1" according to the target signal PD_OUT to generate the code value "17h" (at S1430). Whenever the preparatory code CODEA<4:0> is updated, the code storage circuit 244 can store and output the preparatory code CODEA<4:0> as the first to eighth setting codes CODE0<4:0> to CODE7<4:0>. The first to eighth delay lines 121 to 128 can delay the first data signal DIN<0:7> again by the set delay value according to the adjusted setting code to output the second data signal DDIN<0:7> (at S1440).

[0119] After repeating the above operations S1430 to S1440, when the preparatory code CODEA<4:0> is detected to change between two fixed values, the lock detection circuit 250 can activate the second lock signal BB_DONE. As a result, the lock detection circuit 250 can activate the code lock signal CODE_LOCK ("Yes" in S1450).

[0120] When the code lock signal CODE_LOCK is activated, the pre-code generation circuit 242 can initialize the pre-code CODEA<4:0> to an initial value (e.g., "16h"), and the code storage circuit 244 can lock the current first setting code CODE0<4:0> (e.g., "17h") to prevent it from being updated (at S1460). Thereafter, the input control circuit 260 can activate the second input control signal EN_DQ1 (at S1480).

[0121] As the second to eighth input control signals EN_DQ1 to EN_DQ7 are activated sequentially, the above operations S1420 to S1460 are repeated, and finally, when the eighth setting code CODE7<4:0> for the eighth delay line 128 is locked, the terminal control circuit 270 can activate the training completion signal TR_DONE ("Yes" in S1470).

[0122] Return to reference Figure 14 and Figure 15 The control signal generation circuit 210 can activate the calibration mode signal CAL_EN (at S150) for performing calibration operations based on the training completion signal TR_DONE.

[0123] The calibration circuit 170 can generate terminal control code by performing a ZQ calibration operation based on the calibration mode signal CAL_EN, which adjusts the impedance of the resistor group to be coupled to the calibration pad ZQ to be substantially the same as the external resistor RZQ (at S160).

[0124] As described above, according to one embodiment of the present invention, the semiconductor device can automatically perform a write training operation before performing a ZQ calibration operation based on a calibration command generated therein during power-on. Therefore, operational efficiency can be improved, and at the same time, randomly generated deviations for each semiconductor device can be minimized. Furthermore, during the write training operation, the semiconductor device can sequentially adjust the delay value of the input path of the data signal based on the delay value of the input path of the data strobe signal. Therefore, the phase difference between the data signals can be reduced, while increasing the timing margin to meet the time specification tDQ2DQ between the data signals, and improving operational reliability.

[0125] While the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

[0126] For example, the logic gates and transistors described in the above embodiments can have different locations and types depending on the polarity of the input signal. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: The data input circuit is adapted to receive a training clock to provide a first data signal and a strobe signal in training mode based on multiple input control signals; A delay circuit is adapted to output a second data signal by delaying the first data signal according to a delay value corresponding to a corresponding setting code; A data alignment circuit is adapted to output a third data signal by aligning the second data signal according to the gating signal; The code generation circuit is adapted to generate a preliminary code corresponding to the third data signal according to the training clock, and to store the preliminary code as the setting code sequentially according to the code locking signal; as well as A lock detection circuit is adapted to activate the code lock signal based on the training clock and the pre-set code.

2. The semiconductor device according to claim 1, further comprising: A control signal generation circuit is adapted to generate a training mode signal indicating entry into the training mode in response to a calibration command; A clock generation circuit is adapted to generate the training clock based on the training mode signal; as well as An input control circuit is adapted to generate sequentially activated input control signals based on the training mode signal and the code lock signal.

3. The semiconductor device according to claim 2, It also includes terminal control circuitry adapted to generate a training completion signal based on the code lock signal after all the input control signals have been activated. The control signal generation circuit is further adapted to generate a calibration mode signal for performing calibration operations based on the training completion signal.

4. The semiconductor device according to claim 3, wherein the control signal generation circuit comprises: The first signal generation section is adapted to generate the training mode signal that is activated according to the calibration command and deactivated according to the training completion signal; as well as The second signal generation section is adapted to generate a calibration mode signal that is activated according to the training completion signal and deactivated according to the calibration completion signal.

5. The semiconductor device according to claim 3, wherein the input control circuit comprises: A first input controller is adapted to activate the first input control signal among the first to Nth input control signals when the training mode signal is activated; as well as The second input controller is adapted to sequentially activate the second to the Nth input control signals whenever the code lock signal is activated after the first input control signal is activated.

6. The semiconductor device according to claim 1, The data input circuit includes multiple data buffers coupled to corresponding data pads and adapted to receive corresponding input control signals. Each of the data buffers mentioned above includes: The first buffer circuit is adapted to provide the first node with data signals input through the corresponding data pads in normal mode; A second buffer circuit is adapted to provide the training clock to the first node in response to the corresponding input control signal in the training mode. as well as The third buffer circuit is adapted to output the data signal or the training clock provided to the first node as the corresponding first data signal in the first data signal.

7. The semiconductor device of claim 1, wherein the delay circuit comprises a plurality of delay lines, each delay line being adapted to output a corresponding second data signal in the second data signal by delaying a corresponding first data signal in the first data signal according to the delay value set by a corresponding setting code in the setting code.

8. The semiconductor device according to claim 7, Each of the delay lines comprises a series-coupled unit delay line, and each unit delay line includes: An inverter is coupled between the input and output terminals of the unit delay line; Multiple type-1 MOS capacitors are adapted to receive bits of the corresponding setting code through their respective drains and sources, and are coupled together to the output terminal through their gates; as well as Multiple type II MOS capacitors are adapted to receive the inverted bits of the corresponding setting codes through their respective drains and sources, and are coupled together to the output terminal through their gates.

9. The semiconductor device of claim 1, further comprising a data selection circuit, the data selection circuit being adapted to: The third data signal is selected from the third data signals according to the input control signal, and The selected third data signal is output as the target signal to the code generation circuit.

10. The semiconductor device of claim 1, wherein the code generation circuit comprises: The pre-programmed code generation circuit is capable of operating synchronously with the training clock and is suitable for: The code value of the preparatory code is increased or decreased based on the target signal in the third data signal, and The pre-programmed code is initialized according to the code lock signal; and The code storage circuit is capable of operating synchronously with the training clock and is suitable for: The preparatory code is stored and output sequentially as the setting code, and Whenever the code lock signal is activated, the stored setting codes are locked sequentially.

11. The semiconductor device of claim 10, wherein the code storage circuitry comprises a plurality of registers adapted to store and output the preparatory code as the setup code in synchronization with the training clock, and to sequentially lock the setup codes stored therein whenever the code lock signal is activated.

12. The semiconductor device of claim 1, wherein the lock detection circuit activates the code lock signal when: The training clock is triggered a predetermined number of times. The pre-programmed code changes between two fixed values ​​based on the training clock, or The preparatory code reaches its maximum or minimum value.

13. A method of operating a semiconductor device, comprising: Generate calibration commands during its power-on period; In response to the calibration command, a training mode signal is generated; Training operations are performed according to the training mode signal, wherein the training operations sequentially set the delay values ​​of the corresponding delay lines coupled to the corresponding data pads; After completing the training operation, a calibration mode signal is generated. as well as The calibration operation is performed based on the calibration mode signal.

14. The operation method according to claim 13, wherein the execution of the training operation includes: The code lock signal is activated by performing the following operations for each of the delay values: delaying the training clock via a selected delay line among the delay lines, aligning the delayed clock to output an internal data signal according to a strobe signal, generating a pre-code corresponding to the internal data signal, and adjusting the delay value of the selected delay line according to the pre-code. as well as After activating the code lock signal for all delay lines, a training completion signal indicating the completion is output.

15. The method of operation according to claim 14, wherein generating the preparatory code includes increasing or decreasing the code value of the preparatory code based on the internal data signal.

16. The method of operation according to claim 14, wherein the code lock signal is activated under the following conditions: The training clock is triggered a predetermined number of times. The pre-programmed code changes between two fixed values ​​based on the training clock, or The preparatory code reaches its maximum or minimum value.

17. The method of operation of claim 14, further comprising: When the code lock signal is activated, the pre-set code is locked as a setting code for setting the delay value of the selected delay line.

18. The method of operation of claim 13, wherein the calibration operation comprises: Adjust the impedance of the resistor group to be coupled to the calibration pad to be substantially the same as the external resistor.

19. A semiconductor system, comprising: The controller is suitable for providing initialization commands; as well as Semiconductor equipment, suitable for: Generate calibration commands based on the initialization commands. In response to the calibration command, a training mode signal is generated. Training operations are performed based on the training mode signal, wherein the training operations sequentially set the delay values ​​of the corresponding delay lines coupled to the corresponding data pads. After completing the training operation, a calibration mode signal is generated, and The calibration operation is performed based on the calibration mode signal.

20. The semiconductor system of claim 19, wherein the semiconductor device comprises: A control signal generation circuit is adapted to generate the training mode signal in response to the calibration command; A clock generation circuit is adapted to generate a training clock based on the training mode signal; An input control circuit is adapted to generate a plurality of sequentially activated input control signals based on the training mode signal and the code lock signal; A data input circuit is adapted to receive the training clock to provide a first data signal and a strobe signal according to the input control signal; A delay circuit is adapted to output a second data signal by delaying the first data signal according to a delay value corresponding to a corresponding setting code; A data alignment circuit is adapted to output a third data signal by aligning the second data signal according to the gating signal; The code generation circuit is adapted to generate a preliminary code corresponding to the third data signal according to the training clock, and to store the preliminary code as the setting code sequentially according to the code locking signal; as well as A lock detection circuit is adapted to generate the code lock signal based on the training clock and the pre-trained code.

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