Control device and device control method

Abstract

The embodiment of the application discloses a kind of control equipment and equipment control method, belong to electronic technical field.The control equipment includes processor, first function circuit, second function circuit and output circuit;Processor is used to respond to control instruction, to first function circuit and second function circuit output first control signal, and to first function circuit output first control signal;First function circuit is used to receive first control signal and turn on, and first control signal is transmitted to output circuit;Second function circuit is used to carry out inverting transformation to first control signal, and the second control signal obtained by transformation is output to output circuit;Output circuit is used to send third control signal to controlled equipment based on the first control signal in the level state of first control signal and second control signal is different.Scheme provided in the application embodiment, the anti-interference ability of the transmission signal mode of control equipment is strong, and reliability is high.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a control device and a device control method. Background Technology

[0002] Control devices are typically capable of controlling electronic equipment. For example, a control device is a data acquisition unit in a data center, which can control equipment such as switches or power supplies in the data center.

[0003] In related technologies, control devices include processors and output ports. The processor, in response to device control commands, transmits control signals to the output port, which then transmits these control signals to the controlled device. However, interference with the signal transmission line between the processor and the output port, or processor malfunctions, can all cause interference with the control signals. Therefore, the aforementioned signal transmission methods have weak anti-interference capabilities and low reliability. Summary of the Invention

[0004] This application provides a control device and a device control method, which can improve the anti-interference capability and reliability of the signal transmission method of the control device. The technical solution is as follows:

[0005] On the one hand, a control device is provided, the control device including a processor, a first functional circuit, a second functional circuit and an output circuit;

[0006] The processor is electrically connected to the first functional circuit and the second functional circuit respectively, and the first functional circuit and the second functional circuit are electrically connected to the output circuit respectively;

[0007] The processor is configured to, in response to a control command, output a first control signal to the first functional circuit and the second functional circuit, and output a first conduction signal to the first functional circuit;

[0008] The first functional circuit is used to receive the first conduction signal and conduct, and to transmit the first control signal to the output circuit;

[0009] The second functional circuit is used to invert the first control signal and output the resulting second control signal to the output circuit.

[0010] The output circuit is used to send a third control signal to the controlled device based on the first control signal when the level states of the first control signal and the second control signal are different.

[0011] On the other hand, a device control method is provided, executed by a control device, the control device including a processor, a first functional circuit, a second functional circuit, and an output circuit; the processor is electrically connected to the first functional circuit and the second functional circuit respectively, and the first functional circuit and the second functional circuit are electrically connected to the output circuit respectively; the method includes:

[0012] In response to a control command, the processor outputs a first control signal to the first functional circuit and the second functional circuit, and outputs a first conduction signal to the first functional circuit.

[0013] The first functional circuit receives the first conduction signal and conducts, transmitting the first control signal to the output circuit;

[0014] The second functional circuit performs an inversion transformation on the first control signal and outputs the transformed second control signal to the output circuit;

[0015] When the level states of the first control signal and the second control signal are different, the output circuit sends a third control signal to the controlled device based on the first control signal.

[0016] In one possible implementation, the output circuit includes an XOR gate logic circuit, a third AND gate logic circuit, and a relay; the first functional circuit is electrically connected to the XOR gate logic circuit and the third AND gate logic circuit, respectively; the second functional circuit is electrically connected to the XOR gate logic circuit; the XOR gate logic circuit is electrically connected to the third AND gate logic circuit; and the third AND gate logic circuit is electrically connected to the relay.

[0017] The first functional circuit transmits the first control signal to the output circuit, including:

[0018] The first functional circuit transmits the first control signal to the XOR gate logic circuit and outputs the first control signal to the third AND gate logic circuit;

[0019] The second functional circuit outputs the transformed second control signal to the output circuit, including:

[0020] The second functional circuit outputs the transformed second control signal to the XOR gate logic circuit;

[0021] When the level states of the first control signal and the second control signal are different, the output circuit sends a third control signal to the controlled device based on the first control signal, including:

[0022] When the level states of the first control signal and the second control signal are different, the XOR gate logic circuit outputs a sixth control signal in a high-level state to the third AND gate logic circuit.

[0023] The third AND gate logic circuit outputs the first control signal to the relay, controlling the relay to send the third control signal to the controlled device.

[0024] In another possible implementation, the output circuit further includes a driving circuit; the third AND gate logic circuit is electrically connected to the driving circuit, and the driving circuit is electrically connected to the relay; the third AND gate logic circuit outputs the first control signal to the relay, controlling the relay to send the third control signal to the controlled device, including:

[0025] The third AND gate logic circuit outputs the first control signal to the drive circuit;

[0026] The driving circuit drives the relay so that the relay sends the third control signal to the controlled device.

[0027] In another possible implementation, the control device further includes a readback circuit; the output circuit is electrically connected to the readback circuit, and the readback circuit is electrically connected to the processor; the method further includes:

[0028] When the level states of the first control signal and the second control signal are different, the output circuit also outputs the first control signal to the readback circuit.

[0029] The readback circuit performs an inversion transformation on the first control signal to obtain a seventh control signal, and outputs the seventh control signal to the processor;

[0030] The processor performs an inverse transformation on the seventh control signal, compares the transformed control signal with the first control signal, and if the transformed control signal is different from the first control signal, outputs the first control signal again to the first functional circuit and the second functional circuit.

[0031] In the solution provided in this application embodiment, the control device includes a processor, a first functional circuit, a second functional circuit, and an output circuit. When it is necessary to control the controlled device, the processor outputs a first control signal to the first functional circuit and the second functional circuit respectively, controlling the first functional circuit to conduct. The first functional circuit outputs the first control signal to the output circuit, and the second functional circuit outputs the control signal after inverting the first control signal to the output circuit. When the processor is normal and the signal lines transmitting signals in the control device are not interfered with, the output circuit receives two control signals with different level states, and then controls the controlled device based on the first control signal. However, due to processor malfunction or interference with the signal lines transmitting signals in the control device, it is impossible to simultaneously enable the first functional circuit to conduct and for the first and second control signals output to the output circuit to have different level states. Therefore, no control signal will be sent to the controlled device, reducing the possibility of sending incorrect control signals to the controlled device due to processor malfunction or interference with the signal lines transmitting signals in the control device. This ensures the accuracy of the output control signal. The signal transmission method of this control device has strong anti-interference capability and high reliability. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a control device provided in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of another control device provided in an embodiment of this application;

[0035] Figure 3 This is a schematic diagram of the structure of another control device provided in the embodiments of this application;

[0036] Figure 4 This is a schematic diagram of the structure of another control device provided in the embodiments of this application;

[0037] Figure 5 This is a schematic diagram of the structure of another control device provided in the embodiments of this application;

[0038] Figure 6 This is a schematic diagram of the structure of another control device provided in the embodiments of this application;

[0039] Figure 7 This is a schematic diagram of the structure of another control device provided in the embodiments of this application;

[0040] Figure 8 This is a schematic diagram of the structure of another control device provided in the embodiments of this application;

[0041] Figure 9 This is a flowchart of a device control method provided in an embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0043] The terms “first,” “second,” “third,” “fourth,” “fifth,” “sixth,” etc., used in this application may be used to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are used only to distinguish one concept from another. For example, without departing from the scope of this application, a first control signal may be referred to as a second control signal, and similarly, a second control signal may be referred to as a first control signal.

[0044] As used in this application, the terms "at least one," "multiple," "each," and "any" have the following meanings: at least one includes one, two, or more; multiple includes two or more; each refers to each of the corresponding multiple; and any refers to any one of the multiple. For example, multiple input ports include three input ports, where each refers to each of the three input ports, and any refers to any one of the three input ports, which could be the first input port, the second input port, or the third input port.

[0045] Figure 1 This is a schematic diagram of a control device provided in an embodiment of this application, such as... Figure 1 As shown, the control device includes a processor 101, a first functional circuit 102, a second functional circuit 103, and an output circuit 104.

[0046] In this embodiment, the processor 101 is electrically connected to the first functional circuit 102 and the second functional circuit 103, respectively; the first functional circuit 102 and the second functional circuit 103 are electrically connected to the output circuit 104, respectively. Through its electrical connection with the first functional circuit 102, the processor 101 can output signals to the first functional circuit 102; through its electrical connection with the second functional circuit 103, the processor 101 can output signals to the second functional circuit 103. Through its electrical connection with the output circuit 104, the first functional circuit 102 can output signals to the output circuit 104. Through its electrical connection with the second functional circuit 104, the second functional circuit 103 can output signals to the output circuit 104.

[0047] The processor 101 is configured to, in response to a control command, output a first control signal to the first functional circuit 102 and the second functional circuit 103, and output a first turn-on signal to the first functional circuit 102.

[0048] In this embodiment of the application, the control device is capable of controlling electronic devices. The processor 101 is the control center of the control device, used to output control signals for controlling electronic devices or output signals for controlling circuits. The processor 101 can be any type of processor, for example, the processor 101 is a CPU (Central Processing Unit).

[0049] The control instruction instructs the processor 101 to output a control signal for controlling a controlled device. This first control signal is used to control the controlled device. A first conduction signal is used to control the first functional circuit 102 to conduct. This first conduction signal is a signal at any level, and its level is determined by the configuration of the first functional circuit 102. For example, a high-level signal can enable the first functional circuit 102 to conduct; that is, the first conduction signal output by the processor 101 is a high-level signal. Alternatively, both high-level and low-level signals are required for the first functional circuit 102 to conduct; that is, the first conduction signal output by the processor 101 includes both high-level and low-level signals.

[0050] In this embodiment of the application, when the control device needs to control the controlled device, the processor 101 first outputs the first control signal to the first functional circuit 102 and the second functional circuit 103, and then the first functional circuit 102 and the second functional circuit 103 output the control signal to the output circuit 104 so that the output circuit 104 sends the control signal to the controlled device.

[0051] In this embodiment, when the first functional circuit 102 is in a non-conducting state, the first functional circuit 102 cannot output the signal to the output circuit 104. When the first functional circuit 102 is in a conducting state, the first functional circuit 102 can output the signal to the output circuit 104. For example, the first functional circuit 102 includes an input port and an output port. The input port is electrically connected to the processor 101, and the output port is electrically connected to the output circuit 104. When the first functional circuit 102 is in a non-conducting state, the input port and the output port are disconnected. After the processor 101 outputs the first control signal to the input port of the first functional circuit 102, the first functional circuit 102 cannot output the first control signal received by the input port to the output port. When the first functional circuit 102 is in a conducting state, the input port and the output port are connected. After the processor 101 outputs the first control signal to the input port of the first functional circuit 102, the input port of the first functional circuit 102 can output the first control signal received by the input port to the output port.

[0052] After the processor 101 outputs a first control signal to the first functional circuit 102, if the first functional circuit 102 needs to output the first control signal to the output circuit 104, the processor 101 outputs a first conduction signal to the first functional circuit 102 to control the first functional circuit 102 to conduct, so that the first functional circuit 102 can subsequently output the first control signal to the output circuit 104. In this embodiment, the processor 101 is provided with a computer program that controls the first functional circuit 102. When it is necessary for the first functional circuit 102 to transmit a control signal to the output circuit 104, the processor 101 runs the computer program, first outputs the control signal to the first functional circuit 102, and then outputs the first conduction signal to the first functional circuit 102 to control the first functional circuit 102 to conduct.

[0053] The first functional circuit 102 is used to receive the first conduction signal and conduct it, and to transmit the first control signal to the output circuit 104.

[0054] After receiving the first conduction signal, the first functional circuit 102 is turned on. After the first functional circuit 102 is turned on, it can output the first control signal from the processor 101 to the first functional circuit 102 to the output circuit 104.

[0055] The second functional circuit 103 is used to invert the first control signal and output the resulting second control signal to the output circuit 104.

[0056] The second functional circuit 103 is used to perform an inversion transformation on the control signal and to establish communication between the processor 101 and the output circuit 104. An inversion transformation refers to reversing the level state of a signal. The level state refers to the state of a signal in a digital logic circuit, which includes a high-level state or a low-level state. For example, a high-level state is represented by the digit "1", and a low-level state is represented by the digit "0". For instance, if the first control signal output to the second functional circuit 103 has a high-level state, the second functional circuit 103 performs an inversion transformation on this first control signal, resulting in a second control signal with a low-level state. Similarly, if the first control signal output to the second functional circuit 103 has a low-level state, the second functional circuit 103 performs an inversion transformation on this first control signal, resulting in a second control signal with a high-level state. During the inversion transformation, the phase of the signal is reversed by 180 degrees, thereby reversing the signal's level state.

[0057] The output circuit 104 is used to send a third control signal to the controlled device based on the first control signal when the level states of the first control signal and the second control signal are different.

[0058] In this embodiment, after the first functional circuit 102 is turned on, the processor 101 outputs a first control signal to the first functional circuit 102, which is then output to the output circuit 104. The second functional circuit 103 inverts the first control signal output to the first functional circuit 102 and outputs the resulting second control signal to the output circuit 104. That is, the signal output to the output circuit 104 includes the first control signal and the second control signal. When the processor 101, the first functional circuit 102, and the second functional circuit 103 are all normal and not interfered with, the level states of the first control signal and the second control signal output to the output circuit 104 should be different. Then, the output circuit 104 sends a third control signal to the controlled device based on the first control signal to control the controlled device.

[0059] The output circuit 104 outputs a control signal. The controlled device can be any type of device, such as a switch or a power supply. The third control signal is generated based on the first control signal. For example, the first control signal is a high-level signal, and the controlled device is a switch. When the level of the first control signal differs from that of the second control signal, the output circuit 104 sends a third control signal to the controlled device based on the first control signal to instruct the switch to close. In this embodiment, the output circuit 104 is electrically connected or wirelessly connected to the controlled device. The output circuit 104 can send the third control signal to the controlled device based on this electrical or wireless connection.

[0060] In the solution provided in this application embodiment, the control device includes a processor, a first functional circuit, a second functional circuit, and an output circuit. When it is necessary to control the controlled device, the processor outputs a first control signal to the first functional circuit and the second functional circuit respectively, controlling the first functional circuit to conduct. The first functional circuit outputs the first control signal to the output circuit, and the second functional circuit outputs the control signal after inverting the first control signal to the output circuit. When the processor is normal and the signal lines transmitting signals in the control device are not interfered with, the output circuit receives two control signals with different level states, and then controls the controlled device based on the first control signal. However, due to processor malfunction or interference with the signal lines transmitting signals in the control device, it is impossible to simultaneously enable the first functional circuit to conduct and for the first and second control signals output to the output circuit to have different level states. Therefore, no control signal will be sent to the controlled device, reducing the possibility of sending incorrect control signals to the controlled device due to processor malfunction or interference with the signal lines transmitting signals in the control device. This ensures the accuracy of the output control signal. The signal transmission method of this control device has strong anti-interference capability and high reliability.

[0061] In one possible implementation, such as Figure 2 As shown, the first functional circuit 102 includes a first inverter 1021, a first AND gate logic circuit 1022, and a first latch 1023; the processor 101 is electrically connected to the first inverter 1021, the first AND gate logic circuit 1022, and the first latch 1023, respectively. The first inverter 1021 is electrically connected to the first AND gate logic circuit 1022, the first AND gate logic circuit 1022 is electrically connected to the first latch 1023, and the first latch 1023 is electrically connected to the output circuit 104. The first conduction signal includes a fourth control signal in a low-level state and a first clock signal in a rising-edge state.

[0062] The rising edge state is a state generated by switching from a low level state to a high level state. The fourth control signal is used to control the first functional circuit 102. This fourth control signal can be of any type, for example, an enable signal. In this embodiment, the fourth control signal, which is in a low level state, and the first clock signal, which is in a rising edge state, output by the processor 101 to the first functional circuit 102 work together to control the first functional circuit 102 to be turned on.

[0063] The first inverter 1021 is used to invert the signal, and it can be any type of inverter. The first latch 1023 is a level-sensitive memory cell circuit that changes its state under the action of a specific input pulse level. The first latch 1023 can be any type of latch, for example, an SN74LS273. In this embodiment, the first latch 1023 has two states: an on state and a off state. The default state of the first latch 1023 is the off state, meaning the first functional circuit 102 is not on. Under the action of a rising edge signal, the first latch 1023 switches from the off state to the on state; that is, the rising edge signal controls the first latch 1023 to turn on, which in turn turns the first functional circuit 102 on. Optionally, the first latch 1023 includes at least one pair of ports, each pair including an input port and an output port. After a signal is output to any input port, the first latch 1023 can only output the signal of that input port to the corresponding output port when the first latch 1023 is in the ON state.

[0064] The first AND gate logic circuit 1022 is a logic gate circuit. When the level states of multiple signals output to the first AND gate logic circuit 1022 are all rising edge states or high level states, the first AND gate logic circuit 1022 outputs a signal in the rising edge state or a signal in the high level state. When the level state of any one of the multiple signals output to the first AND gate logic circuit 1022 is falling edge state or low level state, the first AND gate logic circuit 1022 outputs a signal in the low level state. For example, if one of the two signals output to the first AND gate logic circuit 1022 is in a rising edge state and the other is in a high level state, then the first AND gate logic circuit 1022 outputs a signal in a rising edge state; or, if both of the two signals output to the first AND gate logic circuit 1022 are in a high level state, then the first AND gate logic circuit 1022 outputs a signal in a high level state; or, if one of the two signals output to the first AND gate logic circuit 1022 is in a rising edge state and the other is in a low level state, then the first AND gate logic circuit 1022 outputs a signal in a low level state.

[0065] Optionally, the first AND gate logic circuit 1022 includes multiple input ports and one output port. Each input port of the first AND gate logic circuit 1022 is used to receive a signal, and the output port of the first AND gate logic circuit 1022 is used to output a signal.

[0066] In the first AND gate logic circuit 1022, the signals received by the multiple input ports are all in a rising edge state or a high level state, and the output port of the first AND gate logic circuit 1022 outputs a signal in a rising edge state or a high level state. If any signal received by the multiple input ports of the first AND gate logic circuit 1022 is in a falling edge state or a low level state, the output port of the first AND gate logic circuit 1022 outputs a signal in a low level state. In the embodiments of this application, as... Figure 2 As shown, taking the first AND gate logic circuit 1022, which includes two input ports and one output port, as an example, the first inverter 1021 outputs a signal to one input port of the first AND gate logic circuit 1022, and the processor 101 outputs a signal to the other port of the first AND gate logic circuit 1022.

[0067] The processor 101 is configured to respond to the control instruction by outputting the first control signal to the first latch 1023, outputting a fourth control signal in the low-level state to the first inverter 1021, and outputting the first clock signal in the rising edge state to the first AND gate logic circuit 1022.

[0068] The first inverter 1021 is used to invert the fourth control signal to obtain a fourth control signal in a high-level state, and output the fourth control signal in a high-level state to the first AND gate logic circuit 1022.

[0069] The first AND gate logic circuit 1022 is used to output the first clock signal in the rising edge state to the first latch 1023.

[0070] The first latch 1023 is used to receive the first clock signal in the rising edge state and turn it on, and output the first control signal to the output circuit 104.

[0071] After the processor 101 outputs the first control signal to the first latch 1023, it also outputs a first conduction signal to the first functional circuit 102, that is, it outputs a fourth control signal in a low-level state to the first inverter 1021 and a first clock signal in a rising-edge state to the first AND gate logic circuit 1022. The first inverter 1021 inverts the fourth control signal in a low-level state to obtain a fourth control signal in a high-level state, and outputs the fourth control signal in a high-level state to the first AND gate logic circuit 1022. At this time, the signals output to the first AND gate logic circuit 1022 include a fourth control signal in a high-level state and a first clock signal in a rising edge state. The first AND gate logic circuit 1022 outputs the first clock signal in a rising edge state and outputs the first clock signal in a rising edge state to the first latch 1023 to control the first latch 1023 to be turned on. The first latch 1023 then outputs the first control signal output to the first latch 1023 to the output circuit 104.

[0072] In this embodiment, considering that the same interference source usually switches the signal level to a high level or a low level, according to the circuit structure of the first functional circuit, the processor can only turn on the first functional circuit by outputting a fourth control signal in a low level state and a first clock signal in a rising edge state to the first functional circuit, and then transmit the first control signal to the output circuit. In this way, even if the first conduction signal transmitted by the processor to the first functional circuit is interfered with, it will only cause the level states of the two signals contained in the first conduction signal to switch to a high level state or a low level state at the same time, and will not turn on the first latch. This can avoid the situation where the first latch outputs an incorrect signal due to processor abnormality or interference with the signal line of the transmission signal, thereby improving the anti-interference capability of the first functional circuit, that is, improving the anti-interference capability of the control device.

[0073] Optionally, the processor 101 is further configured to output a fourth control signal in a high-level state to the first inverter 1021, and output a first clock signal in a low-level state to the first AND gate logic circuit 1022; after outputting the first control signal to the first functional circuit 102 and the second functional circuit 103, the processor 101 converts the level state of the first clock signal to the high-level state to generate the first clock signal in the rising edge state, and converts the level state of the fourth control signal to the low-level state.

[0074] In this embodiment, the processor 101 continuously outputs a fourth control signal to the first inverter 1021 and a first clock signal to the first AND gate logic circuit 1022. When the first functional circuit 102 does not need to transmit control signals to the output circuit 104, the fourth control signal output by the processor 101 to the first inverter 1021 is at a high level, and the first clock signal output to the first AND gate logic circuit 1022 is at a low level. The first inverter 1021 inverts the fourth control signal to obtain a fourth control signal at a low level and outputs a fourth control signal at a low level to the first AND gate logic circuit 1022. At this time, both the fourth control signal and the first clock signal output to the first AND gate logic circuit 1022 are at a low level, so the first AND gate logic circuit 1022 outputs a signal at a low level to the first latch 1023, making it impossible to control the first latch 1023 to conduct.

[0075] After the processor 101 outputs the first control signal to the first latch 1023 in the first functional circuit 102, the first functional circuit 102 needs to output the first control signal to the output circuit 104. At this time, the processor 101 changes the level of the first clock signal to the high level to generate the first clock signal in the rising edge state, and changes the level of the fourth control signal to the low level state. That is, the processor 101 outputs the fourth control signal in the low level state to the first inverter 1021 and outputs the first clock signal in the rising edge state to the first AND gate logic circuit 1022 to control the first latch 1023 to be turned on, so that the first latch 1023 outputs the first control signal to the output circuit 104.

[0076] In this embodiment, when there is no need to control the controlled device, the processor outputs a fourth control signal in a high-level state to the first inverter and a first clock signal in a low-level state to the first AND gate logic circuit. Only when it is necessary to control the controlled device, the processor first outputs a first control signal to the first functional circuit, and then the processor outputs the first clock signal in a rising edge state and the fourth control signal in a low-level state to the first functional circuit. The second functional circuit is controlled according to this timing relationship. When there is no need to control the controlled device, even if any signal transmitted by the processor to the first functional circuit is interfered with, it will only cause the level state of the fourth control signal or the first clock signal to switch to a high-level state or a low-level state, without turning on the first latch. This can avoid the situation where the latch outputs an incorrect signal due to processor abnormality or interference with the signal line of the transmitted signal. That is, the processor outputs control signals according to this timing relationship, which can also avoid the situation where the latch outputs an incorrect signal, thereby improving the anti-interference capability of the first functional circuit, that is, improving the anti-interference capability and reliability of the control device.

[0077] In one possible implementation, the processor 101 is configured to output a second conduction signal to the second functional circuit 103; the second functional circuit 103 is configured to receive the second conduction signal and conduct, and output the second control signal to the output circuit 104.

[0078] The second conduction signal is used to control the conduction of the second functional circuit 103. This second conduction signal is a signal at any level, and its level is determined by the second functional circuit 103. For example, according to the configured second functional circuit 103, a high-level signal is required to conduct the second functional circuit 103; that is, the second conduction signal output by the processor 101 is a high-level signal. As another example, according to the configured second functional circuit 103, both high-level and low-level signals are required to conduct the second functional circuit 103; that is, the second conduction signal output by the processor 101 includes both high-level and low-level signals.

[0079] In this embodiment, when the second functional circuit 103 is in a non-conducting state, the second functional circuit 103 cannot output the transformed second control signal to the output circuit 104. When the second functional circuit 103 is in a conducting state, the second functional circuit 103 can output the transformed second control signal to the output circuit 104.

[0080] In this embodiment of the application, when the processor 101 needs to output a control signal to the output circuit 104 through the second functional circuit 103, it first outputs a first control signal to the second functional circuit 103, and then outputs a second conduction signal to the second functional circuit 103 to control the second functional circuit 103 to conduct, and then outputs the transformed second control signal to the output circuit 104.

[0081] In this embodiment, the default state of both the first functional circuit and the second functional circuit is an off state. When it is necessary to control the controlled device, the processor outputs a first control signal to the first functional circuit and the second functional circuit, and then outputs a turn-on signal to the first functional circuit and the second functional circuit respectively to turn on the first functional circuit and the second functional circuit. Only then can the control signal be transmitted to the output circuit through the first functional circuit and the second functional circuit. This circuit structure requires interference to be generated on the first functional circuit and the second functional circuit at the same time in order to output an incorrect control signal to the output circuit, thereby reducing the possibility of sending an incorrect control signal to the controlled device and improving the anti-interference performance of the control device.

[0082] Optionally, such as Figure 3 As shown, the second functional circuit 103 includes a second inverter 1031, a third inverter 1032, a second AND gate logic circuit 1033, and a second latch 1034. The processor 101 is electrically connected to the second inverter 1031, the third inverter 1032, and the second AND gate logic circuit 1033, respectively. The second inverter 1031 is electrically connected to the second latch 1034, the third inverter 1032 is electrically connected to the second AND gate logic circuit 1033, and the second AND gate logic circuit 1033 is electrically connected to the second latch 1034. The second latch 1034 is electrically connected to the output circuit 104. The second conduction signal includes a fifth control signal in a high-level state and a second clock signal in a falling edge state.

[0083] The falling edge state is a state generated by switching from a high-level state to a low-level state. The fifth control signal is used to control the second functional circuit 103. This fifth control signal can be of any type, such as an enable signal. In this embodiment, the high-level fifth control signal and the falling-edge second clock signal output by the processor 101 to the second functional circuit 103 work together to control the second functional circuit 103 to be turned on.

[0084] Both the second inverter 1031 and the third inverter 1032 are used to invert signals. The second inverter 1031 and the third inverter 1032 can be of any type. The second latch 1034 is a level-sensitive storage cell circuit. The second latch 1034 changes its state under the influence of a specific input pulse level. The second latch 1034 is similar to the first latch 1023 described above, and will not be described again here. The second AND gate logic circuit 1033 is a logic gate circuit. The second AND gate logic circuit 1033 is similar to the first AND gate logic circuit 1022 described above, and will not be described again here.

[0085] The processor 101 is configured to, in response to the control command, output the first control signal to the second inverter 1031, output the fifth control signal in a high-level state to the second AND gate logic circuit 1033, and output the second clock signal in a falling edge state to the third inverter 1032.

[0086] The second inverter 1031 is used to invert the first control signal to obtain a second control signal, and output the second control signal to the second latch 1034.

[0087] The third inverter 1032 is used to invert the second clock signal in the falling edge state to obtain the second clock signal in the rising edge state, and output the second clock signal in the rising edge state to the second AND gate logic circuit 1033.

[0088] The second AND gate logic circuit 1033 is used to output the second clock signal in the rising edge state to the second latch 1034.

[0089] The second latch 1034 receives the second clock signal in the rising edge state and turns on, and outputs the second control signal to the output circuit 104.

[0090] After the processor 101 outputs the first control signal to the second inverter 1031, it also outputs a second conduction signal to the second functional circuit 103, that is, it outputs a second clock signal in a falling edge state to the third inverter 1032, and outputs a fifth control signal in a high level state to the second AND gate logic circuit 1033. The second inverter 1031 inverts the first control signal to obtain a second control signal with a different level state than the first control signal, and outputs the second control signal to the second latch 1034. The third inverter 1032 inverts the second clock signal in a falling edge state to obtain a second clock signal in a rising edge state, and outputs the second clock signal in a rising edge state to the second AND gate logic circuit 1033. At this time, the signals output to the second AND gate logic circuit 1033 include a fifth control signal in a high-level state and a second clock signal in a rising edge state. The second AND gate logic circuit 1033 outputs the second clock signal in a rising edge state and outputs the second clock signal in a rising edge state to the second latch 1034 to control the second latch 1034 to be turned on. The second latch 1034 then outputs the second control signal output to the second latch 1034 to the output circuit 104.

[0091] In this embodiment, considering that the same interference source usually switches the signal level to a high level or a low level, according to the circuit structure of the second functional circuit, the processor can only turn on the second functional circuit by outputting a fifth control signal in a high level state and a second clock signal in a falling edge state to the second functional circuit, and then transmit the second control signal to the output circuit. In this way, even if the second conduction signal transmitted by the processor to the second functional circuit is interfered with, it will only cause the level states of the two signals contained in the second conduction signal to switch to a high level state or a low level state at the same time, and will not turn on the second latch. This can avoid the situation where the second latch outputs an incorrect signal due to processor abnormality or interference with the signal line of the transmission signal, thereby improving the anti-interference capability of the second functional circuit, that is, improving the anti-interference capability of the control device.

[0092] Optionally, the processor 101 is configured to output the second clock signal in the high-level state to the third inverter 1032 and the fifth control signal in the low-level state to the second AND gate logic circuit 1033; after outputting the first control signal to the first functional circuit and the second functional circuit 103, the processor 101 changes the level state of the second clock signal to the low-level state to generate the second clock signal in the falling edge state, and changes the level state of the fifth control signal to the high-level state.

[0093] In this embodiment, the processor 101 continuously outputs a second clock signal to the third inverter 1032 and a fifth control signal to the second AND gate logic circuit 1033. When the second functional circuit 103 does not need to transmit control signals to the output circuit 104, the second clock signal output by the processor 101 to the third inverter 1032 is at a high level, and the fifth control signal output to the second AND gate logic circuit 1033 is at a low level. The third inverter 1032 inverts the second clock signal to obtain a second clock signal at a low level and outputs this low-level second clock signal to the first AND gate logic circuit. At this time, both the fifth control signal and the second clock signal output to the second AND gate logic circuit 1033 are at a low level, so the second AND gate logic circuit 1033 outputs a low-level signal to the second latch 1034, making it impossible to control the second latch 1034 to conduct.

[0094] After the processor 101 outputs the first control signal to the second latch 1034 in the second functional circuit 103, the second functional circuit 103 needs to output a control signal to the output circuit 104. At this time, the processor 101 changes the level of the second clock signal to the low level to generate the second clock signal in the falling edge state, and changes the level of the fifth control signal to the high level state. That is, the processor 101 outputs the second clock signal in the falling edge state to the third inverter 1032 and outputs the fifth control signal in the high level state to the second AND gate logic circuit 1033 to control the second latch to turn on, so that the second latch 1034 outputs the second control signal to the output circuit 104.

[0095] In this embodiment, when there is no need to control the controlled device, the processor outputs a second clock signal in a high-level state to the third inverter and a fifth control signal in a low-level state to the second AND gate logic circuit. Only when it is necessary to control the controlled device, the processor first outputs a first control signal to the second functional circuit, and then the processor outputs the second clock signal in a falling edge state and the fifth control signal in a high-level state to the second functional circuit. By controlling the second functional circuit according to this timing relationship, even if any signal transmitted by the processor to the second functional circuit is interfered with when there is no need to control the controlled device, only the level state of the fifth control signal or the second clock signal will switch to a high-level state or a low-level state, without turning on the second latch. This can avoid the situation where the latch outputs an incorrect signal due to processor abnormality or interference with the signal line of the transmitted signal. That is, the processor outputs control signals according to this timing relationship, which can also avoid the situation where the latch outputs an incorrect signal, thereby improving the anti-interference capability of the second functional circuit, that is, improving the anti-interference capability and reliability of the control device.

[0096] In one possible implementation, such as Figure 4 As shown, the output circuit 104 includes an XOR gate logic circuit 1041, a third AND gate logic circuit 1042, and a relay 1043. The first functional circuit 102 is electrically connected to the XOR gate logic circuit 1041 and the third AND gate logic circuit 1042, respectively. The second functional circuit is electrically connected to the XOR gate logic circuit 1041. The XOR gate logic circuit 1041 is electrically connected to the third AND gate logic circuit 1042. The third AND gate logic circuit 1042 is electrically connected to the relay 1043.

[0097] The XOR gate logic circuit 1041 is a logic gate circuit that outputs a high-level signal when the level states of multiple signals output to it are different, and a low-level signal when the level states of multiple signals output to it are the same. For example, if one signal is high and the other is low, the XOR gate logic circuit 1041 outputs a high-level signal; or, if both signals are high or both are low, the XOR gate logic circuit 1041 outputs a low-level signal. The third AND gate logic circuit 1042 works similarly to the first AND gate logic circuit described above, and will not be described again here. The relay 1043 is an electrical control device. When the input signal of the relay 1043 meets the set conditions, the output signal of the relay 1043 changes. Optionally, the relay 1043 serves as the DO (Digital Output) port of the control device.

[0098] The first functional circuit 102 is used to transmit the first control signal to the XOR gate logic circuit 1041 and output the first control signal to the third AND gate logic circuit 1042.

[0099] The second functional circuit 103 is used to output the transformed second control signal to the XOR gate logic circuit 1041.

[0100] The XOR gate logic circuit 1041 is used to output a sixth control signal in a high-level state to the third AND gate logic circuit 1042 when the level states of the first control signal and the second control signal are different.

[0101] The third AND gate logic circuit 1042 is used to output the first control signal to the relay 1043.

[0102] The relay 1043 is used to send the third control signal to the controlled device.

[0103] After the first functional circuit is turned on, it outputs the first control signal to the output circuit 104. The second functional circuit inverts the first control signal and outputs the inverted second control signal to the output circuit 104. Under normal control conditions and without interference, the first and second control signals output to the output circuit 104 have different level states. The XOR gate logic circuit 1041 outputs a sixth control signal at a high level only when the level states of the first and second control signals are different, and outputs the sixth control signal to the third AND gate logic circuit 1042. At this time, the signal output to the third AND gate logic circuit 1042 includes the sixth control signal at a high level and the first control signal. Then, the third AND gate logic circuit 1042 outputs the first control signal to the relay 1043 to control the relay 1043 to send a third control signal to the controlled device.

[0104] Furthermore, when the XOR gate logic circuit 1041 has the same level as the first control signal and the second control signal, it outputs a sixth control signal in a low-level state and outputs the sixth control signal in a low-level state to the third AND gate logic circuit 1042. At this time, the signal output to the third AND gate logic circuit 1042 includes the sixth control signal and the first control signal in a low-level state. Therefore, the third AND gate logic circuit 1042 outputs a signal in a low-level state to the relay 1043, and cannot control the relay 1043 to send the third control signal to the controlled device.

[0105] Optionally, the processor 101 outputs a first control signal with a high level. When the control device is operating normally and without interference, the first control signal output to the XOR gate logic circuit 1041 is high, and the second control signal output to the XOR gate logic circuit 1041 is low. Then, the XOR gate logic circuit 1041 outputs a sixth control signal with a high level to the third AND gate logic circuit 1042. At this time, the signal output to the third AND gate logic circuit 1042 includes both the sixth control signal and the first control signal with a high level. The third AND gate logic circuit 1042 then outputs the first control signal with a high level to the relay 1043 to control the relay 1043 to send a third control signal to the controlled device.

[0106] In this embodiment, the level of the first control signal is high, meaning that the input to the third AND gate logic circuit is both a high-level first control signal and a high-level sixth control signal. When neither the first nor the second functional circuit is interfered with, the level of the first and second control signals output to the output circuit is different. Thus, according to this output circuit structure, the relay can be controlled to send a third control signal to the controlled device. This avoids sending incorrect control signals to the controlled device due to interference with the functional circuit, ensuring the accuracy of the third control signal sent to the controlled device, thereby improving the anti-interference capability and reliability of the control device.

[0107] Optionally, such as Figure 5 As shown, the output circuit 104 further includes a drive circuit 1044; a third AND gate logic circuit 1042 is electrically connected to the drive circuit 1044, and the drive circuit 1044 is electrically connected to the relay 1043. The third AND gate logic circuit 1042 is used to output a first control signal to the drive circuit 1044; the drive circuit 1044 is used to drive the relay 1043, so that the relay 1043 sends a third control signal to the controlled device.

[0108] The drive circuit 1044 is used to drive the relay 1043. The relay 1043 needs to be driven by the drive circuit 1044 to send control signals to the controlled device. When it is necessary to send control signals to the controlled device, the first control signal output by the processor 101 is output to the drive circuit 1044, so that the drive circuit 1044 drives the relay 1043, thereby enabling the relay 1043 to send control signals to the controlled device.

[0109] Optionally, the drive circuit 1044 includes an amplifier, and the third AND gate logic circuit 1042 outputs the first control signal to the amplifier and outputs the amplified control signal to the relay 1043 so that the relay 1043 is driven and sends the third control signal to the controlled device.

[0110] The amplifier is used to amplify the voltage of the signal. In this embodiment, the voltage of the first control signal output by the processor is less than the voltage of the signal driving the relay. That is, the voltage of the control signal output by the processor is small and insufficient to drive the relay. Therefore, a driving circuit is added to the output circuit to amplify the voltage of the first control signal, so that the amplified control signal can drive the relay and enable the relay to send a control signal to the controlled device.

[0111] In this embodiment, the output circuit is provided with a driving circuit, which drives the relay and the relay sends a third control signal to the controlled device. This ensures the normal operation of the relay and thus realizes the control of the controlled device.

[0112] Furthermore, considering that the voltage of the signal output by the processor is usually lower than the voltage of the signal driving the relay, a drive circuit is set in the output circuit. This drive circuit has a voltage amplification function, which can amplify the voltage of the control signal output to the drive circuit so as to drive the relay to send a control signal to the controlled device. This enables the relay to output a control signal and realize the control of the controlled device.

[0113] In one possible implementation, such as Figure 6 As shown, the control device also includes a readback circuit 105, an output circuit 104 electrically connected to the readback circuit 105, and a readback circuit 105 electrically connected to the processor 101.

[0114] The output circuit 104 is used to output the first control signal to the readback circuit 105 when the level states of the first control signal and the second control signal are different.

[0115] The readback circuit 105 is used to invert the first control signal to obtain a seventh control signal, and output the seventh control signal to the processor 101.

[0116] The processor 101 is also used to perform an inversion transformation on the seventh control signal, compare the transformed control signal with the first control signal, and if the transformed control signal is different from the first control signal, output the first control signal to the first functional circuit 102 and the second functional circuit 103 again.

[0117] The readback circuit 105 outputs the first control signal from the output circuit 104 to the processor 101, enabling the processor 101 to read back the output control signal. This readback circuit can be a circuit with unidirectional drive characteristics. Optionally, the readback circuit is an SN74LS244 chip; alternatively, the readback circuit includes a fourth inverter, whereby the output circuit 104 outputs the first control signal to the fourth inverter, which inverts the first control signal and outputs the resulting seventh control signal to the processor 101. Optionally, the processor includes a readback interface electrically connected to the readback circuit.

[0118] After the output circuit 104 outputs the first control signal to the readback circuit 105, the readback circuit 105 reverses the first control signal so that the level of the seventh control signal obtained by the reverse transformation is different from that of the first control signal. The seventh control signal obtained by the reverse transformation is then output to the processor 101 so that the processor 101 can compare the seventh control signal with the first control signal output by the processor 101 and determine whether the first control signal needs to be re-output. If the transformed control signal is different from the first control signal, it means that the output first control signal has been interfered with, causing the control signal to change and failing to successfully send the control signal to the controlled device. Therefore, the first control signal needs to be re-sent to the first functional circuit 102 and the second functional circuit 103 to enable subsequent control of the controlled device.

[0119] In this embodiment of the application, in order to ensure the accuracy of the control signal sent to the controlled device, the control device is also provided with a readback circuit to read back the first control signal output. The processor determines whether the control signal output by the output circuit is the same as the first control signal output by the processor. If it is determined that the control signal output by the output circuit is different from the first control signal output by the processor, that is, if it is determined that the control signal was not successfully sent to the controlled device, the processor will re-output the first control signal to initiate the process of re-sending the control signal to the controlled device, thereby realizing the control of the controlled device.

[0120] Furthermore, the readback circuit inverts the received control signal and inputs the inverted control signal into the processor. This allows the processor to verify the control signal output by the output circuit and also prevents the output circuit from being affected by the abnormal readback interface of the processor, which could lead to abnormal relay output. This ensures the reliability of the control equipment.

[0121] In addition, after the processor of the control device restarts, it can also receive the control signal output to the processor by the readback circuit. The processor uses the readback control signal to determine the state of the relay in the output circuit, that is, to determine whether the relay is currently in the state of sending control signals to the controlled device or in the state of not sending control signals to the controlled device. Then, it outputs signals according to the state of the relay to ensure that the signal output by the processor is the same as the signal output by the processor before the processor restarts.

[0122] It should be noted that the above embodiments describe the first functional circuit, the second functional circuit, and the readback circuit as circuits. In another embodiment, the first functional circuit, the second functional circuit, and the readback circuit can also be configured as chips in the control device. For example, the first inverter 1021, the first AND gate logic circuit 1022, and the first latch 1023 included in the first functional circuit 102 can be integrated into a chip using an interface type such as USB (one type of interface), SPI (one type of interface), or I2C (one type of interface) to GPIO (one type of interface).

[0123] In the above Figures 1 to 6 Based on the illustrated embodiment, the control device controls the controlled device based on the operating data of the controlled device. In one possible implementation, the control device acquires the operating data of the controlled device, and when the operating data of the controlled device meets the control strategy, the processor outputs a first control signal to the first functional circuit and the second functional circuit based on the control strategy, so that the control device controls the controlled device according to the above-described... Figures 1 to 6 The embodiment shown sends a third control signal to the controlled device.

[0124] The operational data indicates the operating status of the controlled device, including, for example, the device's temperature and operating time. When the controlled device's operational data satisfies the control strategy, the processor receives a control instruction. This control strategy instructs the processor to control the controlled device based on the operational data. For example, if the control strategy instructs the controlled device to shut down when its temperature reaches 60 degrees Celsius, then when the controlled device's temperature reaches 60 degrees Celsius, the processor outputs a first control signal to the first and second functional circuits to instruct the controlled device to shut down. Subsequently, the output circuit sends a third control signal to the controlled device, which shuts it down.

[0125] For example, the control device is a data acquisition device for scenarios such as data centers, computer rooms, and telecommunications base stations. The control device can collect the operating data of various controlled devices. Based on the operating data of each controlled device, it can determine the operating status of each controlled device. Once it is determined that a certain controlled device meets the control strategy, the first control signal is output to the first functional circuit and the second functional circuit according to the control strategy, so as to control the controlled device according to the control strategy.

[0126] It should be noted that the above Figures 1 to 6 The embodiments shown can be combined arbitrarily, based on the above. Figures 1 to 6 The illustrated embodiments, combined with examples, also provide a structural schematic diagram of a control device, as shown below. Figure 7As shown, taking the processor as an example, which includes interface EN (Enable), interface CLK (Clock), interface WR (Write), EN2, interface CLK2, and interface RD (Read), interface EN1 is used to output the fourth control signal, interface CLK1 is used to output the first clock signal, interface WR is used to output the first control signal, interface EN2 is used to output the fifth control signal, interface CLK2 is used to output the second clock signal, and interface RD is used to receive the control signal output by the readback circuit. Interface RD is also the aforementioned readback interface.

[0127] In this embodiment, interface EN1 is electrically connected to the first inverter 1021, interface CLK1 is electrically connected to the first AND gate logic circuit 1022, interface WR is electrically connected to the first latch 1023 and the second inverter 1031, interface EN2 is electrically connected to the second AND gate logic circuit 1033, interface CLK2 is electrically connected to the third inverter 1032, and RD is electrically connected to the fourth inverter in the readback circuit 105. The first latch 1023 is electrically connected to the XOR gate logic circuit 1041 and the third AND gate logic circuit 1042, respectively; the second latch 1034 is electrically connected to the XOR gate logic circuit 1041. The third AND gate logic circuit 1042 is electrically connected to the fourth inverter in the readback circuit 105.

[0128] In this embodiment, the signal transmission process between the processor 101, the first functional circuit 102, the second functional circuit 103, the output circuit 104, and the readback circuit 105 is the same as described above. Figures 1 to 6 The embodiments shown are similar and will not be described again here.

[0129] In the solution provided in this application embodiment, when there is no need to control the controlled device, the fourth control signal output by the processor to the first functional circuit has an opposite level to the fifth control signal output to the second functional circuit, and the first clock control signal output by the processor to the first functional circuit has an opposite level to the second clock control signal output to the second functional circuit. When it is necessary to control the controlled device, the fourth control signal output by the processor to the first functional circuit has an opposite level to the fifth control signal output to the second functional circuit, and the first clock control signal output by the processor to the first functional circuit has an opposite level to the second clock control signal output to the second functional circuit. That is, only when the processor outputs conduction signals with opposite levels to the first and second functional circuits can the first and second functional circuits be turned on respectively, thereby realizing the transmission of control signals. Considering that the same interference source usually switches the signal level to a high level or a low level, this circuit structure can reduce the situation where the first and second functional circuits are simultaneously interfered with, resulting in the output of incorrect control signals, thereby improving the anti-interference capability of the circuit and thus improving the anti-interference capability and reliability of the control device.

[0130] In addition, in the control equipment, the first functional circuit and the second functional circuit are arranged separately so that there is a distance between the first functional circuit and the second functional circuit. Furthermore, electromagnetic interference protection components can be added between the first functional circuit and the second functional circuit to isolate the first functional circuit and the second functional circuit, thereby reducing the probability that the first functional circuit and the second functional circuit are interfered with at the same time, thereby improving the anti-interference capability and reliability of the control equipment.

[0131] In addition, in the above Figure 7 Based on the embodiments shown, this application also provides a structural schematic diagram of a control device, such as... Figure 8 As shown, the first inverter 1021, the first AND gate logic circuit 1022, and the first latch 1023 in the first functional circuit 102 constitute the first latch circuit. The second inverter 1031, the third inverter 1032, and the second AND gate logic circuit 1033 in the second functional circuit 103 constitute the inverter circuit, and the second latch 1034 in the second functional circuit 103 constitutes the second latch circuit. The XOR gate logic circuit 1041 and the third AND gate logic circuit 1042 in the output circuit 104 constitute the verification circuit.

[0132] Specifically, interfaces EN1, CLK1, and WR in the processor are electrically connected to the first latch circuit, which is electrically connected to the verification circuit; interfaces WR, EN2, and CLK2 in the processor are electrically connected to the inverting circuit, which is electrically connected to the second latch circuit, which is electrically connected to the verification circuit; and the verification circuit is electrically connected to the drive circuit and the readback circuit.

[0133] In this embodiment, the signal transmission process between the processor 101, the first functional circuit 102, the second functional circuit 103, the output circuit 104, and the readback circuit 105 is the same as described above. Figures 1 to 6 The embodiments shown are similar and will not be described again here.

[0134] Figure 9 This is a flowchart of a device control method provided in an embodiment of this application. The method is executed by a control device, which includes a processor, a first functional circuit, a second functional circuit, and an output circuit. The processor is electrically connected to the first functional circuit and the second functional circuit, respectively, and the first functional circuit and the second functional circuit are electrically connected to the output circuit, respectively. The method includes:

[0135] 901. In response to a control instruction, the processor outputs a first control signal to the first functional circuit and the second functional circuit, and outputs a first turn-on signal to the first functional circuit.

[0136] 902. The first functional circuit receives the first conduction signal and conducts, transmitting the first control signal to the output circuit.

[0137] 903. The second functional circuit performs an inversion transformation on the first control signal and outputs the transformed second control signal to the output circuit.

[0138] 904. When the level states of the first control signal and the second control signal are different, the output circuit sends a third control signal to the controlled device based on the first control signal.

[0139] In the solution provided in this application embodiment, the control device includes a processor, a first functional circuit, a second functional circuit, and an output circuit. When it is necessary to control the controlled device, the processor outputs a first control signal to the first functional circuit and the second functional circuit respectively, controlling the first functional circuit to conduct. The first functional circuit outputs the first control signal to the output circuit, and the second functional circuit outputs the control signal after inverting the first control signal to the output circuit. When the processor is normal and the signal lines transmitting signals in the control device are not interfered with, the output circuit receives two control signals with different level states, and then controls the controlled device based on the first control signal. However, due to processor malfunction or interference with the signal lines transmitting signals in the control device, it is impossible to simultaneously enable the first functional circuit to conduct and for the first and second control signals output to the output circuit to have different level states. Therefore, no control signal will be sent to the controlled device, reducing the possibility of sending incorrect control signals to the controlled device due to processor malfunction or interference with the signal lines transmitting signals in the control device. This ensures the accuracy of the output control signal. The signal transmission method of this control device has strong anti-interference capability and high reliability.

[0140] In one possible implementation, the first functional circuit includes a first inverter, a first AND gate logic circuit, and a first latch; the processor is electrically connected to the first inverter, the first AND gate logic circuit, and the first latch respectively; the first inverter is electrically connected to the first AND gate logic circuit, the first AND gate logic circuit is electrically connected to the first latch, and the first latch is electrically connected to the output circuit; the first conduction signal includes a fourth control signal in a low-level state and a first clock signal in a rising edge state;

[0141] The processor, in response to a control instruction, outputs a first control signal to the first functional circuit and a first conduction signal to the first functional circuit, including:

[0142] In response to a control instruction, the processor outputs a first control signal to the first latch, a fourth control signal in a low-level state to the first inverter, and a first clock signal in a rising-edge state to the first AND gate logic circuit.

[0143] The first functional circuit receives and turns on the first conduction signal, and transmits the first control signal to the output circuit, including:

[0144] The first inverter inverts the fourth control signal to obtain a fourth control signal in a high-level state, and outputs the fourth control signal in a high-level state to the first AND gate logic circuit.

[0145] The first AND gate logic circuit outputs a first clock signal in the rising edge state to the first latch;

[0146] The first latch receives the first clock signal at the rising edge and turns on, outputting the first control signal to the output circuit.

[0147] In another possible implementation, before the processor outputs a first control signal to the first functional circuit and the second functional circuit in response to a control instruction, the method further includes:

[0148] The processor outputs a fourth control signal in a high-level state to the first inverter and a first clock signal in a low-level state to the first AND gate logic circuit.

[0149] The processor outputs a fourth control signal in a low-level state to the first inverter and a first clock signal in a rising-edge state to the first AND gate logic circuit, including:

[0150] After outputting the first control signal to the first functional circuit and the second functional circuit, the processor changes the level of the first clock signal to a high level to generate a first clock signal in a rising edge state, and changes the level of the fourth control signal to a low level.

[0151] In another possible implementation, the method also includes:

[0152] The processor outputs a second activation signal to the second functional circuit;

[0153] The second functional circuit outputs the transformed second control signal to the output circuit, including:

[0154] The second functional circuit receives the second conduction signal and conducts, outputting the second control signal to the output circuit.

[0155] In another possible implementation, the second functional circuit includes a second inverter, a third inverter, a second AND gate logic circuit, and a second latch; the processor is electrically connected to the second inverter, the third inverter, and the second AND gate logic circuit, respectively; the second inverter is electrically connected to the second latch; the third inverter is electrically connected to the second AND gate logic circuit; the second AND gate logic circuit is electrically connected to the second latch; and the second latch is electrically connected to the output circuit; the second conduction signal includes a fifth control signal in a high-level state and a second clock signal in a falling-edge state.

[0156] The processor outputs a second turn-on signal to the second functional circuit, including:

[0157] In response to the control instruction, the processor outputs a first control signal to the second inverter, a fifth control signal in a high-level state to the second AND gate logic circuit, and a second clock signal in a falling-edge state to the third inverter.

[0158] The second functional circuit receives the second conduction signal and turns on, performs an inversion transformation on the first control signal, and outputs the second control signal to the output circuit, including:

[0159] The second inverter inverts the first control signal to obtain the second control signal, and outputs the second control signal to the second latch.

[0160] The third inverter inverts the second clock signal in the falling edge state to obtain the second clock signal in the rising edge state, and outputs the second clock signal in the rising edge state to the second AND gate logic circuit.

[0161] The second AND gate logic circuit outputs a second clock signal in the rising edge state to the second latch;

[0162] The second latch receives the second clock signal at the rising edge and turns on, outputting the second control signal to the output circuit.

[0163] In another possible implementation, before the processor outputs a first control signal to the first functional circuit and the second functional circuit in response to a control instruction, the method further includes:

[0164] The processor outputs a second clock signal in a high-level state to the third inverter and a fifth control signal in a low-level state to the second AND gate logic circuit;

[0165] The processor outputs a fifth control signal in a high-level state to the second AND gate logic circuit, and outputs a second clock signal in a falling-edge state to the third inverter, including:

[0166] After outputting the first control signal to the first functional circuit and the second functional circuit, the processor changes the level of the second clock signal to a low level to generate a second clock signal in a falling edge state, and changes the level of the fifth control signal to a high level.

[0167] In another possible implementation, the output circuit includes an XOR gate logic circuit, a third AND gate logic circuit, and a relay; the first functional circuit is electrically connected to the XOR gate logic circuit and the third AND gate logic circuit respectively, the second functional circuit is electrically connected to the XOR gate logic circuit, the XOR gate logic circuit is electrically connected to the third AND gate logic circuit, and the third AND gate logic circuit is electrically connected to the relay.

[0168] The first functional circuit transmits the first control signal to the output circuit, including:

[0169] The first functional circuit transmits the first control signal to the XOR gate logic circuit and outputs the first control signal to the third AND gate logic circuit.

[0170] The second functional circuit outputs the transformed second control signal to the output circuit, including:

[0171] The second functional circuit outputs the transformed second control signal to the XOR gate logic circuit;

[0172] When the level states of the first control signal and the second control signal are different, the output circuit sends a third control signal to the controlled device based on the first control signal, including:

[0173] When the levels of the first control signal and the second control signal are different, the XOR gate logic circuit outputs a sixth control signal in a high-level state to the third AND gate logic circuit.

[0174] The third AND gate logic circuit outputs the first control signal to the relay, which then controls the relay to send the third control signal to the controlled device.

[0175] In another possible implementation, the output circuit further includes a drive circuit; a third AND gate logic circuit is electrically connected to the drive circuit, and the drive circuit is electrically connected to the relay; the third AND gate logic circuit outputs a first control signal to the relay, controlling the relay to send a third control signal to the controlled device, including:

[0176] The third AND gate logic circuit outputs the first control signal to the drive circuit;

[0177] The drive circuit drives the relay so that the relay sends a third control signal to the controlled device.

[0178] In another possible implementation, the control device further includes a readback circuit; the output circuit is electrically connected to the readback circuit, and the readback circuit is electrically connected to the processor; the method further includes:

[0179] When the level states of the first control signal and the second control signal are different, the output circuit also outputs the first control signal to the readback circuit;

[0180] The readback circuit inverts the first control signal to obtain the seventh control signal, and outputs the seventh control signal to the processor.

[0181] The processor performs an inversion transformation on the seventh control signal, compares the transformed control signal with the first control signal, and if the transformed control signal is different from the first control signal, it outputs the first control signal again to the first functional circuit and the second functional circuit.

[0182] It should be noted that the device control method provided in the above embodiments and the control device embodiments belong to the same concept, and the specific implementation process can be found in the control device embodiments, which will not be repeated here.

[0183] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present application should be included within the protection scope of the present application.

Claims

1. A control device, characterized in that, The control device includes a processor, a first functional circuit, a second functional circuit, and an output circuit; The processor is electrically connected to the first functional circuit and the second functional circuit respectively, and the first functional circuit and the second functional circuit are electrically connected to the output circuit respectively; The processor is configured to, in response to a control command, output a first control signal to the first functional circuit and the second functional circuit, and output a first conduction signal to the first functional circuit; The first functional circuit is used to receive the first conduction signal and conduct, and to transmit the first control signal to the output circuit; The second functional circuit is used to invert the first control signal and output the resulting second control signal to the output circuit. The output circuit is used to send a third control signal to the controlled device based on the first control signal when the first control signal is in a high-level state and the level states of the first control signal and the second control signal are different. The output circuit includes an XOR gate logic circuit, a third AND gate logic circuit, and a relay. The first functional circuit is electrically connected to both the XOR gate logic circuit and the third AND gate logic circuit. The second functional circuit is electrically connected to the XOR gate logic circuit. The XOR gate logic circuit is electrically connected to the third AND gate logic circuit. The third AND gate logic circuit is electrically connected to the relay. The first functional circuit transmits the first control signal to the XOR gate logic circuit and outputs the first control signal to the third AND gate logic circuit. The second functional circuit outputs the transformed second control signal to the XOR gate logic circuit. The XOR gate logic circuit outputs a sixth control signal at a high level to the third AND gate logic circuit when the level states of the first control signal and the second control signal are different. The third AND gate logic circuit outputs the first control signal to the relay. The relay sends the third control signal to the controlled device.

2. The control device according to claim 1, characterized in that, The first functional circuit includes a first inverter, a first AND gate logic circuit, and a first latch; the processor is electrically connected to the first inverter, the first AND gate logic circuit, and the first latch respectively; the first inverter is electrically connected to the first AND gate logic circuit, the first AND gate logic circuit is electrically connected to the first latch, and the first latch is electrically connected to the output circuit; the first conduction signal includes a fourth control signal in a low-level state and a first clock signal in a rising edge state; The processor is configured to, in response to the control instruction, output the first control signal to the first latch, output the fourth control signal in the low-level state to the first inverter, and output the first clock signal in the rising edge state to the first AND gate logic circuit. The first inverter is used to invert the fourth control signal to obtain the fourth control signal in a high-level state, and output the fourth control signal in the high-level state to the first AND gate logic circuit. The first AND gate logic circuit is used to output the first clock signal in the rising edge state to the first latch; The first latch is used to receive the first clock signal in the rising edge state and turn it on, and output the first control signal to the output circuit.

3. The control device according to claim 2, characterized in that, The processor is further configured to output the fourth control signal in the high-level state to the first inverter, and to output the first clock signal in the low-level state to the first AND gate logic circuit. The processor is configured to, after outputting the first control signal to the first functional circuit and the second functional circuit, change the level state of the first clock signal to the high level state to generate the first clock signal in the rising edge state, and change the level state of the fourth control signal to the low level state.

4. The control device according to claim 1, characterized in that, The processor is used to output a second conduction signal to the second functional circuit; The second functional circuit is used to receive the second conduction signal and conduct, and output the second control signal to the output circuit.

5. The control device according to claim 4, characterized in that, The second functional circuit includes a second inverter, a third inverter, a second AND gate logic circuit, and a second latch; the processor is electrically connected to the second inverter, the third inverter, and the second AND gate logic circuit respectively; the second inverter is electrically connected to the second latch; the third inverter is electrically connected to the second AND gate logic circuit; the second AND gate logic circuit is electrically connected to the second latch; and the second latch is electrically connected to the output circuit; the second conduction signal includes a fifth control signal in a high-level state and a second clock signal in a falling-edge state. The processor is configured to, in response to the control command, output the first control signal to the second inverter, output the fifth control signal in the high-level state to the second AND gate logic circuit, and output the second clock signal in the falling edge state to the third inverter. The second inverter is used to invert the first control signal to obtain the second control signal, and output the second control signal to the second latch; The third inverter is used to invert the second clock signal in the falling edge state to obtain the second clock signal in the rising edge state, and output the second clock signal in the rising edge state to the second AND gate logic circuit. The second AND gate logic circuit is used to output the second clock signal in the rising edge state to the second latch; The second latch is used to receive the second clock signal in the rising edge state and turn it on, and output the second control signal to the output circuit.

6. The control device according to claim 5, characterized in that, The processor is further configured to output the second clock signal in the high-level state to the third inverter, and to output the fifth control signal in the low-level state to the second AND gate logic circuit; The processor is configured to, after outputting the first control signal to the first functional circuit and the second functional circuit, change the level state of the second clock signal to the low level state to generate the second clock signal in the falling edge state, and change the level state of the fifth control signal to the high level state.

7. The control device according to claim 1, characterized in that, The output circuit further includes a driving circuit; the third AND gate logic circuit is electrically connected to the driving circuit, and the driving circuit is electrically connected to the relay; The third AND gate logic circuit is used to output the first control signal to the driving circuit; The driving circuit is used to drive the relay so that the relay sends the third control signal to the controlled device.

8. The control device according to any one of claims 1-5, characterized in that, The control device further includes a readback circuit; the output circuit is electrically connected to the readback circuit, and the readback circuit is electrically connected to the processor; The output circuit is configured to output the first control signal to the readback circuit when the level states of the first control signal and the second control signal are different. The readback circuit is used to invert the first control signal to obtain a seventh control signal, and output the seventh control signal to the processor. The processor is further configured to perform an inversion transformation on the seventh control signal, compare the transformed control signal with the first control signal, and, if the transformed control signal is different from the first control signal, re-output the first control signal to the first functional circuit and the second functional circuit.

9. A device control method, characterized in that, The method is executed by a control device, which includes a processor, a first functional circuit, a second functional circuit, and an output circuit; the processor is electrically connected to the first functional circuit and the second functional circuit, respectively, and the first functional circuit and the second functional circuit are electrically connected to the output circuit, respectively; the method includes: In response to a control command, the processor outputs a first control signal to the first functional circuit and the second functional circuit, and outputs a first conduction signal to the first functional circuit. The first functional circuit receives the first conduction signal and conducts, transmitting the first control signal to the output circuit; The second functional circuit performs an inversion transformation on the first control signal and outputs the transformed second control signal to the output circuit; When the first control signal is at a high level and the level of the first control signal is different from that of the second control signal, the output circuit sends a third control signal to the controlled device based on the first control signal. The output circuit includes an XOR gate logic circuit, a third AND gate logic circuit, and a relay. The first functional circuit is electrically connected to both the XOR gate logic circuit and the third AND gate logic circuit. The second functional circuit is electrically connected to the XOR gate logic circuit. The XOR gate logic circuit is electrically connected to the third AND gate logic circuit. The third AND gate logic circuit is electrically connected to the relay. The first functional circuit transmits the first control signal to the XOR gate logic circuit and outputs the first control signal to the third AND gate logic circuit. The second functional circuit outputs the transformed second control signal to the XOR gate logic circuit. The XOR gate logic circuit outputs a sixth control signal at a high level to the third AND gate logic circuit when the level states of the first control signal and the second control signal are different. The third AND gate logic circuit outputs the first control signal to the relay. The relay sends the third control signal to the controlled device.

10. The method according to claim 9, characterized in that, The first functional circuit includes a first inverter, a first AND gate logic circuit, and a first latch; the processor is electrically connected to the first inverter, the first AND gate logic circuit, and the first latch respectively; the first inverter is electrically connected to the first AND gate logic circuit, the first AND gate logic circuit is electrically connected to the first latch, and the first latch is electrically connected to the output circuit; the first conduction signal includes a fourth control signal in a low-level state and a first clock signal in a rising edge state; The processor, in response to a control command, outputs a first control signal to the first functional circuit and a first conduction signal to the first functional circuit, including: In response to the control instruction, the processor outputs the first control signal to the first latch, outputs the fourth control signal in the low-level state to the first inverter, and outputs the first clock signal in the rising edge state to the first AND gate logic circuit. The first functional circuit receives the first conduction signal and turns on, transmitting the first control signal to the output circuit, including: The first inverter performs an inversion transformation on the fourth control signal to obtain the fourth control signal in a high-level state, and outputs the fourth control signal in the high-level state to the first AND gate logic circuit; The first AND gate logic circuit outputs the first clock signal in the rising edge state to the first latch; The first latch receives the first clock signal in the rising edge state and turns on, outputting the first control signal to the output circuit.

11. The method according to claim 10, characterized in that, Before the processor outputs a first control signal to the first functional circuit and the second functional circuit in response to a control command, the method further includes: The processor outputs the fourth control signal, which is in the high-level state, to the first inverter, and outputs the first clock signal, which is in the low-level state, to the first AND gate logic circuit. The processor outputs the fourth control signal, which is in the low-level state, to the first inverter, and outputs the first clock signal, which is in the rising-edge state, to the first AND gate logic circuit, including: After outputting the first control signal to the first functional circuit and the second functional circuit, the processor changes the level state of the first clock signal to the high level state to generate the first clock signal in the rising edge state, and changes the level state of the fourth control signal to the low level state.

12. The method according to claim 9, characterized in that, The method further includes: The processor outputs a second activation signal to the second functional circuit; The second functional circuit outputs the transformed second control signal to the output circuit, including: The second functional circuit receives the second conduction signal and conducts, and outputs the second control signal to the output circuit.

13. The method according to claim 12, characterized in that, The second functional circuit includes a second inverter, a third inverter, a second AND gate logic circuit, and a second latch; the processor is electrically connected to the second inverter, the third inverter, and the second AND gate logic circuit respectively; the second inverter is electrically connected to the second latch; the third inverter is electrically connected to the second AND gate logic circuit; the second AND gate logic circuit is electrically connected to the second latch; and the second latch is electrically connected to the output circuit; the second conduction signal includes a fifth control signal in a high-level state and a second clock signal in a falling-edge state. The processor, in response to a control command, outputs a first control signal to the second functional circuit and a second conduction signal to the second functional circuit, including: In response to the control command, the processor outputs the first control signal to the second inverter, outputs the fifth control signal in the high-level state to the second AND gate logic circuit, and outputs the second clock signal in the falling edge state to the third inverter. The second functional circuit receives the second conduction signal and conducts, performs an inversion transformation on the first control signal, and outputs the second control signal to the output circuit, including: The second inverter inverts the first control signal to obtain the second control signal, and outputs the second control signal to the second latch. The third inverter inverts the second clock signal in the falling edge state to obtain the second clock signal in the rising edge state, and outputs the second clock signal in the rising edge state to the second AND gate logic circuit. The second AND gate logic circuit outputs the second clock signal in the rising edge state to the second latch; The second latch receives the second clock signal at the rising edge and turns on, outputting the second control signal to the output circuit.

14. The method according to claim 13, characterized in that, Before the processor outputs a first control signal to the first functional circuit and the second functional circuit in response to a control command, the method further includes: The processor outputs the second clock signal, which is in a high-level state, to the third inverter, and outputs the fifth control signal, which is in a low-level state, to the second AND gate logic circuit. The processor outputs the fifth control signal, which is in the high-level state, to the second AND gate logic circuit, and outputs the second clock signal, which is in the falling-edge state, to the third inverter, including: After outputting the first control signal to the first functional circuit and the second functional circuit, the processor changes the level state of the second clock signal to the low level state to generate the second clock signal in the falling edge state, and changes the level state of the fifth control signal to the high level state.

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