Register address identification method and device, electronic equipment and storage medium

Abstract

This invention provides a register address identification method, apparatus, electronic device, and storage medium, belonging to the field of computer technology. The register address identification method includes: acquiring the model and CPU availability information of the server under test; querying register address information in a database based on the server model to obtain query results; the database stores a target information table, which includes multiple server models and their corresponding register address information; based on the query results and CPU availability information, determining whether register address information corresponding to all available CPUs of the server under test has been obtained; if so, outputting the register address information corresponding to all available CPUs of the server under test; otherwise, dynamically acquiring the register address information corresponding to all available CPUs of the server under test. This invention enables dynamic acquisition of register address information across platforms, facilitating unified maintenance of differentiated register addresses.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a register address identification method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the rapid development of technology, servers are iterating and updating at a fast pace, resulting in a growing number of server models and significant differences in register address information across different platforms. During server platform iteration, it is necessary to obtain the register address information of the server under test (DUT) to perform performance testing. Current technology involves manually obtaining this register address information during platform iteration, which cannot dynamically acquire differentiated register address information across platforms and hinders the unified maintenance of these diverse register addresses across multiple platforms. Summary of the Invention

[0003] This invention provides a register address identification method, apparatus, electronic device, and storage medium to address the shortcomings of existing technologies where, during server platform iteration, register address information of the server under test is obtained manually, making it impossible to dynamically obtain differentiated register address information across platforms and inconvenient for unified maintenance of differentiated register addresses across multiple platforms.

[0004] In a first aspect, the present invention provides a register address identification method, comprising:

[0005] Obtain the model and CPU location information of the server under test;

[0006] Based on the model of the server under test, the register address information is queried in the database to obtain the query result; the database stores a target information table, which includes multiple server models and the corresponding register address information for each server model;

[0007] Based on the query results and the CPU availability information, determine whether the register address information corresponding to all available CPUs of the server under test is obtained. If so, output the register address information corresponding to all available CPUs of the server under test; otherwise, dynamically obtain the register address information corresponding to all available CPUs of the server under test.

[0008] In some embodiments, dynamically obtaining the register address information corresponding to all in-situ CPUs of the server under test includes:

[0009] Control the restart of the server under test;

[0010] Obtain the Baseboard Management Controller (BMC) hierarchical log data generated during the restart process of the server under test;

[0011] The BMC hierarchical log data is parsed to obtain the register address information corresponding to all in-situ CPUs of the server under test.

[0012] In some embodiments, parsing the BMC hierarchical log data to obtain the register address information corresponding to all in-situ CPUs of the server under test includes:

[0013] Using the target flag, a target data list is obtained from the BMC hierarchical log data. The target data list includes the correspondence between all in-situ CPUs of the server under test and the address information of each register.

[0014] Determine whether the target data list is empty. If the target data list is determined to be empty, exit. Alternatively, if the target data list is determined not to be empty, obtain the register address information corresponding to all in-place CPUs of the server under test from the target data list.

[0015] In some embodiments, after dynamically acquiring the register address information corresponding to all in-situ CPUs of the server under test, the method further includes:

[0016] The target information table is updated based on the register address information corresponding to all in-place CPUs of the server under test.

[0017] In some embodiments, determining whether to obtain the register address information corresponding to all in-situ CPUs of the server under test based on the query result and the CPU in-situ information includes:

[0018] The list of register address information contained in the query results is matched with the CPU in-situ information;

[0019] If all in-situ CPUs in the CPU in-situ information match the corresponding register address information, then the register address information corresponding to all in-situ CPUs of the server under test is determined.

[0020] If no corresponding register address information is found for any in-situ CPU in the CPU in-situ information, it is determined that the register address information corresponding to all in-situ CPUs of the server under test has not been obtained.

[0021] In some embodiments, the register address identification method further includes:

[0022] Based on memory characteristic test information, target register address information is selected from the register address information corresponding to all in-place CPUs of the server under test.

[0023] Based on the target register address information and the preset address offset, a list of memory addresses is obtained;

[0024] The memory address list is used to perform memory characteristic tests on the server under test.

[0025] In a second aspect, the present invention provides a register address identification device, comprising:

[0026] The acquisition unit is used to acquire the model and CPU availability information of the server under test.

[0027] The query unit is used to query register address information in the database according to the model of the server under test and obtain the query result; the database stores a target information table, which includes multiple server models and the corresponding register address information of each server model;

[0028] The determining unit is used to determine, based on the query result and the CPU in-situ information, whether the register address information corresponding to all in-situ CPUs of the server under test has been obtained. If so, the register address information corresponding to all in-situ CPUs of the server under test is output; otherwise, the register address information corresponding to all in-situ CPUs of the server under test is dynamically obtained.

[0029] Thirdly, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements any of the register address identification methods described above.

[0030] Fourthly, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the register address identification methods described above.

[0031] Fifthly, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements any of the register address identification methods described above.

[0032] This invention provides a register address identification method, apparatus, electronic device, and storage medium. By acquiring the model and CPU availability information of the server under test, and querying register address information in a database based on the server model, the method obtains the query results. Based on the query results and CPU availability information, it determines whether register address information corresponding to all available CPUs of the server under test has been obtained. If so, the register address information corresponding to all available CPUs of the server under test is output; otherwise, the register address information corresponding to all available CPUs of the server under test is dynamically acquired. This method enables cross-platform dynamic acquisition of differentiated register address information, facilitating unified maintenance of differentiated register addresses across multiple platforms and improving register address identification efficiency. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This is one of the flowcharts illustrating the register address identification method provided in this embodiment of the invention;

[0035] Figure 2 This is a schematic diagram of the process for dynamically obtaining the register address information corresponding to all in-situ CPUs of the server under test, provided in an embodiment of the present invention.

[0036] Figure 3 This is a second flowchart illustrating the register address identification method provided in this embodiment of the invention;

[0037] Figure 4 This is a schematic diagram of the process of identifying register addresses and conducting tests based on the identification results provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the register address recognition device provided by the present invention;

[0039] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0041] Servers iterate rapidly, with numerous product models. Whenever a new server platform is released, its performance needs to be tested and verified. Some tests, such as memory performance testing, require obtaining the corresponding register addresses beforehand. These register addresses are related to the server model and its in-situ Central Processing Unit (CPU). Different server models have significantly different register addresses, and even servers of the same model may have different register addresses for their respective CPUs.

[0042] Current technologies for verifying memory performance require constant monitoring of machine configurations, manual acquisition of server register address information, and addition of test cases for register address-related functionalities. Due to differences in server platforms, many test cases exist for the same functionalities. Existing technologies cannot dynamically obtain and incrementally update the register address list for each server product series for future reference. This necessitates identifying the register address every time server register address information is needed, causing significant inconvenience to test development and maintenance, and reducing testing efficiency.

[0043] To address this, the present invention provides a register address identification method, apparatus, electronic device, and storage medium. By acquiring the model and CPU availability information of the server under test, and based on the server model, register address information is queried in a database to obtain the query results. Based on the query results and CPU availability information, it is determined whether register address information corresponding to all available CPUs of the server under test has been obtained. If so, the register address information corresponding to all available CPUs of the server under test is output; otherwise, the register address information corresponding to all available CPUs of the server under test is dynamically acquired. This invention can dynamically acquire differentiated register address information across platforms, facilitating unified maintenance of differentiated register addresses across multiple platforms and improving register address identification efficiency.

[0044] Figure 1 This is one of the flowcharts illustrating the register address identification method provided in an embodiment of the present invention. Figure 1As shown, a register address identification method is provided, including the following steps: step 110, step 120, and step 130. This method's steps are merely one possible implementation of the present invention.

[0045] Step 110: Obtain the model and CPU information of the server under test.

[0046] A server, also known as a servo server, is a device that provides computing services, including a CPU, hard drive, memory, system bus, etc. In a network environment, servers are classified into file servers, database servers, application servers, etc., based on the type of services they provide.

[0047] The server model usually refers to the model of the server hardware. Different models of servers differ in hardware configuration and performance. For example, different models of servers are equipped with different CPUs and have different memory capacities.

[0048] Among them, CPU in-situ information refers to information such as the number and serial number of CPUs installed on the server under test. A server can be equipped with one or more CPU devices. A CPU includes an arithmetic logic unit, a register unit, an arithmetic logic unit, and a control unit.

[0049] Optionally, the model and CPU availability information of the server under test can be queried through the Baseboard Management Controller (BMC).

[0050] For example, the model of the server under test, such as 5280M6, can be obtained through the BMC's RESTful interface, and the CPU information, such as CPU0 and CPU1, can be obtained, that is, the number of CPUs in place is 2, and the CPU numbers in place are "0" and "1" respectively.

[0051] It is understandable that the register address of the server under test is closely related to the server model and CPU availability information. By obtaining the server model and CPU availability information, it is easier to obtain the register address information of all available CPUs on the server under test.

[0052] Step 120: Based on the model of the server under test, query the register address information in the database to obtain the query results; the database stores a target information table, which includes multiple server models and the corresponding register address information for each server model.

[0053] Optionally, the server under test can connect to the database automatically using Python.

[0054] In a computer, a register address is a unique identifier assigned to a register within the CPU, allowing access to that register. Registers are internal components of the CPU, high-speed storage devices used to temporarily store instructions, data, and addresses. Their read / write speeds are faster than other storage devices such as RAM and hard drives. Types of registers include general-purpose registers, special-purpose registers, and control registers. Each register has an address, and the register addresses of a server depend on its hardware architecture and operating system.

[0055] Optionally, in the target information table, the storage format of the register address is "CPU number: register address information", and the query result can be ["0:0xAF280000", "1:0xC8A80000"]. The first "0" in "0:0xAF280000" represents CPU0 corresponding to the server under test, and "0xAF280000" is the register address information corresponding to CPU0.

[0056] Understandably, the database stores a target information table, which includes multiple server models and their corresponding register address information. If the target information table already contains the model of the server under test and its corresponding register address information, then the register address information of the server under test can be directly obtained by querying the database, without having to check the server configuration to obtain the register address, thus improving the efficiency of register address identification.

[0057] Step 130: Based on the query results and CPU availability information, determine whether the register address information corresponding to all available CPUs of the server under test has been obtained. If so, output the register address information corresponding to all available CPUs of the server under test; otherwise, dynamically obtain the register address information corresponding to all available CPUs of the server under test.

[0058] Optionally, based on the model 5280M6 of the server under test and the in-situ CPU information: CPU0, CPU1, with a length of 2, query the database to see if the (Memory0, MEM0) register address information corresponding to the in-situ CPUs exists. If it does, then the MEM0 register address information corresponding to CPU0 and the MEM0 register address information corresponding to CPU1 are successfully obtained. If the server under test only has CPU0 in-situ CPU, it is only necessary to query whether the MEM0 register address information corresponding to CPU0 exists. If the database does not contain the MEM0 register address information corresponding to CPU0, then the MEM0 register address information corresponding to the in-situ CPU0 of the server under test needs to be dynamically obtained.

[0059] It should be noted that, based on the CPU in-situ information, the number of all in-situ CPUs of the server under test and the number of each in-situ CPU can be obtained. Based on the query results and the CPU in-situ information, it can be determined whether the query results contain the register address information corresponding to all in-situ CPUs of the server under test.

[0060] In some embodiments, based on the query results and CPU availability information, it is determined whether register address information corresponding to all available CPUs of the server under test is obtained, including:

[0061] Match the list of register address information contained in the query results with the CPU in-situ information;

[0062] If all in-situ CPUs in the CPU information match the corresponding register address information, then the register address information corresponding to all in-situ CPUs of the server under test is determined.

[0063] If no corresponding register address information is found for any in-situ CPU in the CPU in-situ information, it is determined that the register address information for all in-situ CPUs of the server under test has not been obtained.

[0064] For example, the CPU presence information includes CPU0 and CPU1. If CPU0 is matched with the corresponding register address information, but CPU1 is not matched with the corresponding register address information, then it is determined that the register address information corresponding to all the CPUs in the server under test has not been obtained.

[0065] Understandably, if the query results contain register address information for all in-situ CPUs of the server under test, then the register address information for all in-situ CPUs of the server under test can be directly output without needing to identify the register addresses through other means. If the query results do not contain register address information for all in-situ CPUs of the server under test, it means that the full register address information for the server under test cannot be obtained through static querying. Therefore, it is necessary to continue to obtain the register address information for all in-situ CPUs of the server under test through dynamic acquisition.

[0066] In this embodiment of the invention, by obtaining the model and CPU availability information of the server under test, register address information is queried in the database based on the model of the server under test to obtain the query results. Based on the query results and CPU availability information, it is determined whether the register address information corresponding to all available CPUs of the server under test is obtained. If so, the register address information corresponding to all available CPUs of the server under test is output; otherwise, the register address information corresponding to all available CPUs of the server under test is dynamically obtained. This enables cross-platform dynamic acquisition of differentiated register address information, which facilitates unified maintenance of differentiated register addresses across multiple platforms and improves register address recognition efficiency.

[0067] It should be noted that each embodiment of the present invention can be freely combined, rearranged, or executed individually, and does not need to rely on or depend on a fixed execution order.

[0068] Figure 2 This is a schematic diagram illustrating the process of dynamically acquiring the register address information corresponding to all in-place CPUs of the server under test, as provided in an embodiment of the present invention. Figure 2 As shown, in some embodiments, step 130 dynamically obtains the register address information corresponding to all in-situ CPUs of the server under test, including steps 131, 132 and 133.

[0069] Step 131: Restart the server under test.

[0070] Optionally, the server under test can connect to the execution machine via a remote connection tool (such as Secure Shell or SSH tools), and the execution machine can control the server under test to restart.

[0071] Optionally, set the serial port log level to 02, i.e., Normal; enter "ipmitool -I lanplus -H <bmcip> -U <user> -P <password>The command "sol activate>sol.log" will output the serial port log data to sol.log using `sol activate`; Entering "ipmitool -I lanplus -H" will also output the serial port log data. <bmcip> -U <user> -P <password>The "powerreset" command restarts the server under test; after the server under test starts up, the sol.log monitoring log is generated.

[0072] Step 132: Obtain the Baseboard Management Controller (BMC) hierarchical log data generated during the restart process of the server under test.

[0073] Among them, BMC is an embedded management controller located on the server motherboard, responsible for monitoring, controlling, managing and maintaining server hardware; BMC hierarchical log data records information on the operating status of server hardware, including information on various aspects such as CPU, registers, memory, disk, and network.

[0074] Step 133: Parse the BMC hierarchical log data to obtain the register address information corresponding to all in-situ CPUs of the server under test.

[0075] Understandably, since the BMC hierarchical log data contains information on various aspects such as CPU, registers, memory, disk, and network, it is necessary to parse the BMC hierarchical log data to obtain the target data, namely the register address information corresponding to all in-situ CPUs of the server under test.

[0076] In this embodiment of the invention, by controlling the restart of the server under test, the BMC hierarchical log data generated during the restart process of the server under test is obtained. The BMC hierarchical log data is parsed to obtain the register address information corresponding to all in-place CPUs of the server under test, thereby improving the accuracy of dynamically obtaining register address information.

[0077] In some embodiments, step 133 involves parsing the BMC hierarchical log data to obtain the register address information corresponding to all in-situ CPUs of the server under test, including:

[0078] Step 1331: Obtain the target data list from the BMC hierarchical log data through the target flag. The target data list includes the correspondence between all in-situ CPUs of the server under test and the address information of each register.

[0079] Optionally, the target data list corresponding to the general-purpose registers can be obtained by using flag 1 "Program Final IO SAD Setting – START" and flag 2 "Program Final IO SAD Setting – END", as shown below:

[0080]

[0081] Here, Socket represents the number of the in-situ CPU of the server under test, and MEM0, MEM1, and MEM2 are registers with different numbers. The target data list is parsed to obtain the MEM0 register address information corresponding to all in-situ CPUs of the server under test, and the MEM0 register address data group is formed, for example, ["0:0xAF280000", "1:0xC8A80000"].

[0082] Step 1332: Determine if the target data list is empty. If the target data list is empty, exit. Alternatively, if the target data list is not empty, obtain the register address information corresponding to all in-place CPUs of the server under test from the target data list.

[0083] Optionally, if it is determined that the target data list is not empty, then the target register address list is obtained based on the target data list. It is then determined whether the number of register addresses corresponding to each register in the target register address list is equal to the number of CPUs in the server under test. If so, the register address information corresponding to all CPUs in the server under test is obtained from the target data list. If not, the process exits.

[0084] Understandably, if the target data list is determined to be empty, meaning there is no valid register address information in the target data list, it proves that the above register address identification method is not applicable to the server under test, so the process is terminated and the use of the register address identification method to identify the register address of the server under test is stopped; if the target data list is determined to be not empty, and it is determined that the target data list contains the register address information corresponding to all in-situ CPUs of the server under test, then the register address information corresponding to all in-situ CPUs of the server under test is obtained from the target data list.

[0085] In this embodiment of the invention, a target data list is obtained from the BMC hierarchical log data by using a target flag. It is then determined whether the target data list is empty. If the target data list is determined to be empty, the process exits. Alternatively, if the target data list is determined not to be empty, the register address information corresponding to all in-situ CPUs of the server under test is obtained from the target data list. This eliminates the special case where the above-mentioned register address identification method is not applicable and further improves the accuracy of register address identification.

[0086] In some embodiments, after dynamically obtaining the register address information corresponding to all in-situ CPUs of the server under test, the method further includes:

[0087] Update the target information table based on the register address information of all in-place CPUs of the server under test.

[0088] Optionally, the MEM0 register address information ["0:0xAF280000", "1:0xC8A80000"] corresponding to all in-situ CPUs of the 5280M6 server is added to the target information table. If the MEM0 register address information corresponding to CPU1 of the 5280M6 server already exists in the target information table, the original MEM0 register address information corresponding to CPU1 of the 5280M6 server in the target information table is overwritten, the MEM0 register address information corresponding to CPU1 is updated to "1:0xC8A80000", and the MEM0 register address information "0:0xAF280000" corresponding to CPU0 is inserted at the corresponding position of the 5280M6 server.

[0089] Understandably, by adding the dynamically acquired register address information of all in-situ CPUs of the server under test to the target information table, updating the target information table, and automatically establishing a register address data list associated with the server model, and automatically maintaining this data list, it is possible to continuously expand the register address list associated with servers of various models across platforms, thereby enabling unified maintenance of differentiated register addresses across multiple platforms.

[0090] Figure 3 This is a second schematic flowchart illustrating the register address identification method provided in an embodiment of the present invention. Figure 3 As shown, a register address identification method is provided, including the following steps: step 310, step 320, and step 330. This method's steps are merely one possible implementation of the present invention.

[0091] Step 310: Execute the register address identification method as described in any of the above embodiments to obtain the register address information corresponding to all in-situ CPUs of the server under test.

[0092] Step 320: Based on memory characteristic test information, filter out the target register address information from the register address information corresponding to all in-place CPUs of the server under test.

[0093] The memory characteristic test information includes the type of memory characteristic test.

[0094] Understandably, based on the type of memory characteristic test, the model of the server under test, and the information of the CPUs in operation, the target register number can be determined. This allows for the selection of the target register address from the register address information corresponding to all the CPUs in operation on the server under test. For example, if the memory characteristic test type is a Clock Enable Power Down (CKE Power Down) test, the server under test is a 5280M6, and the CPUs in operation are CPU0 and CPU1, then the target register is determined to be MEM0, and the register address information corresponding to MEM0 can be obtained.

[0095] Step 330: Obtain the memory address list based on the target register address information and the preset address offset.

[0096] The memory address list is used to test the memory characteristics of the server under test.

[0097] Understandably, each in-situ CPU of the server under test is associated with a target register address and a preset address offset. Each associated target register address and each preset address offset are added together by an address adder to convert them into physical addresses in memory, thus obtaining a list of memory addresses.

[0098] Optionally, the memory characteristic test includes at least one of the following: CKE Power Down characteristic test, clock frequency test, timing parameter test, capacity test, stability test, compatibility test, and read / write efficiency test.

[0099] For example, based on the MEM0 register address information ["0:0xAF280000", "1:0xC8A80000"] corresponding to all in-situ CPUs of a server with model 5280M6, perform CKE Power Down feature testing on the server.

[0100] In this embodiment of the invention, by executing any of the register address identification methods described above, the register address information corresponding to all in-situ CPUs of the server under test can be quickly obtained; based on memory characteristic test information, target register address information is filtered out from the register address information corresponding to all in-situ CPUs of the server under test; based on the target register address information and a preset address offset, a memory address list is obtained; and then, memory characteristic testing of the server under test can be performed based on the memory address list. The same test model can be used to complete memory characteristic testing of differentiated register address associations, reducing the impact of differentiated platforms on testing and greatly improving testing efficiency.

[0101] Figure 4 This is a schematic diagram illustrating the process of identifying register addresses and performing tests based on the identification results, as provided in an embodiment of the present invention. Figure 4 As shown, the register address is identified, and tests are performed based on the identification results, including the following steps:

[0102] Step 401: Obtain the server model and CPU availability information under test;

[0103] Step 402: Query the machine type - register MEM0 address data table B, where the machine type is the machine type of the server under test;

[0104] Step 403: Determine whether the address information of register MEM0 corresponding to all in-situ CPUs has been successfully obtained; if yes, proceed to step 414; if no, proceed to step 404.

[0105] Step 404: Set the BMC hierarchical log level to 02;

[0106] Step 405: Enable sol activate and restart the server under test;

[0107] Step 406: Obtain BMC hierarchical logs;

[0108] Step 407: Obtain the target data list using flag 1 and flag 2;

[0109] Step 408: Determine if the target data list is empty. If yes, proceed to step 409; otherwise, proceed to step 411.

[0110] Step 409: Determine that the register MEM0 list data has not been obtained;

[0111] Step 410: Exit;

[0112] Step 411: Obtain the address list A of register MEM0;

[0113] Step 412: Determine whether the length of the address list A of register MEM0 (i.e. the number of register addresses corresponding to register MEM0) is equal to the number of CPUs in place. If yes, proceed to step 413; otherwise, proceed to step 410.

[0114] Step 413: Update the device model - register MEM0 address data table B;

[0115] Step 414: Add the address data of register MEM0 to the preset address offset;

[0116] Step 415: Verify the CKE Power Down feature test through registers.

[0117] In this embodiment of the invention, by acquiring the server model and CPU in-situ information, the system queries the model-register MEM0 address data table B to determine whether the register MEM0 address information corresponding to all in-situ CPUs has been successfully acquired. If so, the register MEM0 address information corresponding to all in-situ CPUs is output; otherwise, the register MEM0 address information corresponding to all in-situ CPUs is obtained dynamically. The register MEM0 addresses corresponding to all in-situ CPUs are added to a preset address offset to obtain the memory address. Based on the memory address, the CKE Power Down feature test is verified through registers, establishing a correspondence between the server model, in-situ CPUs, and register addresses. This correspondence is automatically maintained in the model-register address data table, facilitating the querying, dynamic acquisition, and unified maintenance of differentiated register addresses corresponding to cross-platform servers. This reduces the impact of platform differences on testing and greatly improves testing efficiency.

[0118] The register address identification device provided in the embodiments of the present invention is described below. The register address identification device described below can be referred to in correspondence with the register address identification method described above.

[0119] Figure 5 This is a schematic diagram of the register address recognition device provided by the present invention, as shown below. Figure 5 As shown, the register address identification device 500 includes:

[0120] The acquisition unit 510 is used to acquire the model and CPU on-premises information of the server under test;

[0121] The query unit 520 is used to query the register address information in the database according to the model of the server under test and obtain the query result; the database stores a target information table, which includes multiple server models and the corresponding register address information of each server model;

[0122] The determining unit 530 is used to determine, based on the query results and CPU in-situ information, whether the register address information corresponding to all in-situ CPUs of the server under test has been obtained. If so, the register address information corresponding to all in-situ CPUs of the server under test is output; otherwise, the register address information corresponding to all in-situ CPUs of the server under test is dynamically obtained.

[0123] Optionally, dynamically obtain the register address information corresponding to all in-situ CPUs of the server under test, including:

[0124] Control the restart of the server under test;

[0125] Acquire the Baseboard Management Controller (BMC) hierarchical log data generated during the restart process of the server under test;

[0126] The BMC hierarchical log data is parsed to obtain the register address information corresponding to all in-situ CPUs of the server under test.

[0127] Optionally, the BMC hierarchical log data is parsed to obtain the register address information corresponding to all in-situ CPUs of the server under test, including:

[0128] The target data list is obtained from the BMC hierarchical log data by using the target flag. The target data list includes the correspondence between all in-situ CPUs of the server under test and the address information of each register.

[0129] Determine if the target data list is empty. If it is determined to be empty, exit. Alternatively, if it is determined that the target data list is not empty, retrieve the register address information corresponding to all in-place CPUs of the server under test from the target data list.

[0130] Optionally, after dynamically obtaining the register address information corresponding to all in-situ CPUs of the server under test, the process also includes:

[0131] The update unit is used to update the target information table based on the register address information of all in-place CPUs of the server under test.

[0132] Optionally, based on the query results and CPU availability information, determine whether the register address information corresponding to all available CPUs of the server under test has been obtained, including:

[0133] Match the list of register address information contained in the query results with the CPU in-situ information;

[0134] If all in-situ CPUs in the CPU information match the corresponding register address information, then the register address information corresponding to all in-situ CPUs of the server under test is determined.

[0135] If no corresponding register address information is found for any in-situ CPU in the CPU in-situ information, it is determined that the register address information for all in-situ CPUs of the server under test has not been obtained.

[0136] Optionally, the register address identification method further includes:

[0137] The filtering unit is used to filter out the target register address information from the register address information corresponding to all in-place CPUs of the server under test based on memory characteristic test information.

[0138] The processing unit is used to obtain a list of memory addresses based on the target register address information and a preset address offset;

[0139] The memory address list is used to test the memory characteristics of the server under test.

[0140] It should be noted that the register address identification device provided in this embodiment of the invention can implement all the method steps implemented in the above-described register address identification method embodiment and can achieve the same technical effect. Here, the parts that are the same as those in the method embodiment and the beneficial effects will not be described in detail.

[0141] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630, and a communication bus 640. The processor 610, communication interface 620, and memory 630 communicate with each other via the communication bus 640. The processor 610 can call logical instructions in the memory 630 to execute a register address identification method. This method includes: acquiring the model and CPU availability information of the server under test; querying register address information in a database based on the model of the server under test to obtain the query result; the database stores a target information table, which includes multiple server models and their corresponding register address information; based on the query result and CPU availability information, determining whether the register address information corresponding to all available CPUs of the server under test has been obtained; if so, outputting the register address information corresponding to all available CPUs of the server under test; otherwise, dynamically acquiring the register address information corresponding to all available CPUs of the server under test.

[0142] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0143] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the register address identification method provided by the above methods. The method includes: obtaining the model and CPU in-situ information of the server under test; querying register address information in a database according to the model of the server under test to obtain a query result; storing a target information table in the database, which includes multiple server models and the register address information corresponding to each server model; and determining, based on the query result and the CPU in-situ information, whether the register address information corresponding to all in-situ CPUs of the server under test has been obtained. If so, the register address information corresponding to all in-situ CPUs of the server under test is output; otherwise, the register address information corresponding to all in-situ CPUs of the server under test is dynamically obtained.

[0144] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the register address identification method provided by the above methods. The method includes: acquiring the model and CPU in-situ information of the server under test; querying register address information in a database according to the model of the server under test to obtain a query result; storing a target information table in the database, the target information table including multiple server models and the register address information corresponding to each server model; determining, based on the query result and the CPU in-situ information, whether the register address information corresponding to all in-situ CPUs of the server under test has been obtained; if so, outputting the register address information corresponding to all in-situ CPUs of the server under test; otherwise, dynamically acquiring the register address information corresponding to all in-situ CPUs of the server under test.

[0145] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0146] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.< / password> < / user> < / bmcip> < / password> < / user> < / bmcip>

Claims

1. A register address identification method, characterized in that, include: Obtain the model and CPU location information of the server under test; Based on the model of the server under test, the register address information is queried in the database to obtain the query results; The database stores a target information table, which includes multiple server models and the corresponding register address information for each server model. Based on the query results and the CPU in-situ information, determine whether the register address information corresponding to all in-situ CPUs of the server under test is obtained. If yes, output the register address information corresponding to all in-situ CPUs of the server under test. Otherwise, dynamically obtain the register address information corresponding to all in-situ CPUs of the server under test. The dynamic acquisition of register address information corresponding to all in-situ CPUs of the server under test includes: Control the restart of the server under test; Obtain the Baseboard Management Controller (BMC) hierarchical log data generated during the restart process of the server under test; The BMC hierarchical log data is parsed to obtain the register address information corresponding to all in-situ CPUs of the server under test; The step of parsing the BMC hierarchical log data to obtain the register address information corresponding to all in-situ CPUs of the server under test includes: Using the target flag, a target data list is obtained from the BMC hierarchical log data. The target data list includes the correspondence between all in-situ CPUs of the server under test and the address information of each register. Determine whether the target data list is empty. If the target data list is determined to be empty, exit. Alternatively, if the target data list is determined not to be empty, obtain the register address information corresponding to all in-place CPUs of the server under test from the target data list.

2. The register address identification method according to claim 1, characterized in that, After dynamically acquiring the register address information corresponding to all in-situ CPUs of the server under test, the method further includes: The target information table is updated based on the register address information corresponding to all in-place CPUs of the server under test.

3. The register address identification method according to claim 1, characterized in that, The step of determining whether to obtain the register address information corresponding to all in-situ CPUs of the server under test based on the query result and the CPU in-situ information includes: The list of register address information contained in the query results is matched with the CPU in-situ information; If all in-situ CPUs in the CPU in-situ information match the corresponding register address information, then the register address information corresponding to all in-situ CPUs of the server under test is determined. If no corresponding register address information is found for any in-situ CPU in the CPU in-situ information, it is determined that the register address information corresponding to all in-situ CPUs of the server under test has not been obtained.

4. The register address identification method according to claim 1, characterized in that, The register address identification method further includes: Based on memory characteristic test information, target register address information is selected from the register address information corresponding to all in-place CPUs of the server under test. Based on the target register address information and the preset address offset, a list of memory addresses is obtained; The memory address list is used to perform memory characteristic tests on the server under test.

5. A register address identification device, characterized in that, include: The acquisition unit is used to acquire the model and CPU availability information of the server under test. The query unit is used to query register address information in the database according to the model of the server under test and obtain the query result; the database stores a target information table, which includes multiple server models and the corresponding register address information of each server model; The determining unit is used to determine, based on the query result and the CPU in-situ information, whether the register address information corresponding to all in-situ CPUs of the server under test is obtained. If so, the register address information corresponding to all in-situ CPUs of the server under test is output; otherwise, the register address information corresponding to all in-situ CPUs of the server under test is dynamically obtained. The dynamic acquisition of register address information corresponding to all in-situ CPUs of the server under test includes: Control the restart of the server under test; Obtain the Baseboard Management Controller (BMC) hierarchical log data generated during the restart process of the server under test; The BMC hierarchical log data is parsed to obtain the register address information corresponding to all in-situ CPUs of the server under test; The step of parsing the BMC hierarchical log data to obtain the register address information corresponding to all in-situ CPUs of the server under test includes: Using the target flag, a target data list is obtained from the BMC hierarchical log data. The target data list includes the correspondence between all in-situ CPUs of the server under test and the address information of each register. Determine whether the target data list is empty. If the target data list is determined to be empty, exit. Alternatively, if the target data list is determined not to be empty, obtain the register address information corresponding to all in-place CPUs of the server under test from the target data list.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the register address identification method as described in any one of claims 1 to 4.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the register address identification method as described in any one of claims 1 to 4.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the register address identification method as described in any one of claims 1 to 4.

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