Super junction MOSFET and manufacturing method thereof

Abstract

The application provides a super-junction MOSFET and a manufacturing method thereof, which comprises a substrate, a buffer zone, a first conductive type column, a second conductive type column, a body region, a source region, a body contact region, a gate structure, a source and a drain, wherein the buffer zone is stacked above the substrate; the first conductive type column and the second conductive type column are juxtaposed and adjacent to the upper surface of the buffer zone; the body region is stacked on the second conductive type column; the source region and the body contact region are adjacent and both located on the upper surface layer of the body region; the gate structure comprises a gate dielectric layer, a first gate and a second gate located on both sides of the first gate; the source covers the upper surface of the device; and the drain covers the bottom surface of the substrate. Through the design of the gate structure, the first gate of the first conductive type and the second gate comprising at least the second conductive type doped region replace the gate, the Miller capacitance when the drain-source voltage is low is reduced, the Miller capacitance when the drain-source voltage is high is not changed, and the on-resistance of the device is unchanged.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a superjunction MOSFET and its fabrication method. Background Technology

[0002] In typical power MOSFETs, the on-resistance is related to the breakdown voltage by a power of 2.5. Therefore, for power MOSFETs, a high breakdown voltage is often accompanied by an exponentially increasing on-resistance; for example, when the breakdown voltage increases from 50V to 500V, the on-resistance of a typical power MOSFET increases by 316 times. The advent of superjunction MOSFETs changes this relationship from 2.5 to 1.3. Therefore, compared to typical power MOSFETs, superjunction MOSFETs can significantly reduce chip area and thus lower chip cost for the same on-resistance. This smaller chip area also helps reduce parasitic capacitance. For power MOSFETs, low parasitic capacitance, especially low Miller capacitance, helps reduce the switching time required, thereby reducing switching losses and increasing efficiency. Furthermore, the switching time of superjunction MOSFETs can also be reduced by decreasing Miller capacitance.

[0003] Currently, split-gate technology is commonly used to reduce Miller capacitance across the entire voltage range in superjunction MOSFETs. However, while reducing Miller capacitance across the entire voltage range, this method results in extremely low Miller capacitance at higher voltages, potentially leading to excessively high dV / dt. This can cause current overshoot, RLC oscillation, and electromagnetic interference (EMI) in the application circuit. Furthermore, the split-gate approach sacrifices a portion of the channel electron accumulation layer, increasing the device's on-resistance to some extent. Implementing a split-gate requires a complex manufacturing process, increasing device manufacturing costs. Another approach is to reduce the doping concentration of the JFET region to lower Miller capacitance in superjunction MOSFETs. However, reducing the JFET doping concentration increases the device's on-resistance, requiring a larger chip area to achieve the same on-resistance, resulting in larger parasitic capacitance and reduced switching speed. Additionally, reducing the JFET doping concentration only reduces Miller capacitance at lower voltages, having no effect on Miller capacitance at higher voltages.

[0004] Therefore, there is an urgent need for a superjunction power MOSFET that can greatly optimize Miller capacitance without increasing the on-resistance of the device or the difficulty of the manufacturing process. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superjunction MOSFET and its fabrication method, which solves the problem that reducing the Miller capacitance of the super MOSFET in the prior art leads to increased on-resistance and increased process difficulty.

[0006] To achieve the above and other related objectives, the present invention provides a superjunction MOSFET, comprising:

[0007] First conductivity type substrate;

[0008] A first conductivity type buffer is located on the upper surface of the substrate;

[0009] A first conductive type pillar is disposed on the upper surface of the buffer and extends in a direction away from the substrate, and the first conductive type pillar includes a first pillar region and a second pillar region stacked on the first pillar region.

[0010] A second conductive type post is disposed on the upper surface of the buffer zone and located on both sides of the first post area. The sidewall of the second conductive type post is adjacent to the sidewall of the first post area, and the upper surface of the second conductive type post is flush with the upper surface of the first post area.

[0011] The second type of conductive body region is stacked on the second type of conductive pillar, and the upper surface of the body region is flush with the upper surface of the second pillar region, and the sidewall of the body region is adjacent to the sidewall of the second pillar region.

[0012] The adjacent first conductivity type source region and the second conductivity type body contact region are located on the upper surface of the body region, and the source region and the body contact region are separated from the first conductivity type pillar by a predetermined distance;

[0013] A gate structure, located on the upper surface of the first conductivity type pillar, includes at least a gate dielectric layer, a first gate, and a second gate located on both sides of the first gate. The gate dielectric layer encloses the first gate and the second gate, and the first gate is located above the first conductivity type pillar. The second gate is located above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar. The first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type.

[0014] The source and drain are provided, wherein the source covers the exposed surfaces of the gate structure, the source region and the body contact region, and the drain covers the bottom surface of the substrate.

[0015] Optionally, the doped region of the second conductivity type is electrically connected to either the second gate or the source.

[0016] Optionally, a first isolation dielectric layer is further provided between the first gate and the second gate to isolate the first gate and the second gate.

[0017] Optionally, when the first gate is entirely a doped region of the second conductivity type, the doped region of the second conductivity type is adjacent to the second gate.

[0018] Optionally, the second conductivity type doped region further includes a first concentration region and a second concentration region located on both sides of the first concentration region, and the doping concentration of the second concentration region is lower than the doping concentration of the first concentration region.

[0019] Optionally, the first gate may further include a doped region of a first conductivity type.

[0020] Optionally, the first conductivity type doped region is located between the second gate and the second conductivity type doped region, and both ends of the first conductivity type doped region are adjacent to the second gate and the second conductivity type doped region, respectively.

[0021] Optionally, the second conductivity type doped region is located between the first conductivity type doped region and the second gate, and the second conductivity type doped region is adjacent to both the first conductivity type doped region and the second gate.

[0022] Optionally, a second isolation dielectric layer is further provided between the second conductivity type doped region and the first conductivity type doped region to isolate the second conductivity type doped region and the first conductivity type doped region.

[0023] This invention also provides a method for fabricating a superjunction MOSFET, comprising the following steps:

[0024] A substrate of a first conductivity type is provided, and a buffer zone of the first conductivity type is formed on the upper surface of the substrate;

[0025] A first conductive type first pillar area and a second conductive type pillar located on both sides of the first pillar area are formed on the upper surface of the buffer zone, and the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar area, and the upper surface of the first pillar area is flush with the upper surface of the second conductive type pillar.

[0026] A second column region of a first conductivity type is formed on the upper surface of the first column region. The first column region and the second column region together form a first conductivity type column. A second conductivity type body region is formed on both sides of the second column region, located on the upper surface of the second conductivity type column and adjacent to the sidewall of the second column region. The upper surface of the body region is flush with the upper surface of the second column region.

[0027] An adjacent first conductive type source region and a second conductive type body contact region are formed in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a predetermined distance;

[0028] A gate structure is formed on the upper surface of the first conductivity type pillar. The gate structure includes a gate dielectric layer, a first gate, and a second gate located on both sides of the first gate. The gate dielectric layer encloses the first gate and the second gate. The first gate is located above the first conductivity type pillar, and the second gate is located above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar. The first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type.

[0029] A source electrode is formed covering the exposed surfaces of the gate structure, the source region, and the body contact region, and a drain electrode is formed on the bottom surface of the substrate covering the bottom surface of the substrate.

[0030] As described above, the superjunction MOSFET and its fabrication method of the present invention redesign the gate structure of the superjunction MOSFET, setting the gate structure to include at least the gate dielectric layer, the first gate, and the second gate located on both sides of the first gate. The first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type. When the depletion layer of the first conductivity type pillar is narrow, the Miller capacitance of the device is reduced by controlling the connection method of the second conductivity type doped region. Furthermore, when the first isolation dielectric layer is provided between the first gate and the second gate, the loss of the gate structure is reduced, and the reverse breakdown voltage between the first gate and the second gate is enhanced. The first conductivity type doped region is provided in the first gate. When the first conductivity type doped region is located between the second gate and the second conductivity type doped region, the Miller capacitance of the device when the depletion layer of the first conductivity type pillar is narrow is controlled by adjusting the width of the first conductivity type doped region and the connection method of the second conductivity type doped region. At least one isolation dielectric layer is provided between the first gate and the second gate and between the first conductivity type doped region and the second conductivity type doped region, thereby reducing the loss of the gate structure. Furthermore, when the voltage of the second gate increases, an induced charge accumulation layer is generated on the upper surface of the first conductivity type pillar below the first gate, which does not affect the on-resistance of the device and has high industrial application value. Attached Figure Description

[0031] Figure 1 The diagram shown is a cross-sectional view of a superjunction MOSFET according to the present invention.

[0032] Figure 2The diagram shows a cross-sectional view of the superjunction MOSFET of the present invention, in which a first isolation dielectric layer is disposed between the first gate and the second gate.

[0033] Figure 3 The diagram shows a cross-sectional structure of the superjunction MOSFET of the present invention when the first conductivity type doped region is located between the second gate and the second conductivity type doped region.

[0034] Figure 4 The diagram shows a cross-sectional view of the superjunction MOSFET of the present invention, in which a second isolation dielectric layer is disposed between the first gate and the third gate.

[0035] Figure 5 The diagram shows a cross-sectional structure of the superjunction MOSFET of the present invention, wherein a first conductivity type doped region is provided and a first isolation dielectric layer is provided between the first gate and the second gate.

[0036] Figure 6 The diagram shows a cross-sectional view of the superjunction MOSFET of the present invention, in which a first isolation dielectric layer and a second isolation dielectric layer are respectively disposed between the first gate and the second gate, and between the first conductivity type doped region and the second conductivity type doped region.

[0037] Figure 7 The diagram shown is a process flow diagram of the fabrication method of the superjunction MOSFET of the present invention.

[0038] Component designation explanation

[0039] 1 Substrate

[0040] 2. Buffer

[0041] 3 First type of conductive column

[0042] 31 First column area

[0043] 32 Second column area

[0044] 4. Second type of conductive column

[0045] 5 body areas

[0046] 6 source regions

[0047] 7. Body contact area

[0048] 8-gate structure

[0049] 81 Gate dielectric layer

[0050] 82 First gate

[0051] 83 Second gate

[0052] 84 First conductivity type doped region

[0053] 85 Second conductivity type doped region

[0054] 86 First isolation medium layer

[0055] 87 Second isolation medium layer

[0056] 9 Source poles

[0057] 10 Drain Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] Example 1

[0061] This embodiment provides a superjunction MOSFET, such as Figure 1The diagram shows a cross-sectional view of the superjunction MOSFET, including a first conductivity type substrate 1, a first conductivity type buffer zone 2, a first conductivity type pillar 3, a second conductivity type pillar 4, a second conductivity type body region 5, a first conductivity type source region 6, a second conductivity type body contact region 7, a gate structure 8, a source 9, and a drain 10. The buffer zone 2 is located on the upper surface of the substrate 1. The first conductivity type pillar 3 is disposed on the upper surface of the buffer zone 2 and extends away from the substrate 1, and includes a first pillar region 31 and a second pillar region 32 stacked on the first pillar region 31. The second conductivity type pillar 4 is disposed on the upper surface of the buffer zone 2 and located on both sides of the first pillar region 31, with its sidewall adjacent to the sidewall of the first pillar region 31, and its upper surface flush with the upper surface of the first pillar region 31. The body region 5 is stacked on the second conductivity type pillar 4, and its upper surface is flush with the upper surface of the second pillar region 32. The sidewall of the source region 6 is adjacent to the sidewall of the second pillar region 32; the source region 6 is adjacent to the body contact region 7, the source region 6 and the body contact region 7 are on the upper surface of the body region 5, and the source region 6 and the body contact region 7 are spaced apart from the first conductivity type pillar 3 by a predetermined distance; the gate structure 8 is located on the upper surface of the first conductivity type pillar 3, the gate structure 8 includes at least a gate dielectric layer 81, a first gate 82 and a second gate 83 located on both sides of the first gate 82, the gate dielectric layer 81 wraps the first gate 82 and the second gate 83, and the first gate 82 is located above the first conductivity type pillar 3, the second gate 83 is located above the source region 6, above the first conductivity type pillar 3 and above the body region 5 between the source region 6 and the first conductivity type pillar 3, and the first gate 82 includes at least a second conductivity type doped region 85, and the second gate 83 is of the first conductivity type; the source electrode 9 covers the exposed surfaces of the gate structure 8, the source region 6 and the body contact region 7, and the drain electrode 10 covers the bottom surface of the substrate 1.

[0062] Specifically, the first conductivity type includes either N-type or P-type, the second conductivity type includes either N-type or P-type, and the first conductivity type and the second conductivity type are opposite in conductivity type.

[0063] Specifically, the substrate 1 is made of silicon or other suitable semiconductor materials. In this embodiment, the substrate 1 is N-type silicon.

[0064] Specifically, the doping concentration of the substrate 1 is higher than that of the buffer 2, and the doping concentration of the first conductivity type pillar 3 is higher than that of the buffer 2.

[0065] Specifically, the thickness of the substrate 1 can be set according to the actual situation, and is not limited here; the thickness of the buffer zone 2 can be set according to the actual situation, and is not limited here; the height of the first conductive type pillar 3 can be set according to the actual situation, and is not limited here.

[0066] Specifically, the first pillar region 31 and the second pillar region 32 have the same doping concentration, and the doping concentration of the first conductivity type pillar 3 is higher than the doping concentration of the buffer zone 2.

[0067] Specifically, the doping concentration of the second conductivity type column 4 can be set according to the actual situation, and is not limited here.

[0068] Specifically, the doping concentration of the body region 5 is lower than that of the second conductivity type pillar 4, and the thickness of the body region 5 can be set according to actual conditions, which is not limited here.

[0069] Specifically, the doping concentration of the body contact region 7 is higher than that of the body region 5, and the doping concentration of the source region 6 is higher than that of the first conductivity type pillar 3.

[0070] Specifically, the thickness of the gate dielectric layer 81 can be set according to the actual situation, and is not limited here.

[0071] As an example, the second conductivity type doped region 85 is electrically connected to either the second gate 83 or the source 9.

[0072] Specifically, when the voltage between the source 9 and the drain 10 is low, the depletion layer formed at the PN junction between the first conductive type pillar 3, the second conductive type pillar 4, and the body region 5 is narrow. As the voltage between the source 9 and the drain 10 increases, the depletion layer formed at the PN junction between the first conductive type pillar 3, the second conductive type pillar 4, and the body region 5 gradually widens until the first conductive type pillar 3 is completely depleted.

[0073] Specifically, the second gate 83 controls the conduction of the channel between the source region 6 and the second pillar region 32, that is, controls the generation of a conductive channel in the body region 5 between the source region 6 and the second pillar region 32.

[0074] As an example, when the first gate 82 is entirely a doped region 85 of the second conductivity type, the doped region 85 of the second conductivity type is adjacent to the second gate 83.

[0075] Specifically, when the first gate 82 is entirely a doped region 85 of the second conductivity type and the second conductivity type doped region 85 is electrically connected to the second gate 83, a weak built-in electric field is formed between the first gate 82 and the second gate 83, thereby forming a narrow depletion layer. When the depletion layer in the first conductivity type pillar 3 is narrow, that is, the voltage between the source 9 and the drain 10 is low, the coupling between the gate structure 8 and the drain 10 is reduced, thereby reducing the Miller capacitance of the device.

[0076] Specifically, when the first gate 82 is entirely a doped region 85 of the second conductivity type and the second conductivity type doped region 85 is electrically connected to the source 9, the source 9 and the first gate 82 have the same potential, the first gate 82 and the second gate 83 have different potentials and are equivalent to a reverse PN junction, a strong built-in electric field is formed between the first gate 82 and the second gate 83, and a depletion layer is formed. When the depletion layer in the first conductivity type pillar 3 is narrow, that is, the voltage between the source 9 and the drain 10 is low, the coupling between the gate structure 8 and the drain 10 is reduced, and the Miller capacitance of the device is reduced.

[0077] As an example, the second conductivity type doped region 85 also includes a first concentration region and a second concentration region located on both sides of the first concentration region, and the doping concentration of the second concentration region is lower than that of the first concentration region, so that the second concentration region is depleted to obtain a wider depletion layer.

[0078] Specifically, the thickness of the depletion layer between the first gate 82 and the second conductivity type doped region 85 is controlled to change the overlap area between the gate structure 8 and the drain 10, that is, to adjust the coupling strength between the gate and the drain, and then to adjust the Miller capacitance of the device when the voltage between the source 9 and the drain 10 is low.

[0079] Specifically, the voltage of the second gate can turn on the conductive channel in the device, and the voltage difference between the second gate 83 and the second conductivity type doped region 85 cannot break down the PN junction between the second gate 83 and the second conductivity type doped region 85.

[0080] Specifically, the doping concentration of the second gate 83 is not less than 10. 19 cm -3 The doping concentration range of the second conductivity type doped region 85 is 10. 13 cm -3 Up to 10 18 cm -3 .

[0081] As an example, such as Figure 2The diagram shows a cross-sectional view of the superjunction MOSFET with a first isolation dielectric layer 86 disposed between the first gate 82 and the second gate 83. The first isolation dielectric layer 86 is also disposed between the first gate 82 and the second gate 83 to isolate the first gate 82 and the second gate 83.

[0082] Specifically, the first isolation dielectric layer 86 separates the first gate 82 from the second gate 83 to reduce the loss of the gate structure 8, and can increase the breakdown voltage between the second conductivity type doped region 85 and the second gate 83.

[0083] Specifically, the material of the first isolation dielectric layer 86 includes silicon dioxide or other suitable dielectric materials.

[0084] Specifically, the thickness of the first isolation medium layer 86 can be set according to the actual situation, and is not limited here.

[0085] As an example, the first gate 82 also includes a first conductivity type doped region 84.

[0086] Specifically, the doping concentration range of the first conductivity type doped region 84 is 10. 12 cm -3 Up to 10 17 cm -3 .

[0087] As an example, such as Figure 3 The diagram shows a cross-sectional view of the first conductivity type doped region 74 located between the second gate 83 and the first conductivity type doped region 85. The first conductivity type doped region 84 is located between the second gate 83 and the second conductivity type doped region 85, and both ends of the first conductivity type doped region 84 are adjacent to the second gate 83 and the second conductivity type doped region 85, respectively.

[0088] Specifically, when the first conductivity type doped region 84 is located between the second gate 83 and the second conductivity type doped region 85, the concentration of the first conductivity type doped region 84 is different from the doping concentration of the second gate 83.

[0089] Specifically, while ensuring that the PN junction between the first conductivity type doped region 84 and the second conductivity type doped region 85 does not undergo reverse breakdown and the device can conduct, as the doping concentration of the first conductivity type doped region 84 increases, the width of the depletion layer between the first conductivity type doped region 84 and the second conductivity type doped region 85 narrows. When the voltage between the source 9 and the drain 10 is low, the depletion layer in the first conductivity type pillar 3 is narrow. By adjusting the doping concentration of the first conductivity type doped region 84, the width of the depletion layer between the first conductivity type doped region 84 and the second conductivity type doped region 85 can be increased to reduce the coupling between the gate structure 8 and the drain 10, thereby reducing the Miller capacitance of the device.

[0090] Specifically, under the condition that the PN junction between the first conductivity type doped region 84 and the second conductivity type doped region 85 does not undergo reverse breakdown and the device can be turned on, the lower the voltage between the second gate 83 and the second conductivity type doped region 85, the narrower the depletion layer between the first conductivity type doped region 84 and the second conductivity type doped region 85. When the voltage between the source 9 and the drain 10 is low, the depletion layer in the first conductivity type pillar 3 is narrower. By adjusting the voltage between the second gate 83 and the second conductivity type doped region 85, the width of the depletion layer between the first conductivity type doped region 84 and the second conductivity type doped region 85 is increased, thereby reducing the coupling between the gate structure 8 and the drain 10, and thus reducing the Miller capacitance of the device.

[0091] Specifically, when the first conductivity type pillar 3 is depleted, that is, the voltage between the drain 10 and the source 9 is high, the width of the depletion layer formed between the first conductivity type doped region 84 and the second conductivity type doped region 85 is negligible compared to the width of the depletion layer in the first conductivity type pillar 3, and thus the Miller capacitance of the device remains approximately unchanged.

[0092] As an example, the second conductivity type doped region 85 is located between the first conductivity type doped region 84 and the second gate 83, and the second conductivity type doped region 85 is adjacent to the first conductivity type doped region 84 and the second gate 83 respectively.

[0093] Specifically, when the second conductivity type doped region 85 is located between the first conductivity type doped region 84 and the second gate 83, the potentials of the second conductivity type doped regions 85 on both sides of the first conductivity type doped region 84 are the same, and a depletion layer is formed between the second conductivity type doped region 85 and the second gate 83. By controlling the width of the second conductivity type doped region 85, the doping concentration of the second conductivity type doped region 85, and the voltage between the second conductivity type doped region 85 and the second gate 83, the width of the depletion layer between the second conductivity type doped region 85 and the second gate 83 is controlled, thereby reducing the coupling between the second gate 83 and the drain 10, and thus reducing the capacitance of the device when the voltage between the source 9 and the drain 10 is low.

[0094] Specifically, when the voltage of the second gate 83 increases, a charge accumulation layer is generated on the upper surface of the first conductivity type pillar 3 located below the second conductivity type doped region 85, thus not affecting the on-resistance when the device is turned on.

[0095] As an example, such as Figure 4 The diagram shows a cross-sectional view of a second isolation dielectric layer 87 disposed between the first conductivity type doped region 84 and the second conductivity type doped region 85. The second conductivity type doped region 85 and the first conductivity type doped region 84 are further provided with a second isolation dielectric layer 87 to isolate the second conductivity type doped region 85 and the first conductivity type doped region 84.

[0096] Specifically, when the second conductivity type doped region 85 is located between the first conductivity type doped region 84 and the second gate 83, the second isolation dielectric layer 87 separates the second gate 83 from the second conductivity type doped region 85 to reduce the loss of the gate structure 8 and enhance the reverse breakdown voltage between the second gate 83 and the second conductivity type doped region 85.

[0097] Specifically, the material of the second insulating dielectric layer 87 includes silicon dioxide or other suitable dielectric materials.

[0098] Specifically, the thickness of the second isolation medium layer 87 can be set according to the actual situation, and is not limited here.

[0099] Specifically, such as Figure 5 and Figure 6The figures show cross-sectional views of the first gate 82 and the second gate 83 with the first isolation dielectric layer 86 disposed between them, and cross-sectional views of the first gate 82 and the second gate 83 with the first conductivity type doped region 84 and the second conductivity type doped region 85 respectively disposed with the first isolation dielectric layer 86 and the second isolation dielectric layer 87 respectively. When the first gate 82 has a first conductivity type doped region 84 and the first gate 82 is composed of the first conductivity type doped region 84 and the second conductivity type 85, the first isolation dielectric layer 86 is disposed between the first gate 82 and the second gate 83, and the second isolation dielectric layer 87 is disposed between the first conductivity type doped region 84 and the second conductivity type doped region 85 respectively, so as to isolate the second gate 83, the first conductivity type doped region 84 and the second conductivity type doped region 85, thereby reducing the loss of the gate structure 8 and increasing the reverse breakdown voltage between the second gate 83 and the second conductivity type doped region 85.

[0100] Specifically, the source electrode 9 is made of one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0101] Specifically, the material of the drain electrode 10 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0102] This embodiment of the superjunction MOSFET redesigns the gate structure 8 by configuring it to include at least the gate dielectric layer 81, the first gate 82, and the second gate 83 located on both sides of the first gate 82. The second gate 83 has a first conductivity type. The first gate 82 includes at least a second conductivity type doped region 85. The second conductivity type doped region 85 is electrically connected to one of the source 9 and the second gate 83 to reduce the Miller capacitance of the device when the depletion layer in the first conductivity type pillar 3 is narrow, without changing the Miller capacitance of the device when the first conductivity type pillar 3 is depleted. When the first gate 82 is entirely the second conductivity type doped region 85 and the first isolation dielectric layer 86 is provided between the first gate 82 and the second conductivity type doped region 85, the loss of the gate structure 8 can be reduced, and the connection between the second conductivity type doped region 85 and the source 9 can be strengthened. The reverse breakdown voltage between the second gate 83 is described; when the first gate 82 is provided with the first conductivity type doped region 84, the width and doping concentration of the second conductivity type doped region 85 or the connection method of the second conductivity type doped region 85 are adjusted to reduce the Miller capacitance of the device when the depletion layer in the first conductivity type pillar 3 is narrow, without changing the Miller capacitance of the device when the first conductivity type pillar 3 is depleted; a second isolation dielectric layer 87 is provided between the second conductivity type doped region 85 and the first conductivity type doped region 84, or a first isolation dielectric layer 86 is provided between the first gate 82 and the second gate 83 and a second isolation dielectric layer 87 is provided between the second conductivity type doped region 85 and the first conductivity type doped region 84, so as to reduce the loss of the gate structure 8 and the reverse breakdown voltage between the second conductivity type doped region 85 and the second gate 83, and the change in the structure of the gate structure 8 does not increase the on-resistance of the device.

[0103] Example 2

[0104] This embodiment provides a method for fabricating a superjunction MOSFET, such as... Figure 7 The diagram shown is a process flow chart for fabricating the superjunction MOSFET, including the following steps:

[0105] S1: Provide a substrate of a first conductivity type, and form a buffer zone of the first conductivity type on the upper surface of the substrate;

[0106] S2: A first conductive type first pillar area and a second conductive type pillar located on both sides of the first pillar area are formed on the upper surface of the buffer zone, and the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar area, and the upper surface of the first pillar area is flush with the upper surface of the second conductive type pillar.

[0107] S3: A second column region of a first conductivity type is formed on the upper surface of the first column region. The first column region and the second column region form a first conductivity type column. A second conductivity type body region is formed on both sides of the second column region, located on the upper surface of the second conductivity type column and adjacent to the side wall of the second column region. The upper surface of the body region is flush with the upper surface of the second column region.

[0108] S4: A first conductive type source region and a second conductive type body contact region are formed adjacent to each other in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a preset distance;

[0109] S5: A gate structure is formed on the upper surface of the first conductivity type pillar. The gate structure includes a gate dielectric layer, a first gate, and a second gate located on both sides of the first gate. The gate dielectric layer encloses the first gate and the second gate. The first gate is located above the first conductivity type pillar, and the second gate is located above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar. The first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type.

[0110] S6: Form a source electrode covering the exposed surfaces of the gate structure, the source region, and the body contact region, and form a drain electrode covering the bottom surface of the substrate.

[0111] Perform step S1: Provide a substrate of a first conductivity type and form a buffer zone of a first conductivity type on the upper surface of the substrate.

[0112] Specifically, the thickness of the buffer can be selected according to the actual situation, and is not limited here.

[0113] Specifically, the method for forming the buffer zone includes chemical vapor deposition or other suitable methods.

[0114] Perform steps S2 and S3: form a first conductive type first pillar region and a second conductive type pillar located on both sides of the first pillar region on the upper surface of the buffer, wherein the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar region, and the upper surface of the first pillar region is flush with the upper surface of the second conductive type pillar; form a second conductive type second pillar region on the upper surface of the first pillar region, wherein the first pillar region and the second pillar region constitute a first conductive type pillar, and form a second conductive type body region on both sides of the second pillar region located on the upper surface of the second conductive type pillar and adjacent to the sidewall of the second pillar region, wherein the upper surface of the body region is flush with the upper surface of the second pillar region.

[0115] Specifically, the method for forming the second conductive type pillar and the first pillar region includes forming multiple pillar region semiconductor layers stacked upwards on the upper surface of the buffer, and forming the first pillar region and the second conductive type pillar in a designated area of ​​the pillar region semiconductor layer after each pillar region semiconductor layer is formed, until the thickness of the first pillar region and the second conductive type pillar reaches a preset thickness.

[0116] Specifically, the method for forming the semiconductor layer in the pillar region includes chemical vapor deposition or other suitable methods.

[0117] Specifically, the methods for forming the second type of conductive column include ion implantation or other suitable methods.

[0118] Specifically, after forming the first pillar region and the second conductivity type pillar, a first semiconductor layer is formed on the upper surface of the pillar region semiconductor layer, and the second pillar region is formed in the first semiconductor layer above the first pillar region to obtain the first conductivity type pillar, and the body region is formed in the first semiconductor layer above the second conductivity type pillar.

[0119] Specifically, the methods for forming the second column region include ion implantation or other suitable methods.

[0120] Specifically, the methods for forming the body region include ion implantation or other suitable methods.

[0121] Specifically, the method for forming the first semiconductor layer includes chemical vapor deposition or other suitable methods.

[0122] Perform steps S4 and S5: Form an adjacent first conductivity type source region and a second conductivity type body contact region in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductivity type pillar by a predetermined distance; form a gate structure on the upper surface of the first conductivity type pillar, the gate structure including a gate dielectric layer, a first gate and a second gate located on both sides of the first gate, the gate dielectric layer encapsulates the first gate and the second gate, and the first gate is located above the first conductivity type pillar, the second gate is located above the body region between the source region, the first conductivity type pillar, the source region and the first conductivity type pillar, the first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type.

[0123] Specifically, the method for forming the source region in the body region includes ion implantation or other suitable methods.

[0124] Specifically, the method for forming the body contact region in the body region includes ion implantation or other suitable methods.

[0125] Specifically, the method for forming the gate dielectric layer includes at least one of thermal oxidation and chemical vapor deposition.

[0126] Specifically, after forming the source region and the body contact region, a first isolation layer and a conductive material layer are sequentially formed on the upper surface of the first semiconductor layer, and the first isolation layer and the conductive material layer are etched to obtain a gate isolation layer and a gate conductive layer; a first gate and a second gate are formed in the gate conductive layer, and a second isolation layer is formed covering the exposed surfaces of the gate conductive layer and the first isolation layer to obtain the gate structure.

[0127] Specifically, the gate dielectric layer includes a first isolation layer and a second isolation layer. The method for forming the first isolation layer includes thermal oxidation, chemical vapor deposition, or other suitable methods. The method for forming the second isolation layer includes thermal oxidation, chemical vapor deposition, or other suitable methods.

[0128] Specifically, the first isolation layer is made of silicon dioxide or other suitable dielectric materials, and the second isolation layer is made of silicon dioxide or other suitable dielectric materials.

[0129] Specifically, the method for forming the conductive material layer includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0130] Specifically, the conductive material layer may be made of polycrystalline silicon or other suitable conductive materials.

[0131] Specifically, the thickness of the conductive material layer can be selected according to the actual situation, and is not limited here.

[0132] Specifically, the method for forming the first gate includes ion implantation or other suitable methods, and the method for forming the second gate includes ion implantation or other suitable methods.

[0133] Specifically, the method for forming the gate conductive layer includes one of dry etching and wet etching, or other suitable methods; the method for forming the gate isolation layer includes one of dry etching and wet etching, or other suitable methods.

[0134] Specifically, the width of the gate conductive layer can be selected according to the actual situation, and is not limited here.

[0135] Specifically, when a first isolation dielectric layer is disposed between the first gate and the second gate, after the first gate and the second gate are formed and before the second isolation layer is formed, a first trench penetrating the gate conductive layer is formed at the adjacent position of the first gate and the second gate, and then the first isolation dielectric layer filling the first trench and the second isolation layer covering the exposed surfaces of the gate conductive layer and the gate isolation layer are formed.

[0136] Specifically, the first isolation medium layer and the second isolation layer can be formed simultaneously.

[0137] Specifically, the method for forming the first trench includes one of dry etching and wet etching, or other suitable methods.

[0138] Specifically, when the first gate has a first conductivity type doped region, the first conductivity type doped region is formed in a designated area of ​​the gate conductive layer by ion implantation or other suitable methods.

[0139] Specifically, when a second isolation dielectric layer is provided between the first conductivity type doped region and the second conductivity type doped region, after the first gate and the second gate are formed and before the second isolation layer is formed, a second trench penetrating the gate conductive layer is formed at the adjacent location of the first conductivity type doped region and the second conductivity type doped region, and then a second isolation dielectric layer filling the second trench and a second isolation layer covering the exposed surfaces of the gate conductive layer and the gate isolation layer are formed.

[0140] Specifically, the second isolation medium layer and the second isolation layer can be formed simultaneously.

[0141] Specifically, the method for forming the second trench includes one of dry etching and wet etching, or other suitable methods.

[0142] Specifically, when the first isolation medium is provided between the first gate and the second gate, and the first isolation dielectric layer and the second isolation dielectric layer are respectively provided between the second conductivity type doped region and the first conductivity type doped region, after the first gate and the second gate are formed and before the second isolation layer is formed, a first trench and a second trench penetrating the gate conductive layer are respectively formed at the adjacent position of the second gate and the first gate and at the adjacent position of the first conductivity type doped region and the second conductivity type doped region. Then, the first isolation dielectric layer filling the first trench, the second isolation dielectric layer filling the second trench, and the second isolation layer covering the exposed surfaces of the gate conductive layer and the gate isolation layer are formed.

[0143] Specifically, the first isolation medium layer, the second isolation medium layer, and the second isolation layer can be formed simultaneously.

[0144] Specifically, the widths of the first groove and the second groove can be selected according to the actual payment request, and are not limited here.

[0145] Specifically, the first trench and the second trench are formed simultaneously.

[0146] Perform step S6: form a source electrode covering the exposed surfaces of the gate structure, the source region, and the body contact region, and form a drain electrode covering the bottom surface of the substrate.

[0147] Specifically, the methods for forming the source electrode include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0148] Specifically, the methods for forming the drain include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0149] The superjunction MOSFET fabrication method of this embodiment ensures the stability of the doping concentration of the first pillar region and the second conductivity type pillar by forming the pillar region semiconductor layer multiple times and performing ion implantation multiple times to form the first pillar region and the second conductivity type pillar. Furthermore, the first conductivity type doped region and the second conductivity type doped region and the second gate are formed in the gate structure by ion implantation without increasing the difficulty of the process.

[0150] In summary, the superjunction MOSFET and its fabrication method of the present invention, through the design of the gate structure, utilizes at least a first gate and a second gate to replace the gate, wherein the first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type. The first gate is positioned above the first conductivity type pillar, and the second gate is located on both sides of the first gate and controls the conductive channel in the device. The second conductivity type doped region is electrically connected to the source or the second gate to reduce the Miller capacitance of the device when the depletion layer of the first conductivity type pillar is narrow, without changing the Miller capacitance of the device when the first conductivity type pillar is depleted. When the first gate is entirely of the second conductivity type and a first isolation dielectric layer is provided between the first gate and the second gate, the loss of the gate structure is reduced, and the reverse breakdown voltage between the first gate and the second gate is increased. When a first conductivity type doped region is provided and the first gate is entirely composed of a first conductivity type doped region and a second conductivity type doped region, the Miller capacitance of the device when the depletion layer of the first conductivity type pillar is narrow is adjusted by regulating the width of the second conductivity type doped region, without changing the Miller capacitance of the device when the first conductivity type pillar is depleted. A first isolation dielectric layer is provided between the first gate and the second gate, and a second isolation dielectric layer is provided between the second conductivity type doped region and the first conductivity type doped region. Alternatively, when the second conductivity type doped region is located on both sides of the second conductivity type doped region, a second isolation dielectric layer is provided between the second conductivity type doped region and the first conductivity type doped region. This reduces the loss of the gate structure and increases the reverse breakdown voltage between the first gate and the second conductivity type doped region. Furthermore, the gate structure design does not increase the on-resistance of the device. In addition, the fabrication of the gate structure does not increase the difficulty of the process. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0151] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superjunction MOSFET, characterized in that, include: First conductivity type substrate; A first conductivity type buffer is located on the upper surface of the substrate; A first conductive type pillar is disposed on the upper surface of the buffer and extends in a direction away from the substrate, and the first conductive type pillar includes a first pillar region and a second pillar region stacked on the first pillar region. A second conductive type post is disposed on the upper surface of the buffer zone and located on both sides of the first post area. The sidewall of the second conductive type post is adjacent to the sidewall of the first post area, and the upper surface of the second conductive type post is flush with the upper surface of the first post area. The second type of conductive body region is stacked on the second type of conductive pillar, and the upper surface of the body region is flush with the upper surface of the second pillar region, and the sidewall of the body region is adjacent to the sidewall of the second pillar region. The adjacent first conductivity type source region and the second conductivity type body contact region are located on the upper surface of the body region, and the source region and the body contact region are separated from the first conductivity type pillar by a predetermined distance; A gate structure, located on the upper surface of the first conductivity type pillar, includes at least a gate dielectric layer, a first gate, and a second gate located on both sides of the first gate. The gate dielectric layer encloses the first gate and the second gate, and the first gate is located above the first conductivity type pillar. The second gate is located above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar. The first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type. The source and drain are provided, wherein the source covers the exposed surfaces of the gate structure, the source region and the body contact region, and the drain covers the bottom surface of the substrate.

2. The superjunction MOSFET according to claim 1, characterized in that: The doped region of the second conductivity type is electrically connected to either the second gate or the source.

3. The superjunction MOSFET according to claim 1, characterized in that: When the first gate is entirely a doped region of the second conductivity type, the doped region of the second conductivity type is adjacent to the second gate.

4. The superjunction MOSFET according to claim 3, characterized in that: The second conductivity type doped region also includes a first concentration region and a second concentration region located on both sides of the first concentration region, and the doping concentration of the second concentration region is lower than the doping concentration of the first concentration region.

5. The superjunction MOSFET according to claim 1, characterized in that: A first isolation dielectric layer is further provided between the first gate and the second gate to isolate the first gate and the second gate.

6. The superjunction MOSFET according to claim 1, characterized in that: The first gate also includes a doped region of a first conductivity type.

7. The superjunction MOSFET according to claim 6, characterized in that: The first conductivity type doped region is located between the second gate and the second conductivity type doped region, and both ends of the first conductivity type doped region are adjacent to the second gate and the second conductivity type doped region, respectively.

8. The superjunction MOSFET according to claim 6, characterized in that: The second conductivity type doped region is located between the first conductivity type doped region and the second gate, and the second conductivity type doped region is adjacent to both the first conductivity type doped region and the second gate.

9. The superjunction MOSFET according to claim 6, characterized in that: A second isolation dielectric layer is provided between the second conductivity type doped region and the first conductivity type doped region to isolate the second conductivity type doped region and the first conductivity type doped region.

10. A method for fabricating a superjunction MOSFET, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, and a buffer zone of the first conductivity type is formed on the upper surface of the substrate; A first conductive type first pillar area and a second conductive type pillar located on both sides of the first pillar area are formed on the upper surface of the buffer zone, and the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar area, and the upper surface of the first pillar area is flush with the upper surface of the second conductive type pillar. A second column region of a first conductivity type is formed on the upper surface of the first column region. The first column region and the second column region together form a first conductivity type column. A second conductivity type body region is formed on both sides of the second column region, located on the upper surface of the second conductivity type column and adjacent to the sidewall of the second column region. The upper surface of the body region is flush with the upper surface of the second column region. An adjacent first conductive type source region and a second conductive type body contact region are formed in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a predetermined distance; A gate structure is formed on the upper surface of the first conductivity type pillar. The gate structure includes a gate dielectric layer, a first gate, and a second gate located on both sides of the first gate. The gate dielectric layer encloses the first gate and the second gate. The first gate is located above the first conductivity type pillar, and the second gate is located above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar. The first gate includes at least a second conductivity type doped region, and the second gate is of the first conductivity type. A source electrode is formed covering the exposed surfaces of the gate structure, the source region, and the body contact region, and a drain electrode is formed on the bottom surface of the substrate covering the bottom surface of the substrate.

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