Scanning drive circuit and display panel

Abstract

This invention relates to the field of display panels, providing a scanning drive circuit and a display panel. The scanning drive circuit includes a multi-stage shift register unit and a timing controller. Each stage of the shift register unit includes 13 transistors and 3 capacitors, and the timing controller includes two timing control signal lines. The scanning drive circuit and display panel of this invention, by providing a novel 13T3C shift register unit, solve the problem of mutual interference between transistors, making the scanning circuit more stable and avoiding display abnormalities caused by transistor aspect ratio fluctuations due to threshold voltage deviation or manufacturing process errors, thus improving the lifespan of the display panel. Furthermore, this shift register unit solves the problem of electrical floating of nodes in the circuit, improving the reliability of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display panels, and more specifically, to a scanning driving circuit and a display panel. Background Technology

[0002] The display panel includes a pixel array and a scanning drive circuit and a light-emitting drive circuit for controlling the pixel array. The display panel adopts a line-by-line scanning display method. The scanning drive circuit is used to generate scanning signals so that each row of pixels is turned on sequentially.

[0003] The scan drive circuit includes multiple cascaded shift register units, each of which is typically composed of several transistors. By inputting a clock signal CKV and a start pulse signal IN into the circuit, the scan signal Gout is output at the output terminal.

[0004] Chinese patent CN105989797A provides a scanning circuit, such as Figure 1 and 2 As shown, Figure 1 A circuit diagram of a prior art shift register unit is shown; Figure 2 The diagram shows the waveform of a prior art shift register unit during operation. Here, "H" represents a high-level signal and "L" represents a low-level signal. In this circuit, T5 and T6 are mutually restrained. After prolonged use of the display panel, the threshold voltage Vth of the transistors may shift, or manufacturing errors in the display panel may cause changes in the transistor aspect ratio, potentially leading to abnormal output from the display panel's scanning circuit. Figure 2 As shown, Gout is the ideal output signal, and Abnormal Gout is the abnormal output signal, causing the display panel to display an abnormal image. Furthermore, the second node N2 in the shift register unit's circuitry exhibits an electrical floating problem at certain times during operation, causing abnormal display on the display panel and reducing reliability.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a scanning driving circuit and a display panel.

[0007] One aspect of the present invention provides a scan driving circuit, including a multi-stage shift register unit, the shift register unit comprising:

[0008] The first transistor has a first terminal connected to the signal input terminal, a second terminal connected to the second node, and a gate connected to the second timing control terminal.

[0009] The second transistor has its second terminal connected to the second node and its gate connected to the first node;

[0010] The third transistor has its first terminal connected to the first power supply, its second terminal connected to the first terminal of the second transistor, and its gate connected to the first timing control terminal.

[0011] The fourth transistor has its first terminal connected to the second power supply, its second terminal connected to the fourth node, and its gate connected to the second timing control terminal.

[0012] The fifth transistor has its first terminal connected to the second timing control terminal, its second terminal connected to the first node, and its gate connected to the second node;

[0013] The sixth transistor has its first terminal connected to the second node, its second terminal connected to the fifth node, and its gate connected to the second power supply.

[0014] The seventh transistor has its first terminal connected to the first power supply, its second terminal connected to the signal output terminal, and its gate connected to the first node;

[0015] The eighth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the first timing control terminal, and its gate connected to the fifth node.

[0016] A ninth transistor, wherein the first terminal of the ninth transistor is connected to the fourth node, the second terminal is connected to the first node, and the gate is connected to the third node;

[0017] The tenth transistor has its first terminal connected to the first timing control terminal, its second terminal connected to the third node, and its gate connected to the signal input terminal.

[0018] The eleventh transistor has its first terminal connected to the third node, its second terminal connected to the second power supply, and its gate connected to the first timing control terminal.

[0019] The twelfth transistor has its first terminal connected to the first node and its gate connected to the fourth node;

[0020] The thirteenth transistor has its first terminal connected to the second terminal of the twelfth transistor, the second terminal connected to the second power supply, and its gate connected to the first timing control terminal.

[0021] A first capacitor, wherein the first terminal of the first capacitor is connected to the first power source, and the second terminal is connected to the first node;

[0022] The second capacitor has its first terminal connected to the fifth node and its second terminal connected to the signal output terminal.

[0023] The third capacitor has its first terminal connected to the fourth node and its second terminal connected to the third node.

[0024] In some embodiments, a timing controller is further included, the timing controller including a first timing control signal line and a second timing control signal line.

[0025] In some embodiments, the first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

[0026] In some embodiments, the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0027] In some embodiments, the shift register unit is used to perform delay processing on the signal received from the signal input terminal under the control of the first timing control signal and the second timing control signal, and the processed signal is output by the signal output terminal.

[0028] In some embodiments, the shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

[0029] In some embodiments, in the odd-level shift register unit, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

[0030] In some embodiments, in the even-numbered shift register units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

[0031] In some embodiments, the first transistor to the thirteenth transistor are all P-type MOS transistors.

[0032] Another aspect of the present invention provides a display panel, characterized in that it includes the scanning drive circuit described in any one of the preceding claims.

[0033] The beneficial effects of this invention compared to the prior art include at least the following:

[0034] The scanning drive circuit and display panel of the present invention provide a new 13T3C shift register unit to solve the mutual interference between transistors, making the scanning circuit more stable, avoiding display abnormalities caused by transistor aspect ratio fluctuations due to threshold voltage deviation or manufacturing process errors, and improving the service life of the display panel; in addition, the shift register unit solves the problem of electrical floating of nodes in the circuit, improving the reliability of the display panel.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0037] Figure 1 A circuit diagram of a prior art shift register unit is shown;

[0038] Figure 2 The diagram shows the waveform of a prior art shift register unit in operation.

[0039] Figure 3 A schematic diagram of the display panel of the present invention is shown;

[0040] Figure 4 A schematic diagram of the cascaded scanning drive circuit of the present invention is shown;

[0041] Figure 5 A circuit diagram of the shift register unit of the present invention is shown;

[0042] Figure 6 Show Figure 5 The waveform diagram of the shift register unit in operation is shown below;

[0043] Figure 7 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t1;

[0044] Figure 8 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t2;

[0045] Figure 9 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t3;

[0046] Figure 10 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t4.

[0047] Figure label:

[0048] 10 Display Panel

[0049] 11 Display Area

[0050] 20. Timing Controller

[0051] 30 Scan drive circuit

[0052] CKV1 First Timing Control Signal Line

[0053] CKV2 Second Timing Control Signal Line

[0054] c1 First timing control terminal

[0055] c2 Second timing control terminal

[0056] IN signal input terminal

[0057] Gout signal output terminal

[0058] T1 First Transistor

[0059] T2 second transistor

[0060] T3 Third Transistor

[0061] T4 fourth transistor

[0062] T5 fifth transistor

[0063] T6 sixth transistor

[0064] T7 Seventh Transistor

[0065] T8 Eighth Transistor

[0066] T9 Ninth Transistor

[0067] T10, the tenth transistor

[0068] T11 Eleventh Transistor

[0069] T12, the twelfth transistor

[0070] T13, the thirteenth transistor.

[0071] C1 First capacitor

[0072] C2, the second capacitor

[0073] C3 Third capacitor

[0074] VDD First Power Supply

[0075] VEE Second Power Supply

[0076] n1 First node

[0077] n2 Second node

[0078] n3 Third node

[0079] n4 Fourth node

[0080] n5 Fifth Node Detailed Implementation

[0081] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0082] The use of terms such as "first," "second," and similar terms in the specific description does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Furthermore, in the description of this invention, terms such as "upper," "lower," etc., indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings. These are merely for ease of description and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention.

[0083] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features in different embodiments can be combined with each other.

[0084] Through meticulous and in-depth research, the inventors in this case have provided a solution to the problems existing in the prior art. For example... Figures 3 to 5 As shown, Figure 3 A schematic diagram of the display panel of the present invention is shown;

[0085] Figure 4 A schematic diagram of the cascaded scanning drive circuit of the present invention is shown; Figure 5The circuit diagram of the shift register unit of the present invention is shown. The present invention discloses a scan drive circuit 30 and a display panel 10. The scan drive circuit 30 includes a multi-stage shift register unit and a timing controller 20. Each stage of the shift register unit includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, and three timing control terminals. The timing controller 20 includes three timing control signal lines. The scan drive circuit and display panel of the present invention, by providing a new 13T3C shift register unit, solve the mutual interference between transistors, making the scan circuit more stable, avoiding display abnormalities caused by transistor aspect ratio fluctuations due to threshold voltage offset or manufacturing process errors, and improving the service life of the display panel; in addition, this shift register unit solves the problem of electrical floating of nodes in the circuit, improving the reliability of the display panel.

[0086] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0087] like Figure 3 As shown, the present invention provides a display panel 10, which includes a display area 11 and a non-display area. A scan driving circuit 30, a data driver, and a light-emitting driving circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the scan driving circuit 30, the data driver, the light-emitting driving circuit, and the pixel circuits.

[0088] like Figure 3 and 4 As shown, the present invention also provides a scan driving circuit 30, which includes a multi-stage shift register unit and a timing controller 20.

[0089] In some embodiments, the shift register unit includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2, and a third timing control terminal c3. Each shift register unit outputs a scan signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive the pixels in that row to emit light. The previous shift register unit simultaneously outputs a scan signal to the signal input terminal IN of the next shift register unit as a start signal. Since the last shift register unit has no next stage, its output scan signal is only input to the pixel circuit of that row.

[0090] Specifically, Figure 4Taking a four-stage cascaded shift register unit as an example, the first-stage shift register unit S1 receives the start pulse signal STV at its input terminal IN1. The first-stage shift register unit S1 outputs a scan signal at its output terminal Gout1, which serves as the input signal for the second-stage shift register unit S2. Gout1 is connected to the second-stage shift register unit S2's input terminal IN2. The second-stage shift register unit S2 outputs a scan signal at its output terminal Gout2, which serves as the input signal for the third-stage shift register unit S3. Gout2 is connected to the third-stage shift register unit S3's input terminal IN3. The third-stage shift register unit S3 outputs a scan signal at its output terminal Gout3, which serves as the input signal for the fourth-stage shift register unit S4. Gout3 is connected to the fourth-stage shift register unit S4's input terminal IN4… This process is repeated for subsequent shift register units, forming the scan drive circuit 30.

[0091] In some embodiments, such as Figure 4 As shown, the timing controller 20 includes a first timing control signal line CKV1 and a second timing control signal line CKV2. The first timing control signal line CKV1 is used to output a first timing control signal. The second timing control signal line CKV2 is used to output a second timing control signal. The first and second timing control signals are square wave signals with the same output frequency and a phase difference of 180°.

[0092] In some preferred embodiments, reference continues to be made to Figure 4 Furthermore, the first timing control terminal c1 of the odd-numbered shift register unit is connected to the first timing control signal line CKV1 to receive the first timing control signal, and its second timing control terminal c2 is connected to the second timing control signal line CKV2 to receive the second timing control signal. The first timing control terminal c1 of the even-numbered shift register unit is connected to the second timing control signal line CKV2 to receive the second timing control signal, and its second timing control terminal c2 is connected to the first timing control signal line CKV1 to receive the first timing control signal.

[0093] In some embodiments, the shift register unit is used to delay the signal received from the signal input terminal IN under the control of the first timing control signal and the second timing control signal. The processed signal is output by the signal output terminal Gout, and the signal is output as a scan signal to the display area 11 or input to the signal input terminal IN of the next level shift register unit.

[0094] In some embodiments, reference Figures 5 to 10 , Figure 6 Show Figure 5 The waveform diagram of the shift register unit in operation is shown below; Figure 7 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t1; Figure 8 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t2; Figure 9 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t3; Figure 10 Show Figure 6 A schematic diagram of the conduction state of the shift register unit in stage t4.

[0095] like Figure 5As shown, the shift register unit of this invention includes 13 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Gout, a first timing control terminal c1, and a second timing control terminal c2. Specifically, the first transistor T1 has its first terminal connected to the signal input terminal IN, its second terminal connected to the second node n2, and its gate connected to the second timing control terminal c2. The second transistor T2 has its second terminal connected to the second node n2, and its gate connected to the first node n1. The third transistor T3 has its first terminal connected to the first power supply VDD, its second terminal connected to the first terminal of the second transistor T2, and its gate connected to the first timing control terminal c1. The fourth transistor T4 has its first terminal connected to the second power supply VEE, its second terminal connected to the fourth node n4, and its gate connected to the second timing control terminal c2. The fifth transistor T5 has its first terminal connected to the second timing control terminal c2, its second terminal connected to the first node n1, and its gate connected to the second node n2. The sixth transistor T6 has its first terminal connected to the second node n2, its second terminal connected to the fifth node n5, and its gate connected to the second power supply VEE. The seventh transistor T7 has its first terminal connected to the first power supply VDD, its second terminal connected to the signal output terminal Gout, and its gate connected to the first node n1. The eighth transistor T8 has its first terminal connected to the signal output terminal Gout, its second terminal connected to the first timing control terminal c1, and its gate connected to the fifth node n5. The ninth transistor T9 has its first terminal connected to the fourth node n4, its second terminal connected to the first node n1, and its gate connected to the third node n3. The tenth transistor T10 has its first terminal connected to the first timing control terminal c1, its second terminal connected to the third node n3, and its gate connected to the signal input terminal IN. The eleventh transistor T11 has its first terminal connected to the third node n3, its second terminal connected to the second power supply VEE, and its gate connected to the first timing control terminal c1. The twelfth transistor T12 has its first terminal connected to the first node n1, and its gate connected to the fourth node n4. The thirteenth transistor T13 has its first terminal connected to the second terminal of the twelfth transistor T12, its second terminal connected to the second power supply VEE, and its gate connected to the first timing control terminal c1. The first capacitor C1 has its first terminal connected to the first power supply VDD, and its second terminal connected to the first node n1. The second capacitor C2 has its first terminal connected to the fifth node n5, and its second terminal connected to the signal output terminal Gout. The third capacitor C3 has its first terminal connected to the fourth node n4, and its second terminal connected to the third node n3. The first power supply VDD provides a positive voltage signal, and the second power supply VEE provides a negative voltage signal.

[0096] In this embodiment, the first transistor T1 to the thirteenth transistor T13 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, and its first terminal is the source and its second terminal is the drain, or vice versa. The PMOS transistor's on-state level is low, and its off-state level is high. In other embodiments, those skilled in the art will readily recognize that the shift register unit provided by this invention can be easily modified to consist entirely of N-type MOS transistors. Alternatively, the shift register unit provided by this invention can also be easily modified to use CMOS transistors, etc.

[0097] In this embodiment, refer to Figure 6 , Figure 6 The waveform diagram shown includes four processes: t1, t2, t3, and t4. During these four processes, the output signal of the shift register unit's output terminal Gout completes one cycle from set to reset. It should be noted that, for ease of understanding, a high-level signal is represented by "H" and a low-level signal by "L" in the attached diagram. The following section will further explain... Figure 6 waveform diagram and Figure 5 The circuit diagram is used to analyze the relationship between the input and output of the shift register unit in the above four processes:

[0098] In this embodiment, refer to Figure 6 and 7 During process t1, the signal input terminal IN is low, the first timing control signal line CKV1 is high, and the second timing control signal line CKV2 is low. At this time, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 are turned on, while the third transistor T3, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned off. Specifically, due to the low levels of the signal input terminal IN, the second timing control signal line CKV2, and the second power supply VEE, the first transistor T1, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are turned on. The second node n2 is written with a low level by the signal input terminal IN through the first transistor T1, and the fifth transistor T5 is turned on. The first node n1 is written with a low level by the second timing control signal line CKV2 through the fifth transistor T5, and the seventh transistor T7 is turned on. At the same time, the eighth transistor T8 is turned on through the sixth transistor T6. Finally, the signal output terminal Gout outputs the first power supply VDD and the first timing control signal line CKV1 at a high potential.

[0099] In this embodiment, refer to Figure 6 and 8During process t2, the signal input terminal IN is high, the first timing control signal line CKV1 is low, and the second timing control signal line CKV2 is high. At this time, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the tenth transistor T10, and the twelfth transistor T12 are turned off. Specifically, the eleventh transistor T11 is turned on by the low level of the first timing control signal line CKV1, the ninth transistor T9 is turned on through the eleventh transistor T11, the high level of the second timing control signal line CKV2 refreshes the first node n1 to a high level through the fifth transistor T5, the seventh transistor T7 is turned off, the second node n2 maintains the low potential of the previous moment, and the eighth transistor T8 is turned on. Finally, the signal output terminal Gout outputs the low potential of the second timing control signal line CKV2.

[0100] In this embodiment, refer to Figure 6 and 9 During process t3, the signal input terminal IN is high, the first timing control signal line CKV1 is high, and the second timing control signal line CKV2 is low. At this time, transistors T1, T2, T4, T6, T7, T9, and T12 are turned on, while transistors T3, T5, T8, T10, T11, and T13 are turned off. Specifically, transistors T1 and T4 are turned on by the second timing control signal line CKV2; node n1 is refreshed to a low level by the second power supply VEE through transistors T9 and T4, turning on transistor T7; node n2 is refreshed to a high level by the signal input terminal IN through transistor T1, turning off transistor T5; and simultaneously, transistor T8 is also turned off through transistor T6. Finally, the signal output terminal Gout outputs a high potential of the first power supply VDD through transistor T7.

[0101] In this embodiment, refer to Figure 6 and 10During process t4, the signal input terminal IN is at a high level, the first timing control signal line CKV1 is at a low level, and the second timing control signal line CKV2 is at a high level. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are turned off. Specifically, transistors T3, T11, and T13 are turned on by the first timing control signal line CKV1; transistors T1 and T4 are turned off by the second timing control signal line CKV2; transistors T9 and T12 maintain their on state from the previous moment through capacitor C3; node n1 is continuously written to a low level by the second power supply VEE through transistors T12 and T13; transistors T2 and T7 are turned on; node n2 is continuously written to a high potential by the first power supply VDD through transistors T3 and T2; and transistor T8 is turned off. Finally, the final signal output terminal Gout outputs the high potential of the first power supply VDD through transistor T7.

[0102] The shift register unit repeats the process from t3 to t4 after t4 until the next frame of the picture begins to be displayed. At this time, the start pulse signal STV or the signal input terminal IN is input with a low potential, and the next round of t1 process is restarted.

[0103] In this embodiment, the relationship between the input and output of the shift register unit is as follows: If the start pulse signal STV or the signal input terminal IN is low during a certain process, then under the action of the first timing control signal line CKV1 and the second timing control signal line CKV2, the signal output terminal Gout will also output a low level in the next process. In other processes, the start pulse signal STV or the signal input terminal IN and the signal output terminal Gout remain high until the start pulse signal STV or the signal input terminal IN is low again, at which point the signal output terminal Gout will output a low level again. This is equivalent to the shift register unit delaying the low-level signal from the start pulse signal STV or the signal input terminal IN before outputting it from the signal output terminal Gout.

[0104] In this embodiment, the 13T3C circuit of the shift register unit adds a thirteenth transistor T13 and changes some wiring settings, which solves the mutual restraint between the fifth transistor T5 and the sixth transistor T6, ensuring the correctness of the output waveform, making the scanning circuit more stable, avoiding display abnormalities caused by transistor aspect ratio fluctuations due to threshold voltage deviation or manufacturing process errors, and improving the service life of the display panel; it also ensures the electrical floating problem of the second node n2, improving the reliability of the display panel.

[0105] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel 10 described above in the embodiments of the present invention. This display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementation of this display device can refer to the embodiments of the display panel 10 described above; repeated details will not be repeated.

[0106] The scanning drive circuit and display panel of the present invention provide a new 13T3C shift register unit to solve the mutual interference between transistors, making the scanning circuit more stable, avoiding display abnormalities caused by transistor aspect ratio fluctuations due to threshold voltage deviation or manufacturing process errors, and improving the service life of the display panel; in addition, the shift register unit solves the problem of electrical floating of nodes in the circuit, improving the reliability of the display panel.

[0107] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A scanning drive circuit, characterized in that, Includes a multi-stage shift register unit, wherein the shift register unit includes: The first transistor has a first terminal connected to the signal input terminal, a second terminal connected to the second node, and a gate connected to the second timing control terminal. The second transistor has its second terminal connected to the second node and its gate connected to the first node; The third transistor has its first terminal connected to the first power supply, its second terminal connected to the first terminal of the second transistor, and its gate connected to the first timing control terminal. The fourth transistor has its first terminal connected to the second power supply, its second terminal connected to the fourth node, and its gate connected to the second timing control terminal. The fifth transistor has its first terminal connected to the second timing control terminal, its second terminal connected to the first node, and its gate connected to the second node; The sixth transistor has its first terminal connected to the second node, its second terminal connected to the fifth node, and its gate connected to the second power supply. The seventh transistor has its first terminal connected to the first power supply, its second terminal connected to the signal output terminal, and its gate connected to the first node; The eighth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the first timing control terminal, and its gate connected to the fifth node. A ninth transistor, wherein the first terminal of the ninth transistor is connected to the fourth node, the second terminal is connected to the first node, and the gate is connected to the third node; The tenth transistor has its first terminal connected to the first timing control terminal, its second terminal connected to the third node, and its gate connected to the signal input terminal. The eleventh transistor has its first terminal connected to the third node, its second terminal connected to the second power supply, and its gate connected to the first timing control terminal. The twelfth transistor has its first terminal connected to the first node and its gate connected to the fourth node; The thirteenth transistor has its first terminal connected to the second terminal of the twelfth transistor, the second terminal connected to the second power supply, and its gate connected to the first timing control terminal. A first capacitor, wherein the first terminal of the first capacitor is connected to the first power source, and the second terminal is connected to the first node; The second capacitor has its first terminal connected to the fifth node and its second terminal connected to the signal output terminal. The third capacitor has its first terminal connected to the fourth node and its second terminal connected to the third node.

2. The scanning drive circuit according to claim 1, characterized in that, It also includes a timing controller, which includes a first timing control signal line and a second timing control signal line.

3. The scanning drive circuit according to claim 2, characterized in that, The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

4. The scanning drive circuit according to claim 3, characterized in that, The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

5. The scanning drive circuit according to claim 3, characterized in that, The shift register unit is used to perform delay processing on the signal received from the signal input terminal under the control of the first timing control signal and the second timing control signal, and the processed signal is output by the signal output terminal.

6. The scanning drive circuit according to claim 2, characterized in that, The shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

7. The scanning drive circuit according to claim 6, characterized in that, In the odd-level shift register unit, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

8. The scanning drive circuit according to claim 7, characterized in that, In the even-numbered shift register unit, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

9. The scanning drive circuit according to claim 1, characterized in that, The first transistor to the thirteenth transistor are all P-type MOS transistors.

10. A display panel, characterized in that, Includes the scanning drive circuit according to any one of claims 1 to 9.

Images