Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate, the substrate is provided with a stack layer comprising alternately stacked sacrificial layers and channel layers, and a BDI structure is further formed in the substrate on both sides of the stack layer; laterally etching the sacrificial layers and filling to form first spacers; laterally etching part of the first spacers to form second grooves; forming an epitaxial layer on the channel layers; etching and removing the remaining first spacers to form third grooves; forming second spacers with air gaps in the third grooves; and forming source / drain electrodes. Due to the existence of the epitaxial layer, the base area of the epitaxial growth of the source / drain electrodes is larger than that without the epitaxial layer, and the epitaxial growth can be performed in all directions at the initial stage, and the epitaxial layers grown from each independent growth base can be fused earlier, thereby improving the fusion of the epitaxial growth of the source / drain electrodes in the presence of the BDI structure, and improving the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of integrated circuit manufacturing process technology nodes, higher requirements have been placed on the gate control capability, size and power consumption of transistors. Compared with FinFET (Fin Field-Effect Transistor), GAA (Gate All Around) can achieve better transistor performance by wrapping the channel (multiple nanosheets / nanowires) on all four sides by the gate.

[0003] Introducing bottom dielectric isolation (BDI) structures into GAA devices can effectively reduce the capacitance in the devices and improve device performance. Figure 1 This is a schematic diagram of the structure of a semiconductor device, such as... Figure 1 As shown, a plurality of stacked layers 20 and a dummy gate 30 are formed on the substrate 10. The stacked layers 20 include alternating sacrificial layers 21 and channel layers 22. BDI structures 11 are also formed on the substrate on both sides of the bottom sacrificial layer 21 of the stacked layers 20. Spacers 23 are formed on both sides of the remaining sacrificial layers 21 of the stacked layers 20, and the outer edges of the spacers 23 are aligned with the outer edges of the channel layers 22. Protective layers 31 are also formed on both sides of the dummy gate 30, and the outer edges of the protective layers 31 are aligned with the outer edges of the channel layers 22. An insulating layer 32 is also formed between the dummy gate 31 and the stacked layers 20. Active / drain electrodes 40 are also formed on the BDI structures on both sides of the stacked layers 20.

[0004] However, the presence of the BDI structure 11 prevents the bottom of the source / drain 40 from serving as an epitaxial growth surface, potentially leading to difficulties in merging the epitaxial growth of the source / drain 40. Figure 1 As shown, this ultimately leads to a decrease in device performance. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problem of difficult fusion of source / drain epitaxial growth due to the presence of BDI structure, thereby improving device performance.

[0006] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0007] A substrate is provided, on which a plurality of stacked layers and a dummy gate are formed, wherein the stacked layers include alternately stacked sacrificial layers and channel layers, and BDI structures are further formed in the substrate on both sides of the bottom sacrificial layer of the stacked layers.

[0008] Laterally etch away a portion of the sacrificial layer at the edge to form a first groove on both sides of the remaining sacrificial layer;

[0009] A first insulating material is deposited to fill the first groove to form a first spacer;

[0010] Laterally etch away a portion of the first spacer at the edge to form a second groove on both sides of the sacrificial layer, the second groove exposing a portion of the top and a portion of the bottom of the channel layer;

[0011] An epitaxial layer is formed on the sidewalls of the channel layer and on the exposed top and bottom surfaces;

[0012] The remaining first spacer is etched away to form a third groove on both sides of the sacrificial layer, the cross-sectional width of the top of the third groove being smaller than the cross-sectional width of the bottom of the third groove;

[0013] A second insulating material is deposited within the third groove, forming second spacers with air gaps on both sides of the sacrificial layer; and

[0014] The source / drain electrodes are formed on both sides of the stacked structure.

[0015] Optionally, the step of depositing the first insulating material to fill the first groove to form the first spacer includes:

[0016] Deposit a first insulating material, the first insulating material filling the first groove and forming first sidewalls on both sides of the stacked layer; and

[0017] The first sidewall on the substrate is selectively etched away, leaving the first sidewall within the first groove to form the first spacer.

[0018] Optionally, the first insulating material comprises silicon nitride, and the first insulating material is deposited using atomic layer deposition.

[0019] Optionally, the sacrificial layer is made of silicon-germanium, and the channel layer is made of silicon.

[0020] Optionally, an epitaxial layer is formed on the sidewalls of the channel layer and on the exposed top and bottom using selective epitaxy; the material of the epitaxial layer comprises silicon.

[0021] Optionally, the method of depositing a second insulating material within the third groove to form a second spacer with air gaps on both sides of the sacrificial layer includes:

[0022] Deposit a second insulating material, the second insulating material filling the third groove and forming second sidewalls on both sides of the stacked layer; and

[0023] The second sidewall on the substrate is selectively etched away, leaving the second sidewall within the third groove to form a second spacer.

[0024] Optionally, the second insulating material comprises silicon nitride, and the second insulating material is deposited using atomic layer deposition.

[0025] Optionally, the source / drain electrodes may be formed using selective epitaxy.

[0026] Optionally, a protective layer is formed on both sides of the dummy gate, and an insulating layer is formed between the dummy gate and the stacked layer.

[0027] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0028] In the semiconductor device and its fabrication method provided by the present invention, due to the presence of the epitaxial layer, the substrate area of ​​the source / drain epitaxial growth is larger than that without the epitaxial layer, and growth can proceed in all directions in the early stage of epitaxial growth. The epitaxial layers grown from each independent growth substrate can fuse earlier, thereby improving the situation where the source / drain epitaxial growth is difficult to fuse in the presence of the BDI structure, reducing the increase in resistance caused by poor fusion, and improving the performance of the device.

[0029] Meanwhile, since an air gap is also formed within the second spacer, and since air has a dielectric constant of 1 and is a good dielectric, the air gap formed within the second spacer can effectively reduce the capacitance introduced by the second spacer, further improving device performance. Attached Figure Description

[0030] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0031] Figure 1 This is a schematic diagram of the structure of a semiconductor device.

[0032] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0033] Figures 3 to 12This is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0034] Figure label:

[0035] Figure 1 middle,

[0036] 10-Substrate; 11-BDI structure; 20-Stacked layer; 21-Sacrificial layer; 22-Channel layer; 23-Spacer; 30-Dummy gate; 31-Protective layer; 32-Insulating layer; 40-Source / drain.

[0037] Figures 3 to 12 middle,

[0038] 100 - Substrate; 110 - BDI structure; 120 - Stacked layer; 121 - Sacrificial layer; 122 - Channel layer; 123 - First trench; 124′ - First sidewall; 124 - First spacer; 125 - Second trench; 126 - Epitaxial layer; 127 - Third trench; 128′ - Second sidewall; 128 - Second spacer; 129 - Air gap; 130 - Dummy gate; 131 - Protective layer; 132 - Insulating layer; 140 - Source / drain. Detailed Implementation

[0039] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0040] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0041] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0042] like Figure 2As shown, the method for fabricating the semiconductor device includes the following steps:

[0043] S1: A substrate is provided, on which a plurality of stacked layers and a dummy gate are formed, wherein the stacked layers include alternately stacked sacrificial layers and channel layers, and BDI structures are also formed in the substrate on both sides of the bottom sacrificial layer of the stacked layers.

[0044] S2: Laterally etch away a portion of the sacrificial layer at the edge to form a first groove on both sides of the remaining sacrificial layer;

[0045] S3: Deposit the first insulating material to fill the first groove to form a first spacer;

[0046] S4: Laterally etch away a portion of the first spacer at the edge to form a second groove on both sides of the sacrificial layer, the second groove exposing a portion of the top and a portion of the bottom of the channel layer;

[0047] S5: An epitaxial layer is formed on the sidewalls of the channel layer and on the exposed top and bottom;

[0048] S6: Etch away the remaining first spacer to form a third groove on both sides of the sacrificial layer, wherein the cross-sectional width of the top of the third groove is smaller than the cross-sectional width of the middle of the third groove;

[0049] S7: Deposit a second insulating material in the third groove to form a second spacer with air gaps on both sides of the sacrificial layer;

[0050] S8: Form source / drain electrodes on both sides of the stacked structure.

[0051] Figures 3 to 12 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of the present invention. Next, we will combine... Figure 2 and Figures 3 to 12 A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.

[0052] In step S1, please refer to Figure 3 As shown, a substrate 100 is provided, on which a plurality of stacked layers 120 and a dummy gate 130 are formed. The stacked layers 120 include alternately stacked sacrificial layers 121 and channel layers 122. BDI structures 110 are also formed in the substrate 100 on both sides of the bottom sacrificial layer 121 in the stacked layers 120.

[0053] The substrate 100 can be made of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 100 is preferably made of silicon.

[0054] A plurality of stacked layers 120 are formed on the substrate 100. Figure 3 Only two of the stacked layers 120 are shown in this embodiment; however, there may be three or more stacked layers 120 in other embodiments, which is not a limitation of the present invention. Adjacent stacked layers 120 are spaced apart for subsequent source / drain formation. The stacked layers 120 include alternating layers of sacrificial layers 121 and channel layers 122. Figure 3 The diagram shows three layers of the sacrificial layer 121 and three layers of the channel layer 122. In other embodiments, other numbers of layers may be used, such as four layers of the sacrificial layer 121 and four layers of the channel layer 122. The present invention is not limited to this. The number of stacked layers 120 and the number of layers can be determined according to actual needs and process conditions. In this embodiment, preferably, the sacrificial layer 121 is made of silicon germanium (SiGe), and the channel layer 122 is made of silicon (Si).

[0055] BDI structures 110 are also formed within the substrate 100 on both sides of the sacrificial layer 121 at the bottom of the stacked layer 120. The BDI structure 110 can effectively reduce the capacitance in subsequently formed semiconductor devices, thereby improving device performance. The material of the BDI structure 110 can be silicon oxide, silicon nitride, silicon oxycarbide (SiOC), or silicon carbonitride (SiOCN), etc. The BDI structure 110 is located within the substrate 100, and its upper surface is higher than the upper surface of the substrate 100, or the upper surface of the BDI structure 110 is flush with the upper surface of the sacrificial layer 121 at the bottom.

[0056] A dummy gate 130 is also formed on the stacked layer 120, and a protective layer 131 is formed on both sides of the dummy gate 130, with the outer edge of the protective layer 131 aligned with the outer edge of the stacked layer 120. An insulating layer 132 is also formed between the dummy gate 130 and the stacked layer 120.

[0057] Figure 3 The semiconductor structure shown can be fabricated using methods known to those skilled in the art, which will not be described in detail in this embodiment.

[0058] In step S2, please refer to Figure 4 As shown, a portion of the sacrificial layer 121 at the edge is etched laterally to form a first groove 123 on both sides of the remaining sacrificial layer 121.

[0059] Specifically, during the etching process, taking advantage of the fact that the etching rate of silicon-germanium is much higher than that of silicon, the sacrificial layer 121 is selectively etched to leave the channel layer 122, and the two sides of the sacrificial layer 121 are removed inward to form the first groove 123. The first groove 132 is located between two adjacent channel layers 122.

[0060] In this embodiment, a portion of the sacrificial layer 121 can be removed using wet etching. The wet etching solution has a high etching rate for the sacrificial layer 121 and a low etching rate for the channel layer 122. Here, "high etching rate" and "low etching rate" are relative terms. This allows the sacrificial layer 121 to be etched away to form the first groove 123, while the channel layer 122 is not etched or is only slightly etched. The etching solution may include hydrogen peroxide (H2O2), hydrochloric acid (HCl), citric acid (C6H8O7), or ammonium hydroxide (NH4OH), or other etching solutions known to those skilled in the art.

[0061] In another embodiment of the present invention, dry etching can also be used to remove part of the sacrificial layer 121. For example, reactive ion etching (RIE) can be used to remove part of the sacrificial layer 121, where the etching gas has a high etching rate on the sacrificial layer 121 and a low etching rate on the channel layer 122. The etching gas may contain hydrogen chloride (HCl), silicon chloride (SiCl4), sulfur hexafluoride (SF6), boron trifluoride (BCl3), or chlorine (Cl2), but is not limited thereto, and may also be other etching gases known to those skilled in the art.

[0062] In step S3, please refer to Figure 6 As shown, a first insulating material is deposited to fill the first groove 123 to form a first spacer 124.

[0063] Specifically, firstly, refer to Figure 5 As shown, a first insulating material is deposited, which fills the first groove 123 and forms first sidewalls 124' on both sides of the stacked layer 120.

[0064] The first insulating material can be an oxide or a nitride, such as silicon oxide or silicon nitride. In this embodiment, the first insulating material is preferably silicon nitride. The first insulating material can be fabricated by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof, or other known methods can be used to form the insulating material. In this embodiment, preferably, the first insulating material is deposited using atomic layer deposition.

[0065] In this embodiment, the first isolation material is deposited on both sides of the stacked layer 120 and the dummy gate 130 using atomic layer deposition to form a first sidewall 124'. Part of the first sidewall 124' fills the first groove 123, and the other part covers the two sidewalls of the stacked layer 120 and the dummy gate 130.

[0066] Next, please refer to Figure 6 As shown, the first sidewall 124' on the substrate 100 is selectively etched away, leaving the first insulating material in the first groove to form the first spacer 124.

[0067] Only longitudinal etching (perpendicular to the substrate 100) is performed to remove a portion of the first sidewall 124', that is, to remove the first sidewall 124' on the substrate 100, while retaining the first insulating material in the first groove in the lateral direction, thereby forming the first spacer 124.

[0068] In step S4, please refer to Figure 7 As shown, a portion of the first spacer 124 at the edge is etched laterally to form a second groove 125 on both sides of the sacrificial layer 121, the second groove 125 exposing a portion of the top and a portion of the bottom of the channel layer 122.

[0069] Selective etching is used to etch the first spacer 124 laterally, that is, to etch the first spacer 124 laterally, removing a portion of the first spacer 124. This means that a portion of the first spacer 124 remains on both sides of the sacrificial layer 121, and the second groove 125 is formed on both sides of the remaining first spacer 124. In the extending direction of the sacrificial layer 121 (i.e.... Figure 7 (In the horizontal direction), the depth of the second groove 125 is less than the depth of the first groove.

[0070] By etching a portion of the first spacer 124, a portion of the bottom and a portion of the top of the channel layer 122 are exposed. The bottom and top are relative terms. In this embodiment, the side closer to the substrate 100 is the bottom, and the side farther from the substrate 100 is the top.

[0071] In step S5, as Figure 8 As shown, an epitaxial layer 126 is formed on the sidewalls of the channel layer 122 and on the exposed top and bottom.

[0072] In this embodiment, the channel layer 122 is preferably made of silicon, and an epitaxial layer 126 is formed on the sidewalls and exposed top and bottom of the channel layer 122 using selective epitaxy; the epitaxial layer 126 is preferably made of silicon. Protrusions are formed on both sides of the channel layer 122 using epitaxy.

[0073] In step S6, as Figure 9 As shown, the remaining first spacer 124 is etched away to form a third groove 127 on both sides of the sacrificial layer 121, wherein the cross-sectional width of the top of the third groove 127 is smaller than the cross-sectional width of the middle of the third groove 127.

[0074] In this embodiment, an acid pickling process is used to remove the remaining first spacer 124, forming a third groove 127 on both sides of the sacrificial layer 121. Because protrusions are formed extending outwards on both sides of the channel layer 122, and... Figure 4 Compared to the first groove 123, the third groove 127 has an increased depth, and due to the presence of the protrusion (i.e., the epitaxial layer 126), the cross-sectional width of the top (i.e., the opening) of the third groove 127 is smaller than the cross-sectional width of the middle of the third groove 127, and also smaller than the cross-sectional width of the bottom of the third groove 127. That is, the cross-sectional width of the top (i.e., the opening) of the third groove 127 is the smallest. This forms a structure similar to a pocket (small opening, large interior). It should be noted that the top, middle, and bottom mentioned here are relative to the third groove 127, and are in the extending direction of the third groove 124 (i.e.,... Figure 9 In the horizontal direction, the top is the opening of the third groove 127, the bottom is the position near the channel layer 122, and the middle is the position between the opening and the bottom.

[0075] In step S7, as Figure 11 As shown, a second insulating material is deposited in the third groove 127, forming a second spacer 128 with an air gap 129 on both sides of the sacrificial layer 121.

[0076] Specifically, firstly, refer to Figure 10As shown, a second insulating material is deposited, which fills the third groove 127 and forms second sidewalls 128' on both sides of the stacked layer 120. Due to the presence of the third groove 127, which resembles a pocket structure, the second insulating material cannot completely fill the third groove 127, thus forming an air gap 129 within the third groove 127.

[0077] The second insulating material can be an oxide or a nitride, such as silicon oxide or silicon nitride. In this embodiment, the second insulating material is preferably silicon nitride. The second insulating material can be fabricated by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof, or other known methods can be used to form the insulating material. In this embodiment, preferably, the second insulating material is deposited using atomic layer deposition.

[0078] In this embodiment, the second isolation material is deposited on both sides of the stacked layer 120 and the dummy gate 130 using atomic layer deposition to form a second sidewall 128'. A portion of the second sidewall 128' fills the third groove 127, and the other portion covers both sidewalls of the stacked layer 120 and the dummy gate 130.

[0079] Next, please refer to Figure 11 As shown, the second sidewall 128' on the substrate 100 is selectively etched away, leaving the second insulating material in the third groove to form the second spacer 128.

[0080] Only longitudinal etching (perpendicular to the substrate 100) is performed to remove part of the second sidewall 128', that is, to remove the second sidewall 128' on the substrate 100, while retaining the second isolation material in the third groove in the lateral direction, thereby forming the second spacer 128, and an air gap 129 is also formed in the second spacer 128.

[0081] In step S8, as Figure 12 As shown, source / drain electrodes 140 are formed on both sides of the stacked structure 120.

[0082] In this embodiment, selective epitaxy is used to form the source / drain 140. The epitaxial layer 126 can be used as a growth substrate for epitaxial growth to form the source / drain 140. Due to the presence of the epitaxial layer 126 (i.e., the protrusions on both sides of the channel layer 122), the growth substrate area for the epitaxial growth of the source / drain 140 is larger than that without the epitaxial layer 126. Furthermore, the epitaxial layer 126 can grow in all directions during the initial stage of epitaxial growth. The epitaxial layers grown from each independent growth substrate (i.e., the epitaxial layer 126) can fuse earlier to form the source / drain 140, thereby improving the situation where the source / drain epitaxy is difficult to fuse in the presence of the BDI structure, reducing the increase in resistance caused by poor fusion, and thus improving the performance of the device.

[0083] Meanwhile, since an air gap 129 is also formed within the second spacer 128, and since air has a dielectric constant of 1 and is a good dielectric, the air gap 129 formed within the second spacer 128 can effectively reduce the capacitance caused by the second spacer 128, further improving the device performance.

[0084] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0085] In summary, in the semiconductor device and its fabrication method provided by this invention, due to the presence of the epitaxial layer, the substrate area for source / drain epitaxial growth is larger than that without the epitaxial layer, and growth can proceed in all directions from the initial stage of epitaxial growth. The epitaxial layers grown from each independently grown substrate can fuse earlier, thereby improving the situation where source / drain epitaxial growth is difficult to fuse in the presence of the BDI structure, reducing the increase in resistance caused by poor fusion, and improving the performance of the device.

[0086] Meanwhile, since an air gap is also formed within the second spacer, and since air has a dielectric constant of 1 and is a good dielectric, the air gap formed within the second spacer can effectively reduce the capacitance introduced by the second spacer, further improving device performance.

[0087] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, on which a plurality of stacked layers and a dummy gate are formed, wherein the stacked layers include alternately stacked sacrificial layers and channel layers, and BDI structures are further formed in the substrate on both sides of the bottom sacrificial layer of the stacked layers. Laterally etch away a portion of the sacrificial layer at the edge to form a first groove on both sides of the remaining sacrificial layer; A first insulating material is deposited to fill the first groove to form a first spacer; Laterally etch away a portion of the first spacer at the edge to form a second groove on both sides of the sacrificial layer, the second groove exposing a portion of the top and a portion of the bottom of the channel layer; An epitaxial layer is formed on the sidewalls of the channel layer and on the exposed top and bottom surfaces; The remaining first spacer is etched away to form a third groove on both sides of the sacrificial layer, wherein the cross-sectional width at the top of the third groove is smaller than the cross-sectional width in the middle of the third groove; A second insulating material is deposited within the third groove, forming second spacers with air gaps on both sides of the sacrificial layer; and Source / drain electrodes are formed on both sides of the stacked layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of depositing a first spacer material to fill the first groove to form a first spacer includes: Deposit a first insulating material, the first insulating material filling the first groove and forming first sidewalls on both sides of the stacked layer; and The first sidewall on the substrate is selectively etched away, leaving the first sidewall within the first groove to form the first spacer.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The first insulating material comprises silicon nitride and is deposited using atomic layer deposition.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The sacrificial layer is made of silicon-germanium, and the channel layer is made of silicon.

5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, An epitaxial layer is formed on the sidewalls of the channel layer and on the exposed top and bottom using selective epitaxy; the material of the epitaxial layer comprises silicon.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The method of depositing a second insulating material within the third groove to form a second spacer with air gaps on both sides of the sacrificial layer includes: Deposit a second insulating material, the second insulating material filling the third groove and forming second sidewalls on both sides of the stacked layer; and The second sidewall on the substrate is selectively etched away, leaving the second sidewall within the third groove to form a second spacer.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The second insulating material comprises silicon nitride and is deposited using atomic layer deposition.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The source / drain electrodes are formed using selective epitaxy.

9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, A protective layer is formed on both sides of the dummy gate, and an insulating layer is formed between the dummy gate and the stacked layer.

10. A semiconductor device, characterized in that, It is manufactured using the method for manufacturing a semiconductor device as described in any one of claims 1 to 9.

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