Key generation method and device, electronic equipment and storage medium

Abstract

The present disclosure relates to a key generation method and device, electronic equipment and storage medium, the method comprising: obtaining a to-be-processed matrix and an initialization parameter; performing elimination processing on the rth row according to the rth row to the nth row of the to-be-processed matrix of the r-1th processing state and the initialization parameter, to obtain an eliminated rth row; determining whether the rth elimination is successful according to the eliminated rth row; if the rth elimination is successful, performing elimination on the r+1th row to the nth row according to the rth row and the initialization parameter, to obtain the to-be-processed matrix of the rth processing state; determining the to-be-processed matrix of the nth processing state as a target matrix; and generating a key according to the target matrix. The key generation method according to the embodiments of the present disclosure can eliminate the rth row based on the initialization parameter, and eliminate other rows in the case of successful elimination, which can reduce the time complexity, make the running time constant, and improve the operation efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular, to a key generation method, an apparatus, an electronic device, and a storage medium. Background Art

[0002] With the rapid development of quantum computing technology, the security of public-key cryptosystems such as RSA that have been widely deployed is now threatened. Therefore, research on cryptographic algorithms that can resist quantum computing attacks has received extensive attention. Among the many algorithm designs with potential quantum resistance, cryptographic algorithms based on coding hard problems are a competitive class of algorithms. In 2020, the National Institute of Standards and Technology (NIST) in the United States announced 7 algorithms that entered the finals of the post-quantum cryptography standard, and the ClassicMcEliece algorithm is constructed based on coding hard problems.

[0003] Key generation is an important part of the Classic McEliece algorithm. A main step of it is to perform Gaussian elimination on a matrix. However, this Gaussian elimination needs to ensure that the running time is constant to prevent key leakage caused by side-channel attacks, that is, it is necessary to ensure that the running time of each step of Gaussian elimination does not change with the change of the input. Specifically, the input of the Gaussian elimination algorithm is an n×m matrix G0, and the elements of the matrix G0 are logical values 0 or 1. Here, m and n are positive integers, and n < m. The output of the Gaussian elimination algorithm is a matrix G1, which satisfies that its left side is an n×n identity matrix I, that is, G1 = [I|G2], and there exists an invertible matrix Q such that G1 = QG0.

[0004] In the related art, in addition to correctness and ensuring constant time, the time complexity of the Gaussian elimination algorithm needs to be considered to measure the advantages and disadvantages of the Gaussian elimination algorithm, that is, the time consumed for one complete Gaussian elimination process. For the Gaussian elimination method in the related art (such as in the Classic McEliece algorithm), its time complexity is relatively high. For a specific number of rows r, for the key logical operation of making the element in the r-th row and r-th column equal to 1 after judgment, its complexity is O(mn), that is, square order. Therefore, it increases the running time required for cryptographic algorithms that can resist quantum computing attacks and reduces the running efficiency. Summary of the Invention

[0005] The present disclosure provides a key generation method, an apparatus, an electronic device, and a storage medium.

[0006] According to one aspect of this disclosure, a key generation method is provided, comprising: obtaining a matrix to be processed in an initial state and initialization parameters, wherein the matrix to be processed is an n-row m-column matrix, the elements of the matrix to be processed are 0 or 1, n and m are both positive integers, and m > n; performing elimination processing on the r-th row elements of the matrix to be processed in the (r-1)th processing state based on the elements of the r-th to n-th rows of the matrix to be processed and the initialization parameters, to obtain the r-th row elements after elimination processing, where r is a positive integer less than or equal to n, and the 0th element is the first element. The matrix to be processed in the processing state is the matrix to be processed in the initial state; based on the element of the r-th row after the elimination process, it is determined whether the r-th elimination was successful; if the r-th elimination was successful, based on the element of the r-th row after the elimination process and the initialization parameters, the elements of the (r+1)-n rows of the matrix to be processed in the (r-1)-th processing state are eliminated to obtain the matrix to be processed in the r-th processing state; the matrix to be processed in the n-th processing state is determined as the target matrix; based on the target matrix, a key for encrypting the target file is generated.

[0007] In one possible implementation, based on the elements of rows r to n of the matrix to be processed in the (r-1)th processing state and the initialization parameters, the elements of row r of the matrix to be processed in the (r-1)th processing state are eliminated to obtain the eliminated elements of row r. This includes: setting the initialization parameters based on the elements of a preset column of row r and the elements of a preset column of row k to obtain a first setting parameter corresponding to row k, where r+1≤k≤n and k is an integer; and eliminating the elements of row r based on the first setting parameter corresponding to row k to obtain the eliminated elements of row r.

[0008] In one possible implementation, the initialization parameters include a first parameter, a second parameter, a third parameter, and a fourth parameter; the first setting parameter includes the set first parameter, the set second parameter, the set third parameter, and the set fourth parameter. The initialization parameters are set according to the elements of the preset columns in the r-th row and the k-th row to obtain the first setting parameter, which includes: setting the first parameter according to the elements of the r-th row and the r-th column, and the k-th row and the r-th column to obtain the set first parameter; and performing a logical OR operation between the set first parameter and the second parameter. The operation is performed to obtain the second parameter after setting, which is used to record the first parameter after setting; the first parameter after setting is performed with the element of the k-th row to obtain the third parameter after setting, which is used to determine the number of rows used in the elimination process of the element of the r-th row based on the first parameter after setting; the fourth parameter after setting is obtained based on the preset running time parameter and the maximum value of the third parameter after setting and the fourth parameter, which is used to represent the number of rows used in the elimination process of the element of the r-th row.

[0009] In one possible implementation, the first parameter is set based on the element in row r and column r and the element in row k and column r to obtain the set first parameter, including: performing a logical XOR operation on the element in row r and column r and the element in row k and column r to obtain the fifth parameter; and inverting the fifth parameter bit by bit and then adding 1 to obtain the set first parameter.

[0010] In one possible implementation, the elements of the r-th row are eliminated according to the first setting parameter corresponding to the k-th row to obtain the eliminated r-th row element, including: when the second setting parameter is true, summing each element in the fourth setting parameter with the corresponding element in the r-th row to obtain the elimination result corresponding to the k-th row; and determining the elimination result corresponding to the n-th row as the eliminated r-th row element.

[0011] In one possible implementation, determining whether the r-th elimination was successful based on the element in the r-th row after the elimination process includes: if the element in the r-th row and r-th column is 1, then the r-th elimination was successful.

[0012] In one possible implementation, based on the elements of the r-th row after elimination processing and the initialization parameters, the elements of the (r+1)-n rows of the matrix to be processed in the (r-1)-th processing state are eliminated to obtain the matrix to be processed in the r-th processing state. This includes: setting the initialization parameters based on the elements of a preset column of the elements of the r-th row after elimination processing and the elements of a preset column of the i-th row to obtain a second setting parameter corresponding to the i-th row, where r+1≤i≤n and i is an integer; performing a logical AND operation between each element of the r-th row after elimination processing and the second setting parameter to obtain the operation result corresponding to each element; summing the operation result corresponding to each element with the corresponding element in the i-th row to obtain the matrix after elimination processing of the elements of the i-th row; and determining the matrix after elimination processing of the elements of the n-th row as the matrix to be processed in the r-th processing state.

[0013] In one possible implementation, the execution time for the elimination process performed on the r-th row element of the matrix to be processed in the (r-1)-th processing state, and the elimination process performed on the r-th to n-th rows element of the matrix to be processed in the (r-1)-th processing state, is a fixed duration.

[0014] According to one aspect of this disclosure, a key generation apparatus is provided, comprising: an acquisition module, configured to acquire a matrix to be processed in an initial state and initialization parameters, wherein the matrix to be processed is an n-row m-column matrix, the elements of the matrix to be processed are 0 or 1, n and m are both positive integers, and m > n; and a first elimination module, configured to perform elimination processing on the r-th row elements of the matrix to be processed in the (r-1)-th processing state based on the elements of the r-th to n-th rows of the matrix to be processed in the (r-1)-th processing state and the initialization parameters, to obtain the r-th row elements after elimination processing, where r is a positive integer less than or equal to n, and the matrix to be processed in the 0th processing state. The initial state is the matrix to be processed; the judgment module is used to determine whether the r-th elimination is successful based on the r-th row element after the elimination process; the second elimination module, if the r-th elimination is successful, performs elimination processing on the elements of the (r+1)-n rows of the matrix to be processed in the (r-1)-th processing state based on the r-th row element after the elimination process and the initialization parameters to obtain the matrix to be processed in the r-th processing state; the target matrix acquisition module is used to determine the matrix to be processed in the n-th processing state as the target matrix; the encryption module 16 is used to generate a key for encrypting the target file based on the target matrix.

[0015] In one possible implementation, the first elimination module is further configured to: set the initialization parameters according to the elements of the preset column of the r-th row and the elements of the preset column of the k-th row to obtain a first setting parameter corresponding to the k-th row, where r+1≤k≤n and k is an integer; and perform elimination processing on the elements of the r-th row according to the first setting parameter corresponding to the k-th row to obtain the eliminated elements of the r-th row.

[0016] In one possible implementation, the initialization parameters include a first parameter, a second parameter, a third parameter, and a fourth parameter; the first setting parameter includes a set first parameter, a set second parameter, a set third parameter, and a set fourth parameter, and the first elimination module is further configured to: set the first parameter based on the element in the r-th row and r-th column, and the element in the k-th row and r-th column, to obtain the set first parameter; perform a logical OR operation on the set first parameter and the second parameter to obtain the set second parameter, which is used to record the set first parameter; perform a logical AND operation on the set first parameter and the element in the k-th row to obtain the set third parameter, which is used to determine the number of rows used in the elimination process of the elements in the r-th row based on the set first parameter; and obtain the set fourth parameter based on a preset running time parameter and the maximum value of the set third parameter and the fourth parameter, which represents the number of rows used in the elimination process of the elements in the r-th row.

[0017] In one possible implementation, the first elimination module is further configured to: perform a logical XOR operation on the element in the r-th row and r-th column and the element in the k-th row and r-th column to obtain the fifth parameter; and invert the fifth parameter bit by bit and add 1 to obtain the first parameter after setting.

[0018] In one possible implementation, the first elimination module is further configured to: when the second parameter after the setting is true, sum each element in the fourth parameter after the setting with the corresponding element in the r-th row to obtain the elimination result corresponding to the k-th row; and determine the elimination result corresponding to the n-th row as the element of the r-th row after the elimination.

[0019] In one possible implementation, the judgment module is further configured to: determine that the r-th elimination was successful if the element in the r-th row and r-th column is 1.

[0020] In one possible implementation, the second elimination module is further configured to: set the initialization parameters based on the elements of the preset columns of the r-th row after elimination processing and the elements of the preset columns of the i-th row, to obtain a second setting parameter corresponding to the i-th row, where r+1≤i≤n and i is an integer; perform a logical AND operation between each element of the r-th row after elimination processing and the second setting parameter to obtain the operation result corresponding to each element; sum the operation result corresponding to each element with the corresponding element in the i-th row to obtain the matrix after elimination processing of the elements in the i-th row; and determine the matrix after elimination processing of the elements in the n-th row as the matrix to be processed in the r-th processing state.

[0021] In one possible implementation, the execution time for the elimination process performed on the r-th row element of the matrix to be processed in the (r-1)-th processing state, and the elimination process performed on the r-th to n-th rows element of the matrix to be processed in the (r-1)-th processing state, is a fixed duration.

[0022] According to one aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the method described above.

[0023] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0024] According to the key generation method of the embodiments of this disclosure, the elements in the r-th row can be eliminated based on the operation of multiple initialization parameters, and if the elimination is successful, the elements in other rows can be eliminated. This can reduce the time complexity, and the operation of the initialization parameters can make the running time constant, thereby reducing the running time of cryptographic algorithms that are resistant to quantum computing attacks and improving the running efficiency.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0027] Figure 1 A flowchart illustrating a key generation method according to an embodiment of the present disclosure is shown;

[0028] Figure 2 A schematic diagram illustrating the application of a key generation method according to an embodiment of the present disclosure is shown.

[0029] Figure 3 A block diagram of a key generation apparatus according to an embodiment of the present disclosure is shown;

[0030] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0031] Figure 5 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0032] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0033] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0034] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0035] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0036] Figure 1 A flowchart illustrating a key generation method according to an embodiment of this disclosure is shown, such as... Figure 1 As shown, the method includes:

[0037] In step S11, the initial state matrix to be processed and the initialization parameters are obtained. The matrix to be processed is an n-row m-column matrix. The elements of the matrix to be processed are 0 or 1. n and m are both positive integers, and m > n.

[0038] In step S12, based on the elements of rows r to n of the matrix to be processed in the (r-1)th processing state and the initialization parameters, the elements of row r of the matrix to be processed in the (r-1)th processing state are eliminated to obtain the elements of row r after elimination, where r is a positive integer less than or equal to n, and the matrix to be processed in the 0th processing state is the matrix to be processed in the initial state.

[0039] In step S13, based on the r-th row element after the elimination process, it is determined whether the r-th elimination was successful.

[0040] In step S14, if the elimination is successful for the rth time, the elements of the rth row after the elimination process and the initialization parameters are used to perform elimination on the elements of the r-1th processing state matrix from the rth row to the nth row to obtain the processing state matrix.

[0041] In step S15, the matrix to be processed in the nth processing state is determined as the target matrix;

[0042] In step S16, a key for encrypting the target file is generated based on the target matrix.

[0043] According to the key generation method of the embodiments of this disclosure, the elements in the r-th row can be eliminated based on the operation of multiple initialization parameters, and if the elimination is successful, the elements in other rows can be eliminated. This can reduce the time complexity, and the operation of the initialization parameters can make the running time constant, thereby reducing the running time of cryptographic algorithms that are resistant to quantum computing attacks and improving the running efficiency.

[0044] In one possible implementation, as described above, the key generation process includes a crucial step of Gaussian elimination on a matrix, which is the matrix to be processed in the initial state. For example, it is an n x m matrix G0, where the elements of matrix G0 are logical values ​​0 or 1, n and m are both positive integers, and m > n (i.e., the number of columns is greater than the number of rows). If Gaussian elimination is successful, a target matrix is ​​obtained. The left side of the target matrix is ​​an n x n identity matrix I, and the right side consists of the remaining column vectors. This disclosure does not restrict the values ​​of the elements in the column vectors. For example, the target matrix is ​​G1 = [I|G2], where G2 is a matrix composed of at least one column vector, and there exists an invertible matrix Q such that G1 = QG0. The target matrix G1 can be used to generate a key for encrypting the file to be encrypted.

[0045] In one possible implementation, in step S11, in addition to processing the matrix G0 to be processed in the initial state described above, at least one initialization parameter can also be obtained. In the example, the initialization parameter may include a first parameter mask, a second parameter found, a third parameter tmpk, and a fourth parameter tmp. Before the elimination process begins, all of the above initialization parameters can be set to 0. In the example, all of the above parameters are 32-bit integer variables. This disclosure does not limit the data type of the initialization parameters.

[0046] In one possible implementation, in step S12, Gaussian elimination can be performed on the initial state's matrix G0. During elimination, the following steps can be used: Eliminate the elements in the r-th row of the matrix to be processed in the current processing state (r-1th processing state). If elimination is successful, eliminate the elements in rows r+1 to n to obtain the matrix to be processed in the next processing state (r-th processing state). The matrix to be processed in the r-1th processing state is obtained by processing the matrix to be processed in the r-2th processing state, where r is a positive integer less than or equal to n, and the matrix to be processed in the 0th processing state is the initial state's matrix G0. This process can be iterated n times, i.e., r traverses from 1 to n. If each elimination operation is successful, the matrix to be processed in the nth processing state is obtained, which is the target matrix.

[0047] In the example, elimination can be performed on the elements of the first row of the matrix G0 to be processed in the initial state. If the elimination is successful, elimination can be performed on the second to nth rows of the matrix G0 to be processed, obtaining the matrix to be processed in the first processing state. Subsequently, elimination can be performed on the second row of the matrix to be processed in the first processing state. If the elimination is successful, elimination can be performed on the third to nth rows of the matrix to be processed in the first processing state, obtaining the matrix to be processed in the second processing state, and so on. Elimination can be performed on the nth row of the matrix to be processed in the (n-1)th processing state. If the elimination is successful, the matrix to be processed in the nth processing state can be obtained, which is the target matrix.

[0048] In one possible implementation, taking the elimination process of the elements in the r-th row of the matrix to be processed in the (r-1)-th processing state as an example, step S12 may include: setting the initialization parameters according to the elements in the preset columns of the r-th row and the elements in the preset columns of the k-th row to obtain a first setting parameter corresponding to the k-th row, where r+1≤k≤n and k is an integer; and performing elimination processing on the elements in the r-th row according to the first setting parameter corresponding to the k-th row to obtain the elements in the r-th row after elimination processing.

[0049] In one possible implementation, during the elimination process for the elements in row r, elimination can be performed based on elements from row r+1 to row n. Each time, elements from one row from row r+1 to row n (e.g., row k, where r+1 ≤ k ≤ n, and k is an integer) and elements from row r can be used to perform elimination on row r. k can iterate through rows r+1 to n, that is, elements from each row r+1 to row n are processed in conjunction with elements from row r to perform elimination on the elements in row r. After the corresponding processing of elements from row n to row r is completed, the elimination process for row r is finished, resulting in the eliminated elements of row r.

[0050] In one possible implementation, taking the elements in row k and row r as examples of performing corresponding processing, the above initialization parameters can be set based on the elements in the preset columns of row r and row k, and the elements in row r can be eliminated based on the set parameters and the elements in row k to obtain the elements in row r after elimination processing.

[0051] In one possible implementation, the first setting parameter includes a first parameter, a second parameter, a third parameter, and a fourth parameter. The initialization parameter is set based on the elements of the preset columns in the r-th row and the k-th row to obtain the first setting parameter. This includes: setting the first parameter based on the elements of the r-th row and r-th column, and the elements of the k-th row and r-th column, to obtain the first parameter; performing a logical OR operation on the first parameter and the second parameter to obtain the second parameter, which is used to record the first parameter; performing a logical AND operation on the first parameter and the elements of the k-th row to obtain the third parameter, which is used to determine the number of rows used in the elimination process of the elements in the r-th row based on the first parameter; and obtaining the fourth parameter based on a preset running time parameter and the maximum value of the third and fourth parameters, which represents the number of rows used in the elimination process of the elements in the r-th row.

[0052] In one possible implementation, since the left side of the target matrix is ​​an identity matrix (i.e., a matrix where the elements on the main diagonal are 1 and the rest are 0), when performing elimination on the elements of the r-th row, the element in the r-th row and r-th column can be processed to make that element 1 and the other elements 0. To achieve this, when processing the elements of the k-th row and the r-th row, the elements in the k-th row and r-th column can be processed together, and the result can be used to set initialization parameters. These initialization parameters can then be used to process the elements of the r-th row, r-th column, making the element in the r-th row and r-th column 1 and the rest of the r-th row 0. In the example, a logical operation can be performed between the elements in the r-th row and r-th column and the elements in the k-th row and r-th column, and the first parameter can be set based on the result of the logical operation.

[0053] In one possible implementation, the first parameter is set based on the element in row r and column r, and the element in row k and column r, to obtain the set first parameter. This includes: performing a logical XOR operation on the element in row r and column r, and the element in row k and column r, to obtain the fifth parameter; and inverting the fifth parameter bit by bit and adding 1 to obtain the set first parameter. In the example, the first parameter mask can be set to G[r][r]^G[k][r], where G[r][r] is the element in row r and column r of the matrix to be processed in the (r-1)th processing state, G[k][r] is the element in row k and column r, and ^ is the XOR operator. That is, the first parameter can be set to the result of a logical XOR operation between the element in the r-th row and r-th column and the element in the k-th row and r-th column (i.e., the fifth parameter), so that the fifth parameter is 1 when the values ​​of the element in the r-th row and r-th column and the element in the k-th row and r-th column are different, and the fifth parameter is 0 when the values ​​of the element in the r-th row and r-th column and the element in the k-th row and r-th column are the same.

[0054] In one possible implementation, the fifth parameter can be bitwise inverted and then incremented by 1, with the result used as the first parameter after setting. In the example, matrix elements are either 0 or 1. However, in actual computer operations, the smallest unit is a byte. Therefore, bitwise inversion and incrementing by 1 is for compatibility with computer operation rules. The value of the fifth parameter is either 0 or 1, but it can be a 32-bit integer variable. For example, when the fifth parameter is 0, bitwise inversion and incrementing by 1 still results in 0; when the fifth parameter is 1, it can be represented as 000…01 (32 bits), and bitwise inversion and incrementing by 1 results in 111…1 (32 bits), meaning all data bits are 1. That is, after the above processing, if the XOR result is 0, the first parameter after setting is still 0; if the XOR result is 1, the first parameter after setting is a value where all data bits are 1.

[0055] In one possible implementation, after obtaining the first parameter after setting it, the second parameter can be set using the first parameter to obtain the second parameter after setting it. In the example, a logical OR operation can be performed between the first parameter and the second parameter (before this setting process, the second parameter `found = 0`), and the result of the logical OR operation can be used as the second parameter after setting it. That is, if the first parameter is 1, the second parameter is also 1, and if the first parameter is 0, the second parameter is also 0. The second parameter after setting it can be used to record the first parameter after setting it, as a subsequent judgment condition, and can also be used to record whether the XOR result of the element in the r-th column of the current row (i.e., row k) and the element in the r-th row and r-th column is 1.

[0056] In one possible implementation, the third parameter can be set based on the first parameter. This can be achieved by performing a logical AND operation between the first parameter and the element of the k-th row, and using the result as the third parameter. Specifically, the third parameter `tmpk` is set to `k&mask`. If the XOR result is 1, the third parameter is the element of the k-th row; if the XOR result is 0, the third parameter is 0. The third parameter determines the number of rows used for elimination processing on the r-th row—whether to use the element of the k-th row to eliminate elements of the r-th row, or to use rows where all elements are 0.

[0057] In one possible implementation, the fourth parameter can be obtained based on a preset runtime parameter and the maximum value of the third and fourth parameters after setting. The preset runtime parameter can be a constant time parameter in the `max` function, meaning the set time is a constant, and the maximum value of the third and fourth parameters is taken when the runtime reaches this constant. This process ensures that the processing time of the above logical operation is constant. The fourth parameter is then the maximum value of the third parameter after setting and the fourth parameter before setting (where `tmp` = 0). Specifically, if the XOR result is 1, the fourth parameter is the element of the k-th row; if the XOR result is 0, the fourth parameter is 0. The fourth parameter indicates the row number used for elimination processing of the elements in the r-th row. That is, if the XOR result is 1, the elements in the k-th row are used to eliminate the elements in the r-th row; if the XOR result is 0, rows with all zeros are used for elimination processing.

[0058] In one possible implementation, after the above settings are performed, a first setting parameter is obtained, which is the first setting parameter corresponding to the k-th row, using the elements of the r-th row and the elements of the k-th row. Then, the elements of the r-th row can be eliminated using the first setting parameter corresponding to the k-th row to obtain the eliminated elements of the r-th row.

[0059] In one possible implementation, the elements of the r-th row are eliminated according to the first setting parameter corresponding to the k-th row to obtain the eliminated r-th row element, including: when the second setting parameter is true, summing each element in the fourth setting parameter with the corresponding element in the r-th row to obtain the elimination result corresponding to the k-th row; and determining the elimination result corresponding to the n-th row as the eliminated r-th row element.

[0060] In one possible implementation, as described above, the set second parameter can be used to record the set first parameter as a subsequent judgment condition. During elimination processing, the value of the set second parameter can be determined. If the second parameter is true (logic 1), then each element in the set fourth parameter can be summed with the corresponding element in the r-th row to obtain the elimination result corresponding to the k-th row. That is, if the above XOR result is 1, then the element in the k-th row (i.e., the element in the k-th row stored in the set fourth parameter) can be summed with the r-th row to obtain the elimination result corresponding to the k-th row. If the above XOR result is 0, then the corresponding element in the r-th row (where all elements are 0) can be summed, keeping the corresponding element in the r-th row unchanged and keeping the computation time constant.

[0061] In one possible implementation, the above process of obtaining the elimination result corresponding to the k-th row can be executed iteratively. That is, k traverses from the (r+1)-th row to the n-th row, so as to obtain the elimination result corresponding to the (r+1)-th row, the elimination result corresponding to the (r+2)-th row, ... the elimination result corresponding to the n-th row respectively during the iteration process. That is, when k = r + 1, if the XOR result of the element in row (r+1) and column (r) is 1, the element in row (r+1) is added to the element in row (r) to obtain the elimination result corresponding to row (r+1). That is, the element in row (r) after adding the element in row (r+1) is added to the element in row (r) (if the XOR result is 0, it is added to the row with all zeros, keeping the element in row (r) unchanged). When k = r + 2, if the XOR result of the element in row (r+2) and column (r) is 1, the element in row (r) is added to the element in row (r+1) to obtain the elimination result (the element in row (r) after adding the element in row (r+1)). The elements in the r-th row are added together to obtain the elimination result corresponding to the (r+2)-th row. That is, the element in the r-th row after adding the elements in the (r+2)-th row (if the XOR result is 0, it is added to the row with all zeros)... When k=n, if the XOR result of the element in the n-th row and the r-th column of the elimination result corresponding to the (n-1)-th row (i.e., the element in the r-th row after elimination obtained when k=n-1) is 1, the element in the n-th row is added to the elimination result corresponding to the (n-1)-th row to obtain the elimination result corresponding to the n-th row. That is, the element in the r-th row after adding the elements in the n-th row (if the XOR result is 0, it is added to the row with all zeros). Therefore, the elimination result corresponding to the n-th row can be determined as the element in the r-th row after elimination.

[0062] In this scenario, if the element in the r-th row and r-th column of the matrix to be processed in the (r-1)-th processing state is 0, then as long as there exists at least one row from the (r+1)-th row to the n-th row with an element in the r-th column that is 1, the element in the r-th row after elimination will be 1. If the element in the r-th row and r-th column of the matrix to be processed in the (r-1)-th processing state is 1, then after the above processing, the element in the r-th row and r-th column will still be 1. Only when all elements in the r-th column of the matrix from the r-th row to the n-th row are 0 will the element in the r-th row after elimination be 0.

[0063] In one possible implementation, in step S13, the elimination process performed on the elements of row r, the subsequent possible elimination processes on rows r+1 to n, and the process of obtaining the matrix to be processed in the r-th processing state can be considered as the r-th elimination process. The success of the r-th elimination process can be determined in step S13. The success of the r-th elimination process depends only on the result of the elimination process on the elements of row r, and not on the result of the subsequent possible elimination processes on rows r+1 to n. Therefore, the success of the elimination process can be determined before performing the elimination processes on rows r+1 to n. This allows for the subsequent elimination processes on rows r+1 to n to proceed only if the elimination is successful, and if the elimination fails, there is no need to perform the subsequent elimination processes on rows r+1 to n. This reduces potential computational steps, lowers computational complexity, and improves computational efficiency.

[0064] In one possible implementation, the success of the r-th elimination depends on the value in the r-th row and r-th column. Step S13 may include: determining that the r-th elimination was successful if the element in the r-th row and r-th column is 1. As mentioned above, only when all elements in the r-th column of rows r to n are 0 will the element in the r-th row after elimination be 0; otherwise, the element in the r-th row after elimination will be 1. Therefore, if the element in the r-th row and r-th column is 0, it means that all elements in the r-th column of rows r to n are 0, that is, the input matrix to be processed in the (r-1)-th processing state does not meet the requirements and cannot be Gaussian eliminated. Therefore, the elimination fails, and no further elimination or subsequent processing is needed. However, if the element in the r-th row and r-th column is 1, the r-th elimination is successful, and subsequent processing can continue.

[0065] In one possible implementation, in step S14, if the above-mentioned elimination of the rth element is successful, the elements of the (r+1)th row to the nth row in the matrix to be processed in the (r-1)th processing state can be eliminated, so that the elimination of all elements from the rth row to the nth row is completed, and the matrix to be processed in the rth processing state is obtained.

[0066] In one possible implementation, step S14 may include: setting the initialization parameters based on the elements of the preset columns of the r-th row after elimination and the elements of the preset columns of the i-th row, to obtain a second setting parameter corresponding to the i-th row, where r+1≤i≤n and k is an integer; performing a logical AND operation between each element of the r-th row after elimination and the second setting parameter to obtain the operation result corresponding to each element; summing the operation result corresponding to each element with the corresponding element in the i-th row to obtain the matrix after elimination of the elements in the i-th row; and determining the matrix after elimination of the elements in the n-th row as the matrix to be processed in the r-th processing state.

[0067] In one possible implementation, the initialization parameters can be set to 0, and then reset according to subsequent processing. In the example, the initialization parameters may include a first parameter, mask, which can be obtained by performing a logical XOR operation between the element in the r-th row and r-th column after elimination and the element in the i-th row and r-th column, then inverting the bits of the XOR result and adding 1 to obtain the second setting parameter. That is, the result of the XOR operation, bit inversion, and addition of 1 is determined as the second setting parameter. When the XOR result is 1 (i.e., the element in the r-th row and r-th column is different from the element in the i-th row and r-th column), the second setting parameter is a value where all data bits are 1; when the XOR result is 0 (i.e., the element in the r-th row and r-th column is the same as the element in the i-th row and r-th column), the second setting parameter is 0.

[0068] In one possible implementation, each element of the r-th row after elimination can be logically ANDed with the second setting parameter to obtain the result of the operation. If the XOR result is 1, the second setting parameter is also a value where each bit is 1, and the result of the logical AND operation between the elements of the r-th row after elimination and the second setting parameter is still the elements of the r-th row after elimination. If the XOR result is 0, the second setting parameter is also 0, and the result of the logical AND operation between the elements of the r-th row after elimination and the second setting parameter is 0.

[0069] In one possible implementation, the result of the operation corresponding to each element can be summed with the corresponding element in the i-th row to obtain the matrix after elimination of the elements in the i-th row. If the XOR result is 1, that is, the element in the r-th column of the r-th row is not the same as the element in the r-th column of the i-th row, in other words, the element in the i-th row and i-th column is 0 (in the case of successful elimination in the r-th row, the element in the r-th column after elimination is 1), then the element in the r-th column can be summed with the elements in the i-th row to obtain the summed elements in the i-th row. If the XOR result is 0, that is, the element in the r-th column of the r-th row is the same as the element in the r-th column of the i-th row, in other words, the element in the i-th row and i-th column is 1, then the result of the above logical AND operation is 0. After summing 0 with the elements in the i-th row, the elements in the i-th row remain unchanged. The matrix with the summed elements in the i-th row is the matrix after elimination of the elements in the i-th row.

[0070] In one possible implementation, the elimination process for the elements of the i-th row can be performed iteratively. After the elimination process for the n-th row is completed (i.e., after the elimination process for all rows is completed), a matrix with the elements of the n-th row eliminated is obtained. This matrix can be determined as the matrix to be processed in the r-th processing state. Further, after obtaining the matrix to be processed in the r-th processing state, the initialization parameter can be set to 0.

[0071] In one possible implementation, the above describes the process of performing elimination on the elements in the r-th row and on the elements from the (r+1)-th row to the n-th row during the r-th elimination process, and obtaining the matrix to be processed in the r-th processing state. Here, r is a positive integer less than or equal to n. In step S15, the above process can be iteratively executed, that is, r traverses from 1 to n until the n-th elimination process is performed, and the matrix to be processed in the n-th processing state is obtained (if each elimination process is successful). This also means obtaining the matrix after eliminating all rows, i.e., the target matrix, where G1 = [I|G2], I is the identity matrix, G2 is a matrix composed of at least one column vector, and there exists an invertible matrix Q such that G1 = QG0. Furthermore, in the process of obtaining the target matrix described above, the execution time required for each iteration is a fixed duration. That is, in each iteration, the execution time for the elimination process performed on the r-th row element of the matrix to be processed in the (r-1)-th processing state, and the execution time for the elimination process performed on the r-th to n-th rows of the matrix to be processed in the (r-1)-th processing state, are both fixed durations. This ensures that the execution time for performing Gaussian elimination on the matrix to be processed in the initial state to obtain the target matrix is ​​also fixed, thus meeting the requirements of subsequent verification processes (e.g., verifying the processing time).

[0072] In one possible implementation, in step S15, the target matrix obtained after Gaussian elimination can be used in the key generation process to obtain a key for encrypting the target file to be encrypted.

[0073] According to the key generation method of this disclosure, the elements in the r-th row can be eliminated based on the operation of multiple initialization parameters. If the elimination is successful, the elements in other rows can then be eliminated, which reduces time complexity. Furthermore, the need for summation can be determined based on a first set parameter, thereby reducing unnecessary summation processes and further reducing time complexity. The operation of the initialization parameters ensures that the running time is constant, reducing the computation time required and improving computational efficiency. Thus, a key is obtained with higher efficiency and lower time complexity for encrypting the target file.

[0074] Figure 2 The illustration shows an application diagram of the key generation method according to an embodiment of the present disclosure, such as... Figure 2 As shown, you can input the matrix that needs Gaussian elimination, that is, an n-row m-column matrix G0. The elements of matrix G0 are logical values ​​0 or 1. n and m are both positive integers, and m > n, that is, the number of columns is greater than the number of rows.

[0075] In the example, you can traverse each row of matrix G0, and for each row, you can perform elimination on that row. If the elimination is successful, you can perform elimination on the subsequent rows of that row to obtain the matrix after the elimination. Then you can perform the next elimination, that is, elimination on the next row and elimination on the subsequent rows of the next row after the elimination is successful.

[0076] In the example, taking the row-th row as an example, 1 ≤ row ≤ n, and row is an integer. During the elimination process of the row-th row of the matrix in the (row-1)th processing state, the initialization parameters can be set, and the elimination process for the r-th row can be performed. This process can include multiple logical operations, which are equivalent to: if the element in the row-th row and the row-th column is 0, then a row whose XOR value with the element in the row-th row and the row-th column is 1 can be found, that is, a row whose element in the row-th column is 1 can be found. After determining the row whose element in the row-th column is 1, the element of that row can be summed with the element of the row-th row, so that the element in the row-th row and the row-th column is set to 1. If the element in the row-th row and the row-th column is 1, then after the above process, the element in the row-th row and the row-th column is still 1. Only when all elements in the row-th column in rows from row-th to n-th are 0 will the element in the row-th row and the row-th column after the elimination process be 0.

[0077] In the example, after the above elimination process, it can be determined whether the elimination was successful. That is, it is determined whether the element in the row-1 and column-1 after the elimination process is 1. If the element is 1, the elimination is successful, and the elimination process can be carried out on the subsequent rows of row 1. If the element in the row-1 and column-1 is 0, that is, all elements in the row-1 to row n are 0, the elimination fails, the matrix cannot be eliminated, and no further processing is required.

[0078] In the example, if the elimination is successful, during the elimination process for subsequent rows of row 'row', the element in the first row and the first column (i.e., 1) can be logically XORed with the element in the first row and the first column of subsequent rows. The XOR result can then be logically ANDed with the element in row 'row', and the result can be added to subsequent rows to complete the elimination process. That is, the elimination of row 'row' and all subsequent rows is performed.

[0079] In the example, the above process can be iteratively executed until all n rows of the matrix have been eliminated (if each elimination is successful), then the target matrix can be obtained, which is the matrix that can be used to generate the key for encrypting the target file to be encrypted.

[0080] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0081] In addition, this disclosure also provides a key generation apparatus, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any of the key generation methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding section of the method and will not be repeated here.

[0082] Figure 3 A block diagram of a key generation apparatus according to an embodiment of the present disclosure is shown, such as Figure 3As shown, the device includes: an acquisition module 11, used to acquire the initial state of the matrix to be processed and initialization parameters, wherein the matrix to be processed is an n-row m-column matrix, the elements of the matrix to be processed are 0 or 1, n and m are both positive integers, and m > n; and a first elimination module 12, used to perform elimination processing on the r-th row elements of the matrix to be processed in the (r-1)-th processing state according to the elements of the r-th to n-th rows of the matrix to be processed in the (r-1)-th processing state and the initialization parameters, to obtain the r-th row elements after elimination processing, where r is a positive integer less than or equal to n, and the matrix to be processed in the 0th processing state is the initial state of the matrix to be processed. The matrix to be processed includes: a judgment module 13, used to determine whether the r-th elimination was successful based on the r-th row element after the elimination process; a second elimination module 14, which, if the r-th elimination was successful, performs elimination processing on the elements of the (r+1)-th to (n)-th rows of the matrix to be processed in the (r-1)-th processing state based on the r-th row element after the elimination process and the initialization parameters, to obtain the matrix to be processed in the r-th processing state; a target matrix acquisition module 15, used to determine the matrix to be processed in the n-th processing state as the target matrix; and an encryption module 16, used to generate a key for encrypting the target file based on the target matrix.

[0083] In one possible implementation, the first elimination module is further configured to: set the initialization parameters according to the elements of the preset column of the r-th row and the elements of the preset column of the k-th row to obtain a first setting parameter corresponding to the k-th row, where r+1≤k≤n and k is an integer; and perform elimination processing on the elements of the r-th row according to the first setting parameter corresponding to the k-th row to obtain the eliminated elements of the r-th row.

[0084] In one possible implementation, the initialization parameters include a first parameter, a second parameter, a third parameter, and a fourth parameter; the first setting parameter includes a set first parameter, a set second parameter, a set third parameter, and a set fourth parameter, and the first elimination module is further configured to: set the first parameter based on the element in the r-th row and r-th column, and the element in the k-th row and r-th column, to obtain the set first parameter; perform a logical OR operation on the set first parameter and the second parameter to obtain the set second parameter, which is used to record the set first parameter; perform a logical AND operation on the set first parameter and the element in the k-th row to obtain the set third parameter, which is used to determine the number of rows used in the elimination process of the elements in the r-th row based on the set first parameter; and obtain the set fourth parameter based on a preset running time parameter and the maximum value of the set third parameter and the fourth parameter, which represents the number of rows used in the elimination process of the elements in the r-th row.

[0085] In one possible implementation, the first elimination module is further configured to: perform a logical XOR operation on the element in the r-th row and r-th column and the element in the k-th row and r-th column to obtain the fifth parameter; and invert the fifth parameter bit by bit and add 1 to obtain the first parameter after setting.

[0086] In one possible implementation, the first elimination module is further configured to: when the second parameter after the setting is true, sum each element in the fourth parameter after the setting with the corresponding element in the r-th row to obtain the elimination result corresponding to the k-th row; and determine the elimination result corresponding to the n-th row as the element of the r-th row after the elimination.

[0087] In one possible implementation, the judgment module is further configured to: determine that the r-th elimination was successful if the element in the r-th row and r-th column is 1.

[0088] In one possible implementation, the second elimination module is further configured to: set the initialization parameters based on the elements of the preset columns of the r-th row after elimination processing and the elements of the preset columns of the i-th row, to obtain a second setting parameter corresponding to the i-th row, where r+1≤i≤n and i is an integer; perform a logical AND operation between each element of the r-th row after elimination processing and the second setting parameter to obtain the operation result corresponding to each element; sum the operation result corresponding to each element with the corresponding element in the i-th row to obtain the matrix after elimination processing of the elements in the i-th row; and determine the matrix after elimination processing of the elements in the n-th row as the matrix to be processed in the r-th processing state.

[0089] In one possible implementation, the execution time for the elimination process performed on the r-th row element of the matrix to be processed in the (r-1)-th processing state, and the elimination process performed on the r-th to n-th rows element of the matrix to be processed in the (r-1)-th processing state, is a fixed duration.

[0090] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0091] This disclosure also proposes a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method. The computer-readable storage medium may be a non-volatile computer-readable storage medium.

[0092] This disclosure also proposes an electronic device, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the above-described method.

[0093] This disclosure also provides a computer program product including computer-readable code, which, when executed on a device, causes a processor in the device to execute instructions for implementing the key generation method provided in any of the above embodiments.

[0094] This disclosure also provides another computer program product for storing computer-readable instructions that, when executed, cause a computer to perform the key generation method provided in any of the above embodiments.

[0095] Electronic devices can be provided as terminals, servers, or other forms of devices.

[0096] Figure 4 This diagram illustrates a block diagram of an electronic device 800 according to an embodiment of the present disclosure. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, or other terminal.

[0097] Reference Figure 4 The electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0098] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0099] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of this data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0100] Power supply component 806 provides power to various components of electronic device 800. Power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0101] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the edges of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0102] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0103] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0104] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0105] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0106] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0107] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 804 including computer program instructions that can be executed by a processor 820 of an electronic device 800 to perform the above-described method.

[0108] Figure 5 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 may be provided as a server. (Refer to...) Figure 5 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0109] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output (I / O) interface 1958. Electronic device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM Mac OS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0110] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0111] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0112] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0113] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0114] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0115] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0116] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0117] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0118] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0119] The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0120] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A key generation method, characterized in that, include: Obtain the initial state matrix to be processed and the initialization parameters. The matrix to be processed is an n-row m-column matrix. The elements of the matrix to be processed are 0 or 1. n and m are both positive integers, and m > n. Based on the elements of rows r to n of the matrix to be processed in the (r-1)th processing state, and the initialization parameters, the elements of row r of the matrix to be processed in the (r-1)th processing state are eliminated to obtain the elements of row r after elimination, where r is a positive integer less than or equal to n, and the matrix to be processed in the 0th processing state is the matrix to be processed in the initial state. Based on the r-th row element after the elimination process, determine whether the r-th elimination was successful; If the elimination is successful on the rth time, based on the element of the rth row after the elimination process and the initialization parameters, the elements of the (r+1)th row to the nth row of the matrix to be processed in the (r-1)th processing state are eliminated to obtain the matrix to be processed in the rth processing state. The matrix to be processed in the nth processing state is determined as the target matrix; Based on the target matrix, generate a key to encrypt the target file; The step of performing elimination processing on the r-th row element of the matrix to be processed in the (r-1)-th processing state, based on the elements of the r-th to n-th rows of the matrix to be processed in the (r-1)-th processing state and the initialization parameters, to obtain the r-th row element after elimination, includes: Based on the elements of the preset column in the r-th row and the elements of the preset column in the k-th row, the initialization parameters are set to obtain the first setting parameter corresponding to the k-th row, where r+1≤k≤n and k is an integer; The elements of the r-th row are eliminated according to the first setting parameter corresponding to the k-th row to obtain the elements of the r-th row after elimination. The initialization parameters include a first parameter, a second parameter, a third parameter, and a fourth parameter; the first setting parameters include the set first parameter, the set second parameter, the set third parameter, and the set fourth parameter. The step of setting the initialization parameters based on the elements of the preset column in the r-th row and the elements of the preset column in the k-th row to obtain the first setting parameters includes: Based on the element in row r and column r, and the element in row k and column r, set the first parameter to obtain the set first parameter; The first parameter and the second parameter after being set are logically ORed to obtain the second parameter after being set. The second parameter after being set is used to record the first parameter after being set. Perform a logical AND operation between the first parameter after setting and the element of the kth row above to obtain the third parameter after setting. The third parameter after setting is used to determine the row number used in the elimination process of the element of the rth row based on the first parameter after setting. Based on the preset running time parameter, and the maximum value of the third and fourth parameters after the setting, the fourth parameter after the setting is obtained. The fourth parameter is used to represent the number of rows used in the elimination process of the elements in the r-th row.

2. The method according to claim 1, characterized in that, Based on the element in row r and column r, and the element in row k and column r, the first parameter is set to obtain the set first parameter, including: Perform a logical XOR operation on the element in row r and column r and the element in row k and column r to obtain the fifth parameter; The fifth parameter is inverted bitwise and then incremented by 1 to obtain the first parameter after the setting.

3. The method according to claim 1, characterized in that, Elimination is performed on the elements of the r-th row according to the first setting parameter corresponding to the k-th row to obtain the eliminated elements of the r-th row, including: If the second parameter after the setting is true, sum each element in the fourth parameter after the setting with the corresponding element in the r-th row to obtain the elimination result corresponding to the k-th row; The elimination result corresponding to the nth row is determined as the element of the rth row after the elimination process.

4. The method according to claim 1, characterized in that, Based on the elements in the r-th row after the elimination process, determine whether the r-th elimination was successful, including: If the element in the r-th row and r-th column is 1, then the r-th elimination is successful.

5. The method according to claim 1, characterized in that, Based on the element of the r-th row after the elimination process and the initialization parameters, the elements of the (r+1)-n rows of the matrix to be processed in the (r-1)-th processing state are subjected to elimination to obtain the matrix to be processed in the r-th processing state, including: Based on the elements of the preset column of the r-th row after the elimination process, and the elements of the preset column of the i-th row, the initialization parameters are set to obtain the second setting parameters corresponding to the i-th row, where r+1≤i≤n, and i is an integer; Perform a logical AND operation between each element of the r-th row after the elimination process and the second setting parameter to obtain the operation result corresponding to each element; The operation results corresponding to each element are summed with the corresponding elements in the i-th row to obtain the matrix after eliminating the elements in the i-th row. The matrix obtained by eliminating elements in the nth row is determined as the matrix to be processed in the rth processing state.

6. The method according to claim 1, characterized in that, The execution time for the elimination process performed on the r-th row element of the matrix to be processed in the (r-1)-th processing state, and the elimination process performed on the r-th to n-th rows of the matrix to be processed in the (r-1)-th processing state, is a fixed duration.

7. A key generation device, characterized in that, include: The acquisition module is used to acquire the initial state matrix to be processed and the initialization parameters. The matrix to be processed is an n-row m-column matrix. The elements of the matrix to be processed are 0 or 1, n and m are both positive integers, and m > n. The first elimination module is used to perform elimination processing on the r-th row element of the matrix to be processed in the (r-1)-th processing state based on the elements from the r-th row to the n-th row of the matrix to be processed in the (r-1)-th processing state and the initialization parameters, to obtain the r-th row element after elimination processing, where r is a positive integer less than or equal to n, and the matrix to be processed in the 0th processing state is the matrix to be processed in the initial state. The judgment module is used to determine whether the r-th elimination was successful based on the r-th row element after the elimination process. The second elimination module, in the case of successful elimination for the rth time, performs elimination processing on the elements of the rth row after the elimination processing and the initialization parameters on the elements of the (r+1)th row to the nth row of the matrix to be processed in the (r-1)th processing state to obtain the matrix to be processed in the rth processing state. The target matrix acquisition module is used to determine the matrix to be processed in the nth processing state as the target matrix; An encryption module is used to generate a key for encrypting the target file based on the target matrix; The first elimination module is further used for: Based on the elements of the preset column in the r-th row and the elements of the preset column in the k-th row, the initialization parameters are set to obtain the first setting parameter corresponding to the k-th row, where r+1≤k≤n and k is an integer; The elements of the r-th row are eliminated according to the first setting parameter corresponding to the k-th row to obtain the elements of the r-th row after elimination. The initialization parameters include a first parameter, a second parameter, a third parameter, and a fourth parameter; the first setting parameters include the set first parameter, the set second parameter, the set third parameter, and the set fourth parameter; the first elimination module is further used for: Based on the element in row r and column r, and the element in row k and column r, set the first parameter to obtain the set first parameter; The first parameter and the second parameter after being set are logically ORed to obtain the second parameter after being set. The second parameter after being set is used to record the first parameter after being set. Perform a logical AND operation between the first parameter after setting and the element of the kth row above to obtain the third parameter after setting. The third parameter after setting is used to determine the row number used in the elimination process of the element of the rth row based on the first parameter after setting. Based on the preset running time parameter, and the maximum value of the third and fourth parameters after the setting, the fourth parameter after the setting is obtained. The fourth parameter is used to represent the number of rows used in the elimination process of the elements in the r-th row.

8. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 6.

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