Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising: a driving circuit, the driving circuit comprising N-stage shift registers which are cascaded with each other, N>=2; the shift register comprising a control unit, an initial output unit and a first output unit; the control unit being configured to control signals of a first output node and a second output node in response to at least an input signal; the initial output unit being configured to receive signals of the first output node and the second output node and control an initial output signal; the initial output signal of an xth-stage shift register being an input signal of a yth-stage shift register, 1<=x<=N, 1<=y<=N; and the first output unit being configured to receive signals of the first output node and the second output node and control a first output signal. The technical scheme of the application can make the display panel meet diversified display requirements.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, electronic products with display functions are widely used in various fields, such as televisions, mobile phones, computers, and personal digital assistants, becoming an indispensable part of people's lives and work. Among them, the display panel is the core structure that realizes the display function in electronic products.

[0003] Display panels typically include a pixel array and a driving circuit for driving the pixel array. The driving circuit enables the pixel array to scan line by line so that the pixel array can display the image. However, due to the limitations of the function and structure of the driving circuit in the existing technology, the driving method of each row of pixels in the pixel array is the same, which makes the display panel unable to meet diverse display needs. Summary of the Invention

[0004] The present invention provides a display panel and a display device, so that the display panel can meet diverse functional requirements and broaden the application scenarios of the display panel.

[0005] According to one aspect of the present invention, a display panel is provided, comprising:

[0006] The driving circuit includes N cascaded shift registers, where N ≥ 2;

[0007] The shift register includes:

[0008] Control unit, initial output unit, and first output unit;

[0009] The control unit is used to receive at least input signals and control the signals of the first output node and the second output node.

[0010] The initial output unit is used to receive at least the signals from the first output node and the second output node, and to control the initial output signal. The initial output signal of the x-th stage shift register is the input signal of the y-th stage shift register, where 1≤x≤N and 1≤y≤N.

[0011] The first output unit is used to receive at least the signal from the first output node and the signal from the second output node, and to control the first output signal.

[0012] According to another aspect of the present invention, a display device is provided, comprising: the above-described display panel.

[0013] The technical solution of this invention includes a shift register comprising a control unit, an initial output unit, and a first output unit. The control unit is capable of responding to an input signal, controlling the initial output unit to output an initial output signal, and controlling the first output unit to output a first output signal. The initial output signal of the x-th stage shift register is used as the input signal of the y-th stage shift register, and the first output signal is used as the driving signal for the pixel circuit in the display panel. This ensures that the initial output signals provided to other stages of shift registers and the first output signal provided to the pixel circuit are independent of each other and do not affect each other. This ensures that while the shift registers can perform signal transmission and shifting, the polarity of the first output signal provided to the pixel circuit can be flexibly controlled. This allows the driving methods of pixel circuits in different rows of the display panel to be the same or different, thereby enabling the display panel to meet diverse display needs and broadening the application scenarios of the display panel.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a display panel based on related technologies;

[0017] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0019] Figure 4 This is a timing diagram of a shift register driver provided in an embodiment of the present invention;

[0020] Figure 5 This is a timing diagram of another shift register provided in an embodiment of the present invention;

[0021] Figure 6 This is a driving timing diagram of a driving circuit provided in an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0026] Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0027] Figure 12 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0028] Figure 13 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0029] Figure 14 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0030] Figure 15 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0031] Figure 16 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0032] Figure 17 This is a timing diagram of a shift register driver provided in an embodiment of the present invention;

[0033] Figure 18 This is a timing diagram of another shift register provided in an embodiment of the present invention;

[0034] Figure 19 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0035] Figure 20 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0036] Figure 21 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0037] Figure 22 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0038] Figure 23This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0039] Figure 24 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0040] Figure 25 This is another driving timing diagram of a shift register provided in an embodiment of the present invention;

[0041] Figure 26 This is another driving timing diagram of a shift register provided in an embodiment of the present invention;

[0042] Figure 27 This is another driving timing diagram of a shift register provided in an embodiment of the present invention;

[0043] Figure 28 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0044] Figure 29 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0045] Figure 30 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0046] Figure 31 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0047] Figure 32 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0048] Figure 33 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0049] Figure 34 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0050] Figure 35 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0051] Figure 36 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0052] Figure 37 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0053] Figure 38 This is another driving timing diagram of a shift register provided in an embodiment of the present invention;

[0054] Figure 39 This is another driving timing diagram of a shift register provided in an embodiment of the present invention;

[0055] Figure 40 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0056] Figure 41 This is another driving timing diagram of a shift register provided in an embodiment of the present invention;

[0057] Figure 42 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0058] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0060] As described in the background section, Figure 1 This is a structural diagram of a display panel based on related technologies, such as... Figure 1As shown, the display panel 01 includes a driving circuit 010 and an array of pixel circuits 020. The driving circuit 010 includes multiple cascaded shift registers 011. The driving signal output of each shift register 011 is electrically connected to the pixel circuits located in the same row to provide driving signals to the pixel circuits in the same row, thereby enabling line-by-line scanning of the pixel circuits. Furthermore, since the cascaded shift registers 011 are connected such that the driving signal output of the previous shift register 011 is electrically connected to the signal input of the next shift register 011, each... The effective pulses of the drive signal output by the stage shift register 011 can be shifted sequentially, and the frequency of the drive signal output by each stage shift register 011 is the same. This results in the same drive cycle for the pixel circuit 020 controlled by the drive signal, which means that the data signals written to each pixel circuit 020 will be refreshed simultaneously. As a result, it is impossible to flexibly control each pixel circuit 020 according to different application scenarios. For example, it is impossible to make the pixel circuits 020 of different display areas have different data refresh frequencies. Consequently, the display panel 01 cannot meet the diverse display requirements, thus limiting the application scenarios of the display panel.

[0061] To address the aforementioned technical problems, embodiments of the present invention provide a display panel comprising: a driving circuit, the driving circuit including N cascaded shift registers, where N≥2; the shift registers including: a control unit, an initial output unit, and a first output unit; the control unit being used to control the signals of a first output node and a second output node; the initial output unit being used to receive at least the signals of the first output node and the second output node, and to control an initial output signal, wherein the initial output signal of the x-th shift register is the input signal of the y-th shift register, 1≤x≤N, 1≤y≤N; and the first output unit being used to receive at least the signals of the first output node and the second output node, and to control a first output signal.

[0062] By adopting the above technical solution, the shift register includes a control unit, an initial output unit, and a first output unit. The control unit can respond to input signals, control the initial output unit to output an initial output signal, and control the first output unit to output a first output signal. The initial output signal of the x-th stage shift register is used as the input signal of the y-th stage shift register, and the first output signal is used as the control signal of the pixel circuit in the display panel. This ensures that the initial output signals provided to other stages of shift registers and the first output signals provided to the pixel circuit are independent of each other and do not affect each other. This ensures that signal transmission can be performed between shift registers while flexibly controlling the polarity of the first output signal provided to the pixel circuit. This allows the driving methods of pixel circuits in different rows of the display panel to be the same or different, thereby enabling the display panel to meet diverse display needs and broaden the application scenarios of the display panel.

[0063] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0064] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 2 and Figure 3 The display panel 100 includes a driving circuit 10; the driving circuit 10 includes N cascaded shift registers G, where N≥2; the shift register G includes a control unit 110, an initial output unit 120, and a first output unit 131; the control unit 110 is used to respond to at least the input signal Vin and control the signals of the first output node N1 and the second output node N2; the initial output unit 120 is used to receive at least the signals of the first output node N1 and the second output node N2 and control the initial output signal Vnext; the first output unit 131 is used to receive at least the signals of the first output node N1 and the second output node N2 and control the first output signal Gout1; wherein, the initial output signal of the x-th shift register Gx is the input signal of the y-th shift register Gy, 1≤x≤N, 1≤y≤N.

[0065] The display panel 100 may include a display area 101 and a non-display area 102 surrounding the display area 101. The driving circuit 10 may be disposed in the non-display area 102. The display area 102 may be provided with an array of pixel circuits 20 and multiple driving signal lines 31. At least some of the pixel circuits 20 located in the same row are electrically connected to the same driving signal line 31. At this time, the output terminal of the first output unit 131 of each level shift register G can be electrically connected to different driving signal lines 31 respectively, so as to output the first output signal Gout1 to each driving signal line respectively, so that each driving signal line 31 can transmit the first output signal Gout1 output by the first output unit 131 of each level shift register G to each row of pixel circuits 20 to drive each row of pixel circuits 20.

[0066] It should be noted that the above description is only exemplified by the example of the driving circuit 10 being located in the non-display area 102 and the pixel circuit 20 being located in the display area 101. In other embodiments of the present invention, the pixel circuit 20 and the driving circuit 10 may also be located in the display area 101, so that the number of devices set in the non-display area 102 of the display panel 100 is sufficiently small, thereby reducing the size of the non-display area 102 of the display panel 100. This is beneficial for the narrow bezel of the display panel 100 and gives the display panel 100 a high screen ratio.

[0067] For ease of description, unless otherwise specified, the embodiments of the present invention will be described exemplarily with the driving circuit located in the non-display area of ​​the display panel and the pixel circuit located in the display area of ​​the display panel.

[0068] Continue to refer to Figure 2 and Figure 3 When the initial output signal of the x-th stage shift register Gx is the input signal of the y-th stage shift register Gy, the output terminal of the initial output unit 120 of the x-th stage shift register Gx can be electrically connected to the input terminal of the control unit 110 of the y-th stage shift register Gy. The x-th stage shift register Gx and the y-th stage shift register Gy can be two adjacent shift registers; in this case, if x equals i, then y can equal i+1. Alternatively, the x-th stage shift register Gx and the y-th stage shift register Gy can also be two non-adjacent shift registers; in this case, x and y can be positive integers greater than or equal to 2. Under the premise of achieving the core inventive points of this embodiment, the values ​​of x and y are not specifically limited in this embodiment.

[0069] For ease of description, unless otherwise specified, the embodiments of the present invention use the x-th shift register and the y-th shift register as two adjacent shift registers as examples to illustrate the technical solutions of the embodiments of the present invention.

[0070] refer to Figure 2 and Figure 3In the same shift register unit G, the control unit 110 can be electrically connected to the initial output unit 120 at the first output node N1 and the second output node N2, respectively, and the control unit 110 can also be electrically connected to the first output unit 131 at the first output node N1 and the second output node N2, respectively. For the first-stage shift register G1, the input signal Vin received by its control unit 110 can be the start signal STV provided by the start control circuit (not shown in the figure), so that the first-stage shift register G1 can at least respond to the start signal STV and provide corresponding signals to its first output node N1 and the second output node N2, respectively. For other shift registers G besides the first-stage shift register G1, the input terminal IN of its control unit 110 can be... The output terminal of the initial output unit 120 of the previous stage shift register G is electrically connected so that each stage shift register unit G can at least respond to the initial output signal Vnext output by the initial output unit 120 of the previous stage shift register G and provide corresponding signals to its first output node N1 and second output node N2. In the same shift register G, the polarity of the signals of the first output node N1 and the second output node N2 can be the same or opposite. In an optional embodiment, the polarity of the signals of the first output node N1 and the second output node N2 is opposite for at least a part of the time. That is, when the first output node N1 is high, the second output node N2 can be low, or when the first output node N1 is low, the second output node N2 can be high.

[0071] Correspondingly, within the same shift register G, the initial output unit 120 can output a corresponding initial output signal Vnext based on the signals received from the first output node N1 and the second output node N2; simultaneously, the first output unit 131 can output a corresponding first output signal Gout1 based on the signals received from the first output node N1 and the second output node N2. Both the initial output signal Vnext and the first output signal Gout1 can be pulse signals composed of high and low levels.

[0072] Since the initial output signal Vnext and the first output signal Gout1 are provided by the initial output unit 120 and the first output unit 131, respectively, and the structures and / or operating modes of the initial output unit 120 and the first output unit 131 can be the same or different, the initial output signal Vnext and the first output signal Gout1 can be the same or different. For example, in some application scenarios, the voltage of the initial output signal Vnex can be different from the voltage of the first output signal Gout1, and / or the frequency of the initial output signal Vnex can be different from the frequency of the first output signal Gout1; in other application scenarios, the initial output signal Vnex can also have the same voltage and / or frequency as the first output signal Gout1.

[0073] Optional, Figure 4 This is a driving timing diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 3 and Figure 4 When the pulse change frequency of the initial output signal Vnext is F0 and the pulse change frequency of the first output signal Gout1 is F1, F0 ≠ F1 for at least a part of the time period during the operation of the display panel.

[0074] Specifically, during at least a portion of the time period during the operation of the display panel, the pulse variation frequency F1 of the first output signal Gout1 is set to be different from the pulse variation frequency F0 of the initial output signal Vnext. That is, the period t01 of the first output signal Gout1 is different from the period t00 of the initial output signal Vnext. At this time, during a portion of the time period during the operation of the display panel, the effective pulse time of the initial output signal Vnext overlaps with the ineffective level time of the first output signal Gout1, and / or the effective pulse time of the first output signal Gout1 overlaps with the ineffective level time of the initial output signal Vnext. This ensures that the effective pulse time of the initial output signal Vnext provided to the next-level shift register G does not overlap with the effective pulse time of the first output signal Gout1 provided to the pixel circuit. As a result, the first output signal Gout1 and the initial output signal Vnext output by the same shift register G are independent of each other and do not affect each other. This satisfies the driving requirements of the driving circuit while ensuring that the display panel can display normally.

[0075] In an optional embodiment, Figure 5 This is another driving timing diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 3 and Figure 5 When the pulse change frequency of the initial output signal Vnext is F0 and the pulse change frequency of the first output signal Gout1 is F1, F0 > F1 during at least a portion of the time period during the operation of the display panel.

[0076] Specifically, during at least a portion of the display panel's operation, the pulse variation frequency F0 of the initial output signal Vnext is set to be greater than the pulse variation frequency F1 of the first output signal Gout1, i.e., the period t01 of the first output signal Gout1 is greater than the period t00 of the initial output signal Vnext. This ensures that during a portion of the display panel's operation, the duration of the effective pulse of the initial output signal Vnext overlaps with the duration of the ineffective level of the first output signal Gout1. Similarly, during another portion of the display panel's operation, the duration of the effective pulse of the first output signal Gout1 overlaps with the duration of the effective pulse of the initial output signal Vnext. This ensures that, during certain time periods, the shift register G normally provides the initial output signal to its next-level shift register G. The signal Vnext is active, while the first output signal Gout1 provided to the pixel circuit is inactive, allowing the next-stage shift register G to function normally without the pixel circuit refreshing its signal. During another time period, the shift register G provides its initial output signal Vnext, which is active, to its next-stage shift register G, and also provides the first output signal Gout1, which is active, allowing the next-stage shift register G to function normally while the pixel circuit refreshes its signal. Thus, during certain time periods, power consumption caused by signal refresh in the pixel circuit is reduced, contributing to low power consumption of the display panel. During other time periods, refreshing the signal in the pixel circuit ensures normal display and prevents screen flicker.

[0077] In one optional embodiment, when the pulse variation frequency F0 of the initial output signal Vnext is greater than the pulse variation frequency F1 of the first output signal Gout1, the pulse variation frequency F0 of the initial output signal Vnext can be an integer multiple of the pulse variation frequency F1 of the first output signal Gout1. For example, F0 can be equal to 2*F1 or 3*F1, etc. In other optional embodiments, the pulse variation frequency F0 of the initial output signal Vnext can also be a non-integer multiple of the pulse variation frequency F1 of the first output signal Gout1. For example, F0 can be equal to 3 / 2*F1 or 12 / 5*F1, etc. The embodiments of the present invention do not limit the relationship between F0 and F1.

[0078] It is understood that when the driving circuit of the display panel includes multiple shift registers G, the pulse change frequency F0 of the initial output signal Vnext of each shift register G can be greater than the pulse change frequency F1 of its first output signal Gout1. In this case, the driving frequency of the driving circuit can be greater than the signal refresh frequency of each pixel circuit. Alternatively, only some shift registers G may have an initial output signal Vnext pulse change frequency F0 greater than the pulse change frequency F1 of their first output signal Gout1. In this case, the initial output signal Vnext pulse change frequency F0 of the other part of the shift registers G can be less than or equal to the pulse change frequency F1 of their first output signal Gout1. Under the premise of meeting the diverse display needs of the display panel, this embodiment of the invention does not impose specific limitations in this regard.

[0079] In one exemplary embodiment, Figure 6 This is a driving timing diagram of a driving circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 2 , Figure 3 and Figure 6The display panel 100 may include a first display area A1 and a second display area A2. Pixel circuits 20 in rows 1 to 1 (i-1), rows 20 in rows 1+1 to 1n, and rows 20 in rows 1+1 to 1n are all second pixel circuits 22. Pixel circuits 20 in rows 1 to 1j are first pixel circuits 21, with the first pixel circuits 21 located in the first display area A1 and the second pixel circuits 22 located in the second display area A2. In this case, if the pulse variation frequency of the first output signal (Gout1i, ..., Gout1j) provided to the first pixel circuit 21 is Fc10, and the pulse variation frequency of the first output signal (Gout11, Gout12, ..., Gout1i-1, Gout1j+1, ..., Gout1n-1, Gout1n) provided to the second pixel circuit 22 is Fc20, then Fc10 > 10. Fc20 ensures that the pulse variation frequency of the initial output signals (Vnext1, Vnext2, ..., Vnexti-1, Vnextj+1, ..., Vnextn-1, Vnextn) output by the first-stage shift register G1 to the (i-1)th-stage shift register Gi-1 and the (j+1)th-stage shift register Gj+1 to the nth-stage shift register Gn is greater than the pulse variation frequency of their first output signals (Gout11, Gout12, ..., Gout1i-1, Gout1j+1, ..., Gout1n-1, Gout1n), while the pulse variation frequency of the initial output signals (Vnexti, ..., Vnextj) output by the ith-stage shift register Gi to the j-th-stage shift register Gj can be equal to the pulse variation frequency F11 of their first output signals (Gout1i, ..., Gout1j).Thus, during time period ta, the effective pulse times of the initial output signals (Vnext1, Vnext2, ..., Vnexti, Vnextj, ..., Vnextn-1, Vnextn) output by each shift register G are shifted sequentially. Simultaneously, the effective pulse times of the first output signals (Gout1i, ..., Gout1j) output by shift registers Gi to Gj are shifted sequentially, while the effective pulse times of the first output signals (Gout11, Gout12, ..., Gout1i-1, Gout1j+1, ..., Gout1n-1, Gout1n) output by shift registers G1 to Gi-1 and Gj+1 to Gn remain at an invalid level. During time period tb, the effective pulse times of the initial output signals (Vnexti, Vnextj, ..., Vnextn-1, Vnextn) output by each shift register G are shifted sequentially. The effective pulse times of the first output signals (Gout11, Gout12, ..., Gout1i, Gout1j, ..., Gout1n-1, Gout1n) and the first output signals (Gout11, Gout12, ..., Gout1i, Gout1j, ..., Gout1n-1, Gout1n) are shifted sequentially so that each first pixel circuit 21 can refresh its signal during the time period ta, while the second pixel circuit 22 cannot refresh its signal. However, during the time period tb, all pixel circuits 20 can refresh their signals. This ensures that the first pixel circuit 22 in the first display area A1 has a high signal refresh frequency, while the second pixel circuit 22 in the second display area A2 has a low signal refresh frequency. This ensures that the display panel 100 has a better display effect while also contributing to the low power consumption of the display panel 100, making the display panel 100 suitable for different application scenarios.

[0080] It is understood that the above description is only exemplified by the example of the first display area A1 being located between two second display areas A2. In the embodiments of the present invention, the first display area and the second display area can be designed according to actual display requirements. For example, when the display panel is in a static standby screen that only displays the time, the image in the area where the time is displayed changes in real time, and the pixel circuit in the area used to display the time needs to be refreshed in real time to ensure that the area can accurately display the time; while the image in other areas remains unchanged, and there is no need to refresh the pixel circuit in that area in real time. At this time, the refresh rate of the area used to display the time can be greater than the refresh rate of other areas, that is, the area used to display the time is the first display area, and the other areas are the second display areas.

[0081] In this embodiment, by using the initial output signal from the initial output unit as the input signal for other stages of shift registers, and the first output signal from the first output unit as the driving signal for the pixel circuit in the display panel, the initial output signals provided to other stages of shift registers and the first output signals provided to the pixel circuit can be independent of each other and do not affect each other. This ensures that while the shift registers can perform signal transmission and shifting, the polarity of the first output signal provided to the pixel circuit can be flexibly controlled. This allows the driving methods of pixel circuits in different rows of the display panel to be the same or different, thereby enabling the display panel to meet diverse display needs and broaden the application scenarios of the display panel. For example, different areas of the display panel can have different refresh rates.

[0082] It should be noted that since both the initial output unit and the first output unit receive signals from at least the first output node and the second output node, the signals from the first output node and the second output node can control the initial output signal output by the initial output unit and the first output signal output by the first output unit. The initial output signal and the first output signal can be the same or different, depending on the specific structure of the initial output unit and the first output unit. The following uses a typical example to illustrate the structure of the initial output unit and the first output unit.

[0083] In an optional embodiment, Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, as shown below. Figure 7 The initial output unit 120 includes a first initial output module 121 and a second initial output module 122; the first initial output module 121 receives at least the initial output control signal CK0 and the signal of the first output node N1, and controls the initial output signal Vnext; the second initial output module 122 receives at least the first voltage signal VGH and the signal of the second output node N2, and controls the initial output signal Vnext.

[0084] Specifically, the first initial output module 121 receives at least the initial output control signal CK0 and the signal from the first output node N1, enabling it to output the initial output signal Vnext under the control of these signals. The second initial output module 122 receives at least the first voltage signal VGH and the signal from the second output node N2, enabling it to output the initial output signal Vnext under the control of these signals. In this configuration, the first output node N1, the second output node N2, the first voltage signal VGH, and the initial output control signal CK0 determine the polarity and amplitude of the initial output signal Vnext.

[0085] In an exemplary embodiment, when the signal of the first output node N1 is at an active level, the first initial output module 121 can control the initial output signal Vnext to be consistent with the initial output control signal CK0, while when the signal of the second output node N1 is at an active level, the second initial output module 122 can control the initial output signal Vnext to be consistent with the first voltage signal VGH.

[0086] Optional, Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 8 As shown, the first initial output module 121 includes a first initial output transistor M01. The first terminal of the first initial output transistor M01 receives an initial output control signal CK0, and the second terminal outputs an initial output signal Vnext. The gate of the first initial output transistor M01 is connected to either a first output node N1 or a third output node N3. The first output node N1 can be directly connected to the third output node N3, meaning the signals of the first output node N1 and the third output node N3 are the same. Thus, the first initial output transistor M01 can be turned on or off under the control of the signal from the first output node N1. When the signal from the first output node N1 controls the first initial output transistor M01 to be turned on, the initial output control signal CK0 received at the first terminal of the first initial output transistor M01 can be transmitted to its second terminal, making the initial output control signal CK0 the initial output signal Vnext output from the second terminal of the first initial output transistor M01.

[0087] Accordingly, continue to refer to Figure 8 The second initial output module 122 may include a second initial output transistor M02. The first terminal of the second initial output transistor M02 is used to receive a first voltage signal VGH, and the second terminal of the second initial output transistor M02 is used to output an initial output signal Vnext. The gate of the second initial output transistor M02 is connected to the second output node N2. Thus, the second initial output transistor M02 can be turned on or off under the control of a signal from the second output node N2. When the second initial output transistor M02 is turned on under the control of a signal from the second output node N2, the first voltage signal VGH received at the first terminal of the second initial output transistor M02 can be transmitted to its second terminal, so that the first voltage signal VGH serves as the initial output signal Vnext output from the second terminal of the second initial output transistor M02.

[0088] In this configuration, the initial output control signal CK0 can be a pulse signal with a frequency of Fc0, allowing it to include both high and low levels. The first voltage signal VGH is a fixed signal; for example, it can be a high-level signal. This allows the first output node N1 to control the first initial output transistor M01 to turn on when the initial output control signal CK0 is high, and / or the second output node N2 to control the second initial output transistor M02 to turn on, ensuring that the initial output signal Vnext is consistent with the high level of the initial output control signal CK0 and / or the first voltage signal VGH. Conversely, when a low-level initial output signal Vnext is required, the first output node N1 can control the first initial output transistor M01 to turn on when the initial output control signal CK0 is low, ensuring that the initial output signal Vnext is consistent with the low level of the initial output control signal CK0. This configuration ensures that the initial output signal Vnext is a pulse signal with both high and low levels, thus meeting the driving requirements of the shift register G.

[0089] In another alternative embodiment, Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 9 As shown, the initial output unit 120 may further include an initial stabilization module 123. In this case, the first output node N1 and the third output node N3 are connected through the initial stabilization module 123, that is, the first output node N1 and the third output node N3 are different nodes. The initial stabilization module 123 can isolate the gate of the first initial output transistor M01 from the first output node N1, ensuring that the signals of the first output node N1 and the third output node N3 are relatively stable, preventing the fluctuation of the first output node N1 and / or the third output node N3 from affecting the accuracy of the initial output signal Vnext output by the first initial output transistor M01, thereby improving the working stability of the shift register G, and thus improving the display effect of the display panel.

[0090] Optionally, the initial stabilization module 123 may include a third initial output transistor M03; the first terminal of the third initial output transistor M03 is connected to the first output node N1, the second terminal of the third initial output transistor M03 is connected to the third output node N3, and the gate of the third initial output transistor M03 receives the second voltage signal VGL.

[0091] The second voltage signal VGL controls the third initial output transistor M03 to remain continuously on, ensuring that the signals at the first output node N1 and the third output node N3 are essentially consistent. However, because the on-state third initial output transistor M03 has a certain resistance, when the signal at the third output node N3, which is electrically connected to the first initial output transistor M01, changes, the third initial output transistor M03 can reduce the amount of change in the signal at the first output node N1 as a result of the changes in the signal at the third output node N3. Similarly, when the signal at the first output node N1 changes, the third initial output transistor M03 can also reduce the amount of change in the signal at the first output node N1 as a result of the changes in the signal at the third output node N3. Thus, by placing the third initial output transistor M03 between the first output node N1 and the third output node N3, the stability of the signals at both nodes can be guaranteed, thereby improving the stability of the initial output signal Vnext output by the first output transistor M01.

[0092] It is understood that the first initial output transistor M01, the second initial output transistor M02, and the third initial output transistor M03 can be either N-type or P-type transistors. For N-type transistors, they are turned on when the signal received at their gate is high and turned off when the signal received at their gate is low. For P-type transistors, they are turned on when the signal received at their gate is low and turned off when the signal received at their gate is high. The high and low levels of the signal at the transistor's gate are relative to the signal at the transistor's source, and the specific amplitude and polarity are not specifically limited in this embodiment. Therefore, for different types of transistors, when the same technical principle needs to be achieved, only the signal at the transistor's gate needs to be adaptively adjusted according to the transistor type. For ease of description, unless otherwise specified, this embodiment uses a P-type transistor as an example to illustrate the technical solution of this embodiment.

[0093] In an optional embodiment, when the second voltage signal VGL is a low-level signal, the low-level second voltage signal VGL can control the third initial transistor M03 to be in the on state, so that the signals of the first output node N1 and the third output node N3 are basically consistent.

[0094] Based on the above embodiments, the initial output unit 120 may further include an initial bootstrap capacitor C01. The initial bootstrap capacitor C01 may be electrically connected between the second terminal of the first initial output transistor M01 and the gate of the first initial output transistor M01. When the initial output signal Vnext of the second terminal of the first initial output transistor M01 transitions from a high level to a low level or from a low level to a high level, the gate signal of the first initial output transistor M01 may change accordingly due to the coupling level of the initial bootstrap capacitor C01. This ensures that the signal at the gate of the first initial output transistor M01 has a sufficiently high driving capability to drive the first initial output transistor M01 to turn on or off.

[0095] In addition, the initial output unit 120 may also include a holding capacitor C02, the first plate of which receives a first voltage signal VGH, and the second plate of which is electrically connected to the second output node N2, so that the holding capacitor C02 can store the signal of the second output node N2 to ensure that the signal of the second output node N2 can continuously control the second initial output transistor M02 to turn on or off.

[0096] Optional, Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 10 As shown, the first output unit 131 may include a first output module 1311 and a second output module 1312; the first output module 1311 receives at least the first output control signal CK1 and the signal of the first output node N1, and controls the first output signal Gout1; the second output module 1312 receives at least the first voltage signal VGH and the signal of the second output node N2, and controls the first output signal Gout1.

[0097] Specifically, the first output module 1311 receives at least the first output control signal CK1 and the signal from the first output node N1, enabling the first output module 1311 to output the first output signal Gout1 under the control of the signals from the first output control signal CK1 and the first output node N1; the second output module 1312 receives at least the first voltage signal VGH and the signal from the second output node N2, enabling the second output module 1312 to output the first output signal Gout1 under the control of the signals from the first voltage signal VGH and the second output node N2. At this time, the first output node N1, the second output node N2, the first voltage signal VGH, and the first output control signal CK1 can determine the polarity and amplitude of the first output signal Gout1.

[0098] In an exemplary embodiment, when the signal of the first output node N1 is at an active level, the first output module 1311 can control the first output signal Gout1 to be consistent with the first output control signal CK1, while when the signal of the second output node N1 is at an active level, the second output module 1312 can control the first output signal Gout1 to be consistent with the first voltage signal VGH.

[0099] Optional, Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of another shift register provided in an embodiment of the present invention, see reference. Figures 11-12 In any of the accompanying drawings, the first output module 1311 includes a first transistor M11; the first terminal of the first transistor M11 is used to receive a first output control signal CK1, and the second terminal of the first transistor M11 is used to output a first output signal Gout1. The gate of the first transistor M11 is connected to either the first output node N1 or the first node N11. The first output node N1 and the first node N11 are directly connected, meaning that the signals of the first output node N1 and the first node N11 are the same. Thus, the first transistor M11 can be turned on or off under the control of the signal from the first output node N1. When the signal from the first output node N1 controls the first transistor M11 to be turned on, the first output control signal CK1 received by the first terminal of the first transistor M11 can be transmitted to its second terminal, so that the first output control signal CK1 serves as the first output signal Gout1 output by the second terminal of the first transistor M11.

[0100] Accordingly, continue to refer to Figures 11-12 In any of the accompanying drawings, the second output module 1312 includes a second transistor M12; the first terminal of the second transistor M12 receives a first voltage signal VGH, the second terminal of the second transistor M12 is used to output a first output signal Gout1, and the gate of the second transistor M2 is connected to the second output node N2. Thus, the second transistor M12 can be turned on or off under the control of the signal from the second output node N2. When the signal from the second output node N2 controls the second transistor M12 to be turned on, the first voltage signal VGH received at the first terminal of the second transistor M12 can be transmitted to its second terminal, so that the first voltage signal VGH serves as the first output signal Gout1 output from the second terminal of the second transistor M12.

[0101] In this configuration, the first output control signal CK1 can be a pulse signal with a frequency of Fc1, allowing it to have both high and low levels. The first voltage signal VGH is a fixed signal; for example, it can be a high-level signal. This allows the first output node N1 to control the first transistor M11 to turn on when the first output control signal CK1 is high, and / or the second output node N2 to control the second transistor M12 to turn on, ensuring that the first output signal Gout1 is consistent with the high level of the first output control signal CK1 and / or the first voltage signal VGH. Conversely, when a low-level first output signal Gout1 is required, the first output node N1 can control the first transistor M11 to turn on when the first output control signal CK1 is low, ensuring that the first output signal Gout1 is consistent with the low level of the first output control signal CK1. This configuration ensures that the first output signal Gout1 is a pulse signal with both high and low levels, thus meeting the driving requirements of the shift register G.

[0102] In another alternative embodiment, Figure 13 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 13 As shown, the first output unit 131 may further include a first stabilization module 1313. In this case, the first output node N1 is connected to the first node N11 through the first stabilization module 1313, that is, the first node N11 and the first output node N1 are different nodes. The first stabilization module 1313 can isolate the first output node N1 and the first node N11, ensuring that the signals of the first output node N1 and the first node N11 are relatively stable, preventing the fluctuation of the first output node N1 and / or the first node N11 from affecting the accuracy of the first output signal Gout1 output by the first transistor M11, thereby improving the working stability of the shift register G, and thus improving the display effect of the display panel.

[0103] Optional, continue to refer to Figure 13 The first stabilization module 1313 may include a third transistor M13; the first terminal of the third transistor M13 is connected to the first output node N1, the second terminal of the third transistor M13 is connected to the first node N1, and the gate of the third transistor M13 receives the second voltage signal VGL.

[0104] The second voltage signal VGL controls the third transistor M13 to remain continuously on, ensuring that the signal at the first output node N1 is essentially consistent with the signal at the first node N11. However, because the on-state third transistor M13 has a certain resistance, when the signal at the first node N11, which is electrically connected to the first transistor M11, changes, the third transistor M13 can reduce the amount of change in the signal at the first output node N1. Similarly, when the signal at the first output node N1 changes, the third transistor M13 can also reduce the amount of change in the signal at the first node N11. Thus, by placing the third transistor M13 between the first output node N1 and the first node N11, the stability of the signals at both nodes can be guaranteed, thereby improving the stability of the first output signal Gout1 output by the first transistor M11.

[0105] In other alternative embodiments, such as Figure 14 As shown, when the initial output unit also includes an initial stabilization module 123, this initial stabilization module 123 can be reused as a first stabilization module 1313. In this case, the first node N1 and the third output node N3 are directly electrically connected, and the first node N1 can be connected to the first output node N1 through the initial stabilization module 123, so that the initial stabilization module 123 can also be used to stabilize the signal of the first node N1. In this way, the structure of the shift register G can be simplified, which is beneficial to reducing the size of the shift register G, and thus beneficial to the narrow bezel of the display panel.

[0106] Based on the above embodiments, refer to Figures 11-14 In any of the accompanying drawings, the first output unit 131 may further include a first bootstrap capacitor C1. The first bootstrap capacitor C1 may be electrically connected between the second terminal of the first transistor M11 and the gate of the first transistor M11. When the first output signal Gout1 of the second terminal of the first transistor M11 transitions from a high level to a low level or from a low level to a high level, the coupling effect of the first bootstrap capacitor C1 can control the gate signal of the first transistor M11 to change accordingly, thereby ensuring that the signal at the gate of the first transistor M11 has a sufficiently high driving capability to drive the first transistor M11 to turn on or off.

[0107] Based on the above embodiments, Figure 15 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 16 This is a schematic diagram of another shift register provided in an embodiment of the present invention, see reference. Figure 15 or Figure 16The control unit 110 may include a first control module 111 and a second control module 112. The first control module 111 may receive at least a first voltage signal VGH, an input signal Vin, an initial output control signal CK0 and a first clock signal XCK0 to control the signal of the first output node N1. The second control module 112 may receive at least a second voltage signal VGL and a first clock signal XCK0 to control the signal of the second output node N2.

[0108] Specifically, the first control module 111 can provide signals to the first output node N1 under the control of the first voltage signal VGH, the first clock signal XCK0, the initial output control signal CK0, and the input signal Vin, so that the first voltage signal VGH, the first clock signal XCK0, the initial output control signal CK0, and the input signal Vin can control the polarity and amplitude of the first output node N1; the second control module 112 can provide signals to the second output node N2 under the control of the second voltage signal VGL and the first clock signal XCK0, so that the second voltage signal VGL and the first clock signal XCK0 can control the polarity and amplitude of the second output node N2.

[0109] In an exemplary embodiment, when the first clock signal XCK0 is at an active level, the first control module 111 can transmit the input signal Vin to the first output node N1, so that the signal of the first output node N1 is consistent with the input signal Vin, and the second control module 112 can transmit the second voltage signal VGL to the second output node N2, so that the signal of the second output node N2 is consistent with the second voltage signal VGL.

[0110] In an optional embodiment, the first control module 111 may include a first control transistor M04, a second control transistor M07, and a third control transistor M08; the first terminal of the first control transistor M04 receives an input signal Vin, the second terminal of the first control transistor M04 is electrically connected to the first output node N1, and the gate of the first control transistor M04 receives a first clock signal XCK0; the first terminal of the second control transistor M07 receives a first voltage signal VGH, the second terminal of the second control transistor M07 is electrically connected to the first terminal of the third control transistor M08, the second terminal of the third control transistor M08 is connected to the first output node N1, the gate of the second control transistor M07 is electrically connected to the second output node N2, and the third control transistor M08 receives an initial output control signal CK0. At this time, the first clock signal XCK0 can control the first control transistor M04 to turn on or off. When the first clock signal XCK0 controls the first control transistor M04 to turn on, the first control transistor M04 can transmit the input signal Vin to the first output node N1, so that the signal of the first output node N1 is consistent with the input signal Vin. The signal of the second output node N2 can control the second control transistor M07 to turn on or off, and the initial output control signal CK0 can control the third control transistor M08 to turn on or off. When the signal of the second output node N2 controls the second control transistor M07 to turn on and the initial output control signal CK0 controls the third control transistor M08 to turn on, the first voltage signal VGH is transmitted to the first output node N1, so that the signal of the first output node N1 is consistent with the first voltage signal VGH.

[0111] Correspondingly, the second control module 112 may include a fourth control transistor M05 and a fifth control transistor M06. The first terminal of the fourth control transistor M05 receives a second voltage signal VGL, the second terminal of the fourth control transistor M05 is electrically connected to the second output node N2, and the gate of the fourth control transistor M05 receives a first clock signal XCK0. The first terminal of the fifth control transistor M06 receives the first clock signal XCK0, the second terminal of the fifth control transistor M06 is electrically connected to the second output node N2, and the gate of the fifth control transistor M06 is electrically connected to the first output node N1. At this time, the first clock signal XCK0 can control the fourth control transistor M05 to turn on or off, and the signal of the first output node N1 controls the fifth control transistor M06 to turn on or off. When the first clock signal XCK0 controls the fourth control transistor M05 to turn on, the fourth control transistor M05 can transmit the second voltage signal VGL to the second output node N2, so that the signal of the second output node N2 is consistent with the second voltage signal VGL. When the signal of the first output node N1 controls the fifth control transistor M06 to turn on, the signal of the second output node N2 is consistent with the first clock signal XCK0.

[0112] It is understandable that the first clock signal XCK0 can be a pulse signal, allowing it to include both high and low levels; the input signal Vin is the initial output signal Vnext of the previous stage shift register G, also allowing it to include both high and low levels; while the first voltage signal VGH and the second voltage signal VGL are both fixed signals, for example, the first voltage signal VGL can be a low-level signal and the second voltage signal VGH can be a high-level signal. The pulse frequencies of the first clock signal XCK0 and the initial output control signal CK0 can be the same, i.e., both pulse frequencies are Fc0. In this case, the phases of the first clock signal XCK0 and the initial output control signal CK0 are different; that is, when the first clock signal XCK0 is active, the initial output control signal CK0 is inactive; conversely, when the initial output control signal CK0 is active, the first clock signal XCK0 is inactive.

[0113] Specifically, when the second output node N2 requires a low-level signal, the first clock signal XCK0 can control the fourth control transistor M05 to turn on, and the low-level first voltage signal VGL can be transmitted to the second output node N2 through the turned-on fourth control transistor M05. And / or, when the first clock signal XCK0 is low, the signal of the first output node N1 controls the fifth control transistor M06 to turn on, so that the low-level XCK0 is transmitted to the second output node N2. When the second output node N2 requires a high-level signal, when the first clock signal XCK0 is high, the signal of the first output node N1 can control the fifth control transistor M06 to turn on, so that the high-level first clock signal XCK0 is transmitted to the second output node N2. Thus, the signal of the second output node N2 can be set according to actual needs.

[0114] Similarly, when the first output node N1 requires a high-level signal, the first clock signal XCK0 can control the first control transistor M04 to turn on when the input signal Vin is high. At this time, the signal of the first output node N1 can be synchronized with the high-level input signal Vin. Alternatively, while the signal of the second output node N2 controls the second control transistor M07 to turn on, the initial output control signal CK0 controls the third control transistor M08 to turn on, allowing the high-level first voltage signal VGH to be transmitted to the first output node N1. Conversely, when the first output node N1 requires a low-level signal, the first clock signal XCK0 can control the first control transistor M04 to turn on when the input signal Vin is low, allowing the first control transistor M04 to transmit the low-level input signal Vin to the first output node N1. This configuration allows for control of the signal of the first output node N1 as needed.

[0115] In one exemplary embodiment, taking a shift register in which all transistors are P-type transistors as an example, Figure 17 This is a driving timing diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 15 and Figure 17 Before stage t1, since the input signal Vin is high, when the first clock signal XCK0 controls the first control transistor M04 to turn on, the first control transistor M04 will transmit the high-level input signal Vin to the first output node N1, making the signal of the first output node N1 high. When the signal of the second output node N2 controls the second control transistor M07 to turn on and the initial output control signal CK0 controls the third control transistor M08 to turn on, the high-level first voltage signal VGH is transmitted to the first output node N1, which will also make the signal of the first output node N1 high, so that the signal of the first output node N1 controls the first initial output transistor M01 and the first transistor M11 to remain in the off state. Since the second voltage signal VGL is low, when the first clock signal XCK0 controls the fourth control transistor M05 to turn on, the low-level second voltage signal VGL will be transmitted to the second output node N2. And since the first output node N1 is not high, the fifth control transistor M06 will remain off. The transition of the first clock signal XCK0 will not affect the signal of the second output node N2, so that the second output node N2 remains a low-level signal. The signal of the second output node N2 can control the second initial output transistor M02 and the second transistor M12 to be on, so that the initial output signal Vnext and the first output signal Gout1 are consistent with the first voltage signal VGH, that is, the initial output signal Vnext and the first output signal Gout1 are high.

[0116] In stage t1, the input signal Vin goes low, and simultaneously the first clock signal XCK0 goes low. The initial output control signal CK0 and the first output control signal CK1 are both high. At this time, the first clock signal XCK0 controls both the first control transistor M04 and the fourth control transistor M05 to turn on. The low-level input signal Vin is transmitted to the first output node N1 through the first control transistor M04, causing the signal at the first output node N1 to go low. This low-level signal controls both the first initial output transistor M01 and the first transistor M11 to turn on, causing the initial output control signal CK0 to be transmitted to the second terminal of the first initial output transistor M01, and the first output control signal CK1 to be transmitted to the second terminal of the first transistor M11. Simultaneously, the second voltage signal VGL also passes through the first... The four control transistors M05 transmit to the second output node N2, causing the second output node N2 to also be at a low level. This low-level signal can simultaneously control the second initial output transistor M02 and the second transistor M12 to turn on, causing the high-level first voltage signal VGH to be transmitted to the second terminal of the second initial output transistor M02, and the first voltage signal VGH will also be transmitted to the second terminal of the second transistor M12. At this time, the signals at the second terminals of the first and second initial output transistors M02 are both high-level signals, causing the initial output signal Vnext to remain high. The signals at the second terminals of the first transistor M11 and the second terminals of the second transistor M12 are also high-level signals, causing the first output signal Gout1 to also remain high. Furthermore, since the signal at the first output node N1 is low, the fifth control transistor M6 is turned on. The low-level first clock signal XCK0 is transmitted to the second output node N2 through the fifth control transistor M06, keeping the second output node N2 at a low level. At the same time, since the signal at the second output node N2 is low, the second control transistor M07 is turned on. However, since the initial output control signal CK0 is high, the third control transistor M08 is turned off, and the first voltage signal VGH cannot be transmitted to the first output node N1. The signal at the first output node N1 is only consistent with the input signal Vin.

[0117] In stage t2, the input signal Vin becomes high, and the first clock signal XCK0 is also high. The initial output control signal CK0 and the first output control signal CK1 are both low. The first clock signal XCK0 controls the first control transistor M04 and the second control transistor M05 to turn off. The first output node N1 remains at the signal input in stage t1, that is, the signal of the first output node N1 remains low, which makes the fifth control transistor M06 turn on. The high-level first clock signal XCK0 is transmitted to the second output node N2 through the fifth control transistor M06, making the second output node N2 become high. The signal of the second output node N2 controls the second control transistor M07 to turn off, and the second voltage signal VGH cannot be transmitted to the first output node N1, making the signal of the first output node N1 remain low. At this time, the signal of the first output node N1 continues to control the first initial output transistor M01 and the first transistor M11 to remain on, while the second output node N1 controls the second initial output transistor M02 and the second transistor M12 to remain off. Thus, the initial output signal Vnext is consistent with the low-level initial output control signal CK0, and the first output signal Gout1 is consistent with the low-level first output control signal CK1.

[0118] In stage t3, the input signal Vin goes high, the first clock signal XCK0 goes low, the initial output control signal CK0 and the first output control signal CK1 both go high, the first control transistor M04 and the fourth control transistor M05 are both turned on, the signal of the first output node N1 is consistent with the high-level input signal Vin, and the signal of the second output node N2 is consistent with the low-level second voltage signal VGL, so that the signal of the first output node N1 controls the first initial output transistor M01 and the first transistor M11 to turn off, and the signal of the second output node N2 controls the second initial output transistor M02 and the second transistor M12 to turn on. At this time, the initial output signal Vnext and the first output signal Gout1 are both consistent with the high-level first voltage signal VGH.

[0119] After stage t3, the first output node N1 and the second output node N2 will remain at the signal level of stage t2 until the input signal Vin goes low again. Thus, when the initial output signal Vnext of the x-th stage shift register Gx is used as the input signal Vin of the y-th stage shift register Gy, the low-level signals of the initial output signals Vnext of the x-th stage shift register Gx and Vnext of the y-th stage shift register Gy can be shifted sequentially. Simultaneously, the low-level signals of the first output signal Gout1 of the x-th stage shift register Gx and the first output signal Gout1 of the y-th stage shift register Gy will also be shifted sequentially. This ensures that the low-level signals of the initial output signals Vnext and the first output signal Gout1 of each stage shift register G of the driving circuit can be shifted sequentially. By using the first output signal Gout1 of each stage shift register G to control the signal refresh time of each row of pixel circuits, line-by-line scanning of the pixel circuits in the display panel can be achieved.

[0120] It is understandable that when the low levels of the initial output signal Vnext and the first output signal Gout1 of each shift register G are shifted sequentially, this low-level signal is the effective level that can control the pixel circuit to refresh the signal; while when the effective level for the pixel circuit to refresh the signal is a high-level signal, such as... Figure 18 As shown, the output times of the high and low levels of the initial output control signal CK0 and the first output control signal CK1, as well as the types of transistors in the shift register, can be adaptively adjusted. This allows the high levels of the initial output signal Vnext and the first output signal Gout1 output by each level of shift register G to be shifted sequentially, enabling the high-level signal to scan each row of pixel circuits line by line.

[0121] Optional, see reference Figure 17 or Figure 18 When the first output signal Gout1 from the shift register can control the pixel circuit to refresh the signal, the pixel circuit may include a preset module. In this case, the first output signal Gout1 of the shift register in the driving circuit is the control signal of the preset module in the pixel circuit; and when the first output signal Gout1 is a valid pulse, the preset module is turned on; when the first output signal Gout1 is an invalid pulse, the preset module is turned off. Thus, the first output signal Gout1 can control the turning on and off of the preset module in the pixel circuit, thereby controlling the refresh time of the signal at the node electrically connected to the preset module.

[0122] In an alternative embodiment, such as Figure 17As shown, when the preset module includes a PMOS transistor and the first output signal is the control signal of the PMOS transistor, when the first output signal Gout1 is a low-level signal, the first output signal Gout1 is a valid pulse, controlling the PMOS transistor to turn on; and when the first output signal Gout1 is a high-level signal, the first output signal Gout1 is an invalid pulse, controlling the PMOS transistor to turn off.

[0123] In another alternative embodiment, such as Figure 18 As shown, when the preset module includes an NMOS transistor and the first output signal is the control signal of the NMOS transistor, when the first output signal Gout1 is a high-level signal, the first output signal Gout1 is a valid pulse, controlling the NMOS transistor to turn on; when the first output signal Gout1 is a low-level signal, the first output signal Gout1 is an invalid pulse, controlling the NMOS transistor to turn off.

[0124] It is understood that the preset module of the pixel circuit can be any module in the pixel circuit, and can be selected according to actual needs. The pixel circuit and its preset module mentioned in the embodiments of the present invention are described below by way of typical examples.

[0125] In an exemplary embodiment of the present invention, Figure 19 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 20 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, such as... Figure 19 As shown in Figure 20, the display panel includes a pixel circuit 20 and a light-emitting element 40. The pixel circuit 20 may include a driving module 210, a data writing module 220, a reset module 230, and a compensation module 240. The driving module 210 can selectively provide a driving current to the light-emitting element 40 to drive it to emit light. The data writing module 220 is connected to the first terminal of the driving module 210 and provides a data signal Vdata to the driving module 210, enabling the driving module 210 to generate a driving current to drive the light-emitting element 40 to emit light based on the data signal Vdata. The reset module 230 is connected to the control terminal of the driving module 210 and provides a reset signal to the driving module 210 to reset it. The compensation module 240 is connected between the control terminal and the second terminal of the driving module 210 to compensate for the data signal Vdata provided by the data writing module 220 to the driving module 210, ensuring that the driving module 210 can provide an accurate driving current to the light-emitting element 40 and control the accuracy of the light emission of the light-emitting element 40.

[0126] Optionally, since the light-emitting element 40 is typically a current-driven element, and the data signal Vdata provided by the data writing module 220 is typically a voltage signal, by setting a driving transistor T1 in the driving module 210, the data signal Vdata provided by the data writing module 220 can be written to the gate of the driving transistor T1. This allows the driving transistor T1 to generate a corresponding driving current based on the signal at its gate and provide it to the light-emitting element 40, driving the light-emitting element 40 to emit light at the corresponding brightness. At this time, one of the source and drain of the driving transistor T1 receives a positive power supply signal PVDD, and the other is coupled to the anode of the light-emitting element 40. The cathode of the light-emitting element 40 can receive a negative power supply signal PVEE. Thus, there is a voltage difference between the positive power supply signal PVDD and the negative power supply signal PVEE, forming a current path. This allows the driving transistor T1 to generate a driving current and provide it to the light-emitting element 40, driving the light-emitting element 40 to emit light.

[0127] It is understandable that, such as Figure 19 As shown, the active layer material of the driving transistor T1 in the driving module 210 may include low-temperature polycrystalline silicon, which gives it a high carrier mobility, thereby meeting the requirements of high response speed and low power consumption. In this case, the driving transistor T1 can be a PMOS transistor. In other optional embodiments, such as Figure 20 As shown, the active layer material of the driving transistor T1 can also include an oxide semiconductor material. In this case, the driving transistor T1 can be an NMOS transistor. Provided that the core inventive points of this embodiment are achieved, this embodiment does not specifically limit the material and type of the driving transistor T1.

[0128] Correspondingly, the data writing module 220 can be connected to the first terminal of the driving transistor T1 to provide a data signal Vdata to the driving transistor T1; the compensation module 230 can be connected between the gate and the second terminal of the driving transistor T1 to compensate for the threshold voltage of the driving transistor T1; and the reset module 240 can be connected to the gate of the driving transistor T1 to provide a reset signal Vref to the gate of the driving transistor T1 and reset the gate of the driving transistor T1.

[0129] The control terminal of the data writing module 220 can receive a first scan signal S1, which controls the opening and closing of the data writing module 220; the control terminal of the compensation module 230 can receive a second scan signal S2, which controls the opening and closing of the compensation module 230; and the control terminal of the reset module 240 receives a third scan signal S3, which controls the opening and closing of the reset module 240.

[0130] When the third scan signal S3 controls the reset module 240 to start, the reset signal Vref can be transmitted to the gate of the driving transistor T1 to reset the gate of the driving transistor T1, thereby clearing the data signal Vdata provided to the gate of the driving transistor T1 in the previous driving cycle and ensuring accuracy for subsequent writing of the data signal Vdata.

[0131] When the first scan signal S1 controls the data writing module 220 to be turned on, the data signal Vdata can be written to the first terminal of the driving transistor T1 through the data writing module 220 to refresh the signal of the first terminal of the driving transistor T1. If the driving transistor T1 is turned on at this time, and the second scan signal S2 controls the compensation module 230 to be turned on, the data signal Vdata can also be provided to the second terminal of the driving transistor T1 through the driving transistor T1, and to the gate of the driving transistor T1 through the compensation module 230, and the threshold voltage Vth of the driving transistor T1 is compensated to the gate of the driving transistor T1 so as to refresh the signals of the gate and the second terminal of the driving transistor T1, so that the driving current generated by the driving transistor T1 is independent of its threshold voltage Vth.

[0132] In an exemplary embodiment, the data writing module 220 may include a data writing transistor T2, the first terminal of which receives a data signal Vdata, the second terminal of which is electrically connected to the first terminal of a driving transistor T1, and the gate of which receives a first scan signal S1, such that the first scan signal S1 controls the data writing transistor T2 to turn on or off; the compensation module 230 includes a compensation transistor T3, the first terminal of which is electrically connected to the second terminal of a driving transistor T1, and the second terminal of which is electrically connected to the gate of a driving transistor T1, and the compensation transistor T3 receives a second scan signal S2, such that the second scan signal S2 controls the compensation transistor T3 to turn on or off; the reset module 240 includes a reset transistor T4, the first terminal of which receives a reset signal Vref, the second terminal of which is electrically connected to the gate of a driving transistor T1, and the gate of which receives a third scan signal S3, such that the third scan signal S3 controls the reset transistor T4 to turn on or off.

[0133] Based on the above embodiments, the pixel circuit 20 may further include an initialization module 250, which is connected to the anode of the light-emitting element 40 and is used to provide an initialization signal Vini to the light-emitting element 40 to initialize the anode of the light-emitting element 40. The initialization module 250 can be turned on or off under the control of the fourth scan signal S4, and when the fourth scan signal S4 controls the initialization module 250 to be turned on, the initialization signal Vini can be provided to the anode of the light-emitting element 40.

[0134] In an exemplary embodiment, the initialization module 250 may include an initialization transistor T5, the first terminal of the initialization transistor T5 receiving an initialization signal Vini, the second terminal of the initialization transistor T5 being electrically connected to the anode of the light-emitting element 40, and the gate of the initialization transistor T5 receiving a fourth scan signal S4, such that the fourth scan signal S4 can control the initialization transistor T5 to be turned on or off.

[0135] Based on the above embodiments, the pixel circuit 20 may further include a light-emitting control module, which may include a first light-emitting control module 260 and a second light-emitting control module 270. The first light-emitting control module 260 and the second light-emitting control module 270 can control the current path between the positive power signal PVDD and the negative power signal PVEE, thereby controlling the time when the driving transistor T1 provides driving current to the light-emitting element 40. The first light-emitting control module 260 and the second light-emitting control module 270 can be turned on or off under the control of the light-emitting control signal EM. When the light-emitting control signal EM controls the first light-emitting control module 260 and the second light-emitting control module 270 to be turned on, the driving transistor T1 can generate driving current and provide the driving current to the light-emitting element 40 to drive the light-emitting element 40 to emit light.

[0136] In an exemplary embodiment, the first light-emitting control module 260 may include a first light-emitting control transistor T6, and the second light-emitting control module 270 may include a second light-emitting control transistor T7. The first terminal of the first light-emitting control transistor T6 receives a positive power supply signal PVDD, the second terminal of the first light-emitting control transistor T6 is electrically connected to the first terminal of the driving transistor T1, the first terminal of the second light-emitting control transistor T7 is electrically connected to the second terminal of the driving transistor T1, and the second terminal of the second light-emitting control transistor T7 is electrically connected to the anode of the light-emitting element 40. The gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T7 both receive a light-emitting control signal EM, so that the light-emitting control signal EM can control the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to be turned on or off simultaneously.

[0137] Based on the above embodiments, the pixel circuit 20 may further include a storage capacitor Cst, the first plate of which receives a fixed signal (e.g., a positive power supply signal PVDD), and the second plate is electrically connected to the gate of the driving transistor T1 to store the signal at the gate of the driving transistor T1.

[0138] In another embodiment of the present invention, Figures 21-24 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figures 21-24In any of the accompanying drawings, based on the above embodiments, the pixel circuit 20 may further include a bias adjustment module 280, which is connected to the first or second end of the driving module 210 and is used to provide a bias adjustment signal V0 to the driving module 210 to adjust the bias of the driving transistor T1 in the driving module 210.

[0139] In this embodiment, when the driving module 210 includes a driving transistor T1, the first terminal of the driving transistor T1 can be the first terminal of the driving module 210, and the second terminal of the driving transistor T1 can be the second terminal of the driving module 210. In this case, the bias adjustment module 280 can be electrically connected to either the first or second terminal of the driving transistor T1. Provided that bias adjustment of the driving transistor T1 can be achieved, this embodiment of the invention does not impose specific limitations on this aspect.

[0140] In an optional embodiment, the bias adjustment module 280 can be turned on or off under the control of the bias adjustment control signal SV. When the bias adjustment control signal SV controls the bias adjustment module 280 to be turned on, the bias adjustment signal V0 can be provided to the first and / or second poles of the driving transistor T1 to adjust the bias of the driving transistor T1.

[0141] In an exemplary embodiment, the bias adjustment module 280 may include a bias adjustment transistor T8. The first terminal of the bias adjustment transistor T8 receives a bias adjustment signal V0. The second terminal of the bias adjustment transistor T8 is electrically connected to the first or second terminal of the driving transistor T1. The gate of the bias adjustment transistor T8 receives a bias adjustment control signal SV, which enables the bias adjustment control signal SV to control the bias adjustment transistor T8 to turn on or off.

[0142] It should be noted that, Figures 19-24 The present invention provides only a few exemplary pixel circuit structures, but does not include all of them. Provided that the core inventive points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not limit the specific structure of the pixel circuit.

[0143] Based on the aforementioned pixel circuits, the driving circuit in this embodiment can provide control signals to any one of the following modules: data writing module 220, compensation module 230, reset module 240, initialization module 250, light emission control module (first light emission control module 260 and second light emission control module 270), and bias adjustment module 280. This allows the preset module of the pixel circuit 200 to be any one of these modules, i.e., the first output signal of the driving circuit can be any one of the following: first scan signal S1, second scan signal S2, third scan signal S3, fourth scan signal S4, light emission control signal EM, and bias adjustment control signal SV. Taking the first scan signal S1, which controls the data writing module 220 to turn on or off, as an example, the driving principle of the pixel circuit 200 will be described below.

[0144] Reference Figure 2 and Figure 19 (or Figures 20-24(As shown in any of the attached figures), shift registers G at different levels provide a first output signal Gout1 to the pixel circuits 20 in different rows to control the data writing module 220 in each row of pixel circuits 20 to turn on or off. Taking the x-th level shift register and the y-th level shift register as examples, when it is necessary to control the data writing module 220 to provide a data signal Vdata to the driving module 210, after the effective pulse of the input signal Vin received by the x-th level shift register, the x-th level shift register can be controlled to output an effective pulse of the first output signal Gout1 to the pixel circuit 20 in the x-th row, so that the data writing module 220 of the pixel circuit 20 in the x-th row is turned on, and the data signal Vdata is written into the driving module 210 of the pixel circuit 20 in the x-th row; at the same time, the x-th level shift register can also output an initial output signal. The valid pulse of the initial output signal Vnext is sent to the y-th stage shift register, so that after the valid pulse of the initial output signal Vnext output by the x-th stage shift register, the driving module 210 of the pixel circuit 20 in the x-th row is turned off, and the valid pulse of the first output signal Gout1 of the y-th stage shift register is sent to the pixel circuit 20 in the y-th row, so that the data writing module 220 of the pixel circuit 20 in the y-th row is turned on, and the data signal Vdata is written into the driving module 210 of the pixel circuit 20 in the y-th row; at the same time, the y-th stage shift register can also output the valid pulse of the initial output signal Vnext. In this way, while each shift register G provides an effective level of the initial output signal Vnext to its next-level shift register, it can also provide a first output signal Gout1 to the data writing module 220 of the pixel circuit 20. This allows the first output signal Gout1 of the control data writing module 220 and the initial output signal Vnext provided to the next-level shift register to be signals with different polarities and amplitudes. This ensures the normal operation of the next-level shift register and refreshes the data signal Vdata of the driving module 210 in the pixel circuit 20. This avoids the situation where the input signal Vin required by the shift register and the control signal required by the pixel circuit 20 are different, which would affect the normal display and illumination of the display panel 100. Thus, the display panel 100 has a diversified structure and meets diversified functional requirements.

[0145] The situation is similar to the above case where the first output signal Gout1 output by the driving circuit 10 is a control signal for other modules in the pixel circuit 20, and will not be described in detail in this embodiment of the invention.

[0146] It is understood that the above description is merely an example of illustrating the operation of the shift register G and the driving process of the first output signal Gout1 output by the shift register to the preset module in the pixel circuit 20, with the pulse frequency Fc0 of the initial output control signal CK0 being the same as the pulse frequency Fc1 of the first output control signal CK1. In other embodiments of the present invention, during at least a portion of the time period of the display panel operation, the pulse change frequency Fc0 of the initial output control signal CK0 may be different from the pulse change frequency Fc1 of the first output control signal CK1, i.e., Fc0 ≠ Fc1.

[0147] In an optional embodiment, Figure 25 This is another driving timing diagram of a shift register provided in an embodiment of the present invention, such as... Figure 25 As shown, when the pulse change frequency of the initial output control signal CK0 is Fc0 and the pulse change frequency of the first output control signal CK1 is Fc1, Fc0 can be greater than Fc1.

[0148] Specifically, with Figure 16 Taking the shift register shown as an example, in conjunction with the reference... Figure 16 and Figure 25 Since the signal of the first output node N1 can simultaneously control the initial output signal Vnext output by the first initial output module 121 and the first output signal Gout1 output by the first output module 1311, when the signal of the first output node N1 is at an effective level, the first initial output module 121 can make the initial output signal Vnext consistent with the initial output control signal CK0, and the first output module 1311 can make the first output signal Gout1 consistent with the first output control signal CK1. Therefore, when the pulse change frequency Fc0 of the initial output control signal CK0 is greater than the pulse change frequency Fc1 of the first output control signal CK1 (i.e., the pulse period of the initial output control signal CK0 is less than the pulse period of the first output control signal CK1), the pulse change frequency of the initial output signal Vnext will be greater than the pulse change frequency of the first output signal Gout1 (i.e., the pulse period of the initial output signal Vnext will be less than the pulse period of the first output signal Gout1). As a result, the number of effective pulses of the initial output signal Vnext will be greater than that of the first output signal Gout1 within a certain period of time. This ensures that even if the pixel circuit 20 electrically connected to the shift register G does not need to refresh the signal during this period of time, the initial output signal Vnext output by the shift register G can still control the shift register electrically connected to its initial output unit 120 to work normally, thus ensuring that the display panel can display the image normally.

[0149] In another alternative embodiment, Figure 26This is another driving timing diagram of a shift register provided in an embodiment of the present invention, such as... Figure 26 As shown, when the operation of the display panel includes a first time period t10 and a second time period t20, in the first time period t10, when the initial output control signal CK0 is a valid pulse, the first output control signal CK1 is a valid pulse; in the second time period t20, when the initial output control signal CK0 is a valid pulse, the first output control signal CK1 is an invalid pulse.

[0150] Thus, in the first time period t10, the pulse change frequency of the initial output control signal CK0 can be the same as the pulse change frequency of the first output control signal CK1. In the second time period t20, the pulse change frequency of the initial output control signal CK0 can be greater than the pulse change frequency of the first output control signal CK1. This ensures that the effective pulse time of the initial output signal Vnext in the first time period t10 is consistent with the effective pulse time of the first output signal Gout1. In the second time period t20, the initial output signal Vnext can include an effective level, while the first output signal Gout1 will remain at an ineffective level. Therefore, in the unprovided time period, the first output signal Gout1 and the initial output signal Vnext can be adaptively adjusted, so that the display panel can meet diverse functional requirements.

[0151] In other alternative embodiments, Figure 27 This is another driving timing diagram of a shift register provided in an embodiment of the present invention, such as... Figure 27 As shown, the operation of the display panel may also include a first mode and a second mode; in the first mode, the pulse change frequency of the first output control signal CK1-1 is Fc11, and in the second mode, the pulse change frequency of the first output control signal CK1-2 is Fc12; wherein, Fc11≠Fc12.

[0152] It is understandable that during the operation of the display panel, the display panel can have different operating modes. For example, the display panel may include a first mode and a second mode. The refresh rate and / or display brightness of the display panel in the first mode may be different from those in the second mode, so that the display panel can meet different display requirements.

[0153] The refresh rate of the display panel is the frequency at which data signals are written to the gates of the driving transistors in the pixel circuit of the display panel. Typically, the time of one frame can include a data writing frame and a hold frame. That is, the operation of the pixel circuit can include a data writing frame and a hold frame. In the data writing frame, the signal of the gate of the driving transistor in the pixel circuit can be refreshed to clear the data signal written to the gate of the driving transistor in the pixel circuit in the time of the previous frame, and write the data signal corresponding to the current frame to the gate of the driving transistor in the pixel circuit. In the hold frame, the gate signal of the driving transistor in the pixel circuit remains unchanged until the data writing frame of the next frame is entered.

[0154] For example, when the display panel maintains the same display content for a long period of time, such as when the display panel is in standby mode, the display panel can have a lower refresh rate, that is, the frame duration is longer during the operation of the pixel circuit. Therefore, the gate signal of the driving transistor in the pixel circuit does not need to be refreshed for a longer period of time, thereby reducing the power consumption caused by data refresh and thus contributing to the low power consumption of the display panel. When the image displayed on the display panel changes in real time, such as when the display panel is in video display mode, the display panel can have a higher refresh rate, that is, the frame duration is shorter during the operation of the pixel circuit. Therefore, the gate signal of the driving transistor needs to be refreshed in real time. This ensures that the light-emitting element emits light accurately when the driving transistor generates a driving current based on its gate signal to drive the light-emitting element to emit light. This helps to improve the screen flicker caused by the display panel when displaying images and improves the smoothness of the displayed image.

[0155] Since the pulse change frequency of the first output control signal CK1 can control the effective pulse change frequency of the first output signal Gout1 output by the shift register, and the first output signal Gout1 can control the signal refresh frequency at the corresponding node in the pixel circuit, when the first output control CK1 has different pulse change frequencies in different modes, the first output signal Gout1 can also have different pulse change frequencies, so that the signal refresh frequency at the corresponding node in the pixel circuit is different in different modes to meet the different display requirements of the display panel.

[0156] Optionally, in the first mode, the pulse variation frequency of the first output control signal CK1-1 is Fc11, and the pulse variation frequency of the first output signal Gout1-1 is Fs1; in the second mode, the pulse variation frequency of the first output control signal CK1-2 is Fc12, and the pulse variation frequency of the first output signal Gout1-2 is Fs12, and Fc11≠Fc12 and Fs11≠Fs12, then (Fc11-Fc12)×(Fs11-Fs12)>0, so that the first output signal Gout1 increases as the pulse variation frequency of the first output control signal CK1 increases, and conversely, the first output signal Gout1 decreases as the pulse variation frequency of the first output control signal CK1 decreases, thereby ensuring that the pulse variation frequency of the first output signal Gout1 is consistent with the pulse variation frequency of the first output control signal CK1.

[0157] Optionally, when the first output signal Gout1 is a signal that controls the preset module in the pixel circuit to turn on or off, and the operation of the pixel circuit includes a data writing frame and a holding frame, the preset module can be a module that is turned on in the data writing frame and turned off in the holding frame.

[0158] For example, with Figure 21 Taking the pixel circuit 20 shown as an example, in conjunction with the reference... Figure 21 and Figure 27 During the non-light-emitting phase of the data writing frame, the reset module 240 can be turned on to provide a reset signal to the gate of the driving transistor T1, resetting the gate of the driving transistor T1. After resetting the gate of the driving transistor T1, the data writing module 220 and the compensation module 230 can be turned on, allowing the data signal to be written to the gate of the driving transistor T1 through the data writing module 220, the driving transistor T1, and the compensation module 230, and compensating the threshold voltage Vth of the driving transistor T1 to its gate. During the light-emitting phase of the data writing frame, the first light-emitting control module 260 and the second light-emitting control module 230 can be turned on. The second light-emitting control module 270 is turned on, causing the driving transistor T1 to generate a driving current, which is provided to the light-emitting element 40, driving the light-emitting element 40 to emit light. During the non-light-emitting phase of the hold frame, the bias adjustment module 280 can be turned on, while other modules are turned off, allowing the bias adjustment signal to be used to adjust the bias of the driving transistor T1. During the non-light-emitting phase of the hold frame, only the first light-emitting control module 260 and the second light-emitting control module 270 are turned on, while other modules are turned off, causing the driving transistor T1 to generate a driving current, which is provided to the light-emitting element 40, driving the light-emitting element 40 to emit light. Thus, the modules that are turned on in the data write frame and turned off in the hold frame can include any one of the reset module 240, the compensation module 230, and the data write module 220.

[0159] Optionally, in the first mode, the data refresh frequency of the pixel circuit is Fp1, and in the second mode, the data refresh frequency of the pixel circuit is Fp2; wherein, Fp1≠Fp2.

[0160] For example, with Figure 21 The pixel circuit 20 shown, and Figure 16 Taking the shift register shown as an example, and referring to the reference... Figure 16 , Figure 21 and Figure 27 The data refresh frequencies of the pixel circuit 20 differ between the first mode and the second mode, resulting in different data refresh intervals and, consequently, different hold frame durations for the pixel circuit 20. When the first output signal Gout1 controls the data writing module 220 in the pixel circuit 20 to be turned on or off, the first output control signal CK1, which is used to control the first output control signal CK1 to have different pulse variation frequencies when the display panel is in different modes, is output by the first output module 1311 receiving the first output control signal CK1 with different pulse variation frequencies. For example, in the first mode, the first output control signal CK1 has a higher pulse variation frequency Fc11, resulting in a shorter effective pulse interval time for the first output signal Gout1-1 and a shorter start-up interval for the data writing module 220. After the data writing module 220 starts up and provides the data signal Vdata of the previous frame to the driving module 210, the data writing module 220 will start up again after an interval t11, so that the data signal Vdat of the current frame can be provided to the driving module 210. This allows the data signal Vdata provided to the driving module 210 to be refreshed in a shorter interval, resulting in a higher data refresh frequency Fp1 for the pixel circuit 20. In the second mode, the first output control signal CK1 has a lower pulse variation frequency Fc12, resulting in a shorter effective pulse interval time for the first output signal Gout1-1 and a shorter start-up interval for the data writing module 220. The effective pulse interval time of out1-2 is relatively long, and the opening interval time of the data writing module 220 is also relatively long. After the data writing module 220 is turned on and provides the data signal Vdata of the previous frame to the driving module 210, the data writing module 220 will be turned on again after an interval of t12, so that the data signal Vdat of the current frame can be provided to the driving module 210 to refresh the data signal Vdata provided to the driving module 210, so that the pixel circuit 20 has a lower data refresh frequency Fp2. In this way, by making the first output control signal CK1 have different pulse change frequencies in different modes, the pixel circuit 20 has different data refresh frequencies in different modes, which is beneficial to the low power consumption and high display quality of the display panel, enabling the display panel to meet diverse display needs.

[0161] It is understood that the data refresh frequency of the pixel circuit 20 is positively correlated with the pulse change frequency of the first output control signal CK1, i.e., the first output control signal. In an optional embodiment, when the display panel includes a first mode and a second mode, and in the first mode the data refresh frequency of the pixel circuit is Fp1 and the pulse change frequency of the first output control signal CK1 is Fc11, and in the second mode the data refresh frequency of the pixel circuit is Fp2 and the pulse change frequency of the first output control signal CK1 is Fc12, if Fc11 is greater than Fc12, then Fp1 is greater than Fp2, or if Fc11 is less than Fc12, then Fp1 is less than Fp2, i.e., (Fp1-Fp2) and (Fc11-Fc12) are positively correlated, thereby making (Fp1-Fp2)×(Fc11-Fc12)>0.

[0162] Optional, Figure 28 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 29 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 28 and Figure 29 When the display panel 100 includes a first pixel circuit 21 and a second pixel circuit 22, the driving circuit 10 may include a first shift register G10 and a second shift register G20; the first output signal Gout1 of the first shift register G10 is a control signal of a preset module in the first pixel circuit 21, and the first output signal Gout2 of the second shift register G20 is a control signal of a preset module in the second pixel circuit 22; wherein, the pulse change frequency of the first output control signal CK11 received by the first shift register G10 is Fct1, and the pulse change frequency of the first output control signal CK12 received by the second shift register G20 is Fct2, and Fct1≠Fct2.

[0163] It is understandable that, since the pulse change frequency of the first output signal Gout1 output by the shift register is related to the pulse change frequency of the first output control signal CK1 received by it, and the pulse change frequency of the first output signal Gout1 is usually the same as the pulse change frequency of the first output control signal CK1, when the pulse change frequency Fct1 of the first output control signal CK11 received by the first shift register G10 is different from the pulse change frequency Fct2 of the second output control signal CK12 received by the second shift register G20, the pulse change frequencies of the first output signal Gout1 output by the first shift register G10 and the first output signal Gout1 output by the second shift register G20 are different. That is, when the pulse change frequency of the first output signal Gout1 received by the preset module of the first pixel circuit 21 is Fs11 and the pulse change frequency of the first output signal Gout1 received by the preset module of the second pixel circuit 22 is Fs22, Fs11≠Fs22.

[0164] In an optional embodiment, when the preset module of the pixel circuit 20 is turned on, enabling the pixel circuit 20 to perform data refresh, by making the first shift register G10 receive the first output control signal CK11 and the second shift register G20 receive the first output control signal CK12 with different pulse change frequencies, the turn-on periods of the preset modules in the first pixel circuit 21 and the second pixel circuit 22 are different, thereby making the first pixel circuit 21 and the second pixel circuit 22 have different data refresh frequencies. That is, when the data refresh frequency of the first pixel circuit 21 is Fp11 and the data refresh frequency of the second pixel circuit 22 is Fp22, Fp11≠Fp22.

[0165] Correspondingly, since the pulse variation frequency of the first output signal Gout1 of the shift register is consistent with that of the first output control signal CK1 it receives, and the first output signal Gout1 is used to control the opening and closing of the preset module in the pixel circuit 20, the opening frequency of the preset module in the pixel circuit 20 is consistent with the pulse variation frequency of the first output signal Gout1. Therefore, the opening frequency of the preset module in the pixel circuit 20 is consistent with the pulse variation frequency of the first output control signal CK1, and the refresh frequency of the pixel circuit 20 is consistent with the pulse variation frequency of the first output control signal CK1. That is, the refresh frequency of the pixel circuit 20 will increase as the pulse variation frequency of the first output control signal CK1 increases. Thus, when (Fct1-Fct2) is positive, (Fp11-FP22) is also positive, or when (Fct1-Fct2) is negative, (Fp11-FP22) is also negative, that is, (Fp11-Fp22)×(Fct1-Fct2)>0.

[0166] In one exemplary embodiment, in conjunction with reference to Figure 28 and Figure 29 As shown, taking the first-stage shift register G1 as the first shift register G10 and the i-th-stage shift register Gi as the second shift register G20 as an example, when the pulse change frequency of the first output control signal CK11 received by the first-stage shift register G1 is greater than the pulse change frequency of the first output control signal CK12 received by the i-th-stage shift register Gi, the pulse change frequency of the first output signal Gout11 output by the first-stage shift register G1 will be greater than the pulse change frequency of the first output signal Gout1i output by the i-th-stage shift register G. At this time, the data of the first pixel circuit 21 receiving the first output signal Gout11 output by the first-stage shift register G1... The refresh frequency is greater than the data refresh frequency of the second pixel circuit 22 that receives the first output signal Gout1i from the i-th stage shift register Gi. At the same time, since the initial output control signal (CK01) received by the first stage shift register G1 is the same as the initial output control signal (CK01) received by the i-th stage shift register Gi, the initial output signal Vnext1 of the first stage shift register G1 can have the same pulse output frequency as the initial output signal Vnexti of the i-th stage shift register Gi. This ensures that both the first shift register G10 and the second shift register G20 in the driving circuit can work normally.

[0167] Optionally, when the display panel 100 includes a first display area A1 and a second display area A2, the first pixel circuit 21 can be located in the first display area A1, and the second pixel circuit 22 can be located in the second display area A2. In this case, since the pulse change frequency of the first output control signal CK11 received by the first shift register G10, which controls the opening or closing of the preset module in the first pixel circuit 21, is Ftc1, and the pulse change frequency of the first output control signal CK12 received by the second shift register G20, which controls the opening or closing of the preset module in the second pixel circuit 22, is Ftc2, the first pixel circuit 21 and the second pixel circuit 22 have different data refresh frequencies. That is, the data refresh frequency of the first pixel circuit 21 in the first display area A1 is different from the data refresh frequency of the second pixel circuit 20 in the second display area A2. Therefore, while meeting the normal display requirements of the display panel 100, the display panel 100 can also have lower power consumption, enabling the display panel 100 to meet diverse display needs.

[0168] It should be noted that, Figure 28The example provided only exemplifies the situation where the first pixel circuit 21 and the second pixel circuit 22 are located in different rows, and the first shift register G10 and the second shift register G20 are located on the same side of the display area 101, and the first shift register G10 and the second shift register G20 are cascaded shift registers. In this case, the first display area A1 and the second display area A2 are arranged along the columns of the pixel circuit 20. However, in other embodiments of the present invention, such as... Figure 30 As shown, at least a portion of the first pixel circuit 21 can be located in the same row as at least a portion of the second pixel circuit 22. In this case, the first display area A1 and the second display area A2 can be arranged along the row direction of the pixel circuit 20. The first shift register G10 and the second shift register G20 can be located on different sides of the display area 101, making the initial output signal Vnext output by the first shift register G10 and the initial output signal Vnext output by the second shift register G20 independent of each other. By controlling the first output control signal CK11 received by the first shift register G10 to be different from the second output control signal CK12 received by the second shift register G20, the first pixel circuit 21 and the second pixel circuit 22 can also have different data refresh frequencies. Therefore, under the premise of achieving the core inventive points of the embodiments of the present invention, the embodiments of the present invention do not limit the setting method of the first shift register G10 and the second shift register G20. For ease of description, the embodiments of the present invention are all referred to as... Figure 28 The following example illustrates the configuration of a shift register.

[0169] In an optional embodiment, Figure 31 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, to... Figure 16 Taking the shift register shown as an example, in conjunction with the reference... Figure 16 , Figure 28 and Figure 31If it is necessary to shift the initial output signal Vnext of each stage shift register G of the driving circuit 10 sequentially, and the first output signal Gout1 of each stage shift register G should also be shifted sequentially, then during the time period t0′, the first stage shift register G1 receives the first clock signal XCK01 as an effective level, so that the effective level of the start signal STV is transmitted to the first output node N1. The signal of the first output node N1 can control the first initial output unit 121 of the first stage shift register G1 to output the received initial output control signal CK01 as its initial output signal Vnext1, and control the first output unit 1311 of the first stage shift register G1 to output the received first output control signal CK111 as its first output signal Gout11. Since the initial output control signal CK01 and the first output control signal CK111 received by the first stage shift register G1 are both ineffective at this time, the initial output signal Vnext1 output by the first stage shift register G1 is not effective. Both next1 and the first output signal Gout11 are invalid. At the same time, the initial output signal Vnext1 of the first-stage shift register G1 is the input signal Vin of the second-stage shift register G2. This means that during this time period, the signal of the first output node N1 in the second-stage shift register G2 cannot control the first initial output unit 121 and the first output unit 1311 to be turned on. As a result, the initial output signal Vnext2 and the first output signal Gout12 of the second-stage shift register G2 are also invalid. The situation is similar for other shift registers (the i-th shift register Gi and the (i+1)-th shift register Gi+1). This means that the initial output signals Vnext (Vnexti, Vnexti+1) and the first output signals Gout1 (Gout1i, Gout1i+1) of the other shift registers (the i-th shift register Gi and the (i+1)-th shift register Gi+1) are also invalid.

[0170] During time interval t1′, the first-stage shift register G1 receives the first clock signal XCK01, which becomes invalid, and the start signal STV also becomes invalid. The signal of the first output node N1 remains the same as the signal in stage t0′, causing the first initial output unit 121 of the first-stage shift register G1 to continue outputting the received initial output control signal CK01 as its initial output signal Vnext1, and the first output unit 1311 of the first-stage shift register G1 to continue outputting the received first output control signal CK111 as its first output signal Gout11. At this time, since the initial output control signal CK01 and the first output control signal CK111 received by the first-stage shift register G1 both become valid, the initial output signal Vnext1 and the first output signal Gout11 output by the first-stage shift register G1 both become valid. Simultaneously, since the first-stage shift register G1... The initial output signal Vnext1 of the first stage shift register G1 is the input signal Vin of the second stage shift register G2. Therefore, the second stage shift register G2 should receive the first clock signal XCK02 as an active level, so that the signal of the first output node N1 in the second stage shift register G2 is consistent with the initial output signal Vnext1 of the first stage shift register G1 during this period. This ensures that the initial output signal Vnext2 of the second stage shift register G2 is consistent with the initial output control signal CK02 it receives, and that the first output signal Gout12 it outputs is consistent with the first output control signal CK112 it receives. In order to ensure that the initial output signals Vnext1 and Gout1 of the first stage shift register G1 and the second stage shift register G2 can be shifted sequentially, the initial output control signal CK02 and the first output control signal CK112 should be inactive during this period. Thus, during this time period, the initial output control signal CK01 received by the first-stage shift register G1 is different from the initial output control signal CK02 received by the second-stage shift register G2, and the first output control signal CK111 received by the first-stage shift register G1 is different from the first output control signal CK112 received by the second-stage shift register G2. However, the initial output control signal CK01 received by the first-stage shift register G1 is the same as the first clock signal XCK02 received by the second-stage shift register G2, and the first clock signal XCK01 received by the first-stage shift register G1 is the same as the initial output control signal CK02 received by the second-stage shift register G2.

[0171] During the time interval t2′, the initial output control signal CK01 and the first output control signal CK111 received by the first-stage shift register G1 are both at invalid levels, while the first clock signal XCK01 received by the first-stage shift register G1 becomes at an effective level, which makes the initial output control signal CK02 and the first output control signal CK112 received by the second-stage shift register G2 both at effective levels, and the initial output signal Vnext2 and the first output signal Gout12 of the second-stage shift register G2 are both at effective levels. During this time period, the initial output control signal CK01 received by the first-stage shift register G1 is different from the initial output control signal CK02 received by the second-stage shift register G2, and the first output control signal CK111 received by the first-stage shift register G1 is different from the first output control signal CK112 received by the second-stage shift register G2. However, the initial output control signal CK01 received by the first-stage shift register G1 is the same as the first clock signal XCK02 received by the second-stage shift register G2, and the first clock signal XCK01 received by the first-stage shift register G1 is the same as the initial output control signal CK02 received by the second-stage shift register G2. In this way, the initial output control signal CK01 of the first-stage shift register G1 can be multiplexed as the first clock signal XCK02 of the second-stage shift register G2, and the initial output control signal CK02 of the second-stage shift register G2 can be multiplexed as the first clock signal XCK01 of the first-stage shift register G1. This reduces the number of signals provided to each stage of the shift registers and the number of pins of the driver chip used to provide signals to each stage of the shift registers, thereby simplifying the structure of the driver chip and reducing its cost. At the same time, the non-display area 102 of the display panel 100 should also be provided with signal lines (37, 36, 32, 33, 34 and 35) for transmitting the first clock signal XCK0, the initial output control signal CK0, and the first output control signals CK111, CK112, CK121 and CK122. When the first clock signal XCK0 and the initial output control signal CK0 of different stages are multiplexed, the number of signal lines provided in the non-display area 102 can be reduced, which is beneficial to the narrow bezel of the display panel 100.

[0172] Correspondingly, during time interval ti′, the state of the i-th stage shift register Gi is similar to the state of the first-stage shift register G1 during time interval t1′, and the state of the (i+1)-th stage shift register Gi+1 is similar to the state of the second-stage shift register G1 during time interval t1′; during time interval ti+1′, the state of the i-th stage shift register Gi is similar to the state of the first-stage shift register G1 during time interval t2′, and the state of the (i+1)-th stage shift register Gi+1 is similar to the state of the second-stage shift register G1 during time interval t2′; therefore, the initial state of the i-th stage shift register Gi... The output control signal CK01 is multiplexed into the first clock signal XCK02 of the (i+1)th stage shift register Gi+1, and the initial output control signal CK02 of the (i+1)th stage shift register Gi+1 is multiplexed into the first clock signal XCK01 of the i-th stage shift register Gi. The initial output control signal CK01 of each shift register in odd-numbered stages is multiplexed into the first clock signal XCK02 of each shift register in even-numbered stages, and the initial output control signal CK02 of each shift register in even-numbered stages is multiplexed into the first clock signal XCK01 of each shift register in odd-numbered stages.

[0173] Furthermore, while ensuring that each level of shift register can output the initial output signal and the first output signal normally, it is also possible to make each odd-numbered shift register receive the same first output control signal, and each even-numbered shift register receive the same first output control signal.

[0174] In one exemplary embodiment, in conjunction with reference to Figure 32 and Figure 33When the display panel 100 includes a first shift register G10 and a second shift register G20, and the pulse change frequencies of the first output signal Gout1 (Gout11, Gout12) output by the first shift register G10 and the first output signal Gout1 (Gout1i, Gout1i+1) output by the second shift register G20 are different, if each odd-numbered shift register (G1, Gi) receives the same first output control signal (CK111, CK121), and each even-numbered shift register (G2, Gi+1) receives the same first output control signal (CK112, CK122), then during the period when each first shift register G10 sequentially outputs the effective level of the initial output signal Vnext and the first output signal Gout1 (i.e., the first time period t10), each odd-numbered shift register... The first output control signals (CK111, CK121) received by shift registers (G1, Gi) are consistent with their respective initial output control signals CK01, and the first output control signals (CK112, CK122) received by each even-numbered shift register (G2, Gi+1) are consistent with their respective initial output control signals CK02. Meanwhile, each second shift register G20 sequentially outputs the effective level of the initial output signal Vnext (i.e., the second time period t20), while the first output signal Gout1 output by each second shift register G20 remains continuously inactive. This allows the first output control signals (CK111, CK121) received by each odd-numbered shift register G1, Gi, and each even-numbered shift register (G2, Gi+1) to remain inactive. In this way, while reducing the signals supplied to each shift register, it is still possible to achieve different output states for the output signals of different shift registers. This ensures that the display panel meets diverse functional requirements while reducing the cost of the driver chip and the narrow bezel of the display panel.

[0175] It should be noted that the above-mentioned settings of the first output control signal, initial output control signal and first clock signal are all exemplary descriptions of the embodiments of the present invention. Under the premise that the core inventive points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not make specific limitations in this regard.

[0176] In an optional embodiment, Figure 34 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 34 As shown, the shift register G also includes a second output unit 132; the second output unit 132 is used to receive at least the signal from the first output node N1 and the signal from the second output node N2, and to control the second output signal Gout2.

[0177] Specifically, since the initial output unit 120, the first output unit 131, and the second output unit 132 all receive signals from the first output node N1 and the second output node N2, the signals from the first output node N1 and the second output node N2 can respectively control the initial output signal Vnext output by the initial output unit 120, the first output signal Gout1 output by the first output unit 131, and the second output signal Gout2 output by the second output unit 132. At this time, the initial output signal Vnext output by the initial output unit 120 serves as the input signal Vin to other stage shift registers, while the first output signal Gout1 and the second output signal Gout2 can both serve as control signals for preset modules in the pixel circuit. The second output signal Gout2 can be different from the first output signal Gout1, allowing the first output signal Gout1 and the second output signal Gout2 to be control signals for preset modules in pixels in different rows, or the first output signal Gout1 and the second output signal Gout2 to be control signals for different preset modules in the same pixel circuit. This reduces the number of shift registers in the driving circuit, thereby reducing the area occupied by the driving circuit. When the driving circuit is placed in the non-display area of ​​the display panel, this facilitates a narrower bezel for the display panel. The structure of the second output unit 132 may be the same as or different from that of the first output unit 131; this embodiment of the invention does not impose specific limitations on this.

[0178] In an optional embodiment, Figure 35 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 35 As shown, the second output unit 132 may include a third output module 1321 and a fourth output module 1322; the third output module 1321 receives at least the second output control signal CK2 and the signal of the first output node N1, and controls the second output signal Gout2; the fourth output module 1322 receives at least the first voltage signal and the signal of the second output node, and controls the second output signal.

[0179] Specifically, the third output module 1321 receives at least the second output control signal CK2 and the signal from the first output node N1, enabling the third output module 1321 to output the second output signal Gout2 under the control of the signals from the second output control signal CK2 and the first output node N1; the fourth output module 1322 receives at least the first voltage signal VGH and the signal from the second output node N2, enabling the fourth output module 1322 to output the second output signal Gout2 under the control of the signals from the first voltage signal VGH and the second output node N2. At this time, the first output node N1, the second output node N1, the first voltage signal VGH, and the second output control signal CK2 can determine the polarity and amplitude of the first output signal Gout1.

[0180] In an exemplary embodiment, when the signal of the first output node N1 is at an active level, the third output module 1321 can control the second output signal Gout2 to be consistent with the second output control signal CK2, while when the signal of the second output node N1 is at an active level, the fourth output module 1322 can control the second output signal Gout2 to be consistent with the first voltage signal VGH.

[0181] Optional, Figure 36 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 36 As shown, the third output module 1321 includes a fourth transistor M21. The first terminal of the fourth transistor M21 is used to receive the second output control signal CK2, and the second terminal of the fourth transistor M21 is used to output the second output signal Gout2. The gate of the fourth transistor M21 is connected to either the first output node N1 or the second node N12. The first output node N1 and the second node N12 are directly connected, meaning that the signals of the first output node N1 and the second node N12 are the same. Thus, the fourth transistor M21 can be turned on or off under the control of the signal from the first output node N1. When the signal from the first output node N1 controls the fourth transistor M21 to be turned on, the second output control signal CK2 received by the first terminal of the fourth transistor M21 can be transmitted to its second terminal, so that the second output control signal CK2 is used as the second output signal Gout2 output by the second terminal of the fourth transistor M21.

[0182] In another alternative embodiment, Figure 37 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 37As shown, the second output unit 132 may further include a second stabilization module 1323. In this case, the first output node N1 is connected to the second node N11 through the second stabilization module 1323, that is, the second node N12 and the first output node N1 are different nodes. The second stabilization module 1323 can isolate the first output node N1 and the second node N12, ensuring that the signals of the first output node N1 and the second node N12 are relatively stable, preventing the fluctuation of the first output node N1 and / or the second node N12 from affecting the accuracy of the second output signal Gout2 output by the fourth transistor M21, thereby improving the working stability of the shift register G, and thus improving the display effect of the display panel.

[0183] Optional, continue to refer to Figure 37 The second stabilization module 1323 may include a sixth transistor M23; the first terminal of the sixth transistor M23 is connected to the first output node N1, the second terminal of the sixth transistor M23 is connected to the second node N2, and the gate of the sixth transistor M23 receives the second voltage signal VGL.

[0184] The second voltage signal VGL controls the sixth transistor M23 to remain continuously on, ensuring that the signal at the first output node N1 is essentially consistent with the signal at the second node N12. However, because the on-state sixth transistor M23 has a certain resistance, when the signal at the second node N12, which is electrically connected to the fourth transistor M21, changes, the sixth transistor M23 can reduce the amount of change in the signal at the first output node N1 as a result of the change in the signal at the second node N1. Similarly, when the signal at the first output node N1 changes, the sixth transistor M23 can also reduce the amount of change in the signal at the second node N12 as a result of the change in the signal at the first output node N1. Thus, by placing the sixth transistor M23 between the first output node N1 and the second node N12, the stability of the signals at both nodes can be guaranteed, thereby improving the stability of the first output signal Gout1 output by the first transistor M11.

[0185] Based on the above embodiments, continue to refer to Figure 36 or Figure 37The fourth output module 1322 includes a fifth transistor M22. The first terminal of the fifth transistor M22 receives a first voltage signal VGH, and the second terminal of the fifth transistor M22 is used to output a second output signal Gout2. The gate of the fifth transistor M22 is connected to the second output node N2. Thus, the fifth transistor M22 can be turned on or off under the control of the signal from the second output node N2. When the signal from the second output node N2 controls the fifth transistor M22 to be turned on, the first voltage signal VGH received by the first terminal of the fifth transistor M22 can be transmitted to its second terminal, so that the first voltage signal VGH serves as the second output signal Gout2 output from the second terminal of the fifth transistor M22.

[0186] In addition, refer to Figure 36 or Figure 37 The second output unit 132 may further include a second bootstrap capacitor C2. The bootstrap capacitor C2 may be electrically connected between the second terminal of the fourth transistor M21 and the gate of the fourth transistor M21. When the second output signal Gout2 of the second terminal of the fourth transistor M21 transitions from a high level to a low level or from a low level to a high level, the gate signal of the fourth transistor M21 may change accordingly due to the coupling effect of the second bootstrap capacitor C2. This ensures that the signal at the gate of the fourth transistor M21 has a sufficiently high driving capability to drive the fourth transistor M21 to turn on or off.

[0187] The second output control signal CK2 can be a pulse signal with a pulse variation frequency of Fc2, allowing it to include both high and low levels. When a high-level second output signal Gout2 is required, the first output node N1 can control the fourth transistor M21 to turn on when CK2 is high, and / or the second output node N2 can control the fifth transistor M22 to turn on, ensuring that Gout2 is consistent with the high level of CK2 and / or the first voltage signal VGH. Conversely, when a low-level second output signal Gout2 is required, the first output node N1 can control the fourth transistor M21 to turn on when CK2 is low, ensuring that Gout2 is consistent with the low level of CK2. This configuration allows the second output signal Gout2 to be a pulse signal with both high and low levels, thus satisfying the driving requirements of the shift register G.

[0188] It is understood that the pulse change frequency Fc2 of the second output control signal CK2 can be the same as or different from the pulse change frequency Fc1 of the first output control signal CK1, so that the pulse change frequency of the first output signal Gout1 and the pulse change frequency of the second output signal Gout2 can be the same as or different. This embodiment of the invention does not make specific limitations in this regard.

[0189] For example, with Figure 36 Taking the shift register shown as an example where all transistors are P-type transistors, and the pulse change frequencies of the first output control signal CK1 and the second output control signal CK2 are the same, Figure 38 This is another driving timing diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 36 and Figure 38 From time T1′ to time T2′, both the input signal Vin and the first clock signal XCK0 are at a high level, making the signal of the first output node N1 an effective level that controls the first initial output transistor M01, the first transistor M11, and the fourth transistor M21 to turn on. This makes the initial output control signal CK0 output by the first initial output transistor M01 serve as the initial output signal Vnext, the first output control signal CK1 output by the first transistor M11 serve as the first output signal Gout1, and the second output control signal CK2 output by the fourth transistor M21 serve as the second output signal Gout2. This ensures that the initial output signal Vnext is consistent with the high level of the initial output control signal CK0, the first output signal Gout1 is consistent with the high level of the first output control signal CK1, and the second output signal Gout2 is consistent with the high level of the second output control signal CK2.

[0190] Between time T2′ and T8′, although the input signal Vin becomes high, the high level of the input signal Vin cannot be transmitted to the first output node N1 because the first clock signal XCK0 remains high, thus keeping the signal of the first output node N1 at an effective level.

[0191] At time T3′, the initial output control signal CK0 goes low, causing the initial output signal Vnext to go low as well. Simultaneously, the first output control signal CK1 goes low, causing the first output signal Gout1 to go low as well. At time T4′, the first output control signal CK1 goes high, causing the first output signal Gout1 to go high as well. At time T5′, the second output control signal CK2 goes low, causing the second output signal Gout2 to go low as well. At time T6′, the initial output control signal CK0 goes high, causing the initial output signal Vnext to go high as well. At time T7′, the second output control signal... When CK2 jumps to a high level, the second output signal Gout2 also jumps to a high level. At time T8′, the first clock signal XCK0 jumps to a low level again, allowing the high-level input signal Vin to be transmitted to the first output node N1. The signal of the first output node N1 controls the first initial output transistor M01, the first transistor M11, and the fourth transistor M21 to turn off, so that the initial output signal Vnext no longer changes with the initial output control signal CK0, the first output signal Gout1 no longer changes with the first output control signal CK1, and the second output signal Gout2 no longer changes with the second output control signal CK2, until the input signal Vin goes low again. In this way, the low-level time of the initial output signal Vnext can overlap with the low-level time of the first output signal Gout1 and the second output signal Gout2. The low levels of the first output signal Gout1 and the second output signal Gout2 are shifted sequentially, so that the first output signal Gout1 and the second output signal Gout2 can control the signal refresh of the pixel circuits in different rows respectively. Therefore, it is not necessary to set up shift registers G for different rows of pixel circuits, thereby reducing the number of shift registers G in the driving circuit, simplifying the structure of the driving circuit, reducing the size of the driving circuit, and facilitating the narrow bezel of the display panel.

[0192] Optionally, the time interval between the start of the valid pulse of the initial output control signal of the x-th stage shift register and the start of the valid pulse of the initial output control signal of the y-th stage shift register is W0; the valid pulse duration of the first output control signal of the x-th stage shift register is W1, and the valid pulse duration of the second output control signal of the x-th stage shift register is W2; wherein, W0≥(W1+W2).

[0193] Specifically, with Figure 36 The shift register shown is an example of a shift register of the xth stage, in conjunction with the reference. Figure 36 and Figure 38Since the valid pulse of the initial output signal Vnext of the x-th stage shift register is provided by the initial output control signal CK0 received by the x-th stage shift register, the initial output signal of the x-th stage shift register is also a valid pulse when the initial output control signal received by the x-th stage shift register is a valid pulse; the valid pulse of the initial output signal of the y-th stage shift register is provided by the initial output control signal received by the y-th stage shift register, the initial output signal of the y-th stage shift register is also a valid pulse when the initial output control signal CK0 received by the y-th stage shift register is a valid pulse; at the same time, the initial output signal Vnext of the x-th stage shift register is the input signal of the y-th stage shift register, so that the initial output signal Vnext output by the x-th stage shift register is consistent with the initial output signal CK0 output by the y-th stage shift register. The valid pulses of the output signal are shifted sequentially. The valid pulses of the initial output control signal CK0 received by the x-th stage shift register and the initial output control signal received by the y-th stage shift register need to be shifted sequentially. That is, the start time of the valid pulse of the initial output control signal CK0 received by the x-th stage shift register and the start time of the valid pulse of the initial output control signal received by the y-th stage shift register have a certain interval W0. When W0 is greater than (W1+W2), the valid pulses of the first output signal Gout1 and the second output signal Gout2 output by the x-th stage shift register can be shifted sequentially before the y-th stage shift register starts to output the valid pulse of the initial output signal. This ensures that the valid pulses of the first output signal and the second output signal output by each stage shift register are shifted sequentially and the times of the valid pulses do not overlap.

[0194] It should be noted that the above example is only exemplified by using the example that the pulse change frequency of the first output control signal CK1 is the same as the pulse change frequency of the second output control signal CK2. In the embodiments of the present invention, the pulse change frequencies of the first output control signal CK1 and the second output control signal CK2 can be set according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0195] Optionally, when the pulse change frequency of the first output control signal CK1 is Fc1 and the pulse change frequency of the second output control signal CK2 is Fc2; wherein, during at least a portion of the time period during the operation of the display panel, Fc1 = Fc2; and / or, during at least a portion of the time period during the operation of the display panel, Fc1 ≠ Fc2.

[0196] For example, Figure 39 This is another driving timing diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 36 and Figure 39During time period t21, the pulse change frequencies of the first output control signal CK1 and the second output control signal CK2 are the same, resulting in the first output signal Gout1 and the second output signal Gout2 having the same pulse change frequency. This allows the data refresh frequency of the pixel circuit controlled by the first output signal Gout1 to be the same as the data refresh frequency of the pixel circuit controlled by the second output signal Gout2. However, during time period t22, the first output control signal CK1 and the second output control signal CK2 are different. For example, the second output control signal CK2 remains at a continuous high level, resulting in the pulse change frequency of the second output control signal CK2 being less than the pulse change frequency of the first output control signal CK1. In this case, the pulse change frequencies of the first output signal Gout1 and the second output signal Gout2 are different, and the data refresh frequency of the pixel circuit controlled by the first output signal Gout1 can be greater than the same as the data refresh frequency of the pixel circuit controlled by the second output signal Gout2. Thus, by setting the pulse variation frequency of the first output control signal CK1 and the second output control signal CK2, the pulse variation frequency of the first output signal Gout1 and the second output signal Gout1 can meet the data refresh requirements of the pixel circuit in the display panel, thereby enabling the display panel to meet diverse display needs.

[0197] In another optional embodiment, when the pulse change frequency of the initial output control signal is Fc0, the pulse change frequency of the first output control signal is Fc1, and the pulse change frequency of the second output control signal is Fc2, during at least a portion of the time period of the operation of the display panel, Fc0 ≥ Fc1, and / or Fc0 ≥ Fc2.

[0198] For example, continue to refer to Figure 36 and Figure 39 During time period t21, the initial output control signal CK0 has the same pulse variation frequency as the first output control signal CK1 and the second output control signal CK2, resulting in the initial output signal Vnext having the same pulse variation frequency as the first output signal Gout1 and the second output signal Gout2. During time period t22, the initial output control signal CK0 has the same pulse variation frequency as the first output control signal CK1, while the initial output control signal CK0 has a different pulse variation frequency than the second output control signal CK1, resulting in the initial output signal Vnext having the same pulse variation frequency as the first output signal Gout1, while the initial output signal Vnext has a different pulse variation frequency than the second output signal Gout2. This results in the refresh frequency of the pixel circuit controlled by the second output signal Gout2 being different from the driving frequency of the shift register, thus meeting the special display requirements of the display panel.

[0199] It is understood that the above-described example only illustrates that during at least a portion of the time the display panel is operating, the pulse change frequency of the first output control signal CK1 is greater than the pulse change frequency of the second output control signal CK2. However, in this embodiment of the invention, the pulse change frequency of the first output control signal CK1 can also be set to be less than the pulse change frequency of the second output control signal CK2. Furthermore, the above-described example only illustrates that during at least a portion of the time the display panel is operating, the initial output control signal CK0 has the same pulse change frequency as the first output control signal CK1, but a different pulse change frequency than the second output control signal CK2. However, in this embodiment of the invention, the initial output control signal CK0 can have pulse change frequencies different from both the first and second output control signals CK1, or the initial output control signal CK0 can only have the same pulse change frequency as the second output control signal CK2. This can be designed according to actual needs, and this embodiment of the invention does not impose specific limitations on this.

[0200] It is also understood that the above example only illustrates the situation where the pulse change frequency of the initial output control signal CK0 is the same as that of the first output control signal CK1 and the second output control signal CK2, and the effective level time of the first output signal Gout1 and the second output signal Gout2 overlaps with the effective level time of the initial output signal Vnext. In other embodiments of the present invention, when the pulse change frequency of the initial output control signal CK0 is the same as that of the first output control signal CK1 and the second output control signal CK2, the effective level time of the first output signal Gout1 and the second output signal Gout2 can also be located after the effective level time of the initial output signal Vnext, and it can also have the same effect as the above embodiment. The similarities can be referred to the above description, and will not be repeated here.

[0201] In other alternative embodiments, Figure 40 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, such as... Figure 40As shown, the shift register may also include an m-th output unit 13m, where m ≥ 3; and the m-th output unit 13m is used to receive at least the signal from the first output node N1 and the signal from the second output node N2, controlling the m-th output signal. In this case, the shift register has a total of m output units: a first output unit 131, a second output unit 132, ..., the m-th output unit 13m. These m output units output a first output signal Gout1, a second output signal Gout2, ..., the m-th output signal Goutm, totaling m output signals. These m output signals can control the opening and closing of preset modules in different pixel circuits, thereby enabling different pixel circuits to share the same shift register G. This reduces the number of shift registers G set in the driving circuit, simplifies the structure of the driving circuit, reduces the size of the driving circuit, and consequently contributes to a narrow bezel on the display panel.

[0202] In an optional embodiment, continuing with reference to 40, the structures of each output unit from the first output unit 131 to the m-th output unit 13m can be substantially the same, that is, similar to the structure of the first output unit 131. The m-th output unit 13m may include a (2m-1)-th output module 13m1 and a (2m)-th output module 13m2. The (2m-1)-th output module 13m1 receives at least the m-th output control signal CKm and the signal of the first output node N1, and controls the m-th output signal Goutm. The (2m)-th output module 13m2 receives at least the first voltage signal VGH and the signal of the second output node N2, and controls the m-th output signal Goutm.

[0203] The (2m-1)th output module 13m1 may include the (3m-2)th transistor Mm1. The first terminal of the (3m-2)th transistor Mm1 receives the m-th output control signal CKm, and the second terminal of the (3m-2)th transistor Mm1 outputs the m-th output signal Goutm. The gate of the (3m-2)th transistor Mm1 is connected to the first output node N1 or the m-th node N1m. The first output node N1 and the m-th node N1m are directly connected, or the first output node N1 and the m-th node N1m are connected through the m-th stabilization module 13m3. The m-th stabilization module 13m3 can stabilize the signals of the first output node N1 and the m-th node N1m, so that the signals of the first output node N1 and the m-th node N1m are approximately the same. Thus, the (3m-2)th transistor Mm1 can be turned on or off under the control of the signal from the first output node N1, and when the signal from the first output node N1 controls the (3m-2)th transistor Mm1 to be turned on, the (3m-2)th transistor Mm1 can output the m-th output control signal CKm as the m-th output signal Goutm.

[0204] Correspondingly, the (2m)th output module 13m2 may include a (3m-1)th transistor Mm2. The first terminal of the (3m-1)th transistor Mm2 receives a first voltage signal VGH, the second terminal of the (3m-1)th transistor Mm2 is used to output the m-th output signal Goutm, and the gate of the (3m-1)th transistor Mm2 is connected to the second output node N2. Thus, the (3m-1)th transistor Mm2 can be turned on or off under the control of the signal from the second output node N2. When the signal from the second output node N2 controls the (3m-1)th transistor Mm2 to be turned on, the (3m-1)th transistor Mm2 can output the first voltage signal VGH as the m-th output signal Goutm.

[0205] Optionally, when the m-th output unit includes the m-th stabilization module 13m3, the m-th stabilization module 13m3 may include the (3m)-th transistor Mm3, the first terminal of the (3m)-th transistor Mm3 is connected to the first output node N1, the second terminal of the (3m)-th transistor Mm3 is connected to the m-th node Nm, and the gate of the (3m)-th transistor Mm3 receives the second voltage signal VGL.

[0206] In addition, the m-th output unit may also include the m-th bootstrap capacitor Cm, which can be electrically connected between the second terminal of the (3m-2)-th transistor Mm1 and the gate of the (3m-2)-th transistor Mm1 to ensure that the signal at the gate of the (3m-2)-th transistor Mm1 has a sufficiently high driving capability to drive the (3m-2)-th transistor Mm1 to turn on or off.

[0207] For example, Figure 41 This is another driving timing diagram of a shift register provided in an embodiment of the present invention. It can be understood that the structure of the m-th output unit 13m is roughly the same as that of the first output unit 131, and it has a similar working principle. The similarities can be referred to the description above. Here, only the relationship between the signals output by each output unit is illustrated with examples, such as... Figure 41 As shown, taking m=4 as an example, within one clock cycle tc, the effective levels of the first output control signal CK1, the second output control signal CK2, the third output control signal CK3, and the fourth output control signal CK4 can be shifted sequentially without overlapping. At this time, the effective levels of the first output signal Gout1, the second output signal Gout2, the third output signal Gout3, and the fourth output signal Gout4 output by the first output unit can be shifted sequentially, so that the first output signal Gout1, the second output signal Gout2, the third output signal Gout3, and the fourth output signal Gout4 can perform line-by-line scanning of different pixel circuits.

[0208] Optionally, the time interval between the activation of the valid pulse of the initial output control signal of the x-th stage shift register and the activation of the valid pulse of the initial output control signal of the y-th stage shift register is W0; the valid pulse duration of the first output control signal of the x-th stage shift register is W1, the valid pulse duration of the second output control signal of the x-th stage shift register is W2, and the valid pulse duration of the m-th output control signal of the x-th stage shift register is Wm; where,

[0209] For example, with Figure 40 The shift register shown is an example of a shift register of the xth stage, in conjunction with the reference. Figure 41 and Figure 40 When the initial output signal Vnext of the x-th stage shift register is the input signal Vin of the y-th stage shift register, and the effective pulses of the initial output signal Vnext and the initial output signal of the y-th stage shift register are shifted sequentially, the effective pulses of the initial output control signal received by the x-th stage shift register and the initial output control signal received by the y-th stage shift register are shifted sequentially. That is, the on-time of the effective pulse of the initial output control signal received by the x-th stage shift register and the on-time of the effective pulse of the initial output control signal received by the y-th stage shift register have a certain interval W0. When Wi is used, the effective pulses of the first output signal Gout1, the second output signal Gout2, the third output signal Gout3, and the fourth output signal Gout4 output by the x-th stage shift register are shifted sequentially before the y-th stage shift register starts outputting the first output signal effective pulse. This ensures that the effective pulses of the first output signal Gout1, the second output signal Gout2, the third output signal Gout3, and the fourth output signal Gout4 output by each stage shift register are shifted sequentially and that the effective pulse times do not overlap.

[0210] Optionally, during at least a portion of the time period during the operation of the display panel, the pulse change frequency Fc1 of the first output control signal CK1 to the pulse change frequency Fcm of the m-th output control signal CKm are all equal; or, at least two of the pulse change frequencies of the first output control signal CK1 to the pulse change frequency of the m-th output control signal CKm are not equal.

[0211] For example, taking m equal to 4 as an example, such as Figure 41As shown, during time period t31, the pulse change frequency Fc1 of the first output control signal CK1 to the pulse change frequency Fcm of the fourth output control signal CK4 are all equal. At this time, the first output unit to the fourth output unit can sequentially output the effective levels of the first output signal Gout1, the second output signal Gout2, the third output signal Gout3, and the fourth output signal Gout4, thereby making each pixel circuit controlled by the first output signal Gout1, the second output signal Gout2, the third output signal Gout3, and the fourth output signal Gout4 have the same data refresh frequency. During time period t32, the pulse change frequency Fc1 of the first output control signal CK1 is different from the pulse change frequency Fcm of the fourth output control signal CK4. For example, the fourth output control signal CK4 is a continuous ineffective level, while the first output... The control signal CK1 includes both active and inactive levels. Specifically, the pulse frequency of the first output control signal CK1 is greater than the pulse frequency of the fourth output control signal CK4. This results in the first output signal Gout1 from the first output unit having an active level, while the fourth output signal Gout4 from the fourth output unit has an inactive level. Consequently, the pixel circuit controlled by the first output signal Gout1 can refresh data during this time period, while the pixel circuit controlled by the fourth output signal Gout4 will not refresh data during this time period. In other words, the data refresh frequency of the pixel circuit controlled by the first output signal Gout1 is greater than the data refresh frequency of the pixel circuit controlled by the fourth output signal Gout4. This allows each pixel circuit of the display panel to refresh data as needed, meeting the display requirements of low power consumption and high display quality.

[0212] Optionally, when the pulse change frequency of the initial output control signal CK1 is Fc0, the pulse change frequency of the m-th output control signal CKm is Fcm; wherein, during at least a portion of the time period of the display panel's operation, Fc0 ≥ Fcm.

[0213] Specifically, continuing with the example of m equaling 4, please refer to... Figure 41During the time period t32, the initial output control signal CK0 has the same pulse change frequency as the first output control signal CK1 and the second output control signal CK2. However, the pulse change frequency of the initial output control signal CK0 is greater than that of the third output control signal CK3 and the fourth output control signal CK4. This results in the initial output signal Vnext having the same pulse change frequency as the first output signal Gout1 and the second output signal Gout2. However, the initial output signal Vnext has a different pulse change frequency than the third output signal Gout3 and the fourth output signal Gout3. This results in the refresh frequency of the pixel circuit controlled by the third output signal Gout3 and the fourth output signal Gout3 being less than the driving frequency of the shift register, thus meeting the special display requirements of the display panel.

[0214] It is understood that the above example is merely illustrative, using the example that the pulse change frequencies of the initial output control signal CK0 are different from those of the third output control signal CK3 and the fourth output control signal CK4. In the embodiments of the present invention, the pulse change frequency of the initial output control signal CK0 can be greater than at least one of the first output control signal CK1, the second output control signal CK2, the third output control signal CK3, and the fourth output control signal CK4. It can be designed according to actual needs, and the embodiments of the present invention do not impose specific limitations on it.

[0215] It should be noted that, Figure 41 The example only shows the output control signals and output signals when m equals 4. However, m can also be any positive integer greater than or equal to 3, such as 3, 5, or 6. As the value of m increases or decreases, the pulse change frequency of each output control signal can decrease or increase accordingly to ensure that the effective pulses of the output signals output by each output unit can be shifted sequentially. The same points can be referred to the description above. The embodiments of the present invention will not describe them one by one.

[0216] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the embodiments of the present invention. Therefore, this display device possesses the technical features of the display panel and its driving method provided in the embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0217] For example, Figure 42 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 42As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0218] It should be understood that the working process of the various forms of pixel circuits shown above can be used to reorder, add, or delete stages. For example, the stages in the working process of the pixel circuits described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is made herein.

[0219] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: The driving circuit includes N cascaded shift registers, where N ≥ 2; The shift register includes: Control unit, initial output unit, and first output unit; The control unit is used to receive at least input signals and control the signals of the first output node and the second output node. The initial output unit is used to receive at least the signals from the first output node and the second output node, and to control the initial output signal; the initial output signal of the x-th stage shift register is the input signal of the y-th stage shift register, 1≤x≤N, 1≤y≤N; The first output unit is used to receive at least the signal from the first output node and the signal from the second output node, and to control the first output signal; The pulse variation frequency of the initial output signal is F0, and the pulse variation frequency of the first output signal is F1; wherein, During at least a portion of the time period during the operation of the display panel, F0 ≠ F1.

2. The display panel according to claim 1, characterized in that, During at least a portion of the time period during the operation of the display panel, F0 > F1.

3. The display panel according to claim 1, characterized in that, The initial output unit includes a first initial output module and a second initial output module; The first initial output module receives at least an initial output control signal and a signal from the first output node, and controls the initial output signal; The second initial output module receives at least the first voltage signal and the signal from the second output node, and controls the initial output signal.

4. The display panel according to claim 3, characterized in that, The first initial output module includes a first initial output transistor; The first terminal of the first initial output transistor is used to receive the initial output control signal, and the second terminal of the first initial output transistor is used to output the initial output signal. The gate of the first initial output transistor is connected to the first output node or the third output node. The first output node and the third output node are directly connected, or the first output node and the third output node are connected through an initial stabilization module.

5. The display panel according to claim 3, characterized in that, The second initial output module includes a second initial output transistor; The first terminal of the second initial output transistor is used to receive the first voltage signal, the second terminal of the second initial output transistor is used to output the initial output signal, and the gate of the second initial output transistor is connected to the second output node.

6. The display panel according to claim 4, characterized in that, The initial stabilization module includes a third initial output transistor; The first terminal of the third initial output transistor is connected to the first output node, the second terminal of the third initial output transistor is connected to the third output node, and the gate of the third initial output transistor receives a second voltage signal.

7. The display panel according to claim 6, characterized in that, The first voltage signal is a high-level signal, and the second voltage signal is a low-level signal.

8. The display panel according to claim 3, characterized in that, The first output unit includes a first output module and a second output module; The first output module receives at least a first output control signal and a signal from the first output node, and controls the first output signal; The second output module receives at least the first voltage signal and the signal from the second output node, and controls the first output signal.

9. The display panel according to claim 8, characterized in that, The first output module includes a first transistor; The first terminal of the first transistor is used to receive the first output control signal, the second terminal of the first transistor is used to output the first output signal, the gate of the first transistor is connected to the first output node or the first node, the first output node is directly connected to the first node, or the first output node is connected to the first node through the first stabilization module.

10. The display panel according to claim 9, characterized in that, The second output module includes a second transistor; The first terminal of the second transistor receives the first voltage signal, the second terminal of the second transistor is used to output the first output signal, and the gate of the second transistor is connected to the second output node.

11. The display panel according to claim 10, characterized in that, The first stabilization module includes a third transistor; The first terminal of the third transistor is connected to the first output node, the second terminal of the third transistor is connected to the first node, and the gate of the third transistor receives a second voltage signal.

12. The display panel according to claim 8, characterized in that, The pulse variation frequency of the initial output control signal is Fc0, and the pulse variation frequency of the first output control signal is Fc1; wherein, During at least a portion of the time period during the operation of the display panel, Fc0 ≠ Fc1.

13. The display panel according to claim 12, characterized in that, Fc0 > Fc1.

14. The display panel according to claim 8, characterized in that, The operation of the display panel includes a first time period and a second time period; During the first time period, when the initial output control signal is a valid pulse, the first output control signal is a valid pulse; During the second time period, when the initial output control signal is a valid pulse, the first output control signal is an invalid pulse.

15. The display panel according to claim 8, characterized in that, The display panel includes a pixel circuit, and the first output signal of the driving circuit is a control signal of a preset module of the pixel circuit. When the first output signal is a valid pulse, the preset module is activated; When the first output signal is an invalid pulse, the preset module is turned off.

16. The display panel according to claim 15, characterized in that, The preset module includes a PMOS transistor, and the first output signal is a control signal for the PMOS transistor. When the first output signal is a low-level signal, it is a valid pulse that controls the PMOS transistor to turn on; or... The preset module includes an NMOS transistor, and the first output signal is a control signal for the NMOS transistor. When the first output signal is a high-level signal, the first output signal is a valid pulse that controls the NMOS transistor to turn on.

17. The display panel according to claim 15, characterized in that, The operation of the display panel includes a first mode and a second mode; In the first mode, the pulse variation frequency of the first output control signal is Fc11; in the second mode, the pulse variation frequency of the first output control signal is Fc12; wherein... Fc11≠Fc12.

18. The display panel according to claim 17, characterized in that, In the first mode, the pulse variation frequency of the first output signal is Fs1; in the second mode, the pulse variation frequency of the first output signal is Fs2; wherein... Fs1≠Fs2.

19. The display panel according to claim 17, characterized in that, The operation of the pixel circuit includes writing data frames and holding frames; wherein... During the data writing frame, the preset module is activated; During the hold frame, the preset module is turned off.

20. The display panel according to claim 19, characterized in that, In the first mode, the data refresh frequency of the pixel circuit is Fp1; in the second mode, the data refresh frequency of the pixel circuit is Fp2; wherein, Fp1≠Fp2.

21. The display panel according to claim 20, characterized in that, (Fp1-Fp2)×(Fc11- Fc12)>0.

22. The display panel according to claim 15, characterized in that, The display panel includes a driving module, a data writing module, a reset module, and a compensation module; wherein, The data writing module is connected to the first end of the driver module and is used to provide data signals to the driver module; the data writing module is the preset module; and / or, The reset module is connected to the control terminal of the drive module and is used to provide a reset signal to the drive module. The reset module is the preset module; and / or, The compensation module is connected between the control terminal and the second terminal of the drive module, and the compensation module is the preset module.

23. The display panel according to claim 22, characterized in that, The display panel also includes a bias adjustment module; The bias adjustment module is connected to the first or second end of the drive module and is used to provide a bias adjustment signal to the drive module. The bias adjustment module is the preset module.

24. The display panel according to claim 15, characterized in that, The display panel includes a first pixel circuit and a second pixel circuit, and the driving circuit includes a first shift register and a second shift register; The first output signal of the first shift register is the control signal of the preset module of the first pixel circuit, and the first output signal of the second shift register is the control signal of the preset module of the second pixel circuit; wherein, The pulse change frequency of the first output control signal received by the first shift register is Fct1, and the pulse change frequency of the first output control signal received by the second shift register is Fct2, where Fct1 ≠ Fct2.

25. The display panel according to claim 24, characterized in that, The pulse change frequency of the first output signal received by the preset module of the first pixel circuit is Fs11, and the pulse change frequency of the first output signal received by the preset module of the second pixel circuit is Fs22; wherein, Fs11≠Fs22.

26. The display panel according to claim 24, characterized in that, The data refresh rate of the first pixel circuit is Fp11, and the data refresh rate of the second pixel circuit is Fp22; wherein, Fp11≠Fp22.

27. The display panel according to claim 26, characterized in that, (Fp11-Fp22)×(Fct1-Fct2)>0.

28. The display panel according to claim 24, characterized in that, The display panel includes a first display area and a second display area, with the first pixel circuit located in the first display area and the second pixel circuit located in the second display area.

29. The display panel according to claim 8, characterized in that, The shift register also includes a second output unit; The second output unit is used to receive at least the signal from the first output node and the signal from the second output node, and to control the second output signal.

30. The display panel according to claim 29, characterized in that, The second output unit includes a third output module and a fourth output module; The third output module receives at least the second output control signal and the signal from the first output node, and controls the second output signal; The fourth output module receives at least the first voltage signal and the signal from the second output node, and controls the second output signal.

31. The display panel according to claim 30, characterized in that, The third output module includes a fourth transistor; The first terminal of the fourth transistor is used to receive the second output control signal, and the second terminal of the fourth transistor is used to output the second output signal. The gate of the fourth transistor is connected to the first output node or the second node. The first output node and the second node are directly connected, or the first output node and the second node are connected through the second stabilization module.

32. The display panel according to claim 31, characterized in that, The fourth output module includes a fifth transistor; The first terminal of the fifth transistor receives the first voltage signal, the second terminal of the fifth transistor is used to output the second output signal, and the gate of the fifth transistor is connected to the second output node.

33. The display panel according to claim 32, characterized in that, The second stabilization module includes a sixth transistor; The first terminal of the sixth transistor is connected to the first output node, the second terminal of the sixth transistor is connected to the second node, and the gate of the sixth transistor receives a second voltage signal.

34. The display panel according to claim 30, characterized in that, The pulse variation frequency of the first output control signal is Fc1, and the pulse variation frequency of the second output control signal is Fc2; wherein, During at least a portion of the time period during the operation of the display panel, Fc1 = Fc2; and / or, During at least a portion of the time period during the operation of the display panel, Fc1 ≠ Fc2.

35. The display panel according to claim 28, characterized in that, The pulse variation frequency of the initial output control signal is Fc0, the pulse variation frequency of the first output control signal is Fc1, and the pulse variation frequency of the second output control signal is Fc2; wherein, During at least a portion of the time period of operation of the display panel, Fc0 ≥ Fc1, and / or Fc0 ≥ Fc2.

36. The display panel according to claim 30, characterized in that, The time interval between the effective pulse of the initial output control signal of the x-th stage shift register being turned on and the effective pulse of the initial output control signal of the y-th stage shift register being turned on is W0; The effective pulse duration of the first output control signal of the x-th stage shift register is W1, and the effective pulse duration of the second output control signal of the x-th stage shift register is W2; wherein, W0≥(W1+W2).

37. The display panel according to claim 29, characterized in that, The shift register also includes an m-th output unit, where m ≥ 3; The m-th output unit is used to receive at least the signals from the first output node and the second output node, and to control the m-th output signal.

38. The display panel according to claim 37, characterized in that, The m-th output unit includes the (2m-1)-th output module and the (2m)-th output module; The (2m-1)th output module receives at least the mth output control signal and the signal from the first output node, and controls the mth output signal; The (2m)th output module receives at least the first voltage signal and the signal from the second output node, and controls the mth output signal.

39. The display panel according to claim 38, characterized in that, During at least a portion of the time period during the operation of the display panel, The pulse variation frequency of the first output control signal to the pulse variation frequency of the m-th output control signal are all equal; or, At least two of the pulse change frequencies of the first output control signal to the m-th output control signal are not equal.

40. The display panel according to claim 38, characterized in that, The pulse variation frequency of the initial output control signal is Fc0, and the pulse variation frequency of the m-th output control signal is Fcm; where, During at least a portion of the time period during the operation of the display panel, Fc0 ≥ Fcm.

41. The display panel according to claim 38, characterized in that, The time interval between the effective pulse of the initial output control signal of the x-th stage shift register being turned on and the effective pulse of the initial output control signal of the y-th stage shift register being turned on is W0; The effective pulse duration of the first output control signal of the x-th stage shift register is W1, the effective pulse duration of the second output control signal of the x-th stage shift register is W2, and the effective pulse duration of the m-th output control signal of the x-th stage shift register is Wm; wherein, W0≥ 。 42. The display panel according to claim 1, characterized in that, The control unit includes a first control module and a second control module; The first control module receives a first voltage signal, the input signal, an initial output control signal, and a first clock signal, and controls the signals of the first output node; The second control module receives the second voltage signal and the first clock signal, and controls the signal of the second output node.

43. A display device, characterized in that, Includes the display panel as described in any one of claims 1-42.

Images