Etch stop detection structure and etch stop detection method

Abstract

This invention provides an etching termination detection structure and an etching termination detection method. The etching termination detection structure includes a substrate, a first dielectric layer, a first termination layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first termination layer is located on the first dielectric layer. The second dielectric layer is located on the first termination layer. A first air gap is formed between the first dielectric layer and the first termination layer in the device region. A trench is formed in the second dielectric layer in the detection region. The trench exposes the first termination layer. The above-described etching termination detection structure can be used to detect an etching termination signal.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a detection method, and more particularly to an etching termination detection structure and an etching termination detection method. Background Technology

[0002] In some semiconductor structures, air gaps are placed between interconnect structures to reduce parasitic capacitance between interconnect structures, thereby reducing resistance-capacitance (RC) delay. However, when a lower air gap and an upper air gap are formed sequentially, it is difficult to control the etching endpoint during the etching process used to form the upper air gap. Therefore, the etching process can damage the semiconductor device located below the lower air gap. Summary of the Invention

[0003] This invention provides an etching termination detection structure and an etching termination detection method, which can be used to detect etching termination signals.

[0004] This invention proposes an etching termination detection structure, comprising a substrate, a first dielectric layer, a first termination layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first termination layer is located on the first dielectric layer. The second dielectric layer is located on the first termination layer. A first air gap is formed between the first dielectric layer and the first termination layer in the device region. A trench is formed in the second dielectric layer in the detection region. The trench exposes the first termination layer.

[0005] According to one embodiment of the present invention, in the above-described etching termination detection structure, the bottom surface of the trench may be higher than the bottom surface of the first termination layer.

[0006] According to one embodiment of the present invention, in the above-described etching termination detection structure, the trench does not penetrate the first termination layer.

[0007] According to one embodiment of the present invention, in the above-described etching termination detection structure, a second air gap may be provided in the second dielectric layer in the device region. The second air gap may be connected to the first air gap.

[0008] According to one embodiment of the present invention, the above-described etching termination detection structure may further include a second termination layer. The second termination layer is located on the second dielectric layer.

[0009] According to one embodiment of the present invention, in the above-described etching termination detection structure, the second air gap can penetrate the second termination layer. The trench can penetrate the second termination layer.

[0010] According to one embodiment of the present invention, the above-described etching termination detection structure may further include a third dielectric layer. The third dielectric layer is located on the second termination layer.

[0011] According to one embodiment of the present invention, in the above-described etching termination detection structure, the second air gap may extend into the third dielectric layer. The trench may extend into the third dielectric layer.

[0012] According to one embodiment of the present invention, in the above-described etching termination detection structure, the detection area may be located next to the device area.

[0013] According to one embodiment of the present invention, in the above-described etching termination detection structure, the substrate may include a chip region and a scribe line region.

[0014] According to one embodiment of the present invention, in the above-described etching termination detection structure, the device region may be located in the chip region. The detection region may be located in the chip region or the dicing channel region.

[0015] This invention proposes an etching termination detection method, comprising the following steps: A substrate is provided. The substrate includes a device region and a detection region. A first dielectric layer is formed on the substrate. A first termination layer is formed on the first dielectric layer. A first air gap is formed between the first dielectric layer and the first termination layer in the device region. A second dielectric layer is formed on the first termination layer. A trench exposing the first termination layer is formed in the second dielectric layer in the detection region, and an etching termination signal is obtained.

[0016] According to an embodiment of the present invention, in the above-described etching termination detection method, the bottom surface of the trench may be higher than the bottom surface of the first termination layer.

[0017] According to an embodiment of the present invention, in the above-described etching termination detection method, the trench does not penetrate the first termination layer.

[0018] According to an embodiment of the present invention, the above-described etching termination detection method may further include the following step: forming a second air gap in a second dielectric layer in the device region. The second air gap may be connected to the first air gap.

[0019] According to an embodiment of the present invention, in the above-described etching termination detection method, the second air gap and the trench can be formed simultaneously.

[0020] According to an embodiment of the present invention, the above-described etching termination detection method may further include the following step: forming a second termination layer on the second dielectric layer.

[0021] According to one embodiment of the present invention, in the above-described etching termination detection method, the second air gap can penetrate the second termination layer. The trench can penetrate the second termination layer.

[0022] According to an embodiment of the present invention, the above-described etching termination detection method may further include the following step: forming a third dielectric layer on the second termination layer.

[0023] According to one embodiment of the present invention, in the above-described etching termination detection method, the second air gap may extend into the third dielectric layer. The trench may extend into the third dielectric layer.

[0024] Based on the above, in the etching termination detection structure and method proposed in this invention, a trench is formed in the second dielectric layer in the detection area, and the trench exposes the first termination layer. Therefore, an etching termination signal can be obtained by detecting the signal of the first termination layer exposed by the trench. In this way, when performing an etching process on the second dielectric layer above the first air gap, the etching termination signal can be used to prevent the etching process from damaging the semiconductor device below the first air gap.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0026] Figures 1A to 1H This is a cross-sectional view of the manufacturing process of the etching termination detection structure according to some embodiments of the present invention;

[0027] Figure 2 This is a top view of a substrate according to some embodiments of the present invention;

[0028] Figure 3 for Figure 1H Top view. Detailed Implementation

[0029] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the top view are not drawn to the same scale as those in the sectional view. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.

[0030] Figures 1A to 1H This is a cross-sectional view of the manufacturing process of an etching termination detection structure according to some embodiments of the present invention. Figure 2 This is a top view of a substrate according to some embodiments of the present invention. Figure 3 for Figure 1H Top view. Figures 1A to 1H For along Figure 3The cross-sectional views along section lines I-I' and II-II' are shown in the top view of this embodiment. Some components are omitted from the cross-sectional views to clearly illustrate the positional relationships between the components in the top view.

[0031] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 includes a device region R1 and a detection region R2. The detection region R2 may be located adjacent to the device region R1. In some embodiments, such as Figure 2 As shown, substrate 100 may include a chip region RC and a dicing region RSL. The dicing region RSL can be used to define the chip region RC. Figure 1A The device region R1 can be located within the chip region RC. The detection region R2 in Figure 1 can be located within... Figure 2 The detection region R2 is located in the chip region RC or the dicing region RSL. In some embodiments, the detection region R2 may be located in the dummy region of the chip region RC. In some embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate, but the present invention is not limited thereto. For example, the substrate 100 may include a substrate layer 100a, an insulating layer 100b, and a semiconductor layer 100c. The material of the substrate layer 100a is, for example, a semiconductor material, such as silicon. The insulating layer 100b is located on the substrate layer 100a. The material of the insulating layer 100b is, for example, silicon oxide. The semiconductor layer 100c is located on the insulating layer 100b. The material of the semiconductor layer 100c is, for example, silicon. In some embodiments, an isolation structure 102 may be formed in the substrate 100. The isolation structure 102 is, for example, a shallow trench isolation structure. The material of the isolation structure 102 is, for example, silicon oxide.

[0032] In some embodiments, a semiconductor device 104 may be formed on a substrate 100. The semiconductor device 104 may be located in a device region R1. In some embodiments, the semiconductor device 104 may be a transistor device. The semiconductor device 104 may include a gate 106, source and drain regions 108, and source and drain regions 110. The gate 106 is located on the substrate 100. The material of the gate 106 is, for example, doped polysilicon. The source and drain regions 108 and 110 are located in the substrate 100 (e.g., semiconductor layer 100c) on both sides of the gate 106. The source and drain regions 108 and 110 may each be doped regions. In some embodiments, the source and drain region 108 may be a source region, and the source and drain region 110 may be a drain region. In other embodiments, the source and drain region 108 may be a drain region, and the source and drain region 110 may be a source region. In addition, the semiconductor device 104 may also include a gate dielectric layer 112. The gate dielectric layer 112 is located between the gate 106 and the substrate 100. The material of the gate dielectric layer 112 is, for example, silicon oxide.

[0033] In some embodiments, the semiconductor device 104 may further include at least one of a spacer 114, a lightly doped drain (LDD) 116, a lightly doped drain 118, a metal silicide layer 120, a metal silicide layer 122, and a metal silicide layer 124. The spacer 114 is located on the sidewall of the gate 106. The spacer 114 may be a single-layer or multi-layer structure. The material of the spacer 114 is, for example, silicon oxide, silicon nitride, or a combination thereof. The lightly doped drain 116 and lightly doped drain 118 are located in the substrate 100 (e.g., semiconductor layer 100c) below the spacer 114. The metal silicide layers 120, 122, and 124 are located on the gate 106, the source and drain regions 108, and the source and drain regions 110, respectively. The materials of metal silicide layer 120, metal silicide layer 122 and metal silicide layer 124 are, for example, cobalt silicide or nickel silicide.

[0034] In some embodiments, a termination layer 126 may be formed on the semiconductor device 104, the substrate 100, and the isolation structure 102. In some embodiments, the termination layer 126 may be used as an etch termination layer. The material of the termination layer 126 is, for example, silicon nitride (SiN) or silicon carbide nitride (SiCN). The method for forming the termination layer 126 is, for example, chemical vapor deposition. In some embodiments, a dielectric layer 128 may be formed on the termination layer 126. The material of the dielectric layer 128 is, for example, silicon oxide. The method for forming the dielectric layer 128 is, for example, chemical vapor deposition. In some embodiments, a termination layer 130 may be formed on the dielectric layer 128. In some embodiments, the termination layer 130 may be used as an etch termination layer. The material of the termination layer 130 is, for example, silicon nitride or silicon carbide nitride. The method for forming the termination layer 130 is, for example, chemical vapor deposition.

[0035] Next, a dielectric layer 132 is formed on the substrate 100. In some embodiments, the dielectric layer 132 may be formed on the termination layer 130. The material of the dielectric layer 132 is, for example, a low dielectric constant (low-k) material. The method for forming the dielectric layer 132 is, for example, chemical vapor deposition.

[0036] In some embodiments, contact windows 134, wires 136, 138, and 140 may be formed. Contact windows 134 and 138 are located in dielectric layer 128. Contact windows 134 and 138 can penetrate terminating layer 126 and are electrically connected to metal silicide layer 122 and metal silicide layer 124, respectively. Wires 136 and 140 are located in dielectric layer 132. Wires 136 and 140 can penetrate terminating layer 130 and are electrically connected to contact windows 134 and 138, respectively. The materials of contact windows 134, 138, wires 136, and 140 are conductive materials such as metals.

[0037] Then, a termination layer 142 is formed on the dielectric layer 132. In some embodiments, the termination layer 142 may also be formed on the conductors 136 and 140. In some embodiments, the termination layer 142 may be used as an etch termination layer. The material of the termination layer 142 is, for example, silicon nitride or silicon carbide nitride. The method for forming the termination layer 142 is, for example, chemical vapor deposition.

[0038] Please refer to Figure 1B An air gap AR1 is formed in the dielectric layer 132 and the stop layer 142 in the device region R1. In some embodiments, the air gap AR1 may also be formed in the dielectric layer 128 and the stop layer 130. In some embodiments, the air gap AR1 can be formed by patterning the stop layer 142, the dielectric layer 132, the stop layer 130 and the dielectric layer 128 by photolithography and etching processes (e.g., dry etching).

[0039] Please refer to Figure 1C A portion of the dielectric layer 132 can be removed to widen the air gap AR1. The method for removing a portion of the dielectric layer 132 is, for example, wet etching.

[0040] Please refer to Figure 1D A dielectric layer 144 is formed on the termination layer 142. In some embodiments, the dielectric layer 144 may also be formed in the air gap AR1, and the dielectric layer 144 does not completely fill the air gap AR1. The material of the dielectric layer 144 is, for example, a low dielectric constant material. The method for forming the dielectric layer 144 is, for example, chemical vapor deposition. In some embodiments, the dielectric layer 144 may undergo a planarization process. The planarization process is, for example, a chemical mechanical polishing process.

[0041] Please refer to Figure 1EInterconnects 146 and 148 can be formed. Interconnects 146 and 148 are located in dielectric layer 144. Interconnects 146 and 148 may each include vias, wires, or combinations thereof. Interconnects 146 and 148 can penetrate terminating layer 142 to electrically connect wires 136 and 140, respectively. The material of interconnects 146 and 148 is, for example, a conductive material such as metal.

[0042] Interconnect structures IS1 and IS2 can be formed using the above method. Interconnect structures IS1 and IS2 can be located in device region R1. Interconnect structure IS1 can be electrically connected to the source and drain regions 108 via a metal silicide layer 122. Interconnect structure IS1 may include a contact window 134, a conductor 136, and an interconnect 146. Conductor 136 is located on contact window 134, and interconnect 146 is located on conductor 136. Furthermore, interconnect structure IS2 can be electrically connected to the source and drain regions 110 via the metal silicide layer 124. Interconnect structure IS2 may include a contact window 138, a conductor 140, and an interconnect 148. Conductor 140 is located on contact window 138, and interconnect 148 is located on conductor 140. Additionally, interconnect structures IS1 and IS2 can be formed using an interconnect process.

[0043] A termination layer 150 may then be formed on the dielectric layer 144. In some embodiments, the termination layer 150 may also be formed on the interconnects 146 and 148. In some embodiments, the termination layer 150 may be used as an etch termination layer. The material of the termination layer 150 may be, for example, silicon nitride or silicon carbide nitride. The method for forming the termination layer 150 may be, for example, chemical vapor deposition.

[0044] Please refer to Figure 1FA trench T is formed in the dielectric layer 144 in the detection region R2, exposing the termination layer 142, and an etching termination signal is obtained. In some embodiments, the etching termination detection method can obtain the etching termination signal by detecting the signal of the termination layer 142 exposed by the trench T. The trench T may penetrate the termination layer 150. The bottom surface BS1 of the trench T may be higher than the bottom surface BS2 of the termination layer 142. In some embodiments, the trench T does not penetrate the termination layer 142. In addition, an air gap AR2 may be formed in the dielectric layer 144 in the device region R1. The air gap AR2 may be connected to the air gap AR1. The air gap AR2 may penetrate the termination layer 150. The air gap AR2 and the trench T may be formed simultaneously. In some embodiments, the trench T and the air gap AR2 may be formed by patterning the termination layer 150 and the dielectric layer 144 through photolithography and etching processes (e.g., dry etching). In addition, when etching the dielectric layer 144 above the air gap AR1 (e.g., dry etching process), an etching stop signal can be used to prevent the etching process from damaging the semiconductor device 104 below the air gap AR1.

[0045] Please refer to Figure 1G A portion of the dielectric layer 144 can be removed to increase the width of the air gap AR2 and / or the width of the trench T. In some embodiments, the method for removing a portion of the dielectric layer 144 is, for example, wet etching.

[0046] Please refer to Figure 1H A dielectric layer 152 is formed on the termination layer 150. In some embodiments, the dielectric layer 152 may also be formed in the air gap AR2 and the trench T, and the dielectric layer 152 does not completely fill the air gap AR2 and the trench T. In this embodiment, the dielectric layer 152 is not formed in the air gap AR1, but the invention is not limited thereto. In other embodiments, the dielectric layer 152 may be formed in the air gap AR1, and the dielectric layer 152 does not completely fill the air gap AR1. In some embodiments, the air gap AR2 may extend into the dielectric layer 152. In some embodiments, the trench T may extend into the dielectric layer 152. The material of the dielectric layer 152 is, for example, a low dielectric constant material. The method for forming the dielectric layer 152 is, for example, chemical vapor deposition. In some embodiments, the dielectric layer 152 may be subjected to a planarization process. The planarization process is, for example, chemical mechanical polishing.

[0047] The following is through Figure 1H The etching termination detection structure 10 of this embodiment will be explained below. Furthermore, although the method for forming the etching termination detection structure 10 is described using the method described above as an example, the present invention is not limited thereto.

[0048] Please refer to Figure 1H , Figure 2 and Figure 3The etching termination detection structure 10 includes a substrate 100, a dielectric layer 132, a termination layer 142, and a dielectric layer 144. The substrate 100 includes a device region R1 and a detection region R2. The detection region R2 may be located adjacent to the device region R1. The substrate 100 may include a chip region RC and a dicing region RSL. The dicing region RSL can be used to define the chip region RC. The device region R1 may be located within the chip region RC. The detection region R2 may be located within either the chip region RC or the dicing region RSL. In some embodiments, the detection region R2 may be located within a virtual region of the chip region RC. The dielectric layer 132 is located on the substrate 100. The termination layer 142 is located on the dielectric layer 132. The dielectric layer 144 is located on the termination layer 142. An air gap AR1 is present in the dielectric layer 132 and the termination layer 142 in the device region R1. A trench T is present in the dielectric layer 144 in the detection region R2. The trench T exposes the termination layer 142. The bottom surface BS1 of the trench T may be higher than the bottom surface BS2 of the termination layer 142. In some embodiments, the trench T does not penetrate the termination layer 142. In some embodiments, an air gap AR2 may be present in the dielectric layer 144 in the device region R1. The air gap AR2 may be connected to the air gap AR1.

[0049] Furthermore, the etching termination detection structure 10 may also include at least one of a termination layer 150 and a dielectric layer 152. The termination layer 150 is located on the dielectric layer 144. An air gap AR2 may penetrate the termination layer 150. A trench T may penetrate the termination layer 150. The dielectric layer 152 is located on the termination layer 150. The air gap AR2 may extend into the dielectric layer 152. The trench T may extend into the dielectric layer 152.

[0050] Furthermore, the remaining details of the etching termination detection structure 10 can be found in the description of the above embodiments, and will not be repeated here.

[0051] As can be seen from the above embodiments, in the etching termination detection structure 10 and the etching termination detection method, a trench T is provided in the dielectric layer 144 in the detection region R2, and the trench T exposes the termination layer 142. Therefore, an etching termination signal can be obtained by detecting the signal of the termination layer 142 exposed by the trench T. In this way, when the etching process is performed on the dielectric layer 144 above the air gap AR1, the etching termination signal can be used to prevent the etching process from damaging the semiconductor device 104 below the air gap AR1. In some embodiments, when the detection region R2 is located in the dicing region RSL, since the trench T does not occupy the area of ​​the chip region RC, the trench T can be designed to have a larger area, thereby improving the signal strength of the etching termination signal.

[0052] In summary, in the etching termination detection structure and method of the above embodiments, a trench exposing the termination layer is provided in the detection area. Therefore, an etching termination signal can be obtained by detecting the signal of the termination layer exposed by the trench. In this way, the etching process can be prevented from damaging the semiconductor device by the etching termination signal.

[0053] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. An etching termination detection structure, characterized in that, include: Substrate, including the device region and the detection region; A first dielectric layer is located on the substrate; The first termination layer is located on the first dielectric layer; as well as The second dielectric layer is located on the first termination layer, wherein A first air gap exists between the first dielectric layer and the first termination layer in the device region. The second dielectric layer in the detection area has trenches. The trench exposes the first termination layer, and the bottom surface of the trench is higher than the bottom surface of the first termination layer; The second dielectric layer in the device region has a second air gap, and The second air gap is connected to the first air gap.

2. The etching termination detection structure according to claim 1, characterized in that, The trench does not penetrate the first termination layer.

3. The etching termination detection structure according to claim 1, characterized in that, Also includes: The second termination layer is located on the second dielectric layer.

4. The etching termination detection structure according to claim 3, characterized in that, The second air gap penetrates the second termination layer, and The trench penetrates the second termination layer.

5. The etching termination detection structure according to claim 3, characterized in that, Also includes: The third dielectric layer is located on the second termination layer.

6. The etching termination detection structure according to claim 5, characterized in that, The second air gap extends into the third dielectric layer, and The trench extends into the third dielectric layer.

7. The etching termination detection structure according to claim 1, characterized in that, The detection area is located next to the device area.

8. The etching termination detection structure according to claim 1, characterized in that, The substrate includes a chip region and a dicing region.

9. The etching termination detection structure according to claim 8, characterized in that, The device region is located within the chip region, and The detection area is located in the chip area or the cutting channel area.

10. A method for detecting etching termination, characterized in that, include: A substrate is provided, wherein the substrate includes a device region and a detection region; A first dielectric layer is formed on the substrate; A first termination layer is formed on the first dielectric layer; A first air gap is formed between the first dielectric layer and the first termination layer in the device region; A second dielectric layer is formed on the first termination layer; A trench is formed in the second dielectric layer in the detection area to expose the first termination layer, and an etching termination signal is obtained, wherein the bottom surface of the trench is higher than the bottom surface of the first termination layer. as well as A second air gap is formed in the second dielectric layer in the device region, wherein the second air gap is connected to the first air gap, and wherein the second air gap is formed simultaneously with the trench.

11. The etching termination detection method according to claim 10, characterized in that, The trench does not penetrate the first termination layer.

12. The etching termination detection method according to claim 10, characterized in that, Also includes: A second termination layer is formed on the second dielectric layer.

13. The etching termination detection method according to claim 12, characterized in that, The second air gap penetrates the second termination layer, and The trench penetrates the second termination layer.

14. The etching termination detection method according to claim 12, characterized in that, Also includes: A third dielectric layer is formed on the second termination layer.

15. The etching termination detection method according to claim 14, characterized in that, The second air gap extends into the third dielectric layer, and The trench extends into the third dielectric layer.

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