A MISFET with a channel bidirectional depletion integrated diode and a method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor field-effect transistors, and more specifically, to a MISFET with a bidirectional channel depletion and integrated diode. The device comprises an n-type gallium oxide substrate, an n-type gallium oxide epitaxial layer formed on the front surface of the n-type gallium oxide substrate, p-type semiconductor material layers formed in rows within and on the upper surface of the n-type gallium oxide epitaxial layer, and a gate electrode, a source electrode, and a drain electrode formed between or above the region between two rows of p-type semiconductor material layers. The portion of the p-type semiconductor material layer located within the n-type gallium oxide epitaxial layer has a multi-step structure, and the region of the p-type semiconductor material layer located between the upper surfaces of the n-type gallium oxide epitaxial layer serves as the gate region. Vertical conductive channels are formed on both sides of the gate region, and a horizontal conductive channel is formed between the vertical conductive channels. The thickness of the horizontal conductive channel is no greater than the height of the vertical conductive channel. The device is a junction enhancement type device capable of simultaneously achieving bidirectional channel depletion and an integrated diode.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor field effect transistors, and in particular to a MISFET with a channel bidirectional depletion integrated diode and a preparation method thereof. Background Art

[0002] Among wide-bandgap semiconductors, gallium oxide (GaO) boasts a bandgap of 4.8 eV, an ideal breakdown electric field strength of 8 MV / cm, and a high BFOM value of 3400, approximately four times that of gallium nitride (GaN) and ten times that of silicon carbide (SiC). Therefore, GaO holds significant research significance and broad market application prospects in today's power electronics applications, which demand higher power density and lower power consumption. However, achieving hole-conducting p-type GaO is nearly impossible for three reasons. First, it is difficult to find acceptor impurities with low activation energy. Second, theoretical calculations show that the valence band maximum of GaO is narrowly dispersed and its effective mass is very large, resulting in a localized distribution of free holes with small μs. Finally, theoretical predictions have been made specifically for GaO that, due to local lattice distortion, free holes experience high local self-trapping energy in the bulk, leading to the formation of small poles, which undoubtedly inhibit effective hole conduction.

[0003] Since gallium oxide lacks an effective p-type semiconductor, it cannot be made into a conventional structure MOSFET like SiC and GaN. It can only be made into a MISFET or JFET device with N-type conductivity in the drain, source and drift region. Gallium oxide MISFET and JFET devices have a depletion layer in the conductive channel due to the work function difference between the gate metal, polysilicon and p-type semiconductor and the gallium oxide epitaxial layer, which affects the working characteristics of the device. When the gate voltage of a planar gallium oxide MISFET device is 0V, the conductive channel can only be partially depleted, not completely depleted. It can only act as a depletion-type device when forward biased. When the device is reverse biased, the gate electrode can shield part of the electric field, but because the gate electrode is on the surface of the gallium oxide epitaxial layer, the depletion region is not extended enough, and the electric field shielding ability is limited. The electric field at the metal-semiconductor interface is still very strong. As the reverse voltage increases, more and more electrons will flow from the source to the drain, resulting in a large reverse leakage current, which leads to poor device reliability. Figure 1The figure shows a planar MISFET device. On the other hand, when the device operates under high current conditions, it generates a large amount of heat. Due to the low thermal conductivity of gallium oxide itself, this causes the device temperature to rise, reducing carrier mobility, which in turn reduces the output current. Although planar MISFETs offer the advantages of the third quadrant, their high reverse leakage makes them impractical. Furthermore, when in the off state, MISFETs are susceptible to high-voltage spikes generated by the inductive load inductor, causing them to burn out. When the current in the load inductor suddenly changes, the energy stored in the inductor cannot be immediately dissipated, resulting in a reverse high-voltage spike. This spike can cause reverse breakdown of the MISFET, damaging the device. A freewheeling diode is often connected in parallel with the inductor to form a freewheeling circuit when the inductive load is turned off, dissipating the induced energy and protecting the MISFET. However, the additional freewheeling diode brings cost implications. Therefore, the development of junction-enhancement-type MISFET devices with integrated diodes is of great significance. Summary of the Invention

[0004] In response to the technical problems existing in the prior art, the present invention provides a MISFET with a channel bidirectional depletion integrated diode. The device is prepared by forming a column of p-type semiconductor material layers inside and on the upper surface of an n-type gallium oxide epitaxial layer, thereby obtaining a junction-enhanced, channel bidirectional depletion integrated diode MISFET.

[0005] The present invention achieves the above technical objectives through the following technical solutions: The present invention provides a MISFET with a channel bidirectional depletion integrated diode, comprising an n-type gallium oxide substrate, an n-type gallium oxide epitaxial layer formed on the front surface of the n-type gallium oxide substrate, p-type semiconductor material layers formed in rows within and on the upper surface of the n-type gallium oxide epitaxial layer, a gate electrode formed between two rows of p-type semiconductor material layers or above the region between them, a source electrode formed on the front surface of the device, and a drain electrode formed on the back surface of the n-type gallium oxide substrate;

[0006] The portion of the p-type semiconductor material layer located inside the n-type gallium oxide epitaxial layer has a multi-step structure. The region between the p-type semiconductor material layer and the upper surface of the n-type gallium oxide epitaxial layer is a gate region. Vertical conductive channels are formed on both sides of the gate region, and a horizontal conductive channel is formed between the vertical conductive channels. The height of the vertical conductive channel is no greater than the thickness of the p-type semiconductor material layer located on the n-type gallium oxide epitaxial layer. The thickness of the horizontal conductive channel is no greater than the height of the vertical conductive channel. The width of the horizontal conductive channel is greater than the minimum spacing between two columns of p-type semiconductor material layers.

[0007] As a preferred embodiment, the vertical conductive channel is prepared by injecting ions into a p-type semiconductor material layer.

[0008] As a preferred embodiment, the vertical conductive channel is prepared by implanting Si ions or N ions into a p-type semiconductor material layer located on the upper surface of the n-type gallium oxide epitaxial layer to form an n-type semiconductor.

[0009] As a preferred embodiment, the horizontal conductive channel is prepared by continuing to epitaxially grow n-type gallium oxide material on the n-type gallium oxide epitaxial layer.

[0010] As a preferred embodiment, the p-type semiconductor material layer is prepared by depositing p-type semiconductor material on the upper surface of the n-type gallium oxide epitaxial layer and etching multi-level grooves in the n-type gallium oxide epitaxial layer, and etching the p-type semiconductor material above the groove area and between the areas.

[0011] As a preferred embodiment, the source electrode and the drain electrode are both ohmic contacts.

[0012] As a preferred embodiment, the p-type semiconductor material includes but is not limited to p-type gallium nitride and p-type silicon carbide.

[0013] As a preferred embodiment, the horizontal plane shape of the gate electrode includes but is not limited to a whole rectangle and a grid.

[0014] As a preferred embodiment, the grid shape includes but is not limited to a rectangular grid shape, a circular grid shape, and a hexagonal grid shape.

[0015] As a preferred embodiment, when the gate electrode is in the shape of a whole rectangle, the horizontal plane shape of the vertical conductive channel includes but is not limited to a whole rectangle, an alternate rectangle, an alternate circle, an alternate hexagon, and an alternate strip.

[0016] The MISFET with a bidirectional channel depletion integrated diode provided by the present invention introduces p-type semiconductor material inside and above an n-type gallium oxide epitaxial layer. The p-type semiconductor material and the n-type gallium oxide epitaxial layer form a PN diode. When the device operates in the third quadrant, the p-type semiconductor material layer can be used as a freewheeling diode, reducing the cost of external devices. The portion of the p-type semiconductor material layer located inside the n-type gallium oxide epitaxial layer adopts a multi-step structure, which introduces the electric field into the device, thereby reducing the electric field intensity on the device surface, effectively shielding the gate electric field, and improving the device's withstand voltage capability. In addition, during forward operation, the current conduction area gradually increases, reducing the on-resistance. The gallium oxide conductive channel is depleted below by the p-type semiconductor material in the trench, and the gallium oxide conductive channel is depleted above by the gate, thereby achieving bidirectional channel depletion. The thickness of the horizontal conductive channel, i.e., the thickness required for complete channel depletion when the device is turned off, can be achieved by controlling the epitaxial growth rate and time, and the process difficulty is relatively low.

[0017] The present invention also provides a method for preparing the above-mentioned MISFET with a bidirectional depletion integrated diode, comprising the following steps:

[0018] An n-type gallium oxide epitaxial layer is prepared on an n-type gallium oxide substrate, and the n-type gallium oxide epitaxial layer is etched to form multiple rows of multi-level trenches, wherein every two rows of multi-level trenches constitute a unit;

[0019] Depositing a p-type semiconductor material on the surface of the trench and the n-type gallium oxide epitaxial layer and planarizing the surface;

[0020] Etching the p-type semiconductor material above the two rows of trench regions in the same unit and the p-type semiconductor material between the regions until the trench tops and the n-type gallium oxide epitaxial layer are exposed. The region where the p-type semiconductor material remains is the source region, and the region where the p-type semiconductor material is etched away is the gate region. The p-type semiconductor material and the n-type gallium oxide epitaxial layer form an integrated body diode.

[0021] Forming a vertical conductive channel by ion implantation into a portion of the p-type semiconductor material on both sides of the gate region;

[0022] Continuing to grow n-type gallium oxide epitaxially between the vertical conductive channels as a horizontal conductive channel, and the thickness of the continued epitaxial n-type gallium oxide does not exceed the thickness of the vertical conductive channel;

[0023] An insulating dielectric and polysilicon are sequentially deposited and patterned on the upper surface of the epitaxial n-type gallium oxide layer to form a gate electrode of the device;

[0024] An interlayer dielectric and ohmic metal are deposited on the front side of the device to form a source electrode, and a drain electrode is formed on the back side of the n-type gallium oxide substrate.

[0025] The present invention forms a multi-level trench structure in a gallium oxide epitaxial layer by etching, fills the trenches with p-type semiconductor material by epitaxy, and flattens the epitaxially grown p-type semiconductor material to obtain a p-type semiconductor material layer with a flat upper surface. The p-type semiconductor material forms a PN heterojunction with the n-type gallium oxide epitaxial layer. Subsequently, part of the p-type semiconductor material is etched, and the retained p-type semiconductor material is used as a source region. The etched area is used as a gate region, and vertical conductive channels are formed on both sides of the gate region. N-type gallium oxide material is further epitaxially grown between the vertical conductive channels as a horizontal conductive channel, and gate electrodes, source electrodes, and drain electrodes are further fabricated to complete the preparation of the MISFET. In this preparation method, gallium oxide layers of different thicknesses, i.e., the depleted conductive channel layer required for the enhancement-mode device, can be achieved simply by controlling the growth rate and time of the second epitaxial n-type gallium oxide material. Therefore, compared with conventional devices in which the conductive channel is prepared by photolithography, the present invention has a lower process difficulty in realizing the enhancement-mode device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1Schematic diagram of the structure of an existing gallium oxide planar MISFET device;

[0027] Figure 2 Schematic diagram of the structure of an existing trench enhancement type MISFET device;

[0028] Figure 3 This is a schematic structural diagram of a MISFET with a bidirectional depletion integrated diode in a channel according to the present invention;

[0029] Figure 4 It is a schematic structural diagram of another MISFET with a bidirectional depletion integrated diode in the channel according to the present invention;

[0030] Figure 5 This is a schematic diagram of the structure of an n-type gallium oxide epitaxial layer after preparation in a specific embodiment;

[0031] Figure 6 is a schematic diagram of the structure after multi-stage trench etching is completed in a specific embodiment;

[0032] Figure 7 is a schematic diagram of the structure after filling and epitaxial growth of p-type semiconductor material in a specific embodiment;

[0033] Figure 8 is a schematic diagram of the structure of the gate region obtained after etching in a specific embodiment;

[0034] Figure 9 is a schematic diagram of the structure after the vertical conductive channel is prepared in a specific embodiment;

[0035] Figure 10 is a schematic structural diagram of a horizontal conductive channel after preparation in a specific embodiment;

[0036] Figure 11 is a schematic structural diagram of a gate electrode after preparation is completed in a specific embodiment;

[0037] Figure 12 is a schematic diagram of the structure after the interlayer dielectric on the gate electrode is prepared in a specific embodiment;

[0038] Figure 13 This is a schematic diagram of the top view structure of the vertical conductive channel when the gate electrode is a whole rectangular segment;

[0039] Figure 14 This is a schematic diagram of the structure when the gate electrode is in a grid shape.

[0040] In the picture:

[0041] 1n-type gallium oxide substrate, 2n-type gallium oxide epitaxial layer, 3p-type semiconductor material layer, 4 horizontal conductive channels, 5 gate electrodes, 6 vertical conductive channels, 7 source electrodes, and 8 drain electrodes. DETAILED DESCRIPTION

[0042] In order to realize enhancement mode devices and reduce the electric field at the metal-semiconductor interface, the gallium oxide epitaxial layer is etched to form grooves on the surface, and then an insulating dielectric such as SiO2 or Al2O3 is deposited into the grooves to form the gate dielectric of the MISFET device. Enhancement mode MISFET devices are made. Figure 2 Compared with planar MISFET devices, enhancement-mode MISFETs have normally-off characteristics because the metal gate or polysilicon gate can completely deplete the conductive channel, and the gate electrode has a certain depth, which can effectively shield part of the electric field during reverse bias, causing the surface electric field to decrease to a certain extent. surf,EMISFET <E surf,plane MISFET , reducing leakage current.

[0043] The problem with the enhancement-mode MISFET is that the low carrier mobility of the gallium oxide material will limit the output current of the device. In addition, the ohmic contact characteristics of the gallium oxide device are difficult to improve, which will also affect the output characteristics of the device. Due to the characteristics of the gallium oxide material, if a gate dielectric deposition of a greater depth is to be achieved, it cannot be achieved through thermal oxidation. It is necessary to form deep trenches in the gallium oxide material and then deposit the gate dielectric on the surface of the deep trench, which places high demands on the process. Although the enhancement-mode MISFET device can effectively reduce the surface electric field when reversed, due to the limited trench depth, the position of the peak electric field is close to the surface, and some electric field lines will still pass through the gate to the source, resulting in the electric field at the metal-semiconductor interface being still very strong, which will still cause the device to generate a large leakage current, affecting the reliability of the device. More importantly, the gate dielectric material typically used to achieve enhancement-mode devices is very thin. When the electric field peak shifts from the surface into the bulk trench, the gate dielectric can only withstand a very small voltage, making the device more susceptible to breakdown at the gate dielectric. Consequently, the breakdown voltage and forward conduction characteristics of enhancement-mode MISFETs are affected by the gate dielectric thickness, preventing the full advantage of gallium oxide's high breakdown field strength. Furthermore, the deeper the trench, the greater the channel resistance, requiring a higher voltage to conduct the same current. Gallium oxide itself has a low thermal conductivity, and the generated heat cannot be dissipated quickly, causing device temperature to rise, affecting the device's output current. Furthermore, existing devices operating in the third quadrant are also affected by the depletion layer in the conductive channel, increasing the on-resistance and hindering third-quadrant operation. A further drawback is that the resulting enhancement-mode device is formed by depleting the gallium oxide epitaxial layer through the trench sidewalls to create an extremely narrow conductive channel. This extremely narrow conductive channel requires electron beam lithography and etching, which is a complex process and not suitable for mass production.

[0044] Based on the problems existing in the above-mentioned prior art, the present invention forms a multi-level trench structure in a gallium oxide (Ga2O3) epitaxial layer by etching, fills the trench with p-type semiconductor material (such as p-GaN, p-SiC) by epitaxy, and then flattens the epitaxially grown p-type semiconductor material by a CMP process to obtain a p-type semiconductor material layer with a flat upper surface, and the p-type semiconductor material forms a PN heterojunction with the n-Ga2O3 epitaxial layer; Si ions or N ions are implanted into part of the p-type semiconductor material to form an n-type semiconductor as a conductive channel in the vertical direction; by etching part of the p-type semiconductor material, the retained p-type semiconductor material is used as the source region, n-Ga2O3 is epitaxially grown in the etched area, and insulating dielectrics such as Al2O3 and polycrystalline silicon are deposited as the gate dielectric layer and the gate. The epitaxial gallium oxide serves as a conductive channel in the horizontal direction, thereby producing a MISFET with a channel bidirectional depletion integrated diode, the structure of which is as follows: Figure 3 、 4 The present invention will be described in further detail below with reference to the accompanying drawings.

[0045] like Figure 3 、 4 As shown, a MISFET with a channel bidirectional depletion integrated diode includes an n-type gallium oxide substrate 1, an n-type gallium oxide epitaxial layer 2 formed on the front surface of the n-type gallium oxide substrate 1, p-type semiconductor material layers 3 formed in rows inside and on the upper surface of the n-type gallium oxide epitaxial layer 2, a gate electrode 5 formed between two rows of p-type semiconductor material layers 3 or above the area between them, a source electrode 7 formed on the front surface of the device, and a drain electrode 8 formed on the back surface of the n-type gallium oxide substrate 1.

[0046] The portion of the p-type semiconductor material layer 3 located inside the n-type gallium oxide epitaxial layer 2 has a multi-step structure. The region between the p-type semiconductor material layer 3 and the upper surface of the n-type gallium oxide epitaxial layer 2 is a gate region. Vertical conductive channels 6 are formed on both sides of the gate region, and horizontal conductive channels 4 are formed between the vertical conductive channels 6. The height (i.e., thickness) of the vertical conductive channels 6 is no greater than the thickness of the p-type semiconductor material layer located on the n-type gallium oxide epitaxial layer 2. The thickness of the horizontal conductive channel 4 is no greater than the height of the vertical conductive channel 6, and the width is greater than the minimum spacing between two columns of p-type semiconductor material layers 3.

[0047] The present invention introduces p-type semiconductor material inside and above the n-type gallium oxide (n-Ga2O3) epitaxial layer. The p-type semiconductor material and n-Ga2O3 form a PN diode. When the device works in the third quadrant, it can be used as a freewheeling diode, reducing the cost of external devices. Figure 3As shown in the figure, A is the current path during forward conduction, and B is the current path during third quadrant operation. Furthermore, the introduction of p-type semiconductor material within the n-type gallium oxide epitaxial layer 2 directs the electric field into the device, reducing the electric field strength on the device surface, effectively shielding the gate electric field, and improving the device's withstand voltage. During forward operation, the current conduction area gradually increases, reducing the on-resistance. Furthermore, the introduction of p-type semiconductor material, which has better thermal conductivity than gallium oxide, improves the device's heat dissipation capabilities.

[0048] By arranging the p-type semiconductor material layer 3 located inside the n-type gallium oxide epitaxial layer 2 to have a multi-step structure, a deeper trench can be achieved without requiring high etching process requirements.

[0049] By epitaxially growing n-type gallium oxide above and between the trench regions to form a conductive channel layer, the lower portion of the gallium oxide channel is depleted by the p-type semiconductor material within the trench, while the upper portion of the gallium oxide channel is depleted by the gate, thus achieving bidirectional channel depletion. Compared to conventional enhancement-mode devices, which deplete the channel solely through the gate electrode, the gallium oxide channel in this invention, i.e., the horizontal conductive channel, can be thicker, thereby reducing channel resistance and increasing output current.

[0050] Conventional gallium oxide trench enhancement-mode MISFET devices rely on the trench sidewalls to deplete the narrow conductive channel of the epitaxial layer. Achieving complete channel depletion at a gate voltage of 0V requires an extremely narrow conductive channel width, which requires electron beam lithography and etching. This process is complex and not suitable for mass production. The horizontal conductive channel in the present invention is achieved through secondary epitaxial n-type gallium oxide. Further, by controlling the epitaxial growth rate and time, different thicknesses of n-Ga2O3 can be achieved. The thickness of the secondary epitaxial n-Ga2O3 is the thickness required for complete channel depletion when the device is turned off. Achieving this channel depletion thickness at a gate voltage of 0V is relatively easy to achieve.

[0051] In the present invention, the vertical conductive channel 6 can be realized by etching and then epitaxy, or can be prepared by directly injecting ions into the p-type semiconductor material layer 3 .

[0052] The height of the vertical conductive channel 6 can be equal to the thickness of the p-type semiconductor material layer 3 on the n-type gallium oxide epitaxial layer 2 , or can be less than or equal to the thickness.

[0053] The vertical conductive channel 6 is preferably formed by implanting Si ions (e.g., when the p-type semiconductor material is GaN) or N ions (e.g., when the p-type semiconductor material is SiC) into the p-type semiconductor material layer 3 located on the surface of the n-type gallium oxide epitaxial layer 2 to form an n-type semiconductor. In other words, the depth of the vertical conductive channel 6 is equal to the thickness of the p-type semiconductor material layer 3 located on the n-type gallium oxide epitaxial layer 2.

[0054] In the present invention, the horizontal conductive channel 4 is prepared by continuing to epitaxially grow n-type gallium oxide material on the n-type gallium oxide epitaxial layer 2 .

[0055] In the present invention, the p-type semiconductor material layer 3 is prepared by depositing p-type semiconductor material on the upper surface of the n-type gallium oxide epitaxial layer 2 and in multi-level grooves etched in the n-type gallium oxide epitaxial layer 2, and etching the p-type semiconductor material above the groove area and all the areas between the areas.

[0056] Furthermore, in the present invention, the source electrode 7 and the drain electrode 8 are both ohmic contacts.

[0057] In the present invention, p-type semiconductor materials include, but are not limited to, p-type gallium nitride and p-type silicon carbide. When p-type gallium nitride is used as the source region, it can achieve higher concentrations of doping, making it easier to form ohmic contact with metal electrodes, thereby further improving the output characteristics of the device. Furthermore, the lattice constant of gallium nitride is smaller than that of gallium oxide. The lattice mismatch between gallium nitride and gallium oxide introduces horizontal tensile stress in the gallium oxide conductive channel, which can change the band structure of the gallium oxide material in the channel and improve the mobility of electrons in the conductive channel. Silicon carbide has a better thermal conductivity, which is more conducive to device heat dissipation.

[0058] In the present invention, the horizontal shape of the gate electrode 5 includes but is not limited to a whole rectangle and a grid. That is, the gate electrode 5 can be a whole rectangle or a shape of small rectangles spaced a certain distance apart to form periodic conduction.

[0059] When the gate electrode 5 is in the shape of a whole rectangle, the horizontal plane shape of the vertical conductive channel 6 includes but is not limited to a whole rectangle, an interval rectangle, an interval circle, an interval hexagon, and an interval bar. Figure 13 As shown, ad is a structural schematic diagram of the vertical conductive channel distribution of a whole rectangle, an interval rectangle, an interval circle, and an interval hexagon when the gate electrode is a whole rectangle.

[0060] Furthermore, the grid shape of the gate electrode 5 includes but is not limited to a rectangular grid shape, a circular grid shape, and a hexagonal grid shape. Figure 14 a to c are rectangular grid, circular grid and hexagonal grid respectively.

[0061] The present invention also provides a method for preparing the above-mentioned MISFET with a bidirectional depletion integrated diode, comprising the following steps:

[0062] First, an n-type gallium oxide epitaxial layer 2 is prepared on an n-type gallium oxide substrate 1, and the n-type gallium oxide epitaxial layer 2 is etched to form multiple rows of multi-level trenches, wherein every two rows of multi-level trenches constitute a unit;

[0063] Depositing a p-type semiconductor material on the surface of the trench and the n-type gallium oxide epitaxial layer 2 and planarizing the surface;

[0064] Etching the p-type semiconductor material above the two rows of trench regions in the same unit and the p-type semiconductor material between the regions until the trench tops and the n-type gallium oxide epitaxial layer 2 are exposed. The region where the p-type semiconductor material remains is the source region, and the region where the p-type semiconductor material is etched away is the gate region. The p-type semiconductor material and the n-type gallium oxide epitaxial layer form an integrated body diode.

[0065] Forming a vertical conductive channel 6 by ion implantation into a portion of the p-type semiconductor material on both sides of the gate region;

[0066] Continue to grow n-type gallium oxide epitaxially between the vertical conductive channels 6 to form the horizontal conductive channels 4, and the thickness of the continued epitaxial n-type gallium oxide does not exceed the thickness of the vertical conductive channels 6;

[0067] An insulating dielectric and polysilicon are sequentially deposited on the upper surface of the epitaxial n-type gallium oxide layer and patterned to form a gate electrode 5 of the device;

[0068] An interlayer dielectric and an ohmic metal are deposited on the front surface of the device to form a source electrode 7 , and a drain electrode 8 is formed on the back surface of the n-type gallium oxide substrate 1 .

[0069] In order to make the technical solution of the present application clearer, the present application is described in more detail below in conjunction with a preparation method of one of the structures:

[0070] Example

[0071] This embodiment provides a MISFET with a bidirectional depletion integrated diode and a method for manufacturing the same. Figure 3 , its specific preparation method is as follows:

[0072] (1) An n-type gallium oxide epitaxial layer 2 with a thickness of about 10 μm is formed on an n-type gallium oxide substrate 1 by hydride vapor phase epitaxy (HVPE). The structure after epitaxy is as follows: Figure 5 shown.

[0073] (2) Etching the gallium oxide epitaxial layer 2 to form multi-level (N≥2) trenches, see Figure 6 .

[0074] (3) A p-type gallium nitride epitaxial layer is formed in the trench and on the surface of the gallium oxide epitaxial layer by metal organic chemical vapor deposition (MOCVD) and planarized. The structure after treatment is shown in FIG. Figure 7 .

[0075] (4) Etch the p-GaN above the trench area and the p-GaN between the trench areas until the top of the trench and the n-type gallium oxide epitaxial layer 2 are exposed. The area where GaN is retained will be used as the source area, and the area where GaN is etched will be used as the gate area. The p-GaN and n-Ga2O3 form an integrated body diode, see Figure 8 .

[0076] (5) Si ions are implanted into the p-GaN on both sides of the gate region to form n-GaN as a vertical conductive channel 6, see Figure 9 .

[0077] (6) A n-Ga2O3 epitaxial layer is formed in the gate region by epitaxy and etching or selective epitaxy as a horizontal conductive channel. The thickness of the secondary epitaxial n-Ga2O3 is the thickness required for the channel to be completely depleted when the device is turned off. The thickness of the n-Ga2O3 does not exceed the thickness of the n-GaN layer. Figure 10 .

[0078] (7) Depositing an insulating dielectric such as aluminum oxide on the surface of n-Ga2O3 and the sidewall of n-GaN, and patterning it to form the gate dielectric of the device, and depositing polysilicon on the surface of the dielectric layer, and patterning it to form the gate electrode of the device 5, see Figure 11 .

[0079] (8) Deposit Al2O3 / silicon oxide and other insulating dielectrics on the surface of the epitaxial layer and pattern them as interlayer dielectrics, see Figure 12 .

[0080] (9) Deposit ohmic metals such as Ti / Al / Ni / Au and pattern them to form a source electrode 7. The metal alloy forms an ohmic contact with the heavily Si-doped region, thereby realizing a MISFET with bidirectional channel depletion. Deposit drain metal on the back of the substrate to make a back ohmic contact to form a drain electrode 8. The completed structure is shown in FIG. Figure 3 .

[0081] The MISFET with a bidirectional depletion channel integrated diode prepared in this embodiment has at least the following advantages:

[0082] First, by introducing p-GaN material inside and above the n-Ga2O3 epitaxial layer, the p-GaN and n-Ga2O3 form a PN diode. When the device operates in the third quadrant, it can be used as a freewheeling diode, reducing the cost of external devices. In addition, using GaN material as the source region can achieve higher doping concentrations, making it easier to form ohmic contact with the metal electrode, thereby improving the device's output characteristics.

[0083] Second, the use of a multi-level stepped trench structure can achieve deeper trenches without requiring high etching processes.

[0084] Third, by filling the n-Ga2O3 epitaxial layer with p-GaN material through multi-level trenches, the electric field is introduced into the device, reducing the electric field strength on the device surface. This effectively shields the gate electric field and improves the device's withstand voltage. During forward operation, the current conduction area gradually increases, reducing the on-resistance. Furthermore, GaN material has better thermal conductivity than gallium oxide, so filling the gallium oxide with GaN material improves the device's heat dissipation capacity.

[0085] Fourth, the n-Ga2O3 channel layer is flanked by n-GaN layers. Since the lattice constant of GaN is smaller than that of Ga2O3, the lattice mismatch between GaN and Ga2O3 introduces horizontal tensile stress in the Ga2O3 conductive channel, changing the band structure of the gallium oxide material in the trench and improving the mobility of electrons in the conductive channel. In addition, the Ga2O3 conductive channel is depleted below by the p-GaN in the trench, and above the Ga2O3 conductive channel by the gate, thus achieving bidirectional depletion of the channel. Compared to conventional enhancement-mode devices that deplete the channel only through the gate electrode, the thickness of the horizontal conductive channel layer of this device can be thicker, thereby reducing the channel resistance and increasing the output current.

[0086] Fourth, conventional gallium oxide trench enhancement-mode MISFET devices rely on the trench sidewalls to deplete the narrow conductive channel of the gallium oxide epitaxial layer. To achieve complete channel depletion at a gate voltage of 0V, the width of the conductive channel must be extremely narrow. This requires electron beam lithography and etching, which is difficult to achieve and does not have mass production characteristics. The device with the above structure can achieve an enhancement-mode MISFET by controlling the thickness of the secondary epitaxial gallium oxide layer. By controlling the epitaxial growth rate and time, n-Ga2O3 layers of different thicknesses can be achieved. The thickness of n-Ga2O3 is the thickness required for the channel to be completely depleted when the device is turned off. The process difficulty of achieving the thickness required for complete channel depletion at a gate voltage of 0V is relatively low.

[0087] It should also be noted that the drawings and examples in this application are illustrative rather than restrictive. Throughout the examples in this specification, the same reference numerals in the drawings identify the same structures. Furthermore, for ease of understanding and description, the drawings may exaggerate the thickness of some layers, films, panels, regions, and the like.

[0088] It is important to note that the above embodiments are intended only to further illustrate and describe the technical solutions of the present invention and are not intended to further limit the technical solutions of the present invention. The methods of the present invention are merely preferred implementations and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A MISFET with a bidirectional depletion channel integrated diode, characterized in that: The device comprises an n-type gallium oxide substrate (1), an n-type gallium oxide epitaxial layer (2) formed on the front surface of the n-type gallium oxide substrate (1), a p-type semiconductor material layer (3) formed in rows inside and on the upper surface of the n-type gallium oxide epitaxial layer (2), a gate electrode (5) formed between two rows of p-type semiconductor material layers (3) or above the region between them, a source electrode (7) formed on the front surface of the device, and a drain electrode (8) formed on the back surface of the n-type gallium oxide substrate (1); The portion of the p-type semiconductor material layer (3) located inside the n-type gallium oxide epitaxial layer (2) presents a multi-level stepped structure; the region between the p-type semiconductor material layer (3) and the upper surface of the n-type gallium oxide epitaxial layer (2) is a gate region; vertical conductive channels (6) are formed on both sides of the gate region; a horizontal conductive channel (4) is formed between the vertical conductive channels (6); the height of the vertical conductive channel (6) is not greater than the thickness of the p-type semiconductor material layer located on the n-type gallium oxide epitaxial layer (2); the thickness of the horizontal conductive channel (4) is not greater than the height of the vertical conductive channel (6); and the width of the horizontal conductive channel (4) is greater than the minimum spacing between two rows of p-type semiconductor material layers (3); the vertical conductive channel (6) is prepared by injecting Si ions or N ions into the p-type semiconductor material layer (3) located on the upper surface of the n-type gallium oxide epitaxial layer to form an n-type semiconductor.

2. The MISFET with a bidirectional depletion channel integrated diode according to claim 1, wherein: The horizontal conductive channel (4) is prepared by continuing epitaxial growth of n-type gallium oxide material on the n-type gallium oxide epitaxial layer (2).

3. The MISFET with a bidirectional depletion channel integrated diode according to claim 1, wherein: The p-type semiconductor material layer (3) is prepared by depositing a p-type semiconductor material onto the upper surface of the n-type gallium oxide epitaxial layer (2) and etching multi-level grooves in the n-type gallium oxide epitaxial layer (2), and etching the p-type semiconductor material above the groove region and between the regions.

4. The MISFET with a bidirectional depletion channel integrated diode according to claim 1, wherein: The source electrode (7) and the drain electrode (8) are both ohmic contacts.

5. The MISFET with a bidirectional depletion channel integrated diode according to claim 1, wherein: The p-type semiconductor material is p-type gallium nitride or p-type silicon carbide.

6. The MISFET with a bidirectional depletion channel integrated diode according to claim 1, wherein: The horizontal plane shape of the gate electrode (5) is a whole rectangle, a rectangular grid, a circular grid or a hexagonal grid.

7. The MISFET with a bidirectional depletion channel integrated diode according to claim 6, characterized in that: When the gate electrode (5) is in the shape of a whole rectangle, the horizontal spatial distribution shape of the vertical conductive channel (6) is in the shape of a whole rectangle, an interval rectangle, an interval circle, an interval hexagon or an interval strip.

8. The method for preparing a MISFET with a bidirectional depletion integrated diode according to any one of claims 1 to 7, characterized in that: The following steps are involved: An n-type gallium oxide epitaxial layer (2) is prepared on an n-type gallium oxide substrate (1), and the n-type gallium oxide epitaxial layer (2) is etched to form multiple rows of multi-level trenches, wherein every two rows of multi-level trenches constitute a unit; Depositing a p-type semiconductor material on the surface of the groove and the n-type gallium oxide epitaxial layer (2) and planarizing the surface; Etching a portion of the p-type semiconductor material above the two rows of trench regions in the same unit and the p-type semiconductor material between the regions until the trench tops and the n-type gallium oxide epitaxial layer (2) are exposed, wherein the region where the p-type semiconductor material is retained is the source region, and the region where the p-type semiconductor material is etched away is the gate region, and the p-type semiconductor material and the n-type gallium oxide epitaxial layer form an integrated body diode; Forming a vertical conductive channel (6) by ion implantation into a portion of the p-type semiconductor material on both sides of the gate region; Continuing to grow n-type gallium oxide epitaxially between the vertical conductive channels (6) as the horizontal conductive channel (4), and the thickness of the continued epitaxial n-type gallium oxide does not exceed the thickness of the vertical conductive channel (6); An insulating dielectric and polysilicon are sequentially deposited on the upper surface of the epitaxial n-type gallium oxide layer and patterned to form a gate electrode (5) of the device; An interlayer dielectric and an ohmic metal are deposited on the front side of the device to form a source electrode (7), and a drain electrode (8) is formed on the back side of an n-type gallium oxide substrate (1).

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