Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes: a first display area and a second display area; a pixel circuit, which includes a first pixel circuit and a second pixel circuit, the first pixel circuit being connected to the light-emitting element of the first display area, and the second pixel circuit being connected to the light-emitting element of the second display area; the operation of the pixel circuit includes a first mode and a second mode; in the first mode, the data refresh frequency of the first display area is F11, and the data refresh frequency of the second display area is F12; in the second mode, the data refresh frequency of the first display area is F21, and the data refresh frequency of the second display area is F22; wherein, |F21-F11|≠|F22-F12|. According to the embodiments of this application, the data refresh frequency of different display areas can be adjusted independently, which is beneficial for different display areas to better perform their respective functions.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the continuous development of display technology and the increasing demands of consumers for display panels, the functions integrated into display panels are becoming more and more numerous. In some scenarios, different display functions are required for the same display panel. For example, displaying game screens and movie screens, as well as displaying text and time information, requires display panels to have different functions.

[0003] When the display functions or display effects of a display panel are different, it is often necessary to carry out differentiated design of the display panel in different areas. Therefore, how to carry out differentiated design is a hot research topic in this field at present. Summary of the Invention

[0004] This application provides a display panel and display device, wherein the data refresh rate of different display areas can be adjusted independently, which is beneficial for different display areas to better perform their respective functions.

[0005] In a first aspect, embodiments of this application provide a display panel, including: a first display area and a second display area; a pixel circuit, the pixel circuit including a first pixel circuit and a second pixel circuit, the first pixel circuit being connected to a light-emitting element of the first display area, and the second pixel circuit being connected to a light-emitting element of the second display area; the operation process of the pixel circuit includes a first mode and a second mode; in the first mode, the data refresh frequency of the first display area is F11, and the data refresh frequency of the second display area is F12; in the second mode, the data refresh frequency of the first display area is F21, and the data refresh frequency of the second display area is F22; wherein, |F21-F11|≠|F22-F12|.

[0006] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display device including a display panel as described in the first aspect embodiment.

[0007] As described above, the display panel and display device provided in this application embodiment have different first display areas and second display areas. In the same mode, the data refresh rates of the first and second display areas have different requirements. In different modes, the data refresh rates of the first and second display areas can still have different requirements. However, in this application embodiment, |F21-F11|≠|F22-F12|, so the changes in the data refresh rates of the two display areas can be inconsistent. The data refresh rates of different display areas can be adjusted independently in different modes, which is beneficial for different display areas to better perform their respective functions. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application;

[0010] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0011] Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of yet another pixel circuit provided in an embodiment of this application;

[0013] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0014] Figure 6 This is a schematic diagram of yet another pixel circuit provided in an embodiment of this application;

[0015] Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0016] Figure 8 This is a schematic diagram of another display panel provided in an embodiment of this application;

[0017] Figures 9 to 21 These are some schematic diagrams showing the data refresh rates of various display areas in the display panel provided in the embodiments of this application;

[0018] Figure 22 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0019] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0020] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0021] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0022] It should be noted that when a component is described as "connected" or "electrically connected" to another component, it can be directly connected to the other component, or there may be one or more intermediate components in between.

[0023] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0024] This application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0025] One aspect of this application provides a display panel, which can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (micro LED) display panel, or other types of display panels. This embodiment does not impose any special limitations on this type of display panel.

[0026] Figure 1A schematic diagram of a display panel according to an embodiment of this application is shown. The display panel includes a first display area 1, a second display area 2, and pixel circuitry.

[0027] The pixel circuit includes a first pixel circuit 101 and a second pixel circuit 201. The first pixel circuit 101 can provide driving current for the light-emitting element L in the first display area 1, and the second pixel circuit 201 can provide driving current for the light-emitting element L in the second display area 2.

[0028] Optional, see reference Figures 2-7 , Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of yet another pixel circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of yet another pixel circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. The pixel circuit provided in this embodiment includes a data writing module 11, a driving module 12, and a compensation module 13; the driving module 12 includes a driving transistor T2, which is used to provide driving current to the light-emitting element L of the display panel 100; the data writing module 11 is connected to the first terminal (i.e., node N2) of the driving transistor T2 and is used to provide a data signal Vdata to the driving transistor T2; the compensation module 13 is connected between the gate (i.e., node N1) and the second terminal (i.e., node N3) of the driving transistor and is used to compensate for the threshold voltage of the driving transistor T2.

[0029] In addition, the pixel circuit may also include a reset module 15 for providing a reset signal Vref to the gate of the driving transistor T2; an initialization module 16 for providing an initialization signal Vini to the light-emitting element L; and a light-emitting control module 17 for selectively allowing the light-emitting element L to enter the light-emitting stage. Optionally, the light-emitting control module 17 includes a first light-emitting control module 171 and a second light-emitting control module 172. The first light-emitting control module 171 is connected between the first power signal terminal PVDD and one terminal of the driving transistor T2, and the second light-emitting control module 172 is connected between the other terminal of the driving transistor T2 and the light-emitting element L.

[0030] Optionally, in this embodiment, the control terminal of the data writing module 11 receives a first scan signal S1, which controls the opening and closing of the data writing module 11; the control terminal of the compensation module 13 receives a second scan signal S2, which controls the opening and closing of the compensation module 13; the control terminal of the reset module 15 receives a third scan signal S3, which controls the opening and closing of the reset module 15; the control terminal of the initialization module 16 receives a fourth scan signal S4, which controls the opening and closing of the initialization module 16; and the control terminal of the light emission control module 17 receives a light emission control signal EM, which controls the opening and closing of the light emission control module 17.

[0031] Alternatively, in this embodiment, the data writing module 11 includes a data writing transistor T1, and a first scan signal S1 controls the turning on and off of the data writing transistor T1; the compensation module 13 includes a compensation transistor T3, and a second scan signal S2 controls the turning on and off of the compensation transistor T3; the reset module 15 includes a reset transistor T5, and a third scan signal S3 controls the turning on and off of the reset transistor T5; the initialization module 16 includes an initialization transistor T6, and a fourth scan signal S4 controls the turning on and off of the initialization transistor T6; the first light-emitting control module 171 includes a first light-emitting control transistor T7, and the second light-emitting control module 172 includes a second light-emitting control transistor T8, and a light-emitting control signal EM controls the turning on and off of the first light-emitting control transistor T7 and the second light-emitting control transistor T8.

[0032] It should be noted that, as Figures 4-7 As shown, the pixel circuit may further include a bias adjustment module 14 for providing a bias adjustment signal to the driving transistor T2. Optionally, as... Figure 4 and Figure 6 As shown, the bias adjustment module 14 is connected to the first terminal (i.e., node N2) of the driving transistor T2; as Figure 5 and Figure 7 As shown, the bias adjustment module 14 is connected to the second terminal (i.e., node N3) of the driving transistor T2. Optionally, the control terminal of the bias adjustment module 14 receives a bias adjustment control signal SV, which controls the switching on and off of the bias adjustment module 14. The bias adjustment module 14 includes a bias adjustment transistor T4, which is switched on and off by the bias adjustment control signal SV.

[0033] Additionally, it should be noted that, as Figure 2 , Figure 4 , Figure 5The pixel circuit shown has a PMOS transistor as the driving transistor T2. The pixel circuit also includes a storage capacitor C1. The first terminal of the storage capacitor C1 is connected to the first power supply signal terminal, and the second terminal is connected to the gate of the driving transistor T2, used to store the signal transmitted to the gate of the driving transistor T2. Figure 3 , Figure 6 , Figure 7 The pixel circuit shown has an NMOS transistor driving transistor T2. The pixel circuit also includes a storage capacitor C1. The first terminal of the storage capacitor C1 is connected to the light-emitting element L, and the second terminal is connected to the gate of the driving transistor T2. The storage capacitor C1 is used to store the signal transmitted to the gate of the driving transistor T2.

[0034] Furthermore, the second electrode of the light-emitting element is connected to the second power signal terminal PVEE. A driving current is generated through the potential difference between the power signal terminals PVDD and PVEE, thereby driving the light-emitting element to emit light. In this embodiment, the positive power signal can be the PVDD signal, and the negative power signal can be the PVEE signal.

[0035] also, Figures 2-7 This application provides only a few exemplary pixel circuit structures, but does not include all of them. Other pixel circuits whose data refresh rates meet the requirements of this application are all within the scope of protection of this application's embodiments, and will not be described further in this embodiment.

[0036] In this embodiment, the operation of the pixel circuit may include a first mode and a second mode.

[0037] In the first mode, the data refresh frequency of the first display area 1 is F11, and the data refresh frequency of the second display area 2 is F12; in the second mode, the data refresh frequency of the first display area 1 is F21, and the data refresh frequency of the second display area 2 is F22; wherein, |F21-F11|≠|F22-F12|.

[0038] The data refresh frequency refers to the frequency at which the data signal Vdata is written into the gate of the driving transistor T2 in the pixel circuit. The higher the data refresh frequency, the higher the frequency of the gate potential change of the driving transistor T2; conversely, the lower the data refresh frequency, the lower the frequency of the gate potential change of the driving transistor T2.

[0039] The display panel has different first and second display areas. In the same mode, the data refresh rates for the first and second display areas have different requirements. In different modes, the data refresh rates for the first and second display areas can still have different requirements. However, in this embodiment, |F21-F11|≠|F22-F12|, so the changes in the data refresh rates of the two display areas can be inconsistent. The data refresh rates of different display areas can be adjusted independently in different modes, which helps to allow different display areas to better perform their respective functions.

[0040] It is understandable that the data refresh frequency of the first and second display areas specified above satisfies |F21-F11|≠|F22-F12|, which can be either |F21-F11|>|F22-F12| or |F21-F11|<|F22-F12|.

[0041] When |F21-F11|>|F22-F12|, it means that the difference between the data refresh rates of the first display area in the first mode and the second mode is greater than the difference between the data refresh rates of the second display area in the first mode and the second mode; when |F21-F11|<|F22-F12|, it means that the difference between the data refresh rates of the first display area in the first mode and the second mode is less than the difference between the data refresh rates of the second display area in the first mode and the second mode.

[0042] For example, |F21-F11|≠|F22-F12| may include the following scenarios:

[0043] Scenario 1: In one of the first and second modes, the data refresh rates of the first and second display areas are the same; in the other mode, the data refresh rates of the first and second display areas are different. For example, in the first mode, the data refresh rates of both the first and second display areas are 120Hz; in the second mode, the data refresh rates of both the first and second display areas may decrease or both increase, but the magnitude of the decrease or increase is different. Another example: in the first mode, the data refresh rates of both the first and second display areas are 60Hz; in the second mode, the data refresh rate of one of the first and second display areas increases, while the data refresh rate of the other decreases. Yet another example: in the first mode, the data refresh rates of both the first and second display areas are 60Hz; in the second mode, the data refresh rate of one of the first and second display areas remains unchanged, while the data refresh rate of the other increases or decreases.

[0044] Scenario 2: In either the first or second mode, the data refresh rates of the first and second display areas are different; in the other mode, the data refresh rates of the first and second display areas remain different. For example, in the first mode, the data refresh rate of the first display area is 120Hz, and the data refresh rate of the second display area is 60Hz; in the second mode, the data refresh rate of at least one of the first and second display areas increases or decreases.

[0045] The above are just examples of several display scenarios, but not all of them. Other scenarios in which the data refresh rates of the first and second display areas meet the requirements of this application are all within the scope of protection of the embodiments of this application, and will not be described in detail in this embodiment.

[0046] The following explains the situation where the data refresh rate of the first and second display areas can be further satisfied.

[0047] In some embodiments, the data refresh rate of the first display area and the second display area can satisfy (F21-F11)×(F22-F12)≥0.

[0048] When (F21-F11)×(F22-F12)=0, the data refresh rate of at least one of the first display area and the second display area can remain unchanged. For example, if F21=F11, the data refresh rate of the first display area is the same in the first mode and the second mode; or, if F22-F12, the data refresh rate of the second display area is the same in the first mode and the second mode.

[0049] When (F21-F11)×(F22-F12)>0, the data refresh rates of the first and second display areas can exhibit the same trend. For example, when switching from the first mode to the second mode, the data refresh rates of both the first and second display areas may increase, or the data refresh rates of both the first and second display areas may decrease.

[0050] In some embodiments, the data refresh rates of the first display area and the second display area may satisfy F11 = F21, F21 ≠ F22; or, F12 = F22, F11 ≠ F21.

[0051] When F11 = F21 and F21 ≠ F22, the first display area has the same data refresh rate in both the first and second modes, while the second display area has different data refresh rates in both modes. For example, the first display area has a data refresh rate of 120Hz in both modes, the second display area has a data refresh rate of 120Hz in the first mode, and the second display area has a data refresh rate of 60Hz or 144Hz in the second mode.

[0052] When F12 = F22 and F11 ≠ F21, the second display area has the same data refresh rate in both the first and second modes; however, it may also have different data refresh rates in the second and second modes. For example, the second display area may have a data refresh rate of 120Hz in both modes, while the first display area may have a data refresh rate of 120Hz in the first mode and a data refresh rate of 60Hz or 144Hz in the second mode.

[0053] In some embodiments, the data refresh rates of the first display area and the second display area may satisfy F21-F11>0, F22-F12>0; or, F21-F11<0, F22-F12<0.

[0054] When F21-F11>0 and F22-F12>0, the data refresh rates of both the first and second display areas increase when switching from the first mode to the second mode. For example, in the first mode, the data refresh rate of the first display area is 60Hz and the data refresh rate of the second display area is 90Hz; in the second mode, the data refresh rate of the first display area is 120Hz and the data refresh rate of the second display area is 144Hz.

[0055] When F21-F11 < 0 and F22-F12 < 0, the data refresh rates of both the first and second display areas decrease when switching from the first mode to the second mode. For example, in the first mode, the data refresh rate of the first display area is 60 Hz and the data refresh rate of the second display area is 90 Hz; in the second mode, the data refresh rate of the first display area is 30 Hz and the data refresh rate of the second display area is 45 Hz.

[0056] In other embodiments, the data refresh rates of the first and second display areas may satisfy (F21-F11)×(F22-F12)<0. The trends of change in the data refresh rates of the first and second display areas may differ. For example, when switching from the first mode to the second mode, the data refresh rate of one of the first and second display areas may increase, while the data refresh rate of the other may decrease.

[0057] In some embodiments, the data refresh rates of the first display area and the second display area may satisfy F21-F11>0, F22-F12<0; or F21-F11<0, F22-F12>0.

[0058] When F21-F11>0 and F22-F12<0, the data refresh rate of the first display area increases and the data refresh rate of the second display area decreases when switching from the first mode to the second mode. For example, in the first mode, the data refresh rate of both the first and second display areas is 10Hz; in the second mode, the data refresh rate of both the first and second display areas is 120Hz and 1Hz.

[0059] When F21-F11 < 0 and F22-F12 > 0, the data refresh rate of the first display area decreases and the data refresh rate of the second display area increases when switching from the first mode to the second mode. For example, in the first mode, the data refresh rate of both the first and second display areas is 120 Hz; in the second mode, the data refresh rate of both the first and second display areas is 60 Hz and 144 Hz.

[0060] In some embodiments, the data refresh rates of the first display area and the second display area can satisfy |F11-F12|≠|F21-F22|. |F11-F12| represents the difference in data refresh rates between the first display area and the second display area in the first mode, and |F21-F22| represents the difference in data refresh rates between the first display area and the second display area in the second mode. The difference in data refresh rates between the first display area and the second display area in different modes can be adjusted independently, which is more conducive to enabling different display areas to better perform their respective functions.

[0061] In some embodiments, the data refresh rates of the first display area and the second display area may satisfy F11 < F21, |F11-F12| < |F21-F22|; or, F11 > F21, |F11-F12| > |F21-F22|.

[0062] When F11 < F21, the data refresh rate of the first display area increases when switching from the first mode to the second mode. The higher the data refresh rate in a certain mode, the greater the difference in data refresh rates between the first and second display areas in that mode.

[0063] When F11 > F21, the data refresh rate of the first display area decreases when switching from the first mode to the second mode. The lower the data refresh rate in a certain mode, the smaller the difference in data refresh rates between the first and second display areas in that mode.

[0064] For example, in the first mode, the data refresh rate of the first display area is 10Hz, and the data refresh rate of the second display area is 1Hz, |F11-F12|=9Hz; in the second mode, the data refresh rate of the first display area is 60Hz, and the data refresh rate of the second display area is 30Hz, |F21-F22|=30Hz. The data refresh rates of the first and second display areas are larger in the second mode, and the difference in data refresh rates between the two display areas increases when switching from the first mode to the second mode.

[0065] For example, in the first mode, the data refresh rate of the first display area is 60Hz, and the data refresh rate of the second display area is 30Hz, |F11-F12|=30Hz; in the second mode, the data refresh rate of the first display area is 10Hz, and the data refresh rate of the second display area is 1Hz, |F21-F22|=9Hz. The data refresh rate of the first and second display areas is higher in the first mode, and the difference in data refresh rates between the two display areas decreases when switching from the first mode to the second mode.

[0066] In some embodiments, the data refresh rates of the first display area and the second display area may satisfy F11 < F21, F11 / F12 > F21 / F22 ≥ 1; or, F11 > F21, 1 ≤ F11 / F12 < F21 / F22.

[0067] When F11 < F21, the data refresh rate of the first display area increases when switching from the first mode to the second mode. The higher the data refresh rate in a given mode, the smaller the ratio of the data refresh rates of the first and second display areas can be in that mode.

[0068] When F11 > F21, the data refresh rate of the first display area decreases when switching from the first mode to the second mode. The lower the data refresh rate in a certain mode, the larger the ratio of the data refresh rates of the first and second display areas can be in that mode.

[0069] For example, in the first mode, the data refresh rate of the first display area is 10Hz, and the data refresh rate of the second display area is 1Hz, F11 / F12 = 10; in the second mode, the data refresh rate of the first display area is 60Hz, and the data refresh rate of the second display area is 30Hz, F21 / F22 = 2. The data refresh rates of the first and second display areas are higher in the second mode, and the ratio of their refresh rates decreases when switching from the first mode to the second mode.

[0070] For example, in the first mode, the data refresh rate of the first display area is 60Hz, and the data refresh rate of the second display area is 30Hz, F11 / F12 = 2; in the second mode, the data refresh rate of the first display area is 10Hz, and the data refresh rate of the second display area is 1Hz, F21 / F22 = 10. The data refresh rates of the first and second display areas are higher in the first mode, so when switching from the first mode to the second mode, the ratio of the data refresh rates of the two display areas in the second mode increases.

[0071] In some embodiments, such as Figure 8 As shown, the display panel also includes a third display area 3. The pixel circuit may further include a third pixel circuit 301, which can provide driving current to the light-emitting element L in the third display area 3.

[0072] In the first mode, the data refresh rate of the third display area is F13; in the second mode, the data refresh rate of the third display area is F23; |F21-F11|≠|F23-F13|; and / or, |F22-F12|≠|F23-F13|. In this embodiment, the change in the data refresh rate of the third display area is different from the change in the data refresh rate of at least one of the first and second display areas, allowing the data refresh rates of the three display areas to be adjusted independently in different modes, which is beneficial for different display areas to better perform their respective functions.

[0073] In some embodiments, such as Figure 8 As shown, the first display area 1, the second display area 2, and the third display area 3 are arranged sequentially along a first direction. The first direction can be a column direction. (F11-F12)×(F12-F13)>0; and / or, (F21-F22)×(F22-F23)>0. In the first mode, the data refresh rate of the three display areas arranged in the first direction can increase or decrease sequentially; and / or, in the second mode, the data refresh rate of the three display areas arranged in the first direction can increase or decrease sequentially. The sequential change in the data refresh rate of the three display areas can improve the flickering problem caused by excessively large transitions in the data refresh rates of different display areas.

[0074] For example, if F11-F12 > 0 and F12-F13 > 0, the data refresh rate of the three display areas can decrease sequentially in the first mode. Alternatively, if F11-F12 < 0 and F12-F13 < 0, the data refresh rate of the three display areas can increase sequentially in the first mode.

[0075] With F21-F22>0 and F22-F23>0, the data refresh rate of the three display areas can be decreased sequentially in the second mode. Alternatively, with F21-F22<0 and F22-F23<0, the data refresh rate of the three display areas can be increased sequentially in the second mode.

[0076] In some embodiments, |F11-F13|≠|F21-F23|; and / or, |F12-F13|≠|F22-F23|. |F11-F13| represents the difference in data refresh rates between the first display area and the third display area in the first mode, and |F21-F23| represents the difference in data refresh rates between the first display area and the third display area in the second mode; |F12-F13| represents the difference in data refresh rates between the second display area and the third display area in the first mode, and |F22-F23| represents the difference in data refresh rates between the second display area and the third display area in the second mode.

[0077] In different modes, the data refresh rate of at least one of the first and second display areas differs from that of the third display area. The difference in data refresh rate between the first and second display areas and the third display area in different modes can be adjusted individually, which is more conducive to enabling different display areas to better perform their respective functions.

[0078] In some embodiments, F11 / F12≤F12 / F13; and / or, F21 / F22≤F22 / F23.

[0079] For example, if F11 / F12 ≤ F12 / F13, in the first mode, the data refresh rate of the three display areas arranged in the first direction can decrease sequentially. As another example, if F21 / F22 ≤ F22 / F23, in the second mode, the data refresh rate of the three display areas arranged in the first direction can decrease sequentially.

[0080] The lower the data refresh rate in a certain mode, the larger the ratio of the data refresh rates of different display areas in that mode can be. For example, in a certain mode between the first and second modes, the data refresh rate of the first display area is 120Hz, the data refresh rate of the second display area is 60Hz, and the data refresh rate of the third display area is 10Hz. F11 / F12 = 120 / 60 = 2, F12 / F13 = 60 / 10 = 6.

[0081] In some embodiments, such as Figure 8 As shown, the first display area 1, the second display area 2, and the third display area 3 are arranged sequentially along the first direction. The first direction can be a column direction. (F12-F11)×(F12-F13)>0; and / or, (F22-F21)×(F22-F23)>0.

[0082] In a first direction, the second display area 2 is located between the first display area 1 and the third display area 3. In a first mode, the data refresh rate of the second display area can be greater than the data refresh rates of the first and third display areas on either side of it; or, in the first mode, the data refresh rate of the second display area can be less than the data refresh rates of the first and third display areas on either side of it. And / or, in a second mode, the data refresh rate of the second display area can be greater than the data refresh rates of the first and third display areas on either side of it; or, in the second mode, the data refresh rate of the second display area can be less than the data refresh rates of the first and third display areas on either side of it.

[0083] For example, such as Figure 9 As shown, in the first mode and / or the second mode, the data refresh rate of the first display area 1 is 30Hz, the data refresh rate of the second display area 2 is 60Hz, and the data refresh rate of the third display area 3 is 30Hz. Alternatively, as... Figure 10 As shown, in the first mode and / or the second mode, the data refresh rate of the first display area 1 is 30Hz, the data refresh rate of the second display area 2 is 10Hz, and the data refresh rate of the third display area 3 is 30Hz.

[0084] For example, such as Figure 11 As shown, in the first mode and / or the second mode, the data refresh rate of the first display area 1 is 10Hz, the data refresh rate of the second display area 2 is 60Hz, and the data refresh rate of the third display area 3 is 30Hz. Alternatively, as... Figure 12 As shown, in the first mode and / or the second mode, the data refresh rate of the first display area 1 is 60Hz, the data refresh rate of the second display area 2 is 10Hz, and the data refresh rate of the third display area 3 is 30Hz.

[0085] In some embodiments, |F12-F11| = |F12-F13|; and / or, |F22-F21| = |F22-F23|. Thus, in the first mode and / or the second mode, the data refresh rates of the first display area and the third display area can be the same; that is, the data refresh rates of the first display area and the third display area can be designed symmetrically with respect to the data refresh rate of the second display area.

[0086] For example, such as Figure 9 As shown, when the data refresh rate of the second display area 2 is higher, the data refresh rates of the first display area 1 and the third display area 3 can be the same. Alternatively, as... Figure 10 As shown, when the data refresh rate of the second display area 2 is low, the data refresh rates of the first display area 1 and the third display area 3 can be the same.

[0087] In other embodiments, |F12-F11|≠|F12-F13|; and / or, |F22-F21|≠|F22-F23|. Thus, in the first mode and / or the second mode, the data refresh rates of the first display area and the third display area can be different; that is, the data refresh rates of the first display area and the third display area can be asymmetrically designed with respect to the data refresh rate of the second display area.

[0088] For example, such as Figure 11 As shown, when the data refresh rate of the second display area 2 is higher, the data refresh rates of the first display area 1 and the third display area 3 can be different. Alternatively, as... Figure 10 As shown, when the data refresh rate of the second display area 2 is low, the data refresh rates of the first display area 1 and the third display area 3 may be different.

[0089] In some embodiments, |F12-F11| > |F12-F13|; and / or, |F22-F21| > |F22-F23|. |F12-F11| represents the difference in data refresh rates between the second display area and the first display area in the first mode, |F12-F13| represents the difference in data refresh rates between the second display area and the third display area in the first mode, |F22-F21| represents the difference in data refresh rates between the second display area and the first display area in the second mode, and |F22-F23| represents the difference in data refresh rates between the second display area and the third display area in the second mode.

[0090] In the first mode, the difference in data refresh rate between the second display area and the first display area can be relatively large, and the difference in data refresh rate between the second display area and the third display area can be relatively small; and / or, in the second mode, the difference in data refresh rate between the second display area and the first display area can be relatively large, and the difference in data refresh rate between the second display area and the third display area can be relatively small.

[0091] In some embodiments, |F12-F11| > |F12-F13|, and |F22-F21| < |F22-F23|; or, |F12-F11| < |F12-F13|, and |F22-F21| > |F22-F23|.

[0092] In the first mode, the difference in data refresh rates between the second and first display areas is greater than the difference in data refresh rates between the second and third display areas; and in the second mode, the difference in data refresh rates between the second and first display areas is less than the difference in data refresh rates between the second and third display areas. Alternatively, in the first mode, the difference in data refresh rates between the second and first display areas is less than the difference in data refresh rates between the second and third display areas; and in the second mode, the difference in data refresh rates between the second and first display areas is greater than the difference in data refresh rates between the second and third display areas.

[0093] In some embodiments, such as Figure 8 As shown, the first display area 1, the second display area 2, and the third display area 3 are arranged sequentially along a first direction, which can be a column direction. (F12-F11)×(F12-F13)>0, and (F21-F22)×(F22-F23)>0; or, (F11-F12)×(F12-F13)>0, and (F22-F21)×(F22-F23)>0.

[0094] When (F12-F11)×(F12-F13)>0 and (F21-F22)×(F22-F23)>0, in the first mode, the data refresh rate of the second display area can be greater than the data refresh rates of the first and third display areas, or in the first mode, the data refresh rate of the second display area can be less than the data refresh rates of the first and third display areas; in the second mode, the data refresh rates of the three display areas can decrease or increase sequentially.

[0095] When (F11-F12)×(F12-F13)>0 and (F22-F21)×(F22-F23)>0, in the first mode, the data refresh rates of the three display areas can decrease or increase sequentially. In the second mode, the data refresh rate of the second display area can be greater than the data refresh rates of the first and third display areas, or, in the second mode, the data refresh rate of the second display area can be less than the data refresh rates of the first and third display areas.

[0096] For example, such as Figure 13 As shown, in the first mode, the data refresh rate of the first display area 1 is 60Hz, the data refresh rate of the second display area 2 is 120Hz, and the data refresh rate of the third display area 3 is 90Hz. In the second mode, the data refresh rate of the first display area 1 is 120Hz, the data refresh rate of the second display area 2 is 90Hz, and the data refresh rate of the third display area 3 is 60Hz.

[0097] For example, such as Figure 14 As shown, in the first mode, the data refresh rate of the first display area 1 is 10Hz, the data refresh rate of the second display area 2 is 30Hz, and the data refresh rate of the third display area 3 is 60Hz. In the second mode, the data refresh rate of the first display area 1 is 30Hz, the data refresh rate of the second display area 2 is 10Hz, and the data refresh rate of the third display area 3 is 60Hz.

[0098] It should be noted that the above embodiments only take two and / or three display areas as examples, and the display panel may include more than three display areas.

[0099] For example, such as Figure 15 As shown, the display panel may include five display areas arranged sequentially in the first direction, namely area A1 to area A5, and three of the areas A1 to area A5 may be the first display area, the second display area and the third display area respectively.

[0100] For example, the display panel may include shift register circuits, wherein shift register circuit VSR1 can be used to control the data refresh frequency of area A1, shift register circuit VSR2 can be used to control the data refresh frequency of area A2, shift register circuit VSR3 can be used to control the data refresh frequency of area A3, shift register circuit VSR4 can be used to control the data refresh frequency of area A4, and shift register circuit VSR5 can be used to control the data refresh frequency of area A5.

[0101] As an example, such as Figure 16 or Figure 17 As shown, for example, the image can be displayed only in area A3, while other areas can be black. In this case, area A3 can be refreshed at a higher data refresh rate, and the data refresh rate can be reduced from the middle area to the two side areas. In this way, the data refresh rate decreases from the display area to the non-display area, which can improve the flickering problem caused by the large difference in data refresh rate and reduce the power consumption of the area with the lower data refresh rate.

[0102] As another example, such as Figure 18 or Figure 19 As shown, for example, the image can be displayed only in area A2, while other areas can be black. In this case, area A2 can be refreshed at a higher data refresh rate, and the data refresh rate can be reduced sequentially from area A2 to the two side areas. In this way, the data refresh rate decreases sequentially from the display area to the non-display area, which can improve the flickering problem caused by the large difference in data refresh rate and reduce the power consumption of areas with lower data refresh rates.

[0103] As yet another example, such as Figure 20 or Figure 21As shown, for example, the image can be displayed only in area A1, while other areas can be black. In this case, area A1 can be refreshed at a higher data refresh rate, and the data refresh rate can be reduced sequentially from area A1 to area A5. In this way, the data refresh rate decreases sequentially from the display area to the non-display area, which can improve the flickering problem caused by the large difference in data refresh rate and reduce the power consumption of areas with lower data refresh rates.

[0104] It should be noted that the specific values ​​of the data refresh frequency of each display area in this application may include, but are not limited to, the specific values ​​of the data refresh frequency in the above examples and figures.

[0105] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of this application are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0106] Based on the same inventive concept, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 22 , Figure 22 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 22 The provided display device 1000 includes a display panel 100, which can be the display panel described in any of the foregoing embodiments. Figure 22 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0107] Based on the above description, the display panel and display device provided in this application include a first display area 1, a second display area 2, and pixel circuitry.

[0108] The pixel circuit includes a first pixel circuit 101 and a second pixel circuit 201. The first pixel circuit 101 can provide driving current for the light-emitting element L in the first display area 1, and the second pixel circuit 201 can provide driving current for the light-emitting element L in the second display area 2.

[0109] The operation of a pixel circuit can include a first mode and a second mode.

[0110] In the first mode, the data refresh frequency of the first display area 1 is F11, and the data refresh frequency of the second display area 2 is F12; in the second mode, the data refresh frequency of the first display area 1 is F21, and the data refresh frequency of the second display area 2 is F22; wherein, |F21-F11|≠|F22-F12|.

[0111] The data refresh frequency refers to the frequency at which the data signal Vdata is written to the gate of the driving transistor T2. The higher the data refresh frequency, the higher the frequency of the gate potential change of the driving transistor T2; conversely, the lower the data refresh frequency, the lower the frequency of the gate potential change of the driving transistor T2.

[0112] The display panel has different first and second display areas. In the same mode, the data refresh rates for the first and second display areas have different requirements. In different modes, the data refresh rates for the first and second display areas can still have different requirements. However, in this embodiment, |F21-F11|≠|F22-F12|, so the changes in the data refresh rates of the two display areas can be inconsistent. The data refresh rates of different display areas can be adjusted independently in different modes, which helps to allow different display areas to better perform their respective functions.

[0113] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, include: First display area and second display area; The pixel circuit includes a first pixel circuit and a second pixel circuit, wherein the first pixel circuit is connected to the light-emitting element of the first display area, and the second pixel circuit is connected to the light-emitting element of the second display area; The operation of the pixel circuit includes a first mode and a second mode. In the first mode, the data refresh rate of the first display area is F11, and the data refresh rate of the second display area is F12; In the second mode, the data refresh rate of the first display area is F21, and the data refresh rate of the second display area is F22; wherein... |F21-F11|≠|F22-F12|; The display panel includes multiple areas arranged sequentially along a first direction. At least one of the multiple areas displays an image, while the other areas are black. The data refresh rate decreases sequentially from the display area to the non-display area.

2. The display panel according to claim 1, characterized in that, (F21-F11)×(F22-F12)≥0.

3. The display panel according to claim 2, characterized in that, F11=F21, F21≠F22; or, F12=F22, F11≠F21.

4. The display panel according to claim 2, characterized in that, F21-F11>0, F22-F12>0; or, F21-F11<0, F22-F12<0.

5. The display panel according to claim 1, characterized in that, (F21-F11)×(F22-F12)<0.

6. The display panel according to claim 5, characterized in that, F21-F11>0, F22-F12<0; or, F21-F11<0, F22-F12>0.

7. The display panel according to claim 1, characterized in that, |F11-F12|≠|F21-F22|.

8. The display panel according to claim 7, characterized in that, F11 < F21, |F11-F12| < |F21-F22|; or, F11>F21, |F11-F12|>|F21-F22|.

9. The display panel according to claim 1, characterized in that, F11 < F21, F11 / F12 > F21 / F22 ≥ 1; or, F11>F21, 1≤F11 / F12<F21 / F22.

10. The display panel according to claim 1, characterized in that, The display panel also includes a third display area; In the first mode, the data refresh rate of the third display area is F13; In the second mode, the data refresh rate of the third display area is F23; |F21-F11|≠|F23-F13|; and / or, |F22-F12|≠|F23-F13|.

11. The display panel according to claim 10, characterized in that, The first display area, the second display area, and the third display area are arranged sequentially along the first direction; (F11-F12)×(F12-F13)>0; and / or, (F21-F22)×(F22-F23)>0.

12. The display panel according to claim 11, characterized in that, |F11-F13|≠|F21-F23|; and / or, |F12-F13|≠|F22-F23|.

13. The display panel according to claim 11, characterized in that, F11 / F12≤F12 / F13; and / or, F21 / F22≤F22 / F23.

14. The display panel according to claim 10, characterized in that, The first display area, the second display area, and the third display area are arranged sequentially along the first direction; (F12-F11)×(F12-F13)>0; and / or, (F22-F21)×(F22-F23)>0.

15. The display panel according to claim 14, characterized in that, |F12-F11|=|F12-F13|; and / or, |F22-F21|=|F22-F23|.

16. The display panel according to claim 14, characterized in that, |F12-F11|≠|F12-F13|; and / or, |F22-F21|≠|F22-F23|.

17. The display panel according to claim 16, characterized in that, |F12-F11|>|F12-F13|;and / or, |F22-F21|>|F22-F23|.

18. The display panel according to claim 17, characterized in that, |F12-F11|>|F12-F13|, and |F22-F21|<|F22-F23|; or, |F12-F11|<|F12-F13|, and |F22-F21|>|F22-F23|.

19. The display panel according to claim 10, characterized in that, The first display area, the second display area, and the third display area are arranged sequentially along the first direction; (F12-F11)×(F12-F13)>0, and (F21-F22)×(F22-F23)>0; or, (F11-F12)×(F12-F13)>0, and (F22-F21)×(F22-F23)>0.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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