Pixel circuit, driving method thereof and display panel

Abstract

The application provides a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a driving module, a first initialization module and a light emitting device. The first initialization module is electrically connected with a second end of the driving module. The first initialization module is configured to transmit a third initialization voltage to a first end and a second end of the driving module in a third initialization stage. The light emitting device is connected between the second end of the driving module and a second power supply. The driving module is configured to generate a driving current to drive the light emitting device to emit light according to a voltage of a control end of the driving module. The technical scheme provided by the application improves the flicker problem of the display panel at low frequency and low gray scale, and improves the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit, its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are increasingly used in various display fields due to their high contrast, thinness, wide viewing angle, fast response speed, and low power consumption. However, current display panels suffer from low-frequency flicker when driven at low frequencies, which affects the display effect. Summary of the Invention

[0003] This invention provides a pixel circuit, its driving method, and a display panel, which improves the low-frequency, low-grayscale flicker problem of the display panel and enhances the display effect.

[0004] According to one aspect of the present invention, a pixel circuit is provided, comprising: a driving module, a first initialization module, and a light-emitting device;

[0005] The first initialization module is electrically connected to the second terminal of the drive module. The first initialization module is used to transmit the third initialization voltage to the first and second terminals of the drive module during the third initialization phase.

[0006] The light-emitting device is connected between the second terminal of the driving module and the second power supply; the driving module is used to generate a driving current to drive the light-emitting device to emit light according to the voltage at the control terminal of the driving module.

[0007] Optionally, the first initialization module includes a dual-gate transistor; the dual-gate transistor includes a first initialization sub-transistor and a second initialization sub-transistor;

[0008] The first terminal of the first initialization sub-transistor is electrically connected to the first initialization voltage terminal, the second terminal of the first initialization sub-transistor is electrically connected to the first terminal of the second initialization sub-transistor, and the second terminal of the second initialization sub-transistor is electrically connected to the second terminal of the driving module; the gates of the first initialization sub-transistor and the gates of the second initialization sub-transistor are used to receive the first scan signal;

[0009] Optionally, a shielding layer is provided around the channel layer in the dual-gate transistor, and the shielding layer is connected to a DC voltage;

[0010] Optionally, the shielding layer is connected to the first power supply voltage.

[0011] Optionally, the first initialization module includes a first metal-oxide-semiconductor transistor;

[0012] The first terminal of the first metal-oxide transistor is electrically connected to the first initialization voltage terminal, and the second terminal of the first metal-oxide transistor is connected to the second terminal of the driving module; the gate of the first metal-oxide transistor is used to receive the first scan signal.

[0013] Optionally, the pixel circuit may also include a data writing module, a compensation module, and a second initialization module;

[0014] The data writing module is electrically connected to the first terminal of the driver module; the compensation module is connected between the control terminal and the second terminal of the driver module; the second initialization module is electrically connected to the second terminal of the driver module.

[0015] The second initialization module is used to transmit the second initialization voltage to the control terminal of the drive module through the compensation module during the second initialization phase.

[0016] The first initialization module is used to transmit the first initialization voltage to the second terminal of the drive module during the first initialization phase, and to transmit the first initialization voltage to the control terminal of the drive module through the compensation module.

[0017] The data writing module is used to input the data voltage to the first terminal of the drive module during the data writing phase;

[0018] The compensation module is used to perform threshold voltage compensation on the drive module during the threshold compensation stage.

[0019] Optionally, the second initialization module is used to transmit the second initialization voltage to the second and first terminals of the drive module during the second initialization phase;

[0020] Optionally, the first initialization voltage is the same as the third initialization voltage;

[0021] Optionally, the second initialization voltage is different from the third initialization voltage;

[0022] Optionally, the second initialization module includes a second metal-oxide transistor;

[0023] The first terminal of the second metal-oxide transistor is electrically connected to the second initialization voltage terminal; the second terminal of the second metal-oxide transistor is electrically connected to the second terminal of the driving module; the gate of the second metal-oxide transistor is used to receive the second scan signal.

[0024] And / or, the compensation module includes a third metal-oxide transistor;

[0025] The first terminal of the third metal-oxide transistor is electrically connected to the second terminal of the driving module and the second terminal of the second initialization module; the second terminal of the third metal-oxide transistor is electrically connected to the control terminal of the driving module; the gate of the third metal-oxide transistor is used to receive the third scan signal.

[0026] Optionally, the pixel circuitry may also include:

[0027] The second light-emitting control module is connected between the second terminal of the driving module and the first electrode of the light-emitting device. The second electrode of the light-emitting device is electrically connected to the second power supply. The control terminal of the second light-emitting control module receives the light-emitting control signal.

[0028] And / or, the pixel circuitry also includes:

[0029] The third initialization module is electrically connected to the first electrode of the light-emitting device; the third initialization module is used to transmit the fourth initialization voltage to the first electrode of the light-emitting device during the third initialization stage.

[0030] Optionally, the control terminal of the third initialization module receives the same scan signal as the control terminal of the first initialization module;

[0031] Optionally, the third initialization module includes a fourth metal-oxide-semiconductor transistor; the first terminal of the fourth metal-oxide-semiconductor transistor is electrically connected to the third initialization voltage terminal, and the second terminal of the fourth metal-oxide-semiconductor transistor is electrically connected to the first terminal of the light-emitting device; the gate of the fourth metal-oxide-semiconductor transistor is used to receive the first scan signal.

[0032] Optionally, a refresh cycle of the pixel circuit includes a data write frame and a hold frame, both of which are equipped with a third initialization phase;

[0033] Optionally, the pixel circuit further includes a first light-emitting control module, which is connected between the first power supply and the first terminal of the driving module; the control terminal of the first light-emitting control module is connected to the light-emitting control signal.

[0034] Optionally, the pixel circuit also includes a storage module, which is connected between the control terminal of the drive module and the first power supply.

[0035] According to another aspect of the present invention, a driving method for a pixel circuit is provided, applied to a pixel circuit in any embodiment of the present invention, comprising:

[0036] In the third initialization phase, the first initialization module is turned on, and the third initialization voltage is transmitted to the first and second terminals of the drive module.

[0037] Optionally, the driving method also includes:

[0038] In the first initialization phase, the control compensation module is turned on, and the first initialization module is also turned on, transmitting the first initialization voltage to the second terminal of the drive module and the control terminal of the drive module.

[0039] In the second initialization phase, the control compensation module is turned on, and the second initialization module is also turned on to transmit the second initialization voltage to the control terminal of the drive module.

[0040] During the data writing phase, the control data writing module is turned on to transmit the data voltage to the first terminal of the drive module; and the compensation module is turned on to compensate the threshold voltage of the drive module.

[0041] Optionally, in the third initialization phase, the control compensation module is disconnected, and the control first initialization module is turned on, so that the third initialization voltage is transmitted to the first and second terminals of the drive module.

[0042] Optionally, during the second initialization phase, the second initialization module is turned on to transmit the second initialization voltage to the second and first terminals of the drive module.

[0043] Optionally, the pixel circuit further includes a light-emitting control module; the light-emitting control module, the driving module, and the light-emitting device are connected between the first power supply and the second power supply; the driving method further includes:

[0044] During the light-emitting stage, the light-emitting control module is turned on so that the driving module generates a driving current to the light-emitting device to drive the light-emitting device to emit light.

[0045] According to another aspect of the present invention, a display panel is provided, including pixel circuitry according to any embodiment of the present invention.

[0046] The technical solution provided by the embodiments of the present invention includes a driving module, a first initialization module, and a light-emitting device in the pixel circuit; the first initialization module is electrically connected to the second terminal of the driving module; in the data writing frame (refresh frame), the first initialization module can transmit the third initialization voltage to the first and second terminals of the driving module in the third initialization stage; this ensures that the bias state of the driving transistors included in the driving module does not differ too much in the data writing frame and the holding frame, thereby improving the low-frequency low grayscale flicker problem of the display panel and improving the display effect of the display panel.

[0047] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0051] Figure 3 This is a circuit diagram of a pixel circuit provided in an embodiment of the present invention;

[0052] Figure 4 This is a timing diagram of the data writing frame of a pixel circuit provided in an embodiment of the present invention;

[0053] Figure 5 This is a timing diagram of the holding frame operation of a pixel circuit provided in an embodiment of the present invention;

[0054] Figure 6 This is a circuit diagram of another pixel circuit provided in an embodiment of the present invention;

[0055] Figure 7 This is a cross-sectional view of a dual-gate transistor provided in an embodiment of the present invention;

[0056] Figure 8 This is a circuit diagram of another pixel circuit provided in an embodiment of the present invention;

[0057] Figure 9 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention;

[0058] Figure 10 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention;

[0059] Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0060] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0062] The pixel circuit, particularly the "7T1C" pixel circuit, significantly impacts the display performance of AMOLED panels, particularly the operating state of the driving transistors. In traditional "7T1C" pixel circuits, the driving transistor's potential cannot remain stable over extended periods. The gate-source potential of the driving transistor differs between the data write frame and hold frame states, resulting in different bias states. This leads to inconsistent brightness between the data write frame and hold frame during low-frequency driving, causing poor low-frequency, low-grayscale display. The data write frame can be understood as a refresh frame; within each refresh frame, the control terminal of the driving module needs to write a data voltage once. When displaying a high refresh rate image, the number of times the data voltage is written to the control terminal of the driving module in the pixel circuit within the same time frame is greater than the number of times it is written when displaying a low refresh rate image. In other words, the number of data write frames is greater when displaying a high refresh rate image than when displaying a low refresh rate image within the same time frame.

[0063] In related technologies, during the data write frame, the threshold voltage (Vth) of the driving transistor is more negatively biased, while in the hold frame, Vth is less negatively biased. Therefore, in the hold frame, the threshold voltage of the driving transistor is higher than that in the data write frame, resulting in frequency switching flicker. Taking a display refresh rate switching from 120Hz to 10Hz as an example, when the refresh rate is 120Hz, data is written in every frame, controlling Vth to be negatively biased. However, when the refresh rate is 10Hz, Vth is negatively biased in the refresh frame, while it tends to stabilize in the hold frame. This difference in the bias state of the driving transistor leads to different brightness levels in the data write and hold frames during low-frequency driving, resulting in poor low-frequency, low-grayscale display.

[0064] Therefore, embodiments of the present invention provide a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 1 The pixel circuit includes: a driving module 10, a first initialization module 40, and a light-emitting device 60;

[0065] The first initialization module 40 is electrically connected to the second terminal of the drive module 10. The first initialization module 40 is used to transmit the third initialization voltage Vref3 to the first and second terminals of the drive module 10 during the third initialization phase.

[0066] The light-emitting device 60 is connected between the second terminal of the driving module 10 and the second power supply; the driving module 10 is used to generate a driving current to drive the light-emitting device 60 to emit light according to the voltage of the control terminal of the driving module 10.

[0067] Specifically, the data writing frame may include a third initialization phase. In the third initialization phase, the first initialization module 40 is turned on, and through the cooperation of the first initialization module 40 and the driving module 10, the third initialization voltage Vref3 is input to the second and first terminals of the driving module 10. Before the holding frame and the holding phase, the potentials of the first and second terminals of the driving module 10 are reset to ensure that the bias state of the driving transistors in the driving module 10 during the data writing frame is not significantly different from that during the holding frame. This improves the problem of inconsistent brightness between the data writing frame and the holding frame during low-frequency driving, preventing poor low-frequency grayscale display.

[0068] The pixel circuit provided in this embodiment of the invention includes a driving module, a first initialization module, and a light-emitting device; the first initialization module is electrically connected to the second terminal of the driving module; in the data writing frame (refresh frame), the first initialization module transmits the third initialization voltage to the first and second terminals of the driving module in the third initialization stage; this ensures that the bias state of the driving transistors included in the driving module does not differ too much in the data writing frame and the holding frame, thereby improving the low-frequency low grayscale flicker problem of the display panel and improving the display effect of the display panel.

[0069] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 2 The pixel circuit also includes: a data writing module 20, a compensation module 30, and a second initialization module 50;

[0070] The compensation module 30 is connected between the control terminal and the second terminal of the drive module 10; the second initialization module 50 is electrically connected to the second terminal of the drive module 10.

[0071] The first initialization module 40 is used to transmit the first initialization voltage Vref1 to the second terminal of the drive module 10 during the first initialization phase, and to transmit the first initialization voltage Vref1 to the control terminal of the drive module 10 through the compensation module 30.

[0072] The second initialization module 50 is used to transmit the second initialization voltage Vref2 to the control terminal of the drive module 10 through the compensation module 30 during the second initialization phase.

[0073] The data writing module 20 is electrically connected to the first terminal of the drive module 10; the data writing module 20 is independently controlled and is used to input the data voltage Vdata to the first terminal of the drive module 10 during the data writing stage.

[0074] The compensation module 30 is used to perform threshold voltage compensation on the drive module 10 during the threshold compensation stage;

[0075] Optionally, the threshold compensation phase may overlap with the data writing phase, for example, they may coincide.

[0076] The first initialization module 40 is also used to transmit the third initialization voltage Vref3 to the first and second terminals of the drive module 10 during the third initialization phase.

[0077] The second initialization module 50 is used to transmit the second initialization voltage to the second terminal and the first terminal of the drive module 10 during the second initialization phase.

[0078] Specifically, the data write frame may include a first initialization stage, a second initialization stage, a data write stage, and a third initialization stage set sequentially. In the first initialization stage, the first initialization module 40 is turned on, transmitting the first initialization voltage Vref1 to the second terminal of the driver module 10. In conjunction with the turn-on of the compensation module 30, the first initialization voltage Vref1 is written to the control terminal of the driver module 10 to improve the hysteresis phenomenon of the drive transistors included in the driver module 10. During this stage, the driver module 10 can be turned off. The first initialization voltage Vref1 can be a positive voltage, such as 5V. During this stage, the data write module 20 can be turned off. During this stage, the second initialization module 50 can be turned off.

[0079] In the second initialization phase, the second initialization module 50 and the compensation module 30 are turned on, transmitting the second initialization voltage Vref2 to the control terminal of the drive module 10. The potential of the control terminal of the drive module 10 is initialized using the second initialization voltage Vref2 to facilitate the writing of the data voltage Vdata during the data writing phase. The polarities of the first initialization voltage Vref1 and the second initialization voltage Vref2 can be opposite. The second initialization voltage Vref2 can be -5V. During this phase, the drive module 10 is turned on. The potentials of the second terminal and the first terminal of the drive module 10 are initialized using the second initialization voltage Vref2. During this phase, the first initialization module 40 can be turned off. During this phase, the data writing module 20 can be turned off.

[0080] During the data writing phase, the control data writing module 20 and the compensation module 30 are turned on. At this time, the control terminal of the drive module 10, under the control of the second initialization voltage Vref2, can keep the drive module 10 in a conducting state. This allows the data voltage Vdata provided by the data voltage terminal to sequentially pass through the data writing module 20, the drive module 10, and the compensation module 30, charging the control terminal of the drive module 10 until the drive module 10 is turned off. At this time, the potential of the control terminal of the drive module 10 is Vdata + Vth, used for threshold voltage compensation, where Vth is the threshold voltage of the drive transistor included in the drive module 10. The pixel circuit also includes a storage module 70, which is connected to the control terminal of the drive module 10 and is used to store the voltage of the control terminal of the drive module 10. The data writing module 20 is independently controlled, avoiding sharing control signals with other modules and thus preventing interference with the compensation effect on the potential of the control terminal of the drive module 10, thereby improving the display effect of the display panel. The data writing module 20 can be turned on only once in a data writing frame. Compared to a scheme where the data writing module 20 is turned on at least twice in a data writing frame, this reduces the load and improves the effectiveness of data writing and threshold compensation. During this stage, the first initialization module 40 can be turned off. During this stage, the second initialization module 50 can be turned off.

[0081] In the third initialization phase, the first initialization module 40 is turned on, and the compensation module 30 is turned off. Through the cooperation of the first initialization module 40 and the drive module 10, the third initialization voltage Vref3 is input to the second and first terminals of the drive module 10. During this phase, the drive module 10 is turned on. During this phase, the data writing module 20 can be turned off. During this phase, the second initialization module 50 can be turned off. Before the holding frame and the holding light-emitting phase, in the third initialization phase of the holding frame, the potentials of the first and second terminals of the drive module 10 are also reset. This ensures that the bias state of the drive transistors included in the drive module 10 during the data writing frame is not significantly different from the bias state of the drive transistors included in the drive module 10 during the holding frame. This improves the problem of inconsistent brightness between the data writing frame and the holding frame during low-frequency driving, preventing poor low-frequency grayscale display.

[0082] The first initialization module is electrically connected to the second terminal of the drive module, and the compensation module is connected between the control terminal and the second terminal of the drive module. The second initialization module is also electrically connected to the second terminal of the drive module. In the refresh frame, the first initialization module transmits the first initialization voltage to the second terminal and the control terminal of the drive module during the first initialization phase to reset the potential of the second terminal and the control terminal of the drive module. The second initialization module transmits the second initialization voltage to the control terminal of the drive module during the second initialization phase. After the data writing module inputs the data voltage to the control terminal of the drive module during the data writing phase, the first initialization module transmits the third initialization voltage to the first and second terminals of the drive module during the third initialization phase. This ensures that the bias state of the drive transistors included in the drive module does not differ significantly between the data writing frame and the holding frame, thereby improving the low-frequency, low-grayscale flicker problem of the display panel and enhancing the display effect. In addition, the data writing module in the pixel circuit is independently controlled, which avoids sharing control signals with other modules and affecting the compensation effect on the potential of the control terminal of the drive module, further improving the display effect of the display panel.

[0083] In one embodiment of the present invention, optionally, the first initialization voltage Vref1 and the third initialization voltage Vref3 are the same. Setting the first initialization voltage Vref1 and the third initialization voltage Vref3 to be the same can simplify the control of the voltage at the first initialization voltage terminal.

[0084] In one embodiment of the present invention, optionally, the second initialization voltage and the third initialization voltage are different. The first initialization voltage Vref1 and the third initialization voltage Vref3 can be positive values, and the second initialization voltage Vref2 can be a negative value. For example, in the first initialization stage, the first initialization module 40 and the compensation module 30 are turned on, transmitting the 5V first initialization voltage Vref1 to the second terminal and the control terminal of the drive module 10. In the second initialization stage, the second initialization module 50 and the compensation module 30 are turned on, and the first initialization module 40 is turned off; the -5V second initialization voltage Vref2 is transmitted to the control terminal of the drive module 10. In the data writing stage, the second initialization module 50 is turned off, and the data writing module 20 and the compensation module 30 are turned on, writing the data voltage to the control terminal of the drive module 10 and performing threshold voltage compensation. In the third initialization stage, the second initialization module 50, the data writing module 20, and the compensation module 30 are turned off, the first initialization module 40 is turned on, and the 5V third initialization voltage Vref3 is transmitted to the second terminal and the first terminal of the drive module 10; during this stage, the drive module 10 is turned on.

[0085] Figure 3 This is a circuit diagram of a pixel circuit provided in an embodiment of the present invention. Figure 4 This is a timing diagram of the data writing frame of a pixel circuit provided in an embodiment of the present invention, with reference to... Figures 3-4 The driving module 10 includes a driving transistor T1; the data writing module 20 includes a data writing transistor T2, whose conduction state is controlled by a fourth scan signal S4; the compensation module 30 includes a compensation transistor T3, whose conduction state is controlled by a third scan signal S3; the first initialization module 40 includes a first initialization transistor T8, whose conduction state is controlled by a first scan signal S1; the second initialization module 50 includes a second initialization transistor T4, whose conduction state is controlled by a second scan signal S2; the light-emitting device is an OLED light-emitting device; and the storage module 70 includes a storage capacitor Cst. In this embodiment, the transistors used can all be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Transistors T1 to T8 can all be P-type transistors. Transistors T1 to T8 can all be N-type transistors. Some transistors T1 to T8 are P-type transistors, and the rest are N-type transistors.

[0086] The data write frame F1 includes a first initialization phase t1, a second initialization phase t2, a data write phase t3, and a third initialization phase t4, which are set sequentially.

[0087] In the first initialization phase t1, the compensation transistor T3 is turned on by the third scan signal S3, and the first initialization transistor T8 is turned on by the first scan signal S1, thereby transmitting the first initialization voltage Vref1 to the second terminal, the first terminal, and the gate of the driving transistor T1. This improves the hysteresis phenomenon of the driving transistor T1 included in the driving module 10. The data writing transistor T2 is turned off by the fourth scan signal S4, and the second initialization transistor T4 is turned off by the second scan signal S2. Figure 3 In the example, compensation transistor T3 is turned on when the third scan signal S3 is high; first initialization transistor T8 is turned on when the first scan signal S1 is low. Data writing transistor T2 is turned off when the fourth scan signal S4 is high; second initialization transistor T4 is turned off when the second scan signal S2 is low.

[0088] In the second initialization phase t2, the compensation transistor T3 is turned on by the third scan signal S3, and the second initialization transistor T4 is turned on by the second scan signal S2, thereby transmitting the second initialization voltage Vref2 to the gate of the driving transistor T1. The potential of the gate of the driving transistor T1 is initialized by the second initialization voltage Vref2 to facilitate the writing of the data voltage Vdata in the data writing phase t3. The data writing transistor T2 is turned off by the fourth scan signal S4, and the first initialization transistor T8 is turned off by the first scan signal S1. Figure 3 In the example shown, the second initialization transistor T4 is turned on when the second scan signal S2 is high.

[0089] During the data writing phase t3, the fourth scan signal S4 controls the data writing transistor T2 to be turned on, inputting the data voltage Vdata to the first terminal of the driving transistor T1; the third scan signal S3 controls the compensation transistor T3 to be turned on, transmitting the data voltage Vdata to the gate of the driving transistor T1. The first scan signal S1 controls the first initialization transistor T8 to be turned off; the second scan signal S2 controls the second initialization transistor T4 to be turned off. Figure 3 In the example, the data writing transistor T2 is shown to be turned on when the fourth scan signal S4 is low.

[0090] In the third initialization phase t4, the compensation transistor T3 is turned off by the third scan signal S3, and the first initialization transistor T8 is turned on by the first scan signal S1, transmitting the third initialization voltage Vref3 to the second and first terminals of the driving transistor T1. The data writing transistor T2, compensation transistor T3, and second initialization transistor T4 are turned off.

[0091] Figure 4This is a timing diagram of a holding frame for a pixel circuit provided in an embodiment of the present invention. The holding frame includes at least one holding emission stage. Figure 4 The example drawing of hold frame F2 includes two hold-light stages: a first hold-light stage t22 and a second hold-light stage t23. Before the hold-light stages, the third initialization stage t21 of the hold frame also resets the potential of the first and second terminals of the driving transistor T1, so that the bias state of the driving transistor T1 in data write frame F1 is not much different from that in hold frame F2. This improves the problem of low-frequency low grayscale display defects caused by the difference in brightness between data write frame F1 and hold frame F2 during low-frequency driving.

[0092] Based on the above embodiments, in one embodiment of the present invention, please continue to refer to... Figure 3 The first initialization module 40 includes a dual-gate transistor; that is, the first initialization transistor T8 is a dual-gate transistor. The dual-gate transistor includes a first initialization sub-transistor and a second initialization sub-transistor;

[0093] The first terminal of the first initialization sub-transistor is electrically connected to the first initialization voltage terminal, the second terminal of the first initialization sub-transistor is electrically connected to the first terminal of the second initialization sub-transistor, and the second terminal of the second initialization sub-transistor is electrically connected to the second terminal of the driving module 10 and the first terminal of the compensation module 30; the gate of the first initialization sub-transistor and the gate of the second initialization sub-transistor are used to receive the first scan signal.

[0094] The dual-gate transistor can be a P-type transistor. It can also be a polysilicon transistor. Specifically, the transistor included in the first initialization module 40 adopts a dual-gate design. When the dual-gate transistor is turned off, it facilitates complete shutdown, further reducing the risk of bright spots caused by leakage current in the first initialization module 40 or the forward bias of its threshold voltage Vth.

[0095] Optionally, the first initialization module 40 includes a first initialization transistor T8. A shielding layer is disposed around the channel layer of the first initialization transistor T8 (for example, the shielding layer is located on the side of the channel layer of the first initialization transistor T8 away from the gate of the first initialization transistor T8). The shielding layer is connected to a DC voltage VGH, which can reduce the probability of bright spots caused by the forward bias of the threshold voltage Vth of the first initialization transistor T8, and is beneficial to improving the reliability of the first initialization transistor T8. The first initialization transistor T8 can also be a single transistor. Optionally, the DC voltage connected to the shielding layer can be the same logic as the turn-off level of the first initialization transistor T8. The first initialization transistor T8 can be a P-type transistor. The first initialization transistor T8 can be a polysilicon transistor. The DC voltage connected to the shielding layer can be a high voltage. The shielding layer can be electrically connected to the power lines (for transmitting DC voltage VGH) of the scan driving circuit 100 and / or the light emission control driving circuit 200 on the display panel.

[0096] Optional, Figure 6 This is a circuit diagram of another pixel circuit provided in an embodiment of the present invention. Figure 7 This is a cross-sectional view of a dual-gate transistor provided in an embodiment of the present invention, with reference to... Figure 6 and Figure 7 A dual-gate transistor includes a gate G, a first terminal, and a second terminal. The first terminal of the dual-gate transistor is the source S, and the second terminal is the drain D; or the first terminal is the drain D, and the second terminal is the source S. A shielding layer 01 is disposed around the channel layer of the dual-gate transistor (for example, the shielding layer 01 is located on the side of the channel layer of the dual-gate transistor away from the gate of the dual-gate transistor), and the shielding layer 01 is connected to a DC voltage VGH. The shielding layer 01 around the channel layer of the dual-gate transistor, and the shielding layer 01 being connected to a DC voltage potential, can reduce the probability of bright spots caused by the forward bias of the threshold voltage Vth of the dual-gate transistor, and is beneficial to improving the reliability of the dual-gate transistor. The DC voltage connected to the shielding layer 01 can be a first power supply voltage. Optionally, the DC voltage connected to the shielding layer 01 can have the same logic as the turn-off level of the dual-gate transistor, for example, the DC voltage connected to the shielding layer 01 can be a high level. The shielding layer 01 can be electrically connected to the power lines of the scanning driving circuit 100 and / or the light emission control driving circuit 200 on the display panel.

[0097] Alternatively, in another embodiment of the invention, Figure 8 This is a circuit diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 8 The first initialization module 40 includes a first metal-oxide transistor; that is, the first initialization transistor T8 is a metal-oxide transistor. The first initialization transistor T8 can be an N-type transistor.

[0098] The first terminal of the first metal-oxide transistor is electrically connected to the first initialization voltage terminal, and the second terminal of the first metal-oxide transistor is electrically connected to the second terminal of the driving module 10 and the first terminal of the compensation module 30; the gate of the first metal-oxide transistor is used to receive the first scan signal.

[0099] Specifically, the first initialization module 40 includes a first metal-oxide transistor. The metal-oxide transistor can be an indium gallium zinc oxide (IGZO) thin-film transistor (TFT). The use of an IGZO transistor in the first initialization module 40 can reduce the bright spot problem caused by leakage current in the first initialization module 40.

[0100] Optional, such as Figure 8 As shown, the second initialization module 50 includes a second initialization transistor T4, which is a polysilicon transistor with a relatively small size, which is beneficial for setting high pixel resolution (PPI). The second initialization transistor T4 can be a P-type transistor.

[0101] Based on the above embodiments, in one embodiment of the present invention, reference is made to... Figure 3 and Figure 6 The second initialization module 50 includes a second metal-oxide-semiconductor transistor; that is, the second initialization transistor T4 is a metal-oxide-semiconductor transistor. The second initialization transistor T4 can be an N-type transistor.

[0102] The first terminal of the second metal-oxide-semiconductor (MOSFET) is electrically connected to the second initialization voltage terminal; the second terminal of the second MOSFET is electrically connected to the second terminal of the driving module 10 and the first terminal of the compensation module 30; the gate of the second MOSFET is used to receive the second scan signal. It can be understood that the second initialization module 50 uses an IGZO transistor, which can improve the bright spot problem caused by leakage current in the second initialization module 50.

[0103] Optional, see reference Figure 3 , Figure 6 and Figure 8 The compensation module 30 includes a third metal-oxide transistor; that is, the compensation transistor T3 is a metal-oxide transistor. The compensation transistor T3 can be an N-type transistor.

[0104] The first terminal of the third metal-oxide transistor is electrically connected to the second terminal of the driving module 10 and the second terminal of the second initialization module 50; the second terminal of the third metal-oxide transistor is electrically connected to the control terminal of the driving module 10; the gate of the third metal-oxide transistor is used to receive the third scan signal. It can be understood that the compensation module 30 is directly electrically connected to the control terminal of the driving module 10. The compensation module 30 uses an IGZO transistor, which can reduce or avoid potential changes at the control terminal of the driving module 10 caused by leakage current in the compensation module 30, thereby improving the display effect of the display panel.

[0105] Based on the above embodiments, in one embodiment of the present invention, please continue to refer to... Figure 3 , Figure 6 and Figure 8 The pixel circuit also includes:

[0106] A third initialization module 80 is electrically connected to the first electrode (e.g., anode) of the light-emitting device 60. The third initialization module 80 is used to transmit a fourth initialization voltage to the first electrode (e.g., anode) of the light-emitting device 60 during at least one of the first initialization stage, the second initialization stage, and the third initialization stage. Optionally, the third initialization module 80 is used to transmit the fourth initialization voltage to the first electrode (e.g., anode) of the light-emitting device 60 during the third initialization stage.

[0107] Specifically, the first terminal of the third initialization module 80 receives the fourth initialization voltage Vref4, and the second terminal of the third initialization module 80 is electrically connected to the first electrode (e.g., anode) of the light-emitting device 60. By controlling the conduction state of the third initialization module 80, the fourth initialization voltage Vref4 can be transmitted to the first electrode (e.g., anode) of the light-emitting device 60 in at least one of the first initialization stage, the second initialization stage, and the third initialization stage to initialize the potential of the first electrode (e.g., anode) of the light-emitting device 60, thereby controlling the light-emitting device 60 to not emit light and clearing residual charge from the first electrode (e.g., anode) of the light-emitting device 60. The third initialization module 80 includes a third initialization transistor T7. The fourth initialization voltage can be a negative voltage, such as -4V.

[0108] In one embodiment of the present invention, please continue to refer to the reference. Figure 3 , Figure 6 and Figure 8The control terminal of the third initialization module 80 receives the same scan signal as the control terminal of the first initialization module 40. Optionally, the control terminal of the third initialization module 80 and the control terminal of the first initialization module 40 are electrically connected to the same scan signal line. The third initialization module 80 and the first initialization module 40 can be turned on and off simultaneously. The transistors in the third initialization module 80 and the transistors in the first initialization module 40 can have the same channel type.

[0109] Specifically, the control terminal of the third initialization module 80 receives the same scanning signal as the control terminal of the first initialization module 40, which can reduce the number of scanning signals and scanning signal lines in the display panel, and reduce the difficulty of wiring in the display panel. At this time, the third initialization module 80 can transmit the fourth initialization voltage Vref4 to the first electrode (e.g., anode) of the light-emitting device 60 in the first and third initialization stages to initialize the potential of the first electrode (e.g., anode) of the light-emitting device 60.

[0110] Optional, such as Figure 8 As shown, the third initialization module 80 includes a fourth metal-oxide transistor, that is, the third initialization transistor T7 is a metal-oxide transistor. The third initialization transistor T7 can be an N-type transistor.

[0111] The first terminal of the fourth metal-oxide-semiconductor (MOSFET) is electrically connected to the third initialization voltage terminal, and the second terminal of the fourth MOSFET is electrically connected to the first electrode (e.g., anode) of the light-emitting device 60; the gate of the fourth MOSFET is used to receive the first scan signal S1. It can be understood that the third initialization module 80 uses an IGZO transistor, which can improve the bright spot problem caused by leakage current in the third initialization module 80.

[0112] Optional, such as Figure 3 and Figure 6 As shown, the third initialization module 80 includes a third initialization transistor T7, which is a polysilicon transistor. The third initialization transistor T7 can be a P-type transistor.

[0113] Based on the above embodiments, in one embodiment of the present invention, please continue to refer to... Figure 3 , Figure 6 and Figure 8 The pixel circuit light-emitting control module, driving module 10, and light-emitting device 60 are connected between a first power supply and a second power supply. The light-emitting control module is used to control the conduction during the light-emitting phase. One of the first power supply and the second power supply is a high voltage, and the other is a low voltage. The first power supply is used to provide a first power supply voltage ELVDD, which can be a high voltage, and the second power supply is used to provide a second power supply voltage ELVSS, which can be a low voltage.

[0114] refer to Figure 4 In the data write frame F1, a light emission stage t5 is included after the third initialization stage t4. In the light emission stage t5, the light emission control module is turned on to cause the drive module 10 to generate a drive current to the light-emitting device 60, thereby driving the light-emitting device 60 to emit light. The light emission control module can be turned off during the first initialization stage t1, the second initialization stage t2, the data write stage t3, and the third initialization stage t4.

[0115] The light-emitting control module may include a first light-emitting control module 91 and / or a second light-emitting control module 92. The first light-emitting control module 91 is connected between the first power supply and the first terminal of the drive module 10. The control terminal of the first light-emitting control module 91 is connected to the light-emitting control signal EM.

[0116] The second light-emitting control module 92 is connected between the second terminal of the driving module 10 and the first electrode (e.g., anode) of the light-emitting device 60. The second electrode (e.g., cathode) of the light-emitting device 60 is electrically connected to the second power supply. The control terminal of the second light-emitting control module 92 is connected to the light-emitting control signal EM.

[0117] The control terminals of the first light-emitting control module 91 and the second light-emitting control module 92 receive the same light-emitting control signal EM. In one embodiment of the present invention, the first light-emitting control module 91 includes a first light-emitting control transistor T5, and the second light-emitting control module 92 includes a second light-emitting control transistor T6. The light-emitting stage t5 includes at least one light-emitting sub-stage. Figure 4 The illuminating stage t5 is illustrated in the example, which includes a first illuminating sub-stage t51 and a second illuminating sub-stage t52. In the first illuminating sub-stage t51 and the second illuminating sub-stage t52, the first illuminating control transistor T5 and the second illuminating control transistor T6 are turned on.

[0118] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish the two terminals of the transistor (excluding the gate), one terminal is referred to as the first terminal, and the other as the second terminal. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first terminal can be the drain, and the second terminal can be the source; alternatively, the first terminal can be the source, and the second terminal can be the drain.

[0119] This invention also provides a driving method for a pixel circuit, applicable to the pixel circuit of any embodiment of this invention. Figure 9 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention, see reference. Figure 9 , combined Figure 1 The driving methods for pixel circuits include:

[0120] S110. In the third initialization phase, control the first initialization module to turn on, and transmit the third initialization voltage to the first and second terminals of the drive module.

[0121] Specifically, in the data writing frame, the first initialization module transmits the third initialization voltage to the first and second terminals of the driving module during the third initialization phase; this ensures that the bias state of the driving transistors included in the driving module does not differ too much between the data writing frame and the holding frame, thereby improving the low-frequency, low-grayscale flicker problem of the display panel and enhancing the display effect of the display panel.

[0122] Figure 10 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention, see reference. Figure 10 , combined Figure 2 The driving methods for pixel circuits include:

[0123] S210. In the first initialization phase, the control compensation module is turned on, and the first initialization module is turned on to transmit the first initialization voltage to the second terminal of the drive module and the control terminal of the drive module.

[0124] Specifically, in the first initialization phase t1, the first initialization module 40 is turned on, which transmits the first initialization voltage Vref1 provided by the first initialization voltage Vref1 terminal to the second terminal of the drive module 10. In conjunction with the turn-on of the compensation module 30, the first initialization voltage Vref1 can be written to the control terminal of the drive module 10 to improve the hysteresis phenomenon of the drive transistors included in the drive module 10. During this phase, the drive module 10 is turned off.

[0125] S220. In the second initialization phase, the control compensation module is turned on, and the second initialization module is turned on to transmit the second initialization voltage to the control terminal of the drive module.

[0126] Specifically, in the second initialization phase t2, the second initialization module 50 and the compensation module 30 are turned on, transmitting the second initialization voltage Vref2 provided by the second initialization voltage Vref2 terminal to the control terminal of the drive module 10. The potential of the control terminal of the drive module 10 is initialized by the second initialization voltage Vref2 to facilitate the writing of data voltage during the data writing phase. Optionally, in the second initialization phase t2, the second initialization module is turned on, transmitting the second initialization voltage to the second terminal and the first terminal of the drive module.

[0127] S230. During the data writing phase, control the data writing module to turn on and transmit the data voltage to the first terminal of the drive module; and control the compensation module to turn on to compensate the threshold voltage of the drive module.

[0128] Specifically, during the data writing phase t3, the control data writing module 20 and the compensation module 30 are turned on. At this time, the drive module 10, under the action of the second initialization voltage Vref2, can be in a conducting state. This allows the data voltage Vdata provided by the data voltage terminal to sequentially pass through the data writing module 20, the drive module 10, and the compensation module 30, charging the control terminal of the drive module 10 until the drive module 10 is turned off. At this time, the potential of the control terminal of the drive module 10 is Vdata + Vth, for threshold voltage compensation, where Vth is the threshold voltage of the drive transistor included in the drive module 10. The drive circuit also includes a storage module 70, which is connected to the control terminal of the drive module 10 and is used to store the voltage of the control terminal of the drive module 10. The data writing module 20 is independently controlled, which avoids sharing control signals with other modules and affecting the compensation effect on the potential of the control terminal of the drive module 10, thus improving the display effect of the display panel.

[0129] S240. In the third initialization phase, the control compensation module is turned off, and the control first initialization module is turned on, so as to transmit the third initialization voltage to the first and second terminals of the drive module.

[0130] Specifically, in the third initialization phase t4, the first initialization module 40 is turned on, and the compensation module 30 is turned off. Through the cooperation of the first initialization module 40 and the drive module 10, the third initialization voltage Vref3 is input to the second terminal and the first terminal of the drive module 10. During this phase, the drive module 10 is turned on.

[0131] Before the holding frame and the holding light-emitting stage, the third initialization stage t21 of the holding frame will also reset the potential of the first terminal and the second terminal of the driving module 10, so that the bias state of the driving transistors included in the driving module 10 in the data writing frame is not much different from the bias state of the driving transistors included in the driving module 10 in the holding frame, so as to improve the problem of low frequency low grayscale display failure caused by the difference in brightness between the data writing frame and the holding frame when driving at low frequency.

[0132] Optional, see reference Figure 2 , Figure 6 and Figure 8 The pixel circuit also includes: a third initialization module 80, which is electrically connected to the first electrode (e.g., anode) of the light-emitting device 60; the driving method of the pixel circuit also includes:

[0133] The control third initialization module 80 transmits the fourth initialization voltage Vref4 to the first electrode (e.g., anode) of the light-emitting device 60 during at least one of the first initialization phase, the second initialization phase, and the third initialization phase.

[0134] Specifically, the fourth initialization voltage Vref4 is transmitted to the first electrode (e.g., anode) of the light-emitting device 60 to initialize the potential of the first electrode (e.g., anode) of the light-emitting device 60, so as to control the light-emitting device 60 to not emit light and to remove the residual charge on the first electrode (e.g., anode) of the light-emitting device 60.

[0135] Optionally, the pixel circuit further includes a light-emitting control module; the light-emitting control module, the driving module 10, and the light-emitting device 60 are connected between the first power supply and the second power supply; after the third initialization phase of the data writing frame, and / or after the third initialization phase of the holding frame, it further includes:

[0136] During the light-emitting stage, the light-emitting control module is turned on so that the driving module 10 generates a driving current to the light-emitting device 60 to drive the light-emitting device 60 to emit light.

[0137] Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 11 The present invention also provides a display panel, including the pixel circuit provided in any of the above embodiments.

[0138] The display panel includes, for example, Figure 11 The diagram shows a scan driving circuit 100, a light emission control driving circuit 200, and a driving chip. The display area includes an array substrate and a light emission device layer disposed on the array substrate. The array substrate is a film layer structure that can provide driving signals to the display panel and play a role in buffering, protection, or support. It includes a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes multiple pixel circuit units, multiple data signal lines (D1 to Dn), multiple scan signal lines (C1 to Cm), multiple light emission control signal lines (E1 to Eo), and multiple power supply lines. The data driver 300 is connected to multiple data signal lines (D1 to Dn), the scan driving circuit 100 is connected to multiple scan signal lines (C1 to Cm), and the light emission control driving circuit 200 is connected to multiple light emission control signal lines (E1 to Eo).

[0139] The light-emitting device layer includes multiple light-emitting devices. A circuit unit and a light-emitting device connected to the circuit unit constitute a sub-pixel. The display area may include multiple sub-pixels Pxij, where i and j can be natural numbers. The pixel circuit unit may include at least the pixel circuit provided in any of the above embodiments. The pixel circuit is connected to a scan signal line, a light emission control signal line, and a data signal line, respectively. The data signal line is configured to provide a data voltage to the pixel driving circuit, the scan signal line is configured to provide a scan signal to the pixel circuit, and the light emission control signal line is configured to provide a light emission control signal to the pixel circuit, thereby realizing the light emission control of the light-emitting devices.

[0140] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit comprises a driving module, a first initialization module, a compensation module, a second initialization module and a light emitting device. The first initialization module is electrically connected with the second end of the driving module, and the compensation module is connected between the control end and the second end of the driving module. The first initialization module is configured to transmit a first initialization voltage to the second end of the driving module in a first initialization stage, and transmit the first initialization voltage to the control end of the driving module through the compensation module. The second initialization module is configured to transmit a second initialization voltage to the second end and the first end of the driving module in a second initialization stage, and transmit the second initialization voltage to the control end of the driving module through the compensation module. The first initialization module is configured to transmit a third initialization voltage to the first end and the second end of the driving module in a third initialization stage. The light emitting device is connected between the second end of the driving module and a second power supply, and the driving module is configured to generate a driving current to drive the light emitting device to emit light according to the voltage of the control end of the driving module. The first initialization voltage is the same as the third initialization voltage. The second initialization voltage is different from the third initialization voltage. The first initialization module comprises a double-gate transistor, and the double-gate transistor comprises a first initialization sub-transistor and a second initialization sub-transistor.

2. The pixel circuit of claim 1, wherein, The first pole of the first initialization sub-transistor is electrically connected with a first initialization voltage terminal, the second pole of the first initialization sub-transistor is electrically connected with the first pole of the second initialization sub-transistor, and the second pole of the second initialization sub-transistor is electrically connected with the second end of the driving module; and the gate of the first initialization sub-transistor and the gate of the second initialization sub-transistor are configured to receive a first scanning signal. A shielding layer is located on the side of the channel layer of the double-gate transistor away from the gate of the double-gate transistor, and the shielding layer is connected to a direct current voltage.

3. The pixel circuit of claim 2, wherein, The shielding layer is connected to a first power supply voltage.

4. The pixel circuit of claim 3, wherein, The first initialization module comprises a first metal oxide transistor.

5. The pixel circuit of claim 1, wherein, The first pole of the first metal oxide transistor is electrically connected with a first initialization voltage terminal, and the second pole of the first metal oxide transistor is electrically connected with the second end of the driving module; and the gate of the first metal oxide transistor is configured to receive a first scanning signal. The pixel circuit further comprises a data writing module.

6. The pixel circuit of claim 1, wherein, The data writing module is electrically connected with the first end of the driving module. The data writing module is configured to input a data voltage to the first end of the driving module in a data writing stage.

7. The pixel circuit of claim 6, wherein, The compensation module is configured to perform threshold voltage compensation on the driving module in a threshold compensation stage. The second initialization module comprises a second metal oxide transistor.

8. The pixel circuit of claim 7, wherein, The first pole of the second metal oxide transistor is electrically connected with a second initialization voltage terminal; the second pole of the second metal oxide transistor is electrically connected with the second end of the driving module; and the gate of the second metal oxide transistor is configured to receive a second scanning signal. ​ And / or, the compensation module comprises a third metal oxide transistor; The first electrode of the third metal oxide transistor is electrically connected with the second end of the driving module and the second end of the second initialization module; the second electrode of the third metal oxide transistor is electrically connected with the control end of the driving module; and the gate electrode of the third metal oxide transistor is used for receiving a third scan signal.

9. The pixel circuit according to any one of claims 1 to 8, characterized in that, The pixel circuit further comprises a second light-emitting control module, which is connected between the second end of the driving module and the first electrode of the light-emitting device, and the second electrode of the light-emitting device is electrically connected with a second power supply; and the control end of the second light-emitting control module is connected with a light-emitting control signal. And / or, the pixel circuit further comprises: A third initialization module, which is electrically connected with the first electrode of the light-emitting device; and the third initialization module is used for transmitting a fourth initialization voltage to the first electrode of the light-emitting device in a third initialization stage.

10. The pixel circuit of claim 9, wherein, The control end of the third initialization module receives the same scan signal as the control end of the first initialization module.

11. The pixel circuit of claim 10, wherein, The third initialization module comprises a fourth metal oxide transistor; the first electrode of the fourth metal oxide transistor is electrically connected with a third initialization voltage end, the second electrode of the fourth metal oxide transistor is electrically connected with the first electrode of the light-emitting device; and the gate electrode of the fourth metal oxide transistor is used for receiving a first scan signal.

12. The pixel circuit of claim 1, wherein, A refresh cycle of the pixel circuit comprises a data writing frame and a holding frame, and the data writing frame and the holding frame are both provided with the third initialization stage.

13. The pixel circuit of claim 1, wherein, The pixel circuit further comprises a first light-emitting control module, which is connected between a first power supply and the first end of the driving module, and the control end of the first light-emitting control module is connected with a light-emitting control signal.

14. The pixel circuit of claim 1, wherein, The pixel circuit further comprises a storage module, which is connected between the control end of the driving module and the first power supply.

15. The pixel circuit of claim 1, wherein, A refresh cycle of the pixel circuit comprises a data writing frame, and the data writing frame comprises the first initialization stage, the second initialization stage, a data writing stage and the third initialization stage which are sequentially arranged.

16. A driving method of a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 15, characterized by, Comprise: In the third initialization stage, the first initialization module is controlled to be turned on, and a third initialization voltage is transmitted to the first end and the second end of the driving module; The driving method further comprises: In the first initialization stage, the compensation module is controlled to be turned on, and the first initialization module is controlled to be turned on, and a first initialization voltage is transmitted to the second end of the driving module and the control end of the driving module; In the second initialization stage, the second initialization module is controlled to be turned on, the compensation module is controlled to be turned on, a second initialization voltage is transmitted to the second end and the first end of the driving module, and the second initialization voltage is transmitted to the control end of the driving module; In the third initialization stage, the compensation module is controlled to be turned off, and the first initialization module is controlled to be turned on, and a third initialization voltage is transmitted to the first end and the second end of the driving module.

17. The driving method of the pixel circuit according to claim 16, wherein The driving method further comprises: In the data writing stage, the control data writing module is turned on, the data voltage is transmitted to the first end of the driving module, and the compensation module is controlled to be turned on to compensate the threshold voltage of the driving module.

18. The driving method of the pixel circuit according to claim 17, wherein The pixel circuit further comprises a light emitting control module; the light emitting control module, the driving module and the light emitting device are connected between a first power supply and a second power supply; and the driving method further comprises: In the light emitting stage, the light emitting control module is controlled to be turned on, so that the driving module generates a driving current to the light emitting device to drive the light emitting device to emit light.

19. A display panel, characterized by The pixel circuit comprises any one of claims 1-15.

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