Thickness analysis wafer, system and method, chip manufacturing method

Abstract

The application provides a thickness analysis wafer, a system and a method, a chip preparation method, and relates to the chip field.The thickness analysis wafer comprises a test metal plate, a to-be-tested insulating layer arranged on the test metal plate, and a metal layer arranged on the to-be-tested insulating layer, wherein the to-be-tested insulating layer is located between the test metal plate and the metal layer; wherein a parasitic capacitance value between the test metal plate and the metal layer is used to determine the thickness of the to-be-tested insulating layer.Through the thickness analysis wafer, the thickness of the to-be-tested insulating layer with different surface shapes can be measured, and the accuracy and efficiency of measuring the thickness of the to-be-tested insulating layer are improved.

Description

Technical Field

[0001] This application relates to the field of chips, and more specifically, to a thickness analysis wafer, system and method, and a chip fabrication method. Background Technology

[0002] Some chips incorporate specific circuit structures to improve their performance. For example, MIM (Metal-Insulator-Metal) capacitors are used in chips to suppress instantaneous fluctuations in power supply voltage.

[0003] Some circuit structures can affect the pattern of various layers in a chip, thus affecting the manufacturing difficulty and yield rate. For example, when manufacturing MIM capacitors in a chip, after the oxide layer is grown, the oxide layer at the MIM capacitor location will be higher than other locations, forming a protrusion and changing the surface shape of the oxide layer.

[0004] When polishing and grinding oxide layers, the grinding rate of some polishing and grinding methods is affected by the pattern of the surface being ground. For example, CMP (Chemical Mechanical Polish) technology has a higher grinding speed for raised areas than for other areas, and the denser the raised areas, the faster the grinding speed, which will result in different oxide layer thicknesses under the same process.

[0005] Currently, optical inspection instruments, such as ellipsometers, can be used to detect oxide layer thickness. These instruments detect thickness based on the principle of light reflection. However, the accuracy of the detection is affected by the surface shape of the measured surface. Typically, they can only detect oxide layer thickness under repeated patterns. If the surface shape of the measured surface changes, the optical instrument may not be able to detect it accurately. Different MIM capacitance densities will cause changes in the surface shape of the generated oxide layer, resulting in lower accuracy for oxide layer thickness detection using optical inspection instruments, thus leading to lower detection efficiency. Summary of the Invention

[0006] In view of this, this application aims to provide a thickness analysis wafer, system, and method, and a chip fabrication method, to improve the accuracy and efficiency of measuring the thickness of insulating layers with different surface shapes.

[0007] In a first aspect, embodiments of this application provide a thickness analysis wafer, including a test metal plate; an insulating layer to be tested disposed on the test metal plate; and a metal layer disposed on the insulating layer to be tested, wherein the insulating layer to be tested is located between the test metal plate and the metal layer; wherein the parasitic capacitance value between the test metal plate and the metal layer is used to determine the thickness of the insulating layer to be tested.

[0008] In this embodiment, the insulating layer to be tested is disposed between the test metal plate and the metal layer, thereby forming a capacitor-like structure between the test metal plate and the metal layer. When power is supplied to the test metal plate and the metal layer, parasitic capacitance is generated. The capacitance value is related to the distance between the two plates. Therefore, the distance between the test metal plate and the metal layer can be calculated by the parasitic capacitance value, and the distance between them is the thickness of the insulating layer to be tested. This method of measuring the thickness of the insulating layer to be tested is less affected by the surface shape of the insulating layer to be tested, and compared with the measurement by optical inspection instruments, it can effectively improve the accuracy and efficiency of measuring the thickness of the insulating layer to be tested.

[0009] In one embodiment, the thickness analysis wafer further includes a substrate insulating layer, on which a plurality of test capacitors are spaced apart, each test capacitor including two metal plates; the test metal plates are the metal plates of the test capacitors that are in contact with the insulating layer to be tested; wherein, the thickness of the insulating layer to be tested is related to the density of the test capacitors disposed on the substrate insulating layer.

[0010] In this embodiment, during the growth of the insulating layer under test (DUT), protrusions are formed at the test capacitors. The density of these protrusions affects the grinding thickness of the DUT; therefore, the density of the test capacitors is related to the thickness of the DUT. By setting multiple test capacitors on the substrate, different surface shapes of the DUT can be simulated, enabling the measurement and analysis of the thickness of the DUT with different surface shapes. Furthermore, using the metal plate of the test capacitors as the test metal plate eliminates the need for an additional test metal plate on the wafer, reducing the wafer area occupied by the test metal plate.

[0011] In one embodiment, the plurality of test capacitors are disposed within a predetermined region of the substrate insulating layer, wherein the number of test capacitors within the predetermined region characterizes the density.

[0012] Different regions of a wafer may have different properties. In this embodiment, the test capacitor is set in a preset area, thereby reducing the influence of different regions of the wafer on the analysis of the thickness of the insulating layer to be tested and improving the accuracy of the analysis of the thickness of the insulating layer to be tested.

[0013] In one embodiment, the thickness analysis wafer further includes a first contact and a second contact; the first contact and the second contact are disposed on the surface of the thickness analysis wafer; the first contact is connected to the test metal plate, and the second contact is connected to the metal layer.

[0014] In this embodiment, the metal layer and the test metal plate are connected to the contacts on the wafer surface. Thus, the parasitic capacitance value can be measured through the first and second contacts on the surface, reducing the difficulty of measuring the parasitic capacitance value and improving the efficiency of determining the thickness of the insulating layer to be tested by measuring the parasitic capacitance value.

[0015] In a second aspect, embodiments of this application provide a thickness analysis system, comprising: a capacitance measurement device and a thickness analysis wafer as described in any of the first aspects; the capacitance measurement device is connected to a test metal plate and a metal layer in the thickness analysis wafer, respectively, and the capacitance measurement device is configured to measure the parasitic capacitance value between the test metal plate and the metal layer; the parasitic capacitance value is used to determine the thickness of the insulating layer to be tested in the thickness analysis wafer.

[0016] In one embodiment, the capacitance measuring device is further configured to determine the thickness of the insulating layer to be measured based on the parasitic capacitance value and a preset relationship between the parasitic capacitance value and the thickness.

[0017] In one embodiment, the thickness analysis system further includes: a processing device connected to the capacitance measuring device, the processing device being used to acquire the parasitic capacitance value sent by the capacitance measuring device, and to determine the thickness of the insulation layer to be measured based on the parasitic capacitance value and a preset relationship between the parasitic capacitance value and the thickness.

[0018] Thirdly, embodiments of this application provide a thickness analysis method, comprising: obtaining the parasitic capacitance value of a thickness analysis wafer; wherein the thickness analysis wafer includes a test metal plate, an insulating layer to be tested, and a metal layer arranged sequentially; the parasitic capacitance value is the capacitance value between the metal layer and the test metal plate; and the thickness of the insulating layer to be tested is determined based on the parasitic capacitance value and a preset relationship between the parasitic capacitance value and the thickness.

[0019] In one embodiment, obtaining the parasitic capacitance value of the thickness analysis wafer includes: using a capacitance measurement device to detect the parasitic capacitance value between the metal layer and the test metal plate, wherein the capacitance measurement device is connected to both the metal layer and the test metal plate.

[0020] In one embodiment, before obtaining the parasitic capacitance value of the thickness analysis wafer, the thickness analysis method further includes: laying out test capacitors with a preset test capacitance density on a substrate insulating layer; generating the test insulating layer related to the density on the test capacitors, wherein the test capacitors include two metal plates; the test metal plate is one of the metal plates of the test capacitors; generating the metal layer on the test insulating layer to obtain the thickness analysis wafer.

[0021] When polishing and grinding the insulating layer under test, the thickness of the polished insulating layer is affected by the surface shape of the insulating layer under test. In this embodiment, the test capacitor with capacitance density is placed on the substrate insulating layer. Different test capacitor densities will cause the surface of the insulating layer under test to have different shapes. Therefore, test capacitors with a preset density can be placed on the insulating layer under test to analyze the correspondence between the test capacitor density and the insulating layer under test, which can assist in the design of chip circuits and wafer production, and improve the yield of wafer fabrication.

[0022] Fourthly, embodiments of this application provide a chip fabrication method, comprising: acquiring multiple thickness analysis wafers manufactured using the same manufacturing process, wherein the density of test capacitors in the different thickness analysis wafers is different; wherein each thickness analysis wafer includes a test capacitor, a test insulating layer, and a metal layer disposed sequentially; the test insulating layer is disposed between one of the metal plates in the test capacitor and the metal layer, and the parasitic capacitance value between the metal plate and the metal layer is used to determine the thickness of the test insulating layer; the thickness of the test insulating layer is related to the density of the test capacitor; measuring the thickness of the test insulating layer in each thickness analysis wafer respectively; establishing a first correspondence between the density of the test capacitor and the thickness of the test insulating layer; the first correspondence is used to indicate the fabrication of the chip.

[0023] In this embodiment, a thickness analysis wafer with different test capacitance densities is used to determine a first correspondence between the test capacitance density and the thickness of the insulating layer to be tested. This first correspondence can be referenced during subsequent chip fabrication and design to improve the efficiency and yield of chip fabrication.

[0024] In one embodiment, before establishing a first correspondence between the density of the test capacitor and the thickness of the insulating layer to be tested, the method further includes: determining that the thickness of the insulating layer to be tested in all thickness analysis wafers is within a preset thickness range.

[0025] In this embodiment, if the thickness of the insulating layer to be tested is within a preset thickness range, then the wafer for thickness analysis does not meet the process requirements. Therefore, by determining whether the thickness of the insulating layer to be tested is within a preset range, wafers that do not meet the process requirements are identified, thereby improving the accuracy of the first correspondence between the thickness of the insulating layer to be tested and the test capacitance density, thus assisting in chip fabrication and improving chip quality and yield.

[0026] In one embodiment, the method further includes: if the thickness of the insulating layer to be tested on any of the thickness analysis wafers is outside a preset thickness range, then re-fabricate a thickness analysis wafer with the same test capacitance density based on a second manufacturing process; if the thickness of the insulating layer to be tested on the re-fabricated thickness analysis wafer is within the preset thickness range, then establish a second correspondence between the second manufacturing process and the test capacitance density; the second correspondence is used to indicate the fabrication of the chip.

[0027] In this embodiment of the application, if the thickness of the insulating layer to be tested is not within the preset range, the process that meets the preparation requirements for the thickness of the insulating layer to be tested can be re-determined, and a second correspondence relationship can be established to indicate the preparation of the chip, thereby improving the yield and quality of chip preparation. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a thickness analysis wafer provided in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of a thickness analysis wafer structure including a test capacitor provided in an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of a preset area provided in an embodiment of this application;

[0032] Figure 4 A schematic diagram of a thickness analysis system provided in an embodiment of this application;

[0033] Figure 5 A flowchart of a thickness analysis method provided in an embodiment of this application;

[0034] Figure 6 This is a flowchart of a chip fabrication method provided in an embodiment of this application.

[0035] Icons: Test capacitor 110; Test metal plate 111; Insulation layer under test 120; Metal layer 130; Substrate insulation layer 140; Capacitance measuring device 200. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0037] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a thickness analysis wafer provided in an embodiment of this application. The thickness analysis wafer includes: a test metal plate 111, an insulating layer 120 to be tested, and a metal layer 130. The test metal plate 111, the insulating layer 120 to be tested, and the metal layer 130 are arranged sequentially, that is, the insulating layer 120 to be tested is disposed on the test metal plate 111, and the metal layer 130 is disposed on the insulating layer 120 to be tested.

[0038] The test metal plate 111 can be placed on the substrate insulating layer and connected to the insulating layer 120 to be tested.

[0039] During wafer manufacturing, each layer of the structure is generated sequentially, with each layer growing on top of another and unable to be separated. Therefore, in this embodiment, the test metal plate 111 can be placed on the insulating layer of the wafer substrate for thickness analysis before the insulating layer 120 to be measured is generated. Placing the test metal plate 111 on the insulating layer of the substrate avoids connection between the test metal plate 111 and the conductive layers in the wafer, thus preventing any impact on the accuracy of the test results.

[0040] In one embodiment, the area of ​​the test metal plate 111 is larger than a preset area, which is determined based on the measurement limits of the capacitance measuring device.

[0041] In this embodiment, the area of ​​the test metal plate 111 is known. It is understood that the capacitance value is related to the distance between the two metal plates constituting the capacitor. In the embodiments provided in this application, this characteristic of capacitance is utilized when measuring the thickness of the insulating layer 120 to be measured. By testing the capacitance value between the metal plate 111 and the metal layer 130, and then using the relationship between a preset parasitic capacitance value and thickness, the distance between the test metal plate 111 and the metal layer 130 is determined, and this distance is used as the thickness of the insulating layer 120 to be measured. Therefore, in the thickness analysis wafer provided in this embodiment, the area of ​​the test metal plate 111 can be obtained in advance, or the area of ​​the test metal plate 111 can be set to a preset size.

[0042] Since capacitance measuring devices have measurement limits, the preset area can be determined based on these limits. For example, for a capacitance measuring device with a detection limit in the fF range, the area of ​​any one of the capacitor's plates must be at least greater than 12µm. 2 That is, the preset surface area is 12um 2The area of ​​the test metal plate must be at least 12µm. 2 .

[0043] In some embodiments provided in this application, the test metal plate 111 can be an independently set metal plate, and the test metal plate 111 is set in a designated area on the wafer. The designated area can be an area that does not affect the electrical performance of the wafer or has a small impact on the electrical performance of the wafer.

[0044] Since the test metal plate 111 occupies a certain area of ​​the chip and may affect the thickness of the chip, in this embodiment, the test metal plate 111 can be set in a designated area on the wafer. For example, the designated area can be an area in the chip where no circuit is set, thereby reducing the impact of the test metal plate 111 on the electrical performance of the wafer.

[0045] In other embodiments, the test metal plate 111 may also be part of certain functional devices in the wafer. For example, if the two plates of a capacitor are metal plates, the test metal plate 111 may be one of the two plates of a capacitor device in the wafer. Therefore, without affecting wafer performance, the metal plate of the capacitor device can be shared to measure the thickness of the insulating layer 120 under test, thereby simplifying the structure of the wafer for thickness analysis. This eliminates the need for a separate test metal plate 111, thus reducing the additional chip area occupied by the test metal plate.

[0046] In some embodiments, the thickness analysis wafer may also be a wafer specifically designed for analyzing the thickness of the insulating layer 120 under test or thickness-related factors. For example, this thickness analysis wafer may only have a test metal plate and no other functional circuits or devices, so as to analyze the relationship between the thickness of the insulating layer 120 under test and the surface shape and material of the insulating layer 120. In this type of thickness analysis wafer, the test metal plate 111 can be arbitrarily set, including but not limited to the position and number of metal plates.

[0047] In this embodiment, the insulating layer 120 to be tested is the layer whose thickness needs to be measured. It can be an oxide layer disposed on the MIM capacitor in the wafer, or other insulating layers whose thickness needs to be measured.

[0048] In this embodiment, the insulating layer 120 to be tested can be made of different materials, such as aluminum oxide, silicon dioxide, etc., without limitation. It is understood that the capacitance value is also related to the dielectric between the two metal plates of the capacitor. Therefore, in this embodiment, when using multiple thickness analysis wafers to investigate the influencing factors of the thickness of the insulating layer to be tested, the materials of the insulating layer 120 to be tested on different wafers are the same. This eliminates the difference in capacitance value of the parasitic capacitance formed between the test metal plate 111 and the metal layer 130 caused by material differences. The type of material used in the insulating layer to be tested can be directly obtained to determine the dielectric constant corresponding to the insulating layer to be tested, so as to calculate the thickness of the insulating layer to be tested based on the parasitic capacitance value.

[0049] During wafer manufacturing, if the oxide layer is too thick, it may affect the electrical performance of the wafer. Therefore, the oxide layer needs to be polished to reduce its thickness to the required range. In this embodiment, the insulating layer can be any oxide layer. Since the thickness measurement wafer provided in this application is used to determine the thickness of the insulating layer 120 under test based on the parasitic capacitance value, and the method of measuring the thickness is not affected by the surface shape of the insulating layer under test, it can be measured regardless of whether the insulating layer 120 under test has been polished. Therefore, the insulating layer 120 under test in this embodiment can be a polished insulating layer.

[0050] In this embodiment, a metal layer 130 is disposed on top of the insulating layer 120 to be tested. This allows the insulating layer 120 to be located between the test metal plate 111 and the metal layer 130. After connecting the metal layer 130 and the test metal plate 111 to a power supply, they form a capacitor structure. The capacitance of this capacitor structure is the parasitic capacitance value. The distance between these capacitor structures is the thickness of the insulating layer 120 to be tested. Therefore, the capacitance value of this capacitor structure can be measured, and the distance between the two plates can be determined using the capacitance value. In other words, the thickness of the insulating layer 120 to be tested can be calculated using the parasitic capacitance value between the test metal plate 111 and the metal layer 130.

[0051] The metal layer 130 can be any material in the wafer. The type and material of the metal layer 130 can refer to various metal layers 130 in existing wafers, and are not limited here.

[0052] In one embodiment, the thickness analysis wafer further includes a first contact and a second contact, which are disposed on the surface of the thickness analysis wafer; the first contact is connected to the test metal plate 111, and the second contact is connected to the metal layer 130.

[0053] Each layer of the wafer is led out to the wafer surface via metal wires and connected to contacts on the wafer surface, allowing external circuitry to conduct through the contacts to the internal layers of the wafer. In this embodiment, the first and second contacts can be connected to the test metal plate 111 and the metal layer 130 respectively. This allows a capacitance measurement device to connect to the test metal plate 111 and the metal layer 130 via the first and second contacts, enabling the measurement of parasitic capacitance. This improves measurement efficiency and reduces connection requirements.

[0054] In the thickness analysis wafer provided in the above embodiment, the test metal plate 111 and the metal layer 130 form a structure similar to a capacitor. After connecting them to a power source, a capacitor can be formed between them. The capacitance value is related to the area of ​​the two metal plates forming the capacitor, the distance between the two metal plates, and the dielectric constant of the dielectric between the metal plates. Given that the material of the insulating layer 120 to be tested, the dielectric constant of the insulating layer 120 to be tested, and the area of ​​the test metal plate 111 are determined, the distance between the metal layer 130 and the test metal plate 111 can be determined by measuring the capacitance between them. Since only the insulating layer 120 to be tested is disposed between them, the distance between them is the thickness of the insulating layer 120 to be tested. Therefore, the thickness of the insulating layer 120 to be tested can be measured using the thickness analysis wafer. The influencing factors and calculation methods of the capacitance value can be referred to in the prior art and will not be elaborated here.

[0055] In the thickness analysis wafer provided in the above embodiment, the measurement of the thickness of the insulating layer 120 is independent of the surface shape of the insulating layer 120. Compared with optical inspection instruments, the thickness analysis wafer is not affected by the surface shape of the insulating layer 120, and can realize the measurement of the thickness of the insulating layer 120 under different surface shapes, effectively improving the accuracy and efficiency of the measurement of the thickness of the insulating layer 120 under different surface shapes.

[0056] Furthermore, the thickness analysis wafer provided in the above embodiments can be used to analyze the relationship between the thickness of the insulating layer 120 under test and the surface shape of the insulating layer 120 under test under the same manufacturing process.

[0057] In one embodiment, multiple test capacitors can be spaced apart on the substrate insulating layer 140 of the thickness analysis wafer, and the metal plate of any test capacitor connected to the insulating layer under test is used as the test metal plate 111 to measure the thickness of the insulating layer 120 under test.

[0058] Please see Figure 2 , Figure 2 This is a schematic diagram of a thickness analysis wafer structure including a test capacitor, provided as an embodiment of this application.

[0059] In this embodiment, the test capacitor 110 refers to a capacitor, such as a MIM capacitor, a capacitor with filtering function, or a capacitor with energy storage function. It should be distinguished that the parasitic capacitance formed between the test metal plate 111 and the metal layer 130 is a structure with similar characteristics to a capacitor due to their position; the test metal plate 111 and the metal layer 130 are not capacitors themselves.

[0060] The test capacitor 110 includes two metal plates. In this embodiment, the metal plate connected to the insulating layer 120 under test can be used as the test metal plate 111. There are no other structures outside the insulating layer under test between the test metal plate and the metal layer, which simplifies the measurement of parasitic capacitance.

[0061] The capacitor has a certain thickness. A test capacitor 110 is set on the substrate insulating layer 140. Subsequently, an oxide layer will be formed on the surface of the test capacitor 110, creating a protrusion. In some wafer manufacturing processes, the oxide layer is polished to reduce its thickness. However, the protrusion may affect the polishing rate. The more numerous and denser the protrusions, the faster the polishing rate. If the oxide layer is polished using the process for low-density protrusions, over-polishing may occur, reducing the electrical performance of the wafer. Therefore, the thickness of the oxide layer is related to the density of the capacitors set on the substrate insulating layer 140.

[0062] The oxide layer mentioned above can be the insulating layer 120 to be tested in the embodiments of this application. In this embodiment, multiple test capacitors 110 can be set on the substrate insulating layer 140 of the analysis wafer with different thicknesses. The number of test capacitors 110 can be different, and the setting position of the test capacitors 110 can be different. After the insulating layer 120 to be tested is generated on the surface of the test capacitor 110 and polished, multiple protrusions will be formed on the surface of the insulating layer 120 to simulate different surface shapes of the insulating layer 120 to be tested, thereby analyzing the relationship between the thickness of the insulating layer 120 to be tested and the surface shape of the insulating layer 120 to be tested or the density of the test capacitors 110.

[0063] When multiple test capacitors 110 are disposed on the substrate insulating layer 140, the metal plates of one or more test capacitors 110 can be led out to contacts on the surface of the thickness analysis wafer. It can be understood that the parasitic capacitance value between the metal plate of a test capacitor 110 and the metal layer 130 can be used to calculate the thickness of the insulating layer 120 under test. The parasitic capacitance values ​​between the metal plates of different test capacitors 110 and the metal layer 130 can be measured separately, and an average value can be calculated based on multiple parasitic capacitance values. The thickness of the insulating layer 120 under test can then be determined based on this average capacitance value, or the thickness can be determined using other statistical methods. This utilizes more measurement data to improve the accuracy of the parasitic capacitance values, thereby improving the accuracy of the determined thickness of the insulating layer under test.

[0064] In one embodiment, a plurality of test capacitors 110 may be disposed in a preset area of ​​the substrate insulating layer 140, wherein the number of test capacitors 110 in the preset area represents the density of the test capacitors 110.

[0065] like Figure 3 As shown, in this embodiment, the preset region can be any pre-defined region on the insulating layer 140 of the thickness analysis wafer substrate, and the specific location of the preset region is not limited. Different thickness analysis wafers have the same preset region location and the same electrical properties. For example, if the preset region of one thickness analysis wafer is region A on that wafer, then the preset region of another thickness analysis wafer is also region A on that wafer. Within this region, a corresponding number of test capacitors 110 can be set as needed, so that the surface shape of the insulating layer 120 under test in this region changes according to the density of the test capacitors 110. For example, N test capacitors 110 can be set in the preset region of the first thickness analysis wafer, 2N test capacitors 110 can be set on the second thickness analysis wafer, 3N test capacitors 110 can be set on the third thickness analysis wafer, and so on. The above are merely examples and are not intended to limit this application.

[0066] Different locations on a wafer may have different characteristics. In this embodiment, different numbers of test capacitors 110 can be set in preset areas of wafers with different thicknesses. Thus, when analyzing the relationship between the density of the test capacitors 110 and the thickness of the insulating layer 120 to be tested, the influence of different locations on the wafer on the analysis can be reduced, so that the conditions of each wafer with different thicknesses are kept consistent, thereby improving the accuracy of the measured parasitic capacitance value and the calculated thickness, and improving the effectiveness of the thickness analysis.

[0067] Based on the same inventive concept, this application also provides a thickness analysis system. Please refer to [link to relevant documentation]. Figure 4 The thickness analysis system includes: a thickness analysis wafer and a capacitance measurement device 200.

[0068] The thickness analysis wafer can be any of the thickness analysis wafers provided in the above embodiments or wafers with similar functions, and will not be described in detail here.

[0069] The capacitance measurement device 200 is used to measure the parasitic capacitance between the test metal plate and the metal layer in a thickness analysis wafer.

[0070] In this embodiment, the capacitance measuring device 200 can be any type of device used for measuring capacitance, including but not limited to various capacitance testers, multimeters, oscilloscopes, digital bridges, etc., which will not be described in detail here.

[0071] In this embodiment, the two test terminals of the capacitance measuring device 200 can be connected to the test metal plate 111 and the metal layer 130 of the thickness analysis wafer, respectively, to test the parasitic capacitance value between the test metal plate 111 and the metal layer 130 in the thickness analysis wafer. Specifically, the test terminals can be connected to a first contact and a second contact on the surface of the thickness analysis wafer. The first contact is connected to the test metal plate 111 inside the wafer via a metal wire, and the second contact is connected to the metal layer 130 inside the wafer via a metal wire. Therefore, the thickness of the insulating layer 120 between the test metal plate 111 and the metal layer 130 can be calculated based on the parasitic capacitance value.

[0072] In one embodiment, the capacitance measuring device 200 may also be configured to determine the thickness of the insulating layer 120 to be measured based on the parasitic capacitance value and a preset relationship between the parasitic capacitance value and the thickness.

[0073] The preset relationship between parasitic capacitance and thickness can be expressed by a capacitance calculation formula, where the capacitance calculation formula can be:

[0074] C=εS / 4πkd

[0075] Where C is the capacitance, ε is the dielectric constant, S is the area of ​​the capacitor plates facing each other, d is the distance between the capacitor plates, and k is the electrostatic constant.

[0076] The dielectric constant ε is related to the material of the insulating layer under test, and its specific value can be determined when the material of the insulating layer under test is determined. In the thickness analysis wafer, the area of ​​the test metal plate is the area of ​​the electrode plates facing each other, and the electrostatic constant k is constant. Therefore, after measuring the parasitic capacitance value, the distance between the metal layer and the test metal plate can be determined by the above calculation formula, that is, the thickness of the insulating layer under test can be obtained.

[0077] The capacitance measuring device 200 may be a device equipped with a processor and a memory. The memory stores a program, and the processor can perform different calculations according to the program stored in the processor. It is understood that some capacitance measuring devices 200 can be configured with different programs to meet different calculation needs. Therefore, in this embodiment, a program can be configured in the capacitance measuring device 200 to determine the thickness of the insulating layer 120 to be measured based on the parasitic capacitance value and a preset relationship between the parasitic capacitance value and the thickness, so that the capacitance measuring device 200 can directly determine the thickness of the insulating layer 120 to be measured.

[0078] In some embodiments, the thickness analysis system may further include a processing device connected to the capacitance measuring device 200. The processing device is used to acquire the parasitic capacitance value sent by the capacitance measuring device 200, and determine the thickness of the insulating layer 120 to be measured based on the parasitic capacitance value and a preset relationship between the parasitic capacitance value and the thickness.

[0079] In this embodiment, the processing device can be various host computers, servers, etc. The processing device is configured with a program that calculates the thickness of the insulating layer 120 to be tested based on the parasitic capacitance value and a preset relationship between the parasitic capacitance value and the thickness. It can calculate the thickness of the insulating layer 120 to be tested based on the input parasitic capacitance value. Different processing devices may configure the program in different ways; the implementation methods of different processing devices can refer to existing technologies, and will not be elaborated here.

[0080] In some embodiments of this application, if the capacitance measuring device 200 does not have a processing module, or the processing module of the capacitance measuring device 200 does not have the function of calculating the thickness of the insulation layer 120 to be tested, the capacitance measuring device can be connected to the processing device so that after obtaining the parasitic capacitance value, the processing device can calculate the thickness of the insulation layer 120 to be tested based on the preset parasitic capacitance value and the preset relationship between the parasitic capacitance value and the thickness.

[0081] In some embodiments of this application, if the capacitance testing device cannot communicate with other devices, the parasitic capacitance value measured by the capacitance measuring device 200 can be manually input into the processing device so that the processing device can determine the thickness of the insulation layer 120 to be tested based on the parasitic capacitance value and the relationship between the preset parasitic capacitance value and the thickness.

[0082] Through the aforementioned thickness analysis system, the capacitance measurement device 200 can determine the thickness of the insulating layer 120 to be measured by analyzing the parasitic capacitance value between the test metal plate 111 and the metal layer 130 in the wafer. Since the thickness is calculated by capacitance, it is not affected by the surface shape of the insulating layer 120 to be measured. Therefore, the accuracy and efficiency of measuring the thickness of the insulating layer 120 to be measured can be improved.

[0083] Based on the same inventive concept, embodiments of this application provide a thickness analysis method. Please refer to... Figure 5 , Figure 5 This is a flowchart of a thickness analysis method provided in an embodiment of this application. The thickness analysis method includes:

[0084] S310, obtain the parasitic capacitance value of the thickness analysis wafer.

[0085] In this embodiment, for a wafer whose thickness of the insulating layer 120 needs to be analyzed, a test metal plate 111 can be disposed on the substrate insulating layer 140 during the wafer fabrication process, and the insulating layer 120 and the metal layer 130, as well as other structures of the wafer, can be grown layer by layer. The metal layer 130, the insulating layer 120, and the test metal plate 111 can form the thickness analysis wafer mentioned in the above embodiments of this application. Therefore, the thickness of the insulating layer 120 can be determined by measuring the parasitic capacitance between the metal layer 130 and the test metal plate 111 in the thickness analysis wafer.

[0086] In conjunction with the description of the above embodiments, in one embodiment of this application, the capacitance between the metal layer 130 and the test metal plate 111 can be detected using a capacitance measuring device 200.

[0087] In this embodiment, the capacitance measuring device 200 can be the capacitance measuring device 200 mentioned in the above embodiments, which is equipped with a program based on the relationship between parasitic capacitance value and thickness, and can calculate the thickness of the insulating layer 120 to be tested based on the input parasitic capacitance value. The metal layer 130 and the test metal plate 111 of the thickness analysis wafer are connected to the contacts on the wafer surface via metal wires. Therefore, different test terminals of the capacitance measuring device 200 can be connected to the corresponding contacts of the metal layer 130 and the test metal plate 111 to measure the parasitic capacitance value, thereby determining the thickness of the insulating layer 120 to be tested on the wafer.

[0088] In some embodiments, if it is necessary to analyze the relationship between the thickness of the insulation layer 120 under test and the surface shape of the insulation layer 120 under test, or to analyze the relationship between the thickness of the insulation layer 120 under test and the manufacturing process of the insulation layer 120 under test, test capacitors 110 with a preset test capacitor density can be arranged on the substrate insulation layer 140, and a density-related insulation layer 120 under test can be generated on the test capacitors 110.

[0089] The test capacitor 110 includes two metal plates, and the test metal plate 111 is one of the metal plates of the test capacitor 110. Details regarding the test capacitor 110 can be found in the foregoing embodiments and will not be repeated here.

[0090] In this embodiment, the higher the density of the test capacitors, the denser the protrusions of the insulating layer under test, and the faster the grinding rate of the insulating layer under test under the same manufacturing process. Therefore, the density of the test capacitors 110 can simulate different surface shapes of the insulating layer under test 120. Thus, by arranging test capacitors 110 with different densities, wafers with different surface shapes of the insulating layer under test 120 or wafers with different thicknesses of the insulating layer under test 120 can be obtained. This allows for the analysis of the relationship between the thickness of the insulating layer under test 120 and the manufacturing process or the surface shape of the insulating layer under test 120, thereby instructing the design and manufacturing of subsequent chips.

[0091] S320, based on the parasitic capacitance value and the relationship between the preset parasitic capacitance value and the thickness, determines the thickness of the insulation layer 120 to be tested.

[0092] In this embodiment, the material used for the insulating layer 120 under test can be determined during wafer growth, thereby determining the dielectric constant of the insulating layer 120 under test. Furthermore, the area of ​​the test metal plate 111 is known; therefore, the distance between the test metal plate and the metal layer 130, i.e., the thickness of the insulating layer 120 under test, can be directly determined using the capacitance calculation formula.

[0093] The thickness analysis method is similar to the function achieved by the aforementioned thickness analysis wafers and systems, and will not be repeated here.

[0094] Based on the same inventive concept, embodiments of this application also provide a chip fabrication method. Please refer to... Figure 6 , Figure 6 This application provides a flowchart of a chip fabrication method, which includes:

[0095] S410: Obtain multiple thickness analysis wafers manufactured using the same process, with different densities of test capacitors 110 in the different thickness analysis wafers.

[0096] The thickness analysis wafer can be the thickness analysis wafer provided in the above embodiments or a wafer with a similar structure, and will not be described in detail here.

[0097] In this embodiment, different test capacitor 110 densities can be set in analysis wafers of different thicknesses to analyze the relationship between the test capacitor 110 density and the thickness of the insulating layer 120 to be tested.

[0098] For example, firstly, a wafer with a substrate insulating layer 140 can be obtained, and a test capacitor 110 can be set on the surface of the substrate insulating layer 140. When setting the test capacitor 110 for wafers of different thicknesses, the test capacitor 110 can be uniformly set at a preset position on the substrate insulating layer 140 of the thickness analysis wafer, thereby reducing the differences caused by different setting positions of the test capacitor 110. The different wafers can be wafers produced in the same batch, thereby reducing the differences between wafers.

[0099] Next, the same manufacturing process is used to form the test insulation layer 120 on the surface of the test capacitor 110. After polishing and grinding the test insulation layer 120, a metal layer 130 is formed on the surface of the test insulation layer 120, and metal contacts are provided to connect with each structural layer. Specifically, wafers with different densities of test capacitors 110 are used in the same batch for forming the test insulation layer 120 and metal layer 130 to reduce differences in the test insulation layer 120 caused by equipment and processes.

[0100] It is understandable that using the same manufacturing process for each thickness analysis wafer is to reduce differences caused by the manufacturing process. During manufacturing, wafers manufactured in the same batch and using the same equipment to generate each structure can be prepared using the same manufacturing process. This can reduce the differences that may be caused by different factors, thereby reducing the impact of the manufacturing process on the thickness of the insulating layer 120 to be measured and improving the accuracy of the thickness analysis of the insulating layer 120 to be measured.

[0101] S420 measures the thickness of the insulating layer 120 in each thickness analysis wafer.

[0102] In this embodiment, after obtaining the thickness analysis wafer, thickness analysis wafers with different density test capacitors 110 can be connected to the capacitance measurement device 200 to measure the parasitic capacitance values ​​of the different thickness analysis wafers, and the thickness of the insulating layer 120 to be tested can be calculated based on the parasitic capacitance values. The measurement of the thickness of the insulating layer 120 to be tested can be referred to the foregoing content, and will not be repeated here.

[0103] S431, establish the first correspondence between the density of the test capacitor 110 and the thickness of the insulation layer 120 to be tested.

[0104] In this embodiment, after measuring the thickness of the insulating layer 120 to be tested, the density of the test capacitor 110 can be matched with the thickness of the insulating layer 120 to establish a first correspondence. This first correspondence can be a coordinate system, table, etc., recording different densities of the test capacitor 110 and their corresponding thicknesses of the insulating layer 120, or a calculation formula for calculating the thickness of the insulating layer 120 based on the density of the test capacitor 110. There are various types of first correspondences, which will not be described in detail here.

[0105] Wafer fabrication includes, but is not limited to, wafer design and production. During wafer circuit and process design, this first correspondence assists designers in designing circuits and processes, reducing trial-and-error costs. During wafer production, the first correspondence helps engineers and operators determine the process parameters required for the current batch of wafers, enabling more accurate wafer manufacturing and improving wafer yield.

[0106] In one embodiment, before establishing the first correspondence, it can also be determined whether the thickness of the insulating layer 120 to be tested in all thickness analysis wafers is within a preset thickness range.

[0107] The preset thickness range can be the preset thickness range of the insulating layer 120 under test in the wafer manufacturing process, that is, the process requirements of the insulating layer 120 under test. Different wafers may have different preset thickness ranges, which will not be discussed here.

[0108] By determining whether the thickness of the insulating layer 120 to be tested in the thickness analysis wafer is within the preset thickness range, the insulating layer 120 that obviously does not meet the process requirements can be selected and thus excluded from the consideration of the first correspondence relationship. This ensures that the data referenced by the first correspondence relationship all meet the process requirements, improves the accuracy of the first correspondence relationship, and can improve the yield and output of chip fabrication when using the first correspondence relationship.

[0109] In one embodiment, if the thickness of the insulating layer 120 to be tested on any thickness analysis wafer is outside the preset thickness range, a thickness analysis wafer with the same test capacitor 110 density can be remade based on the second manufacturing process; if the thickness of the insulating layer 120 to be tested on the remade thickness analysis wafer is within the preset thickness range, a second correspondence between the second manufacturing process and the test capacitor 110 density is established.

[0110] In this embodiment, when establishing the first correspondence, if the thickness of the insulating layer 120 to be tested of any thickness analysis wafer is outside the preset thickness range, it indicates that the thickness analysis wafer does not meet the process requirements, and also indicates that the first manufacturing process currently used is not suitable for preparing the wafer at the corresponding test capacitor density 110. At this time, if it is still necessary to prepare the wafer at the test capacitor density 110, the manufacturing process can be adjusted and the thickness analysis wafer at the test capacitor density 110 can be remanufactured.

[0111] Adjusting the manufacturing process includes, but is not limited to, adjusting the time for growing the insulation layer 120 to be tested, adjusting the time for polishing and grinding the insulation layer 120 to be tested, and adjusting the type and concentration of the chemical reagents used for polishing and grinding.

[0112] If the thickness of the insulating layer 120 to be tested on the thickness analysis wafer obtained after adjusting the manufacturing process is within the preset range, the adjusted manufacturing process can be used as the second manufacturing process to establish a second correspondence between the manufacturing process and the density of the test capacitor 110. When a wafer with the required test capacitor density needs to be prepared, relevant personnel can be instructed to use the second manufacturing process to manufacture it, thereby reducing trial and error costs and improving the yield of wafer production.

[0113] The chip manufacturing method described above can determine the first and / or second correspondence to indicate chip preparation, thereby improving chip yield and quality.

[0114] The above detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0115] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0116] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0117] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A thickness analysis wafer, characterized in that, include: Test metal plate; The insulation layer to be tested is disposed on the test metal plate; A metal layer is disposed on the insulating layer to be tested, wherein the insulating layer to be tested is located between the test metal plate and the metal layer; The parasitic capacitance value between the test metal plate and the metal layer is used to determine the thickness of the insulating layer under test. The thickness analysis wafer further includes a substrate insulating layer, on which a plurality of test capacitors are spaced apart, each of the test capacitors including two metal plates; the test metal plate is the metal plate of any of the test capacitors that is in contact with the insulating layer to be tested; The thickness of the insulating layer under test is related to the density of the test capacitors disposed on the substrate insulating layer.

2. The thickness analysis wafer according to claim 1, characterized in that, The plurality of test capacitors are disposed within a predetermined region of the substrate insulating layer, wherein the number of test capacitors within the predetermined region represents the density.

3. The thickness analysis wafer according to claim 1 or 2, characterized in that, The thickness analysis wafer further includes a first contact and a second contact; the first contact and the second contact are disposed on the surface of the thickness analysis wafer; the first contact is connected to the test metal plate, and the second contact is connected to the metal layer.

4. A thickness analysis system, characterized in that, include: Capacitance measurement equipment and thickness analysis wafer as described in any one of claims 1-3; The capacitance measurement device is connected to the test metal plate and the metal layer in the thickness analysis wafer, respectively. The capacitance measurement device is configured to measure the parasitic capacitance value between the test metal plate and the metal layer. The parasitic capacitance value is used to determine the thickness of the insulating layer to be tested in the thickness analysis wafer.

5. The thickness analysis system according to claim 4, characterized in that, The capacitance measuring device is further configured to determine the thickness of the insulating layer to be measured based on the parasitic capacitance value and the relationship between the preset parasitic capacitance value and the thickness.

6. The thickness analysis system according to claim 4, characterized in that, The thickness analysis system also includes: A processing device is connected to the capacitance measuring device. The processing device is used to acquire the parasitic capacitance value sent by the capacitance measuring device, and to determine the thickness of the insulation layer to be measured based on the parasitic capacitance value and the relationship between the parasitic capacitance value and the thickness.

7. A thickness analysis method, characterized in that, include: Obtain the parasitic capacitance value of a thickness analysis wafer; wherein, the thickness analysis wafer includes a test metal plate, an insulating layer to be tested, and a metal layer arranged sequentially; the parasitic capacitance value is the capacitance value between the metal layer and the test metal plate; The thickness of the insulating layer to be tested is determined based on the parasitic capacitance value and the preset relationship between the parasitic capacitance value and the thickness. Before obtaining the parasitic capacitance value of the wafer for thickness analysis, the thickness analysis method further includes: Test capacitors with a preset test capacitance density are arranged on the substrate insulating layer; An insulating layer of the test, related to the density, is formed on the test capacitor, wherein the test capacitor comprises two metal plates; the test metal plate is one of the metal plates of the test capacitor; The metal layer is generated on the insulating layer to be tested to obtain the thickness analysis wafer.

8. The thickness analysis method according to claim 7, characterized in that, The process of obtaining the parasitic capacitance value of the thickness analysis wafer includes: The parasitic capacitance between the metal layer and the test metal plate is detected using a capacitance measuring device, wherein the capacitance measuring device is connected to both the metal layer and the test metal plate.

9. A chip fabrication method, characterized in that, include: Multiple thickness analysis wafers manufactured using the same process are obtained, with different densities of test capacitors in the wafers of different thicknesses. Each thickness analysis wafer includes a test capacitor, a test insulating layer, and a metal layer arranged sequentially. The test insulating layer is disposed between one of the metal plates in the test capacitor and the metal layer. The parasitic capacitance value between the metal plate and the metal layer is used to determine the thickness of the test insulating layer. The thickness of the test insulating layer is related to the density of the test capacitor. The thickness of the insulating layer to be tested in each of the thickness analysis wafers is measured separately. A first correspondence is established between the density of the test capacitor and the thickness of the insulating layer to be tested; the first correspondence is used to indicate the fabrication of the chip.

10. The chip fabrication method according to claim 9, characterized in that, Before establishing a first correspondence between the density of the test capacitor and the thickness of the insulating layer to be tested, the method further includes: determining that the thickness of the insulating layer to be tested in all thickness analysis wafers is within a preset thickness range.

11. The chip fabrication method according to claim 9, characterized in that, The method further includes: If the thickness of the insulating layer to be tested on any of the thickness analysis wafers is outside the preset thickness range, then a thickness analysis wafer with the same test capacitance density is remade based on the second manufacturing process. If the thickness of the insulating layer to be tested on the re-made thickness analysis wafer is within the preset thickness range, a second correspondence is established between the second manufacturing process and the test capacitance density; the second correspondence is used to indicate the fabrication of the chip.

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