Semiconductor structure and its fabrication method, semiconductor device

Abstract

This disclosure provides a semiconductor structure, its fabrication method, and a semiconductor device. The semiconductor structure includes a substrate, active pillars, gate structures, a metal silicide layer, and an isolation layer. The active pillars are located on the substrate and arranged in an array, extending in a direction perpendicular to the substrate. The gate structures are located on the substrate, spaced apart along a first direction, and surrounding a portion of the active pillars. The metal silicide layer is located on the top surface of the active pillars, and the projection of the metal silicide layer onto the substrate coincides with the projection of the top surface of the active pillars onto the substrate. The isolation layer is located between adjacent gate structures and adjacent active pillars, and the height of the isolation layer is higher than the height of the top surface of the metal silicide layer. The semiconductor structure of this disclosure reduces contact resistance, lowers energy consumption, and improves the operating speed of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method, and a semiconductor device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. Currently, DRAM with 4F... 2 In DRAM with cell structure and vertical channel transistors, the contact between the source / drain of the transistor and the memory cell is that the silicon active pillars are in direct contact with the metal layer of the memory cell. However, due to the high resistance of the silicon pillars, the contact resistance between the two is high, which reduces the operating speed of the semiconductor device and degrades the performance of the semiconductor device.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a semiconductor device in which the metal silicide layer has a low contact resistance, which can improve operating speed and reduce energy consumption.

[0005] This disclosure also provides a method for fabricating a semiconductor structure that can reduce the contact resistance of active pillars and improve the operating speed of the semiconductor structure.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a substrate, active pillars, gate structures, a metal silicide layer, and an isolation layer. The active pillars are located on the substrate and arranged in an array, extending in a direction perpendicular to the substrate; the gate structures are located on the substrate, spaced apart along a first direction, and surrounding a portion of the active pillars; the metal silicide layer is located on the top surface of the active pillars, and the projection of the metal silicide layer onto the substrate coincides with the projection of the top surface of the active pillars onto the substrate; the isolation layer is located between adjacent gate structures and adjacent active pillars, and the height of the isolation layer is higher than the height of the top surface of the metal silicide layer.

[0007] According to an exemplary embodiment of this disclosure, the metal element in the metal silicide layer includes at least one of Co, Ni, Pt, Ti, Ta, Mo, and W.

[0008] According to an exemplary embodiment of the present disclosure, the gate structure includes: a gate insulating layer surrounding the side of the active pillar, wherein the top surface of the gate insulating layer is lower than the top surface of the metal silicide layer in a direction perpendicular to the substrate; and a word line layer surrounding a portion of the side of the gate insulating layer.

[0009] According to an exemplary embodiment of this disclosure, the distance between the top surface of the gate insulating layer and the top surface of the metal silicide layer is 5 to 40 nm.

[0010] According to an exemplary embodiment of this disclosure, the semiconductor structure further includes: a connection layer located on the metal silicide layer, wherein the projection of the connection layer on the substrate covers the projection of the metal silicide layer on the substrate.

[0011] According to an exemplary embodiment of this disclosure, the isolation layer extends in a direction perpendicular to the substrate, and the top surface of the isolation layer is flush with the top surface of the connecting layer.

[0012] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate having an array of active pillars extending in a direction perpendicular to the substrate; forming gate structures on the substrate, spaced apart in a first direction and surrounding a portion of the active pillars; forming an isolation layer between adjacent gate structures and adjacent active pillars, the isolation layer having a height higher than the height of the top surface of the active pillars; and forming a metal silicide layer on the top surface of the active pillars, wherein the projection of the metal silicide layer onto the substrate coincides with the projection of the top surface of the active pillars onto the substrate.

[0013] According to an exemplary embodiment of the present disclosure, forming a gate structure includes: forming a gate insulating layer on the surface of the active pillar; and forming a word line layer around a portion of the sidewall of the gate insulating layer.

[0014] According to an exemplary embodiment of this disclosure, forming a gate insulating layer on the surface of the active post includes: forming a first insulating layer on the surface of the active post; filling a first isolation layer between the first insulating layers; etching back the first insulating layer to a first preset depth to expose a first portion of the active post; etching the sidewall of the first portion to form a first post; and forming a second insulating layer on the surface of the first post, wherein the second insulating layer and the first insulating layer form the gate insulating layer.

[0015] According to an exemplary embodiment of the present disclosure, forming a word line layer around a portion of the sidewall of the gate insulating layer includes: filling a word line metal layer between adjacent second insulating layers; and etching back the word line metal layer to a second predetermined depth to form the word line layer.

[0016] According to an exemplary embodiment of this disclosure, forming an isolation layer includes: forming a second isolation layer between adjacent gate insulating layers and on the word line layer; the first isolation layer and the second isolation layer form the isolation layer.

[0017] According to an exemplary embodiment of this disclosure, after the second isolation layer is formed, a chemical mechanical polishing process is used to make the top surfaces of the first isolation layer, the second isolation layer, and the second insulating layer flush.

[0018] According to an exemplary embodiment of this disclosure, the method further includes: removing the second insulating layer from the top surface of the first column to expose the top surface of the first column.

[0019] According to an exemplary embodiment of this disclosure, removing the second insulating layer on the top surface of the first pillar includes: etching back the second insulating layer, removing the second insulating layer on the top surface of the first pillar, and etching back the second insulating layer located on the side surface of the first pillar to a third preset depth.

[0020] According to an exemplary embodiment of this disclosure, the third preset depth is 5 to 40 nm.

[0021] According to an exemplary embodiment of this disclosure, forming a metal silicide layer includes: forming a first metal layer on the top surface of the active pillar; performing heat treatment on the active pillar to form a metal silicide layer on the top of the active pillar; and removing the remaining first metal layer.

[0022] According to an exemplary embodiment of this disclosure, the method further includes: forming a connection material layer on the top surface of the metal silicide layer, the top surface of the gate structure, and the top surface of the isolation layer; removing a portion of the connection material layer to expose the isolation layer, and forming a connection layer with the remaining connection material layer having a top surface flush with the top surface of the isolation layer.

[0023] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a semiconductor structure and a memory cell as described in any of the above embodiments; wherein the memory cell is electrically connected to the semiconductor structure via a connection layer.

[0024] As can be seen from the above technical solution, this disclosure possesses at least one of the following advantages and positive effects:

[0025] The active pillar of the semiconductor structure in this embodiment has a metal silicide layer on its top surface. The metal silicide layer has a small resistance. Therefore, the active pillar of this disclosure contacts the metal pad through the metal silicide layer, which reduces the contact resistance, reduces energy consumption, and improves the operating speed of the semiconductor structure. Attached Figure Description

[0026] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0027] Figure 1 A top view of a semiconductor structure according to an exemplary embodiment of this disclosure;

[0028] Figure 2 For along Figure 1 Cross-sectional view of the semiconductor structure of the XX and YY lines;

[0029] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of this disclosure;

[0030] Figures 4 to 17 This is a schematic diagram of the semiconductor structure during the fabrication process of an exemplary embodiment of this disclosure.

[0031] Explanation of reference numerals in the attached figures:

[0032] 1. Substrate; 2. Bit line; 21. Metal silicide region; 3. Active pillar; 31. First pillar; 4. Gate structure; 41. Gate insulating layer; 411. First insulating layer; 412. Second insulating layer; 42. Word line layer; 421. Word line metal layer; 5. Metal silicide layer; 51. First metal layer; 6. Isolation layer; 61. First isolation layer; 62. Second isolation layer; 7. Connecting layer; 71. Connecting material layer; F1. First direction; F2. Second direction; G. Groove. Detailed Implementation

[0033] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0034] In the following description of various exemplary embodiments of this disclosure, the accompanying drawings form part of this disclosure, and different exemplary structures that can implement various aspects of this disclosure are shown by way of example. It should be understood that other specific solutions for components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of this disclosure. Moreover, although the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of this disclosure, these terms are used herein only for convenience, such as the orientation according to the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this disclosure. Furthermore, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and are not intended to limit the number of objects thereof.

[0035] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0036] Furthermore, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Above" and "below" are technical terms indicating location, which are used merely to make the description clearer and are not intended to be limiting.

[0037] In related technologies, a semiconductor substrate has an active region and pads. A transistor is located in the active region, and the pads are electrically connected to the source / drain electrodes of the transistor, providing circuitry for the semiconductor structure and electrically connecting the transistor to the memory cell. The source / drain electrodes in these technologies are typically made of silicon-containing active region materials, which have high resistance, resulting in high contact resistance with the pads.

[0038] According to one aspect of this disclosure, a semiconductor structure is provided. For example... Figure 1 and Figure 2 As shown, where, Figure 1 A top view of a semiconductor structure according to an embodiment of the present disclosure is shown. Figure 2 It shows the respective along Figure 1 A cross-sectional view of the semiconductor structure with XX and YY lines. (See attached image.) Figure 1 and Figure 2As shown, the semiconductor structure of this embodiment includes: a substrate 1, active pillars 3, gate structures 4, a metal silicide layer 5, and an isolation layer 6. The active pillars 3 are located on the substrate 1 and arranged in an array, extending along a direction perpendicular to the substrate 1. The gate structures 4 are located on the substrate 1, spaced apart along a first direction F1, and surround a portion of the active pillars 3. The metal silicide layer 5 is located on the top surface of the active pillars 3, and the projection of the metal silicide layer 5 onto the substrate 1 coincides with the projection of the top surface of the active pillars 3 onto the substrate 1. The isolation layer 6 is located between adjacent gate structures 4 and adjacent active pillars 3, and the height of the isolation layer 6 is higher than the height of the top surface of the metal silicide layer 5.

[0039] The active pillar 3 of the semiconductor structure in this embodiment has a metal silicide layer 5 on its top surface. The metal silicide layer 5 has a small resistance. Therefore, the active pillar 3 of this disclosure contacts the metal pad through the metal silicide layer 5, thereby reducing contact resistance, reducing energy consumption, and improving the operating speed of the semiconductor structure.

[0040] The semiconductor structure of the embodiments of this disclosure will be described in detail below.

[0041] In the embodiments of this disclosure, "upper" and "lower" are directional terms indicating relative position, such as in... Figure 2 In this context, if the active pillar 3 is located on the substrate 1, then the substrate 1 is located below the active pillar 3. This directional term is only for clarity and does not have any limiting meaning.

[0042] like Figure 1 and Figure 2 As shown, the substrate 1 in this embodiment can be made of silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon-on-insulator, silicon-on-germanium, silicon-on-insulator, or germanium, etc.

[0043] In some embodiments, shallow trench isolation (not shown) is formed in substrate 1, and active regions are provided between the shallow trench isolations. Bit lines 2 are connected to the active regions. The active pillars 3 in this embodiment are formed by etching substrate 1, that is, the active pillars 3 and substrate 1 can be integral, and the active pillars 3 are located in the active regions of substrate 1. For clarity, the substrate portion located below the active pillars 3 can be named substrate 1.

[0044] In some embodiments, the metal elements of the metal silicide layer 5 include at least one of Co, Ni, Pt, Ti, Ta, Mo and W. These metal elements can combine with silicon in the substrate 1 to form a stable metal silicide and reduce resistance.

[0045] In some embodiments, such as Figure 2As shown, the gate structure 4 includes a gate insulating layer 41, which surrounds the side of the active pillar 3. In a direction perpendicular to the substrate 1, the top surface of the gate insulating layer 41 is lower than the top surface of the metal silicide layer 5. The gate insulating layer 41 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0046] The gate structure 4 also includes a word line layer 42, which surrounds a portion of the side surface of the gate insulating layer 41. For example... Figure 1 As shown, word line layers 42 are spaced apart in a first direction F1, and each word line layer 42 extends along a second direction F2. The word line layers 42 surrounding the surface of the gate insulating layer 41 can serve as gate electrodes; that is, the gate electrode can be part of the word line layer 42. In some embodiments, the material of the word line layer 42 may include at least one of TiN, W, Al, Cu, and Au.

[0047] like Figure 2 As shown, in the direction perpendicular to the substrate 1, the top surface of the gate insulating layer 41 is lower than the top surface of the metal silicide layer 5, that is, the gate insulating layer 41 forms a groove around the metal silicide layer 5. At least a portion of the interconnect layer 7 can be located in this groove, making the connection between the interconnect layer 7 and the active pillar 3 more stable.

[0048] In some embodiments, the distance between the top surface of the gate insulating layer 41 and the top surface of the metal silicide layer 5 is 5–40 nm, that is, the depth of the aforementioned groove is 5–40 nm. Specifically, in addition to the two extreme values ​​of the above range, the value of this distance can also be 25 nm, 30 nm, 35 nm, or 38 nm, or the distance between the top surface of each gate insulating layer 41 and the top surface of the metal silicide layer 5 can also vary within the range of 5–40 nm depending on the position, that is, each groove does not have a uniform depth, and different positions of each groove can have different depths. Those skilled in the art can choose according to actual needs, and no special limitation is made here. In some embodiments, the bottom surface of the groove is higher than the bottom surface of the metal silicide layer 5 (the bottom surface of the metal silicide layer 5 near the substrate 1), avoiding partial contact between the connection layer 7 and the active pillar 3, realizing complete contact between it and the metal silicide layer 5, reducing contact resistance, and increasing the contact area between the connection layer 7 and the metal silicide layer 5, thereby improving the operating speed of the semiconductor structure.

[0049] In some embodiments, such as Figure 2As shown, the semiconductor structure also includes an interconnect layer 7. Located on the metal silicide layer 5, the projection of the interconnect layer 7 onto the substrate 1 overlaps the projection of the metal silicide layer 5 onto the substrate 1. This interconnect layer 7 can be a pad metal, electrically connected to the metal silicide layer 5 on the active pillar 3, thereby achieving electrical connection between the metal silicide layer 5 and the memory cell. In some embodiments, the material of the interconnect layer 7 can be at least one of TiN, W, Al, Cu, and Au.

[0050] In some embodiments, such as Figure 2 As shown, the isolation layer 6 extends in a direction perpendicular to the substrate 1, and the top surface of the isolation layer 6 is flush with the top surface of the interconnect layer 7, so as to facilitate the setting of memory cells in subsequent processes.

[0051] In some embodiments, the semiconductor structure further includes bit lines 2, such as Figure 1 As shown, bit lines 2 are located in substrate 1 and are spaced apart along the second direction F2. The first direction F1 and the second direction F2 are not parallel, as shown... Figure 1 As shown, the first direction F1 and the second direction F2 are perpendicular. The material of bit line 2 includes metal silicide, such as... Figure 2 As shown, the area represented by the dashed ellipse is the metal silicide region 21, i.e., the region where the metal silicide is distributed in the bit line 2. In this embodiment, the bit line 2 is a buried bit line, formed by implanting impurity ions into the substrate 1. Since the bit line 2 formed solely by impurity ion implantation is not metal, but rather silicon wiring doped with impurity ions, the bit line 2 has a high resistance. To reduce the resistance of the bit line 2, the bit line 2 in this embodiment includes metal silicide. Metal silicide has low resistance, which reduces the resistance of the bit line 2 and decreases the energy consumption of the semiconductor structure during operation.

[0052] In summary, the active pillar 3 of the semiconductor structure in this embodiment has a metal silicide layer 5 on its top surface. The metal silicide layer 5 has a small resistance. Therefore, the active pillar 3 of this disclosure contacts the metal pad (connection layer 7) through the metal silicide layer 5, which reduces the contact resistance, reduces energy consumption, and improves the operating speed of the semiconductor structure.

[0053] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided. For example... Figures 3 to 17 As shown, where Figure 3 This is a flowchart of a semiconductor structure fabrication method. Figures 4 to 17 This is a schematic diagram of the semiconductor structure during the fabrication process. (Example:) Figure 3 As shown, the method for fabricating the semiconductor structure according to an embodiment of this disclosure includes:

[0054] Step S200: Provide a substrate 1, on which active pillars 3 are arranged in an array, the active pillars 3 extending in a direction perpendicular to the substrate 1.

[0055] Step S400: Form a gate structure 4 on the substrate 1, arranged at intervals along the first direction F1, and surrounding a portion of the active pillar 3.

[0056] Step S600: Form an isolation layer 6 between adjacent gate structures 4 and adjacent active pillars 3. The height of the isolation layer 6 is higher than the height of the top surface of the active pillars 3.

[0057] Step S800: Form a metal silicide layer 5, located on the top surface of the active pillar 3, and the projection of the metal silicide layer 5 on the substrate 1 coincides with the projection of the top surface of the active pillar 3 on the substrate 1.

[0058] The semiconductor structure fabrication method of this disclosure reduces the contact resistance of the active pillar 3 and improves the operating speed of the semiconductor structure by forming a metal silicide layer 5 on the top surface of the active pillar 3.

[0059] The method for fabricating the semiconductor structure according to the embodiments of this disclosure will be described in detail below.

[0060] Step S200: Provide a substrate 1, on which active pillars 3 are arranged in an array, the active pillars 3 extending in a direction perpendicular to the substrate 1.

[0061] like Figure 4 As shown, a substrate 1 is provided, and a mask layer (not shown) is formed on the substrate 1, and an array of active pillar patterns is formed on the mask layer. Based on the active pillar pattern, the substrate 1 is etched using an etching process to form an array of active pillars 3. In some embodiments, the etching process can be a wet etching process, which uses concentrated sulfuric acid and hydrogen peroxide as etchants. The etching depth is adjusted by controlling the concentration and ratio of the etchants, thereby controlling the height of the active pillars 3. In some embodiments, the etching process can be a dry etching process, which has good shape retention and can form vertical active pillars.

[0062] In some embodiments, substrate 1 is a silicon substrate and active pillar 3 is a silicon pillar.

[0063] Step S400: Form a gate structure 4, which is located on the substrate 1, spaced apart along the first direction F1, and surrounds a portion of the active pillar 3. Specifically, this may include steps S401 to S402.

[0064] Step S401: Form a gate insulating layer 41 on the surface of the active pillar 3. For example... Figure 5As shown, a first insulating layer 411 is formed on the surface of the active pillar 3. The first insulating layer 411 can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The first insulating layer 411 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Figure 6 As shown, a first insulating layer 61 is filled between the first insulating layers 411. The first insulating layer 61 may be silicon nitride or silicon oxynitride, and it serves to insulate adjacent active pillars 3. (Continue to the previous section) Figure 6 In some embodiments, the height of the first isolation layer 61 is higher than the height of the top surface of the active pillar 3. For example... Figure 7 As shown, the first insulating layer 411 is etched back to a first preset depth, exposing the first portion of the active pillar 3. The etch-back of the first insulating layer 411 can be performed using either a wet etching process or a dry etching process. A dry etching process can be a plasma etching process, where the etching gas used can be chlorine. By controlling the amount of etching gas, the etching degree can be controlled. A wet etching process can use concentrated sulfuric acid and hydrogen peroxide as etchants. By adjusting the concentration of the etchant, the etching degree can also be controlled, thereby regulating the value of the first preset depth. This first preset depth can be set according to the actual situation of the semiconductor structure and is not specifically limited here. Figure 8 As shown, the sidewall of the first portion of the active pillar 3 is etched to form a first pillar 31, such that the critical dimensions of the first pillar 31 are reduced compared to the critical dimensions of other portions of the active pillar 3, and then the first pillar 31 is cleaned. Figure 9 As shown, a second insulating layer 412 is formed on the surface of the first pillar 31, and the second insulating layer 412 and the first insulating layer 411 form a gate insulating layer 41. The second insulating layer 412 can be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The second insulating layer 412 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the first insulating layer 411 and the second insulating layer 412 are formed using the same deposition process, and the first insulating layer 411 and the second insulating layer 412 are made of the same material, which simplifies the process and makes the connection between the first insulating layer 411 and the second insulating layer 412 more stable.

[0065] Step S402: A word line layer 42 is formed around a portion of the side surface of the gate insulating layer 41. (e.g.) Figure 10As shown, word line metal layers 421 are filled between adjacent second insulating layers 412. These word line metal layers 421 can be filled using a deposition process, and the material of the word line metal layers 421 may include at least one of TiN, W, Al, Cu, and Au. Figure 11 As shown, the word line metal layer 421 is etched back to a second preset depth to form a word line layer 42. This word line layer 42 can serve as the gate electrode of the gate structure 4. The second preset depth can be set according to the desired gate electrode height, and no special limitation is made here.

[0066] Step S600: Form an isolation layer 6 between adjacent gate structures 4 and adjacent active pillars 3. The height of the isolation layer 6 is higher than the height of the top surface of the metal silicide layer 5.

[0067] Specifically, an isolation layer 6 is formed between two adjacent active pillars 3 that have a gate insulating layer 41 and a word line layer 42. For example... Figure 12 As shown, a second isolation layer 62 is formed between adjacent gate insulating layers 41 and on the word line layer 42, forming an isolation layer 6 with the first isolation layer 61. That is, the second isolation layer 62 fills the space between adjacent active pillars 3 where gate insulating layers 41 and word line layers 42 are formed, ensuring complete insulation between the adjacent active pillars 3. The second isolation layer 62 can be silicon nitride or silicon oxynitride. In some embodiments, the top surfaces of the first isolation layer 61 and the second isolation layer 62 are flush, so that the top surface of the isolation layer 6 formed by them is higher than the top surface of the active pillars 3, providing space for the subsequent formation of the connection layer 7. In some embodiments, the first isolation layer 61 and the second isolation layer 62 can be formed using the same process, such as at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition. The materials of the first isolation layer 61 and the second isolation layer 62 are the same, thus simplifying the process and improving the stability of the connection between the first isolation layer 61 and the second isolation layer 62.

[0068] In some embodiments, continue to refer to Figure 12 After the second isolation layer 62 is formed, the top surfaces of the second isolation layer 62, the first isolation layer 61, and the second insulating layer 412 can be made flush using a chemical mechanical polishing process, thereby making the top surface of the semiconductor structure in this step planar, which is beneficial for subsequent processing.

[0069] In some embodiments, such as Figure 13 As shown, the method further includes: removing the second insulating layer 412 from the top surface of the first pillar 31 to expose the top surface of the first pillar 31.

[0070] In some embodiments, such as Figure 13As shown, removing the second insulating layer 412 from the top surface of the first pillar 31 includes: etching back the second insulating layer 412, removing the second insulating layer 412 from the top surface of the first pillar 31, and etching back the second insulating layer 412 located on the side of the first pillar 31 to a third preset depth, so that the top surface of the gate insulating layer 41 is lower than the top surface of the first pillar 31 in the direction perpendicular to the substrate 1. That is, a groove G is formed on the periphery of the top of the active pillar 3. The depth of the groove G is the third preset depth. The third preset depth can be set according to the actual situation and is not specifically limited here. In subsequent processes, a first metal layer 51 will be formed on the active pillar 3. The setting of the groove G improves the stability of the first metal layer 5.

[0071] The third preset depth is 5 to 40 nm. Specifically, in addition to the two extreme values ​​of the above range, the value of the third preset depth can also be 25 nm, 30 nm, 35 nm, or 38 nm. The third preset depth varies in the range of 5 to 40 nm depending on the position. That is, each groove G does not have a uniform depth. Different positions of each groove G can have different depths. Those skilled in the art can choose according to actual needs, and no special limitation is made here.

[0072] In other embodiments, removing the second insulating layer 412 on the top surface of the first pillar 31 includes etching away only the second insulating layer 412 located on the top surface of the first pillar 31, without etching the second insulating layer 412 further downwards, i.e., without forming the groove G in the above embodiments. This simplifies the process and saves time.

[0073] Step S800: Form a metal silicide layer 5, located on the top surface of the active pillar 3, and the projection of the metal silicide layer 5 on the substrate 1 coincides with the projection of the top surface of the active pillar 3 on the substrate 1.

[0074] Specifically, in some embodiments, step S800 may include steps S801 to S803.

[0075] Step S801: As Figure 14 As shown, a first metal layer 51 is formed on the top surface of the active pillar 3. The first metal layer 51 can be formed on the top surface of the active pillar 3 using a deposition process, and the first metal layer can be at least one of Co, Ni, Pt, Ti, Ta, Mo and W. The deposition process can be physical vapor deposition.

[0076] Step S802: As Figure 14 and Figure 15 As shown, the active pillar 3 is heat-treated to form a metal silicide layer 5 on top of the active pillar 3. This heat treatment can be annealing, which causes the metal of the first metal layer 51 to react with the active pillar 3, resulting in the doping of a metal silicide, such as CoSi, on top of the active pillar 3. xNiSi x or TiSi x This leads to the formation of a metal silicide layer 5. Since the top of the active pillar 3 is a metal silicide, the resistance at the top of the active pillar 3 is reduced, thus reducing its contact resistance with the pad metal. The annealing temperature can be between 400℃ and 1000℃. Specifically, in addition to the two extremes of the above temperature range, the annealing temperature can also be 500℃, 600℃, 700℃, 800℃, or 900℃, or vary within the range of 400℃ to 1000℃; no special limitation is made here. Steps S801 and S802 are self-aligned silicide processes, which do not require photolithography patterning to form the metal silicide, simplifying the fabrication process.

[0077] Step S803: As Figure 15 As shown, the remaining first metal layer 51 is removed. Specifically, the remaining first metal layer 51 can be removed by an etching process. This etching process can be wet etching or dry etching, and those skilled in the art can choose according to the actual situation; no special limitation is made here.

[0078] In some embodiments, such as Figure 16 As shown, the method for fabricating the semiconductor structure disclosed herein further includes forming a connecting material layer 71 on the top surface of the metal silicide layer 5, the top surface of the gate structure 4, and the top surface of the isolation layer 6.

[0079] In some embodiments, such as Figure 16 As shown, in step 604, since a groove G is formed on the outer periphery of the top of the active column 3, and the bottom of the connecting material layer 71 is formed in the groove G, the stability of the connecting material layer 71 is increased.

[0080] In some embodiments, such as Figure 17 As shown, the method for fabricating a semiconductor structure according to an embodiment of this disclosure further includes: removing a portion of the connection material layer 71 to expose the isolation layer 6, and the remaining connection material layer 71 forming a connection layer 7, the top surface of which is flush with the top surface of the isolation layer 6.

[0081] Specifically, a portion of the bonding material layer 71 is removed using a chemical mechanical polishing process to form a bonding layer 7, making the top surface of the bonding layer 7 flush with the top surface of the isolation layer 6. This isolates the bonding layer 7 above adjacent active pillars 3 and flattens the surface of the semiconductor structure, which is beneficial for the arrangement of memory cells.

[0082] The projection of the interconnect layer 7 onto the substrate 1 overlaps the projection of the metal silicide layer 5 onto the substrate 1, ensuring sufficient contact between the interconnect layer 7 and the metal silicide layer 5. The interconnect layer 7 can be understood as a metal pad, electrically connected to the metal silicide layer 5, thereby achieving electrical connection between the active pillar 3 and the memory cell (not shown in the figure) located above the metal pad. The material of the interconnect layer 7 is at least one of TiN, W, Al, Cu, and Au. (Continue to the previous section) Figure 17 The bottom surface of the groove G is higher than the bottom surface of the metal silicide layer 5, which avoids partial contact between the connecting layer 7 and the active pillar 3, and enables it to fully contact the metal silicide layer 5, reducing the contact resistance. At the same time, it increases the contact area between the connecting layer 7 and the metal silicide layer 5, thereby improving the operating speed of the semiconductor structure.

[0083] In some embodiments, before step S400, step S300 may be included: forming bit lines 2, the bit lines 2 being located within the substrate 1 and spaced apart along the second direction F2. For example... Figure 1 As shown, the second direction F2 is not parallel to the first direction F1; for example, the second direction F2 is perpendicular to the first direction F1.

[0084] In some embodiments, forming bit line 2 may include steps S301 to S304.

[0085] Step S301: Form bit line 2 in substrate 1 between active pillars 3 along the second direction F2. Specifically, bit line 2 can be formed by doping impurity ions into substrate 1 between active pillars 3 along the second direction F2 using an ion implantation process, or by doping the aforementioned impurity ions into substrate 1 below the active pillars 3.

[0086] Step S302: Form a second metal layer on bit line 2. Specifically, a metal layer can be formed above bit line 2 using a deposition process, such as... Figure 4 As shown, a second metal layer is deposited on the surface of the region corresponding to the dashed ellipse. The second metal layer can be at least one of Co, Ni, Pt, Ti, Ta, Mo, and W, and the deposition process can be physical vapor deposition (PVD).

[0087] Step S303: The substrate 1 is heat-treated to form a bit line 2 doped with metal silicide. Specifically, this heat treatment may be annealing, which causes the metal of the second metal layer to react with the silicon of the bit line 2 to form a bit line 2 doped with metal silicide, wherein the metal silicide is located at... Figure 4 Within the metal silicide region 21 shown. Because the bit line 2 contains metal silicides, such as CoSi... x NiSi x or TiSi xTherefore, the resistance of bit line 2 decreases. The annealing temperature can be between 400℃ and 1000℃. Specifically, in addition to the two extremes of the above temperature range, the annealing temperature can also be 500℃, 600℃, 700℃, 800℃, or 900℃, or the annealing temperature can vary within the range of 400℃ to 1000℃; no special limitation is made here. Steps S402 and S403 are self-aligned silicide processes, which do not require photolithography patterning to form metal silicides, simplifying the fabrication process.

[0088] Step S304: Remove the remaining second metal layer. Specifically, the remaining second metal layer can be removed by an etching process. This etching process can be wet etching or dry etching, and those skilled in the art can choose according to the actual situation; no special limitation is made here.

[0089] In some embodiments, the metal silicide in bit line 2 has the same metal element as the metal silicide layer 5, which simplifies the process and saves energy.

[0090] In summary, the semiconductor structure fabrication method in this embodiment forms a metal silicide layer 5 on the top surface of the active pillar 3, thereby reducing the contact resistance between the active pillar 3 and the metal pad, lowering energy consumption, and improving the operating speed of the semiconductor structure.

[0091] According to another aspect of this disclosure, a semiconductor device is provided, including the semiconductor structure and memory cell described in any of the above embodiments, wherein the memory cell is electrically connected to the semiconductor structure via a connection layer 7. The semiconductor structure and the connection layer 7 are the same as in the above embodiments, and will not be described again here.

[0092] The semiconductor device of this disclosure has a metal silicide layer 5 on the active pillar 3 in the semiconductor structure, which has a small contact resistance, thereby improving the operating speed of the semiconductor device and reducing energy consumption.

[0093] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to utilize this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided having an array of active pillars extending in a direction perpendicular to the substrate; A gate structure is formed on the substrate, arranged at intervals along a first direction, and surrounding a portion of the active pillar; An isolation layer is formed between adjacent gate structures and adjacent active pillars, the height of the isolation layer being greater than the height of the top surface of the active pillars; A metal silicide layer is formed on the top surface of the active pillar, and the projection of the metal silicide layer on the substrate coincides with the projection of the top surface of the active pillar on the substrate. Forming the gate structure includes: A gate insulating layer is formed on the surface of the active post; A word line layer is formed around a portion of the sidewall of the gate insulating layer; Forming a gate insulating layer on the surface of the active post includes: A first insulating layer is formed on the surface of the active post; A first insulating layer is filled between the first insulating layers; The first insulating layer is etched back to a first preset depth, exposing the first portion of the active pillar; The sidewalls of the first portion are etched to form the first column; A second insulating layer is formed on the surface of the first column, and the second insulating layer and the first insulating layer form the gate insulating layer.

2. The method according to claim 1, characterized in that, The word line layer is formed around a portion of the sidewall of the gate insulating layer, including: A word line metal layer is filled between adjacent second insulating layers; The word line metal layer is etched back to a second preset depth to form a word line layer.

3. The method according to claim 2, characterized in that, The formation of the isolation layer includes: A second isolation layer is formed between adjacent gate insulating layers and on the word line layer; the first isolation layer and the second isolation layer form the isolation layer.

4. The method according to claim 3, characterized in that, After the second insulating layer is formed, the top surfaces of the first insulating layer, the second insulating layer, and the second insulating layer are made flush using a chemical mechanical polishing process.

5. The method according to claim 4, characterized in that, Also includes: Remove the second insulating layer from the top surface of the first column to expose the top surface of the first column.

6. The method according to claim 5, characterized in that, Removing the second insulating layer from the top surface of the first column includes: The second insulating layer is etched back to remove the second insulating layer on the top surface of the first pillar, and the second insulating layer located on the side surface of the first pillar is etched back to a third preset depth.

7. The method according to claim 6, characterized in that, The third preset depth is 5-40 nm.

8. The method according to any one of claims 1 to 7, characterized in that, The formation of the metal silicide layer includes: A first metal layer is formed on the top surface of the active column; The active pillar is heat-treated to form a metal silicide layer on the top of the active pillar; Remove the remaining first metal layer.

9. The method according to claim 1, characterized in that, Also includes: A connecting material layer is formed on the top surface of the metal silicide layer, the top surface of the gate structure, and the top surface of the isolation layer; A portion of the connecting material layer is removed to expose the isolation layer, and the remaining connecting material layer forms a connecting layer, with the top surface of the connecting layer flush with the top surface of the isolation layer.

10. A semiconductor structure, said semiconductor structure being prepared by the method according to any one of claims 1-9, characterized in that, include: Substrate; Active pillars are located on the substrate and arranged in an array, and the active pillars extend in a direction perpendicular to the substrate; A gate structure is located on the substrate, arranged at intervals along a first direction, and surrounds a portion of the active pillar; A metal silicide layer is located on the top surface of the active pillar, and the projection of the metal silicide layer on the substrate coincides with the projection of the top surface of the active pillar on the substrate. An isolation layer is located between adjacent gate structures and adjacent active pillars, and the height of the isolation layer is higher than the height of the top surface of the metal silicide layer.

11. The semiconductor structure according to claim 10, characterized in that, The metal element in the metal silicide layer includes at least one of Co, Ni, Pt, Ti, Ta, Mo, and W.

12. The semiconductor structure according to claim 10, characterized in that, The gate structure includes: A gate insulating layer is provided around the side of the active pillar, and in a direction perpendicular to the substrate, the top surface of the gate insulating layer is lower than the top surface of the metal silicide layer; A word line layer, surrounding a portion of the side of the gate insulating layer.

13. The semiconductor structure according to claim 12, characterized in that, The distance between the top surface of the gate insulating layer and the top surface of the metal silicide layer is 5–40 nm.

14. The semiconductor structure according to claim 10, characterized in that, Also includes: A bonding layer is located on the metal silicide layer, and the projection of the bonding layer on the substrate covers the projection of the metal silicide layer on the substrate.

15. The semiconductor structure according to claim 14, characterized in that, The isolation layer extends in a direction perpendicular to the substrate, and the top surface of the isolation layer is flush with the top surface of the connecting layer.

16. A semiconductor device, characterized in that, include: The semiconductor structure as described in any one of claims 10 to 15; The storage cell is electrically connected to the semiconductor structure via a connection layer.

Images