A piecewise linear reference voltage generation circuit and a reference voltage output control method

Abstract

This invention belongs to the field of switching power supply technology and discloses a segmented linear reference voltage generation circuit and a reference voltage output control method. The segmented linear reference voltage generation circuit includes a first linear voltage generation circuit and a second linear voltage generation circuit, both connected to a current detection signal input terminal and a reference voltage input terminal, respectively. The other end of the first linear voltage generation circuit is sequentially connected to a first upper limit limiting circuit and a first lower limit limiting circuit. The other end of the second linear voltage generation circuit is sequentially connected to a second upper limit limiting circuit and a second lower limit limiting circuit, with the first lower limit limiting circuit connected to the second upper limit limiting circuit. This invention uses an operational amplifier circuit, combined with a limiting circuit composed of an operational amplifier and diodes, to achieve a segmented linear reference voltage output based on the output current detection value. This circuit is a fully analog circuit, which can be easily applied to analog control switching power supply converters, offering good real-time performance, high reliability, and low cost.

Description

Technical Field

[0001] This invention belongs to the field of switching power supply conversion technology, and particularly relates to a segmented linear reference voltage generation circuit and a reference voltage output control method. Background Technology

[0002] In the design and application of high-power switching power supply converters, it is often necessary for the power supply to have output power limiting functionality under output overload conditions, while power control also needs to meet the power supply requirements of certain special loads. For example, the 28V main power supply used in the power distribution system of modern multi-electric / all-electric aircraft is implemented using a 270V to 28V DC switching power supply converter to power the aircraft starter generator. When starting the engine, the starter motor requires a large starting current from the power supply, but the voltage can be lower than the normal output voltage of the power supply. As the motor starts, the speed gradually increases, the motor supply current gradually decreases, and the supply voltage gradually increases. This motor power supply characteristic exhibits a piecewise linear relationship, requiring the 28V power supply to typically be able to quickly adjust the output voltage according to the load current. While meeting the motor starting requirements, it is necessary to limit the maximum output power of the power supply to prevent the 28V power supply from operating at overpower, thereby improving reliability. A motor starting voltage-current relationship curve is shown below. Figure 3 As shown.

[0003] Figure 3 The corresponding voltage-current relationship is:

[0004]

[0005] The curve contains three plateaus and two linear regions, with different slopes and biases in the linear regions.

[0006] For DC-DC switching power converters, achieving this output characteristic typically involves closed-loop output voltage control. This requires a dedicated reference voltage generation module for the voltage loop. This module generates a piecewise linear reference voltage based on the real-time acquired output current value, following a piecewise linear output voltage-current curve. This reference voltage serves as the base voltage for the voltage control loop, ensuring the output voltage meets the final output voltage-current relationship curve. For digitally controlled switching power converters, this can be implemented in software using AD and DA converters. However, for analog-controlled switching power converters, it is difficult to implement using DA converters.

[0007] Based on the above analysis, the problems and defects of the existing technology are as follows: If the existing reference voltage generation module is to achieve piecewise linear reference voltage output, it needs to use a microprocessor and DA chip in combination with software programming, which is costly and cannot be applied to fully analog control switching power converter applications. Summary of the Invention

[0008] To overcome the problems existing in related technologies, the present invention provides a piecewise linear reference voltage generating circuit and a reference voltage output control method.

[0009] The technical solution of the present invention is as follows: A segmented linear reference voltage generating circuit is provided, comprising a first linear voltage generating circuit and a second linear voltage generating circuit. The first linear voltage generating circuit and the second linear voltage generating circuit are respectively connected to a current detection signal input terminal and a reference voltage input terminal. The other end of the first linear voltage generating circuit is sequentially connected to a first upper limit limiting circuit and a first lower limit limiting circuit. The other end of the second linear voltage generating circuit is sequentially connected to a second upper limit limiting circuit and a second lower limit limiting circuit. The first lower limit limiting circuit is connected to the second upper limit limiting circuit.

[0010] The reference voltage input terminal is also connected to a multi-channel reference voltage generating circuit. The multi-channel reference voltage generating circuit has a first reference voltage output terminal, a second reference voltage output terminal, and a third reference voltage output terminal. The first reference voltage output terminal, the second reference voltage output terminal, and the third reference voltage output terminal are respectively connected to a first upper limit limiting circuit, a first lower limit limiting circuit, and a second lower limit limiting circuit.

[0011] Furthermore, the first linear voltage generating circuit includes: an operational amplifier U2A, a capacitor C2, a resistor R2, a resistor R4, a resistor R8, and a resistor R10;

[0012] The reference voltage input terminal is connected to the non-inverting input of pin 3 of operational amplifier U2A via resistor R4. One end of resistor R2 is connected to the non-inverting input of pin 3 of operational amplifier U2A, and the other end is grounded. The current detection signal input terminal is connected to the inverting input of pin 2 of U2A via resistor R8. Resistor R10 is connected between pins 1 and 2 of operational amplifier U2A. Capacitor C2 is connected between pins 4 and 8 of operational amplifier U2A.

[0013] Furthermore, the second linear voltage generating circuit includes: operational amplifier U2B, resistor R12, resistor R13, resistor R15 and resistor R18;

[0014] The reference voltage input terminal is connected to the non-inverting input of pin 5 of operational amplifier U2B via resistor R13. One end of resistor R12 is connected to the non-inverting input of pin 5 of operational amplifier U2B, and the other end is grounded. The current detection signal input terminal is connected to the inverting input of pin 6 of operational amplifier U2B via resistor R15. Resistor R18 is connected between pins 6 and 7 of operational amplifier U2B.

[0015] Furthermore, the first upper limit limiting circuit includes: operational amplifier U1A, capacitor C1, resistor R1, resistor R6, and diode D2;

[0016] The output voltage of pin 1 of the operational amplifier U2A is connected to the inverting input of pin 2 of the operational amplifier U1A through resistor R6. The first reference voltage output is connected to the non-inverting input of pin 3 of the operational amplifier U1A through resistor R1. The inverting input of pin 2 of the operational amplifier U1A is connected to the output of pin 1 of the operational amplifier U1A through diode D2. Pin 2 of the operational amplifier U1A is connected to the anode of diode D2. Capacitor C1 is connected between pins 4 and 8 of the operational amplifier U1A.

[0017] Furthermore, the first lower limit limiting circuit includes: operational amplifier U1B, resistor R3, resistor R5, and diode D1;

[0018] Pin 2 of the operational amplifier U1A and the anode of diode D2 are connected to the inverting input of pin 6 of the operational amplifier U1B through resistor R5. The output terminal of the second reference voltage is connected to the non-inverting input of pin 5 of the operational amplifier U1B through resistor R3. Pin 7 of the operational amplifier U1B is connected to the inverting input pin 6 through diode D1. Pin 6 of the operational amplifier U1B is connected to the cathode of diode D1.

[0019] Furthermore, the second upper limit limiting circuit includes: operational amplifier U3A, capacitor C3, resistor R16, resistor R19, and diode D3;

[0020] The non-inverting input (pin 3) of operational amplifier U3A is connected to the inverting input (pin 6) of operational amplifier U1B and the cathode of diode D1 via resistor R16. The inverting input (pin 2) of operational amplifier U3A is connected to the output (pin 7) of operational amplifier U2B via resistor R19. The inverting input (pin 2) of operational amplifier U3A is connected to the output (pin 1) via diode D3. Pin 2 of operational amplifier U3A is connected to the anode of diode D3. Capacitor C3 is connected between pins 4 and 8 of operational amplifier U3A.

[0021] Furthermore, the second lower limit limiting circuit includes: operational amplifier U3B, resistor R17, resistor R20 and diode D4, wherein the non-inverting input of pin 5 of operational amplifier U3B is connected to the output terminal of the third reference voltage through resistor R20;

[0022] Pin 2 of the operational amplifier U3A and the anode of diode D3 are connected to the inverting input of pin 6 of the operational amplifier U3B through resistor R17. Pin 7 of the operational amplifier U3B is connected to the inverting input pin 6 through diode D4. The inverting input pin 6 of the operational amplifier U3B is connected to the cathode of diode D4 to form the final output reference voltage.

[0023] Furthermore, the multi-channel reference voltage generating circuit includes: resistors R7, R9, R11, and R14, which are connected in series between the reference voltage and the reference ground.

[0024] The first reference voltage is output by a voltage divider consisting of resistors R7, R9, R11, and R14 connected in series; the second reference voltage is output by a voltage divider consisting of resistors R7, R9, R11, and R14 connected in series; and the third reference voltage is output by a voltage divider consisting of resistors R7, R9, R11, and R14 connected in series.

[0025] Another objective of this invention is to provide a reference voltage output control method, comprising: employing multiple linear voltage generating circuits, combined with a limiting circuit composed of operational amplifiers and diodes, to perform segmented linear reference voltage output control based on the output current detection value, specifically including:

[0026] The current detection signal Ioss and the reference voltage Vref are input to the first linear voltage generating circuit and the second linear voltage generating circuit, respectively. The first linear voltage generating circuit generates a linear reference voltage under low overload current. The output of the first linear voltage generating circuit is connected to the input of the first upper limit limiting circuit, and the other input of the first upper limit limiting circuit is connected to the first reference voltage Vref1 to realize the plateau voltage in the initial current stage. The output of the first upper limit limiting circuit is connected to the input of the first lower limit limiting circuit, and the other input of the first lower limit limiting circuit is connected to the second reference voltage Vref2 to generate the plateau voltage after the first segment of linear voltage. The second linear voltage generating circuit generates a linear reference voltage under high overload current. The output of the second linear voltage generating circuit is connected to the input of the second upper limit limiting circuit, and the other input of the second upper limit limiting circuit is connected to the output of the first lower limit limiting circuit. The output of the second upper limit limiting circuit is connected to the input of the second lower limit limiting circuit, and the other input of the second lower limit limiting circuit is connected to the third reference voltage Vref3 to generate the final plateau voltage. The input of the multi-reference voltage generating circuit is connected to Vref, converting it into three reference voltage outputs.

[0027] Furthermore, the upper limit limiting circuit output voltage regulation method of the first upper limit limiting circuit includes: the output voltage of pin 1 of operational amplifier U2A is connected to the inverting input of pin 2 of operational amplifier U1A through resistor R6; the first reference voltage Vref1 is connected to the non-inverting input of pin 3 of operational amplifier U1A through resistor R1; when the output voltage of pin 1 of operational amplifier U2A is higher than the first reference voltage Vref1, the output voltage of pin 1 of operational amplifier U1A is low, diode D2 is turned on, and the inverting input of pin 2 of U1A is connected to the non-inverting input of pin 3 of operational amplifier U1A through diode D2. When pin 1 is turned on, negative feedback is formed, and the voltage at pin 2 of operational amplifier U1A and the anode voltage of diode D2 are clamped to the first reference voltage Vref1. Conversely, when the output voltage at pin 1 of operational amplifier U2A is lower than the first reference voltage Vref1, the output voltage at pin 1 of operational amplifier U1A is at a saturation high level, close to the operational amplifier supply voltage. Diode D2 is turned off, and the voltage at pin 2 of operational amplifier U1A and the anode voltage of diode D2 are equal to the output voltage at pin 1 of operational amplifier U2A, thus achieving the upper limit limiting function.

[0028] Furthermore, the output voltage regulation method of the first lower limit limiting circuit includes: pin 2 of operational amplifier U1A and the anode of diode D2 are connected to the inverting input of pin 6 of operational amplifier U1B through resistor R5; the second reference voltage Vref2 is connected to the non-inverting input of pin 5 of operational amplifier U1B through resistor R3; when the anode voltage of diode D2 is greater than the voltage of the second reference voltage Vref2, the output of pin 7 of operational amplifier U1B is saturated low level, close to ground potential, diode D1 is cut off, and the voltage of the cathode of diode D1 and the voltage of pin 6 of operational amplifier U1B are equal to the anode voltage of diode D2; when diode D... When the anode voltage is less than the second reference voltage Vref2, the output of pin 7 of operational amplifier U1B is high, diode D1 is turned on, and pin 7 of operational amplifier U1B is connected to pin 6 of the inverting input through diode D1 to form negative feedback. The voltage of the cathode of diode D1 and the voltage of pin 6 of operational amplifier U1B are clamped to the second reference voltage Vref2. At this time, the voltage of the cathode of diode D1 and the voltage of pin 2 of operational amplifier U1A is equal to the output voltage of pin 1 of operational amplifier U2A. The lower limit of the linear voltage output of pin 1 of operational amplifier U2A is clamped to the second reference voltage Vref2, realizing the lower limit limiting function.

[0029] The second upper limit limiting circuit constructed by operational amplifier U3A is consistent with the upper limit limiting circuit output voltage regulation process of the first upper limit limiting circuit constructed by operational amplifier U1A. The non-inverting input of operational amplifier U3A is connected to the output terminal of the first lower limit limiting circuit constructed by U1B through resistor R16. The upper limit value of the linear voltage output at pin 7 of operational amplifier U2B is clamped to the cathode of diode D1 and the voltage value at pin 6 of operational amplifier U1B.

[0030] The second lower limit limiting circuit constructed by operational amplifier U3B is consistent with the output voltage regulation process of the first lower limit limiting circuit constructed by operational amplifier U1B. In this circuit, the non-inverting input of operational amplifier U3B is connected to the third reference voltage Vref3 through resistor R20, clamping the lower limit value of the linear voltage output from pin 7 of operational amplifier U2B to the voltage value of the third reference voltage Vref3.

[0031] Combining all the above technical solutions, the advantages and positive effects of this invention are as follows: The piecewise linear reference voltage generating circuit involved in this invention employs an operational amplifier circuit, combined with a limiting circuit composed of an operational amplifier and diodes, to achieve a piecewise linear reference voltage output based on the output current detection value. This circuit is implemented using a fully analog circuit, with all components being general-purpose analog devices, including general-purpose operational amplifiers, diodes, resistors, and capacitors. It eliminates the need for expensive microprocessors and DA chips, and requires no software design, effectively reducing costs and improving reliability. Simultaneously, it exhibits good real-time performance, solving the application challenges of fully analog control switching power supplies.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the disclosure of the present invention. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0034] Figure 1 This is a block diagram of the segmented linear reference voltage generating circuit provided in an embodiment of the present invention;

[0035] Figure 2 This is a circuit diagram of the segmented linear reference voltage generating circuit provided in an embodiment of the present invention;

[0036] Figure 3 This is a graph showing the relationship between the starting voltage and current of a motor in the prior art;

[0037] In the diagram: 1. First linear voltage generating circuit; 2. Second linear voltage generating circuit; 3. First upper limit limiting circuit; 4. First lower limit limiting circuit; 5. Second upper limit limiting circuit; 6. Second lower limit limiting circuit; 7. Multi-channel reference voltage generating circuit. Detailed Implementation

[0038] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0039] The innovation of the segmented linear reference voltage generating circuit provided in this embodiment of the invention lies in the use of multiple linear voltage generating circuits (operational amplifier circuits) combined with a limiting circuit composed of an operational amplifier and diodes to achieve segmented linear reference voltage output based on the output current detection value.

[0040] Example 1, such as Figure 1 As shown, the segmented linear reference voltage generating circuit provided in this embodiment of the invention includes a first linear voltage generating circuit 1, a second linear voltage generating circuit 2, a first upper limit limiting circuit 3, a first lower limit limiting circuit 4, a second upper limit limiting circuit 5, a second lower limit limiting circuit 6, and a multi-channel reference voltage generating circuit 7.

[0041] The structure and parameters of the first upper limit limiting circuit 3 and the second upper limit limiting circuit 5 are completely identical, and the structure and parameters of the first lower limit limiting circuit 4 and the second lower limit limiting circuit 6 are completely identical.

[0042] The first linear voltage generating circuit 1 and the second linear voltage generating circuit 2 are respectively connected to the current detection signal input terminal and the reference voltage input terminal. The other end of the first linear voltage generating circuit 1 is connected to the first upper limit limiting circuit 3 and the first lower limit limiting circuit 4 in sequence. The other end of the second linear voltage generating circuit 2 is connected to the second upper limit limiting circuit 5 and the second lower limit limiting circuit 6 in sequence. The first lower limit limiting circuit 4 is connected to the second upper limit limiting circuit 5.

[0043] The reference voltage input terminal is also connected to a multi-channel reference voltage generating circuit 7. The multi-channel reference voltage generating circuit 7 has a first reference voltage output terminal, a second reference voltage output terminal, and a third reference voltage output terminal. The first reference voltage output terminal, the second reference voltage output terminal, and the third reference voltage output terminal are respectively connected to a first upper limit limiting circuit 3, a first lower limit limiting circuit 4, and a second lower limit limiting circuit 6.

[0044] like Figure 2As shown, the first linear voltage generating circuit 1 is an inverting linear amplifier composed of operational amplifier U2A and resistors R2, R4, R8, and R10. The reference voltage "Vref" is divided by resistors R2 and R4 and then connected to the non-inverting input (pin 3) of operational amplifier U2A. The current detection signal "Ioss" is connected to the inverting input (pin 2) of operational amplifier U2A via resistor R8. The negative feedback resistor R10 is connected between pins 1 and 2 of operational amplifier U2A. The output voltage at pin 1 of operational amplifier U2A has a negative slope linear relationship with the input current detection signal "Ioss". The slope is set by the ratio of resistors R10 and R8. The bias is determined by the voltage divider network of "Vref" and resistors R2 and R4, thus realizing the function of the first linear voltage generating circuit 1, i.e., generating... Figure 3 The circuit shows a linear reference voltage with a current range of 200A~350A. The second linear voltage generating circuit 2, consisting of operational amplifier U2B and resistors R12, R13, R15, and R18, shares the same design principle as the first linear voltage generating circuit 1. By selecting different ratios of resistors R18, R15, R12, and R13, different slopes and biases can be set to generate... Figure 3 The linear reference voltage is shown for the current range of 400A to 800A.

[0045] In summary, the first linear voltage generating circuit 1, the first upper limit limiting circuit 3, and the first lower limit limiting circuit 4 together achieve... Figure 3 The reference voltage curve for the current range of 0A to 400A shown is output through the cathode of diode D1 and pin 6 of operational amplifier U1B.

[0046] Example 2: This invention provides a method for regulating the output of a segmented linear reference voltage generator circuit, comprising: using multiple linear voltage generator circuits, combined with a limiting circuit composed of an operational amplifier and diodes, to perform segmented linear reference voltage output regulation based on the output current detection value, specifically including:

[0047] The current detection signal "Ioss" and the reference voltage "Vref" are input to the first linear voltage generating circuit 1 and the second linear voltage generating circuit 2, respectively; the first linear voltage generating circuit 1 is used to generate a linear reference voltage under low overload current (see...). Figure 3 (See the voltage curve for the 200A~350A current range); the output of the first linear voltage generating circuit 1 is connected to the input of the first upper limit limiting circuit 3, and the other input of the first upper limit limiting circuit 3 is connected to the first reference voltage "Vref1" to achieve the plateau voltage during the initial current stage (see...). Figure 3The voltage curve for the 0A~200A current range is shown in the image. The output of the first upper limit limiting circuit 3 is connected to the input of the first lower limit limiting circuit 4. The other input of the first lower limit limiting circuit 4 is connected to the second reference voltage "Vref2" to generate the plateau voltage after the first linear voltage segment (see [reference]). Figure 3 The voltage curve for the 350A~400A current range is shown in the figure; the second linear voltage generating circuit 2 is used to generate a linear reference voltage under high overload current (see [reference]). Figure 3 The voltage curve for the 400A~800A current range is shown in the diagram. The output of the second linear voltage generating circuit 2 is connected to the input of the second upper limit limiting circuit 5. The other input of the second upper limit limiting circuit 5 is connected to the output of the first lower limit limiting circuit 4, ensuring that the reference voltage curve below 400A is determined by the first linear voltage generating circuit 1, the first upper limit limiting circuit 3, and the first lower limit limiting circuit 4, while the reference voltage curve above 400A is determined by the second linear voltage generating circuit 2 and the second lower limit limiting circuit 6. The output of the second upper limit limiting circuit 5 is connected to the input of the second lower limit limiting circuit 6. The other input of the second lower limit limiting circuit 6 is connected to the third reference voltage "Vref3" to generate the final plateau voltage (see [reference]). Figure 3 The voltage curve for the 800A~1000A current range is shown in the figure. The input terminal of the multi-channel reference voltage generator circuit 7 is connected to "Vref" and converted into three reference voltage outputs, namely "Vref1", "Vref2" and "Vref3".

[0048] In this embodiment of the invention, the upper limit limiting circuit output voltage regulation method of the first upper limit limiting circuit 3 includes: the output voltage of pin 1 of operational amplifier U2A is connected to the inverting input of pin 2 of operational amplifier U1A through resistor R6; the first reference voltage "Vref1" is connected to the non-inverting input of pin 3 of operational amplifier U1A through resistor R1; when the output voltage of pin 1 of operational amplifier U2A is higher than the first reference voltage "Vref1", the output voltage of pin 1 of operational amplifier U1A is low, diode D2 is turned on, and the inverting input of pin 2 of U1A is connected to the output of pin 1 through diode D2, forming negative feedback; operational amplifier U1... The voltage at pin 2 of operational amplifier U1A and the anode voltage of diode D2 are clamped to the first reference voltage "Vref1". Conversely, when the output voltage at pin 1 of operational amplifier U2A is lower than the first reference voltage "Vref1", the output voltage at pin 1 of operational amplifier U1A is at a saturation high level, close to the operational amplifier's supply voltage. Diode D2 is cut off, and the voltage at pin 2 of operational amplifier U1A and the anode voltage of diode D2 are equal to the output voltage at pin 1 of operational amplifier U2A. This achieves the upper limit limiting function. Pin 2 of operational amplifier U1A and the anode of diode D2 are the output terminals of the upper limit limiting circuit. This circuit ensures that the current detection value is within the upper limit limiting range. Figure 3The output voltage of the upper limit limiting circuit is limited to an upper limit value, namely the first reference voltage "Vref1", within the range of 0~200A.

[0049] In this embodiment of the invention, the method for regulating the output voltage of the lower limit limiting circuit 4 of the first lower limit limiting circuit includes: pin 2 of operational amplifier U1A and the anode of diode D2 are connected to the inverting input of pin 6 of operational amplifier U1B through resistor R5; the second reference voltage "Vref2" is connected to the non-inverting input of pin 5 of operational amplifier U1B through resistor R3; when the anode voltage of diode D2 is greater than the voltage of the second reference voltage "Vref2", pin 7 of operational amplifier U1B outputs a saturated low level, close to ground potential, diode D1 is cut off, and the voltage of the cathode of diode D1 and the voltage of pin 6 of operational amplifier U1B are equal to the anode voltage of diode D2; when the anode voltage of diode D2 is less than the voltage of the second reference voltage "Vref2", the output voltage of operational amplifier U1B is lower than the voltage of the second reference voltage "Vref2". When the voltage is "ef2", pin 7 of operational amplifier U1B outputs a high level, diode D1 conducts, and pin 7 of operational amplifier U1B is connected to pin 6 of the inverting input through diode D1 to form negative feedback. The voltage of the cathode of diode D1 and pin 6 of operational amplifier U1B is clamped to the second reference voltage "Vref2". Since the voltage of the cathode of diode D1 and pin 2 of operational amplifier U1A is equal to the output voltage of pin 1 of operational amplifier U2A at this time, the lower limit of the linear voltage output of pin 1 of operational amplifier U2A is clamped to the second reference voltage "Vref2", thus realizing the lower limit limiting function. The cathode of diode D1 and pin 6 of operational amplifier U1B are the output terminals of the lower limit limiting circuit.

[0050] In this embodiment of the invention, the working principles (output voltage regulation of the upper limit limiting circuit 5 constructed by operational amplifier U3A and output voltage regulation of the lower limit limiting circuit 6 constructed by operational amplifier U3B) are completely the same as those of the first upper limit limiting circuit 3 constructed by operational amplifier U1A and the first lower limit limiting circuit 4 constructed by operational amplifier U1B, except that the reference voltage input at their non-inverting terminals is different, which is used to generate different limiting voltage values; wherein the non-inverting terminal of operational amplifier U3A is connected to the output terminal of the first lower limit limiting circuit 4 constructed by U1B through resistor R16, so that the upper limit value of the linear voltage output at pin 7 of operational amplifier U2B is clamped to the cathode of diode D1 and the voltage value at pin 6 of operational amplifier U1B, that is Figure 3 The reference voltage curve value corresponding to the current range below 400A; the non-inverting input of operational amplifier U3B is connected to the third reference voltage "Vref3" through resistor R20, clamping the lower limit of the linear voltage output from pin 7 of operational amplifier U2B to the voltage value of the third reference voltage "Vref3".

[0051] Thus, by using three combined operational amplifiers U1, U2, and U3, along with corresponding resistors and diodes, to construct a linear amplifier circuit and a limiting circuit, a complete piecewise linear reference voltage curve can be achieved. The input reference sources of each limiting circuit are connected to the non-inverting input of the operational amplifiers via resistors, resulting in very high input impedance. Therefore, the reference voltages "Vref1", "Vref2", and "Vref3" can be achieved through simple voltage division using resistors, such as... Figure 2 The resistor voltage divider network consists of resistors R7, R9, R11, and R14.

[0052] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features, and such modifications or substitutions should be covered within the protection scope of the present invention.

Claims

1. A piecewise linear reference voltage generating circuit, comprising a first linear voltage generating circuit (1) and a second linear voltage generating circuit (2); characterized in that, The first linear voltage generating circuit (1) and the second linear voltage generating circuit (2) are respectively connected to the current detection signal input terminal and the reference voltage input terminal. The other end of the first linear voltage generating circuit (1) is connected to the first upper limit limiting circuit (3) and the first lower limit limiting circuit (4) in sequence. The other end of the second linear voltage generating circuit (2) is connected to the second upper limit limiting circuit (5) and the second lower limit limiting circuit (6) in sequence. The first lower limit limiting circuit (4) is connected to the second upper limit limiting circuit (5). The reference voltage input terminal is also connected to a multi-channel reference voltage generating circuit (7). The multi-channel reference voltage generating circuit (7) has a first reference voltage output terminal, a second reference voltage output terminal and a third reference voltage output terminal. The first reference voltage output terminal, the second reference voltage output terminal and the third reference voltage output terminal are respectively connected to the first upper limit limiting circuit (3), the first lower limit limiting circuit (4) and the second lower limit limiting circuit (6).

2. The piecewise linear reference voltage generating circuit according to claim 1, characterized in that, The first linear voltage generating circuit (1) includes: operational amplifier U2A, capacitor C2, resistor R2, resistor R4, resistor R8 and resistor R10; The reference voltage input terminal is connected to the non-inverting input of pin 3 of operational amplifier U2A via resistor R4. One end of resistor R2 is connected to the non-inverting input of pin 3 of operational amplifier U2A, and the other end is grounded. The current detection signal input terminal is connected to the inverting input of pin 2 of U2A via resistor R8. Resistor R10 is connected between pins 1 and 2 of operational amplifier U2A. Capacitor C2 is connected between pins 4 and 8 of operational amplifier U2A. The second linear voltage generating circuit (2) includes: operational amplifier U2B, resistor R12, resistor R13, resistor R15 and resistor R18; The reference voltage input terminal is connected to the non-inverting input of pin 5 of operational amplifier U2B via resistor R13. One end of resistor R12 is connected to the non-inverting input of pin 5 of operational amplifier U2B, and the other end is grounded. The current detection signal input terminal is connected to the inverting input of pin 6 of operational amplifier U2B via resistor R15. Resistor R18 is connected between pins 6 and 7 of operational amplifier U2B.

3. The piecewise linear reference voltage generating circuit according to claim 2, characterized in that, The first upper limit limiting circuit (3) includes: operational amplifier U1A, capacitor C1, resistor R1, resistor R6 and diode D2; The output voltage of pin 1 of the operational amplifier U2A is connected to the inverting input of pin 2 of the operational amplifier U1A through resistor R6. The first reference voltage output is connected to the non-inverting input of pin 3 of the operational amplifier U1A through resistor R1. The inverting input of pin 2 of the operational amplifier U1A is connected to the output of pin 1 of the operational amplifier U1A through diode D2. Pin 2 of the operational amplifier U1A is connected to the anode of diode D2. Capacitor C1 is connected between pins 4 and 8 of the operational amplifier U1A.

4. The piecewise linear reference voltage generating circuit according to claim 3, characterized in that, The first lower limit limiting circuit (4) includes: operational amplifier U1B, resistor R3, resistor R5 and diode D1; Pin 2 of the operational amplifier U1A and the anode of diode D2 are connected to the inverting input of pin 6 of the operational amplifier U1B through resistor R5. The output terminal of the second reference voltage is connected to the non-inverting input of pin 5 of the operational amplifier U1B through resistor R3. Pin 7 of the operational amplifier U1B is connected to the inverting input pin 6 through diode D1. Pin 6 of the operational amplifier U1B is connected to the cathode of diode D1.

5. The piecewise linear reference voltage generating circuit according to claim 4, characterized in that, The second upper limit limiting circuit (5) includes: operational amplifier U3A, capacitor C3, resistor R16, resistor R19 and diode D3; The non-inverting input (pin 3) of operational amplifier U3A is connected to the inverting input (pin 6) of operational amplifier U1B and the cathode of diode D1 via resistor R16. The inverting input (pin 2) of operational amplifier U3A is connected to the output (pin 7) of operational amplifier U2B via resistor R19. The inverting input (pin 2) of operational amplifier U3A is connected to the output (pin 1) via diode D3. Pin 2 of operational amplifier U3A is connected to the anode of diode D3. Capacitor C3 is connected between pins 4 and 8 of operational amplifier U3A.

6. The piecewise linear reference voltage generating circuit according to claim 5, characterized in that, The second lower limit limiting circuit (6) includes: operational amplifier U3B, resistor R17, resistor R20 and diode D4. The non-inverting input of pin 5 of the operational amplifier U3B is connected to the output terminal of the third reference voltage through resistor R20. Pin 2 of the operational amplifier U3A and the anode of diode D3 are connected to the inverting input of pin 6 of the operational amplifier U3B through resistor R17. Pin 7 of the operational amplifier U3B is connected to the inverting input pin 6 through diode D4. The inverting input pin 6 of the operational amplifier U3B is connected to the cathode of diode D4 to form the final output reference voltage.

7. The piecewise linear reference voltage generating circuit according to claim 1, characterized in that, The multi-channel reference voltage generating circuit (7) includes: resistors R7, R9, R11, and R14, which are connected in series between the reference voltage and the reference ground. The first reference voltage is output by a voltage divider consisting of resistors R7, R9, R11, and R14 connected in series; the second reference voltage is output by a voltage divider consisting of resistors R7, R9, R11, and R14 connected in series; and the third reference voltage is output by a voltage divider consisting of resistors R7, R9, R11, and R14 connected in series.

8. A method for regulating the output of a reference voltage, characterized in that, The reference voltage output control method is used to control the segmented linear reference voltage generating circuit according to any one of claims 1-7. The method includes: employing multiple linear voltage generating circuits, combined with a limiting circuit composed of an operational amplifier and diodes, to perform segmented linear reference voltage output control based on the output current detection value, specifically including: The current detection signal Ioss and the reference voltage Vref are respectively input to the first linear voltage generating circuit (1) and the second linear voltage generating circuit (2); the first linear voltage generating circuit (1) generates a linear reference voltage under low overload current; the output of the first linear voltage generating circuit (1) is connected to the input terminal of the first upper limit limiting circuit (3), and the other input terminal of the first upper limit limiting circuit (3) is connected to the first reference voltage Vref1 to realize the plateau voltage in the initial current stage; the output of the first upper limit limiting circuit (3) is connected to the input terminal of the first lower limit limiting circuit (4), and the other input terminal of the first lower limit limiting circuit (4) is connected to the second reference voltage Vref2. The platform voltage after generating the first segment of linear voltage; the second linear voltage generating circuit (2) generates the linear reference voltage under high overload current; the output of the second linear voltage generating circuit (2) is connected to the input terminal of the second upper limit limiting circuit (5), the other input terminal of the second upper limit limiting circuit (5) is connected to the output terminal of the first lower limit limiting circuit (4), the output of the second upper limit limiting circuit (5) is connected to the input terminal of the second lower limit limiting circuit (6), the other input terminal of the second lower limit limiting circuit (6) is connected to the third reference voltage Vref3, generating the last segment of platform voltage; the input terminal of the multi-reference voltage generating circuit (7) is connected to Vref, converting it into three reference voltage outputs.

9. The reference voltage output control method according to claim 8, characterized in that, The upper limit limiting circuit (3) output voltage regulation method includes: the output voltage of pin 1 of operational amplifier U2A is connected to the inverting input of pin 2 of operational amplifier U1A through resistor R6; the first reference voltage Vref1 is connected to the non-inverting input of pin 3 of operational amplifier U1A through resistor R1; when the output voltage of pin 1 of operational amplifier U2A is higher than the first reference voltage Vref1, the output voltage of pin 1 of operational amplifier U1A is low, diode D2 is turned on, and the inverting input of pin 2 of U1A is connected to the non-inverting input of pin 3 of operational amplifier U1A through diode D2. When pin 1 is open, negative feedback is formed, and the voltage at pin 2 of operational amplifier U1A and the anode voltage of diode D2 are clamped to the first reference voltage Vref1. Conversely, when the output voltage at pin 1 of operational amplifier U2A is lower than the first reference voltage Vref1, the output voltage at pin 1 of operational amplifier U1A is at a saturation high level, close to the operational amplifier supply voltage. Diode D2 is cut off, and the voltage at pin 2 of operational amplifier U1A and the anode voltage of diode D2 are equal to the output voltage at pin 1 of operational amplifier U2A, thus achieving the upper limit limiting function.

10. The reference voltage output control method according to claim 8, characterized in that, The first lower limit limiting circuit (4) output voltage regulation method includes: pin 2 of operational amplifier U1A and the anode of diode D2 are connected to the inverting input of pin 6 of operational amplifier U1B through resistor R5; the second reference voltage Vref2 is connected to the non-inverting input of pin 5 of operational amplifier U1B through resistor R3; when the anode voltage of diode D2 is greater than the voltage of the second reference voltage Vref2, the pin 7 of operational amplifier U1B outputs a saturated low level, close to ground potential, diode D1 is cut off, and the voltage of the cathode of diode D1 and the voltage of pin 6 of operational amplifier U1B are equal to the anode voltage of diode D2; when diode D2 When the anode voltage is less than the second reference voltage Vref2, pin 7 of operational amplifier U1B outputs a high level, diode D1 conducts, and pin 7 of operational amplifier U1B is connected to pin 6 of the inverting input through diode D1 to form negative feedback. The voltage of the cathode of diode D1 and pin 6 of operational amplifier U1B is clamped to the second reference voltage Vref2. At this time, the voltage of the cathode of diode D1 and pin 2 of operational amplifier U1A is equal to the output voltage of pin 1 of operational amplifier U2A. The lower limit of the linear voltage output of pin 1 of operational amplifier U2A is clamped to the second reference voltage Vref2, realizing the lower limit limiting function. The upper limit limiting circuit (5) constructed by operational amplifier U3A is consistent with the upper limit limiting circuit output voltage regulation process of the first upper limit limiting circuit (3) constructed by operational amplifier U1A. The non-inverting input of operational amplifier U3A is connected to the output terminal of the first lower limit limiting circuit (4) constructed by U1B through resistor R16. The upper limit value of the linear voltage output by pin 7 of operational amplifier U2B is clamped to the cathode of diode D1 and the voltage value of pin 6 of operational amplifier U1B. The second lower limit limiting circuit (6) constructed by operational amplifier U3B is consistent with the output voltage regulation process of the first lower limit limiting circuit (4) constructed by operational amplifier U1B. The non-inverting input of operational amplifier U3B is connected to the third reference voltage Vref3 through resistor R20, which clamps the lower limit value of the linear voltage output by pin 7 of operational amplifier U2B to the voltage value of the third reference voltage Vref3.

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