Video up-sampling using one or more neural networks

Abstract

This invention discloses video upsampling using one or more neural networks, specifically disclosing apparatus, systems, and techniques for enhancing video. In at least one embodiment, one or more neural networks are used to create a higher-resolution video using upsampled frames from a lower-resolution video.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202080062960.4, filed on August 26, 2020.

[0002] Cross-reference to related applications

[0003] This application is a continuation-to-file of U.S. Patent Application No. 16 / 565,088, filed September 9, 2019, entitled “Video Upsampling Using One or More Neural Networks”, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0004] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training neural networks according to various new technologies described herein. Background Technology

[0005] As video content is consumed in increasingly diverse ways, on different devices, and from diverse sources, in some cases, the quality of the video content is not optimal for the devices used to display it. Methods to improve content quality are often subject to human intervention or result in lower-than-expected quality, and obtaining live video is difficult. Attached Figure Description

[0006] The various embodiments disclosed herein will be described with reference to the accompanying drawings, in which:

[0007] Figure 1A and Figure 1B Image data to be processed or generated according to at least one embodiment is shown;

[0008] Figure 2A and Figure 2B A method for upsampling video content according to at least one embodiment is shown;

[0009] Figure 3 Components of a system for temporal anti-aliasing upsampled video content according to at least one embodiment are shown;

[0010] Figure 4 A process for upsampling video content according to at least one embodiment is illustrated;

[0011] Figure 5 A partial process for inferring upsampled video frames from video frames, according to at least one embodiment, is illustrated;

[0012] Figure 6 A system for training and inference using one or more neural networks, according to at least one embodiment, is shown;

[0013] Figure 7 A system for training one or more neural networks according to at least one embodiment is shown;

[0014] Figure 8 The structure of a neural network according to at least one embodiment is shown;

[0015] Figure 9A The inference and / or training logic according to at least one embodiment is illustrated;

[0016] Figure 9B The inference and / or training logic according to at least one embodiment is illustrated;

[0017] Figure 10 An example data center system according to at least one embodiment is shown;

[0018] Figure 11 A computer system according to at least one embodiment is shown;

[0019] Figure 12 A computer system according to at least one embodiment is shown;

[0020] Figure 13 A computer system according to at least one embodiment is shown;

[0021] Figure 14 A computer system according to at least one embodiment is shown;

[0022] Figure 15A A computer system according to at least one embodiment is shown;

[0023] Figure 15B A computer system according to at least one embodiment is shown;

[0024] Figure 15C A computer system according to at least one embodiment is shown;

[0025] Figure 15D A computer system according to at least one embodiment is shown;

[0026] Figure 15E and Figure 15F A shared program model according to at least one embodiment is shown;

[0027] Figure 16 An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0028] Figures 17A-17B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0029] Figures 18A-18B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0030] Figure 19 A computer system according to at least one embodiment is shown;

[0031] Figure 20A A parallel processor according to at least one embodiment is shown;

[0032] Figure 20B A partitioning unit according to at least one embodiment is shown;

[0033] Figure 20C A processing cluster according to at least one embodiment is shown;

[0034] Figure 20D A graphics multiprocessor according to at least one embodiment is shown;

[0035] Figure 21 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0036] Figure 22 A graphics processor according to at least one embodiment is shown;

[0037] Figure 23 The microarchitecture of a processor according to at least one embodiment is shown;

[0038] Figure 24 A deep learning application processor according to at least one embodiment is shown;

[0039] Figure 25 A processor with an example neuromorphism according to at least one embodiment is shown;

[0040] Figure 26 and Figure 27 At least a portion of a graphics processor according to at least one embodiment is shown;

[0041] Figure 28 At least a portion of a graphics processor core according to at least one embodiment is shown;

[0042] Figures 29A-29B At least a portion of a graphics processor core according to at least one embodiment is shown;

[0043] Figure 30 A parallel processing unit (PPU) according to at least one embodiment is shown;

[0044] Figure 31 A total processing cluster (“GPC”) according to at least one embodiment is shown;

[0045] Figure 32 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0046] Figure 33 A streaming multiprocessor according to at least one embodiment is shown. Detailed Implementation

[0047] In at least one embodiment, such as Figure 1A As shown, a sequence 100 of video frames can be received on a video stream. In at least one embodiment, the video frames from this sequence are generated by a game engine 102, which renders video frames representing gameplay for at least one player in the current game session. In at least one embodiment, the video frames can be received from another source, such as a video hosting site, and can be received at any time after the video content has been hosted at that video hosting site. In at least one embodiment, successive video frames may include variations of earlier video frames due to changes in gameplay state. In at least one embodiment, the sequence 100 generated by the game engine 102 may have a default or specified resolution or display size. In at least one embodiment, the resolution of the video frames in the sequence 100 may be lower than the possible, preferred, or current resolution setting of the display 104 used to view the sequence 100, such as a monitor, touchscreen, or television used to display gameplay video rendered by the game engine 102.

[0048] In at least one embodiment, the upsampling system 152 (or service, module, or device) can be used to upsample individual frames of sequence 100, such as Figure 1B View 150 is shown. In at least one embodiment, frames from game engine 102 can be fed to upsampling system 152 to increase the resolution of individual frames, generating a higher-resolution sequence that can be displayed on display 104 at a higher resolution. In at least one embodiment, the amount of upsampling to be performed can depend on the initial resolution of sequence 100 and the target resolution of display 104, for example, from 1080p to 4k resolution. In at least one embodiment, additional processing can be performed as part of the upsampling process, as it may include anti-aliasing and timing smoothing. In at least one embodiment, any suitable upsampling algorithm can be used, such as an algorithm using a Gaussian filter. In at least one embodiment, the upsampling processing takes into account dithering that can be applied on a per-frame basis.

[0049] In at least one embodiment, deep learning can be used to infer the upsampled video frames of the sequence. In at least one embodiment, a supersampling algorithm without machine learning can be used to upsample the current input frame of the video sequence. In at least one embodiment, a Temporal Anti-aliasing Upsampling (TAAU) algorithm can be used, which provides initial anti-aliasing and upsampling in a combined manner. In at least one embodiment, information from the corresponding video frame sequence can be used to infer a higher quality upsampled image. In at least one embodiment, one or more heuristics based on prior knowledge of the rendering pipeline that does not require learning from the data can be used. In at least one embodiment, this can include jitter-aware upsampling and accumulated samples at the upsampling resolution. In at least one embodiment, prior processing data 208 can be provided as input to an upsampler system 210 including at least one neural network along with the current input video frame 202 and the prior inference frame 206 to infer a higher quality upsampled output image 204 than that produced by the upsampling algorithm alone, such as... Figure 2A As shown in view 200.

[0050] In at least one embodiment, the upsampling system 210 can provide deep learning for temporal supersampling, offering anti-aliasing and super-resolution over a stream (or other sequence or file) of image or video frames. In at least one embodiment, basic upsampling methods, such as... Figure 2B As shown in view 250. In at least one embodiment, the low-resolution pixel 252 can be divided into a plurality of higher-resolution (or smaller) pixels 254. In at least one embodiment, upsampling can be as follows: Figure 2B The illustrated 4x upsampling involves dividing each pixel of the input image into four higher-resolution pixels. In at least one embodiment, the location of sample 256 in the low-resolution pixel 252 can be used to compute an upsampling kernel for one or more corresponding high-resolution pixels. In at least one embodiment, this kernel provides at least one for blurring, embossing, sharpening, or edge detection.

[0051] In at least one embodiment, system 300 can perform actions such as Figure 3 The image frame sequence shown is upsampled. In at least one embodiment, an input image 302 corresponding to a video frame sequence or stream is received. In at least one embodiment, the input image 302 is a low-resolution, dense image. In at least one embodiment, the upsampling module 304 (or system, component, device, or service) can be applied as described above and regarding... Figure 2BThe illustrated upsampling algorithm can provide subpixel offset-aware upsampling. In at least one embodiment, the upsampled image can be fed into a trained neural network 320. In at least one embodiment, the trained network 320 can accept additional input to attempt to infer a higher quality upsampled image or video frame. In at least one embodiment, the trained network 320 also accepts video frame data from previously inferred frames as input. In at least one embodiment, historical input data can be provided to the trained network 320 using a dense, large history image 328 inferred for a previous frame in the sequence. In at least one embodiment, a motion warping module 330 or process can be applied to generate a bicubic warped history image 308. In at least one embodiment, motion warping can be used to apply small offsets to the data to satisfy one or more constraints. In at least one embodiment, the offsets depend at least in part on determined or predicted motion for a portion of the image. In at least one embodiment, the history image 308 can be processed using a color space conversion module 310, for example, to generate a bicubic warped image 312 in a specific color space, such as the YCoCg color space containing luminance values ​​and two chrominance values. In at least one embodiment, the bicubic distortion image 312 may be fed to the brightness determination module 318 to provide brightness-specific image data as input to the trained network 320. In at least one embodiment, the brightness determination module 318 may also accept an anti-aliasing image 316 generated by the temporal anti-aliasing module 314 to provide anti-aliasing brightness values ​​to smooth the upsampling results of the processed image. In at least one embodiment, the historical images provided as input to the neural network 320 may already be mixed with the current frame 306 to some extent based on the application's determined jitter offset, which may help temporally converge to a good, clear, high-resolution image.

[0052] In at least one embodiment, a trained neural network 320 generates blending factors and kernels that can be used to blend the input image 302 and the historical image 328 to produce an inferred output image 326. In at least one embodiment, the output image 326 has the same resolution as the magnified image 306. In at least one embodiment, a shader module 324 can be used to perform another color space transformation, for example, so that the trained network 320, even operating on image data in the YCoCg color space, can make the output image 326 exist in the RGB color space. In at least one embodiment, the kernels inferred by the trained model 320 can help improve the perceptual quality of the output image 326, which also serves as the historical image 328 for the next input video frame of the corresponding sequence. In at least one embodiment, kernel factors output from the trained network 320 can be applied to improve various qualities of the inferred, upsampled image 326, which may include sharpening and reducing ghosting or artifacts. In at least one embodiment, at least some of the core data may be provided as additional input 322 to the trained network 320 for subsequent image or video frames in an attempt to improve the quality of one or more subsequent processed frames of the sequence.

[0053] In at least one embodiment, neural network 320 is trained using a dataset including annotated images or video frames. In at least one embodiment, image pairs are used for training, including an image to be upsampled and a corresponding anti-aliasing, upsampled, higher-resolution image. In at least one embodiment, neural network 320 can be trained to learn appropriate mappings between these image pairs. In at least one embodiment, neural network 320 can also be trained to determine appropriate blending factors and one or more kernel factors to apply. In at least one embodiment, a multi-factor loss function can be used to optimize neural network 320 during training, for example, by optimizing network parameters to minimize the corresponding loss value. In at least one embodiment, a multi-factor loss function is used because modeling human perception of image quality can be complex and difficult to capture mathematically. In at least one embodiment, the loss function used to train the network (e.g., neural network 298) can utilize style components and temporal components, as well as other losses (such as L2 loss) to minimize error. In at least one embodiment, spatial components help minimize the occurrence of ghosting or other similar artifacts, while temporal components help smooth motion between frames in the output sequence. In at least one embodiment, sequences of these frame pairs are used for training to provide improved temporal smoothing.

[0054] In at least one embodiment, the neural network 320 predicts various factors for each pixel. In at least one embodiment, the network 320 predicts or infers ten factors, including a blending factor and nine elements to be applied to the core of the corresponding image input. In at least one embodiment, these nine factors can be applied to the current upsampled frame data when generating a prediction. In at least one embodiment, the processed upsampled frame can be blended with data from previously inferred frames using a determined blending factor. In at least one embodiment, only one luminance channel is used for this processing and blending, which can provide results similar to those using a full-color image, but requires far less data management and processing.

[0055] In at least one embodiment, the loss can be weighted using a per-pixel weighting factor. In at least one embodiment, per-pixel weighting can focus more attention on regions where de-occlusion may occur, or regions that were previously occluded but are no longer occluded, thereby making one or more objects suddenly visible or represented in a sequence of video frames. In at least one embodiment, successful de-occlusion management can help reduce the presence of ghosting artifacts. In at least one embodiment, the weighting factor is calculated by comparing the current reference frame with a previous distorted reference frame. In at least one embodiment, if a pixel of the previously distorted reference frame falls within the bounding box of the color distribution of the corresponding current reference frame, it can be assumed that there may be no de-occlusion at that location. In at least one embodiment, if a significant color difference is determined between the previously distorted reference frame and the current reference frame, a high weight can be applied to the spatial loss. In at least one embodiment, such a high weight for the spatial loss forces the spatial loss to be more influenced by regions with large color differences between the current and previous reference frames.

[0056] In at least one embodiment, only the last distorted frame prediction is provided as input to the current frame, rather than a set of previous predictions. In at least one embodiment, this last prediction will be based on information from past frames and will include updated information to minimize artifacts and provide superior sharpness in the inference image. In at least one embodiment, errors in predictions during training are implicitly managed using a loss function, because bad frames or frames with artifacts will have high loss values ​​during evaluation, which will cause the prediction to be discarded. In at least one embodiment, drastic changes due to scene variations or camera shake may also cause the last prediction to be discarded instead of being used for upsampling, because large changes in color values ​​or positions may be irrelevant to, or at least substantially different from, the current frame.

[0057] In at least one embodiment, for example regarding Figure 6As described, oversampling can be performed in multiple locations, such as on a client device, by a content provider, or by a cloud resource provider. In at least one embodiment, a client device having at least one graphics processor receives or acquires lower-resolution data and then upsamples that data before displaying or rendering it. In at least one embodiment, the lower-resolution data may include video data received on a stream, generated by a game or rendering engine, generated by a camera or sensor, or contained in a file. In at least one embodiment, upsampling can occur almost in real time or for subsequent viewing or rendering offline. In at least one embodiment, applications such as games may require rapid upsampling to allow players to view upgraded content near real time without perceptible latency, so as to enjoy the gaming experience without being disadvantaged by significant delays.

[0058] In at least one embodiment, one or more other inputs 322 may include difference information determined between the current frame and previously predicted frames. In at least one embodiment, these inputs can help identify pixels or pixel regions that exhibit significant differences in pixel values. In at least one embodiment, this information can be advantageously used during training or inference time to determine the weights of certain pixel values ​​in different regions of the image. In at least one embodiment, hidden historical data may also be generated from network 320 and used as input to subsequent frames, which allows network 320 to apply information that may be useful for subsequent frames, or can be used as a starting point for analyzing or inferring subsequent frames.

[0059] In at least one embodiment, it can be used Figure 4The process 400 shown is used to perform upsampling of video frames. In at least one embodiment, a lower-resolution video stream is received 402 or otherwise obtained. In at least one embodiment, individual frames of the stream can be analyzed upon receipt to provide a higher-resolution version of the stream for display. In at least one embodiment, the current video frames of the stream can be upsampled 404 using an upsampling algorithm. In at least one embodiment, a previously warped video frame prediction is obtained 406, which will produce the same resolution as the upsampling. In at least one embodiment, these frames are converted 408 to a target color space, and a single channel of the target color space is used for the representation of those frames to be processed. In at least one embodiment, these frames are provided 410, with at least some additional information where applicable, as input to a trained neural network to determine a blending factor and one or more core factors. In at least one embodiment, these inference factors and the input frames are used to generate 412 an output version of the corresponding current input video frame with high image quality and a target upsampling resolution. In at least one embodiment, the output video frame 414 can be provided for display as part of a video stream so that the video stream received at a first, lower resolution can be displayed at a second, higher resolution, which has good image quality and a small amount of artifacts from upsampling.

[0060] In at least one embodiment, it can be used Figure 4 The process 400 shown is used to perform upsampling of a video frame. In at least one embodiment, 502 a current frame of video data is received. In at least one embodiment, the current video frame of the video data is upsampled 504 to a target higher resolution using an upgrade process. In at least one embodiment, 506 the upsampled current frame is provided, with a previously inferred frame having the target higher resolution as input to a trained neural network. In at least one embodiment, 508 an output version of the current video frame is inferred based at least in part on a mixture of pixel values ​​from the upsampled current frame and the previously inferred frame. In at least one embodiment, 510 the output version can be provided for display and for processing subsequent video frames received at a lower resolution.

[0061] Neural network training and deployment

[0062] A growing number of industries and applications are leveraging machine learning. In at least one embodiment, deep neural networks (DNNs) developed on processors have been used in a variety of use cases, from self-driving cars to faster drug development, from automated image analysis for security systems to intelligent real-time language translation in video chat applications. In at least one embodiment, deep learning is a technique that models the neural learning process of the human brain, continuously learning, becoming smarter, and providing more accurate results faster over time. Initially, adults teach children to correctly identify and classify various shapes, eventually enabling them to recognize shapes without any guidance. Similarly, in at least one embodiment, it will be necessary to train deep learning or neural learning systems designed to perform similar tasks to become smarter and more efficient in recognizing basic objects, occluded objects, etc., while also assigning context to these objects.

[0063] In at least one embodiment, neurons in the human brain examine various received inputs, assign importance levels to each of these inputs, and then pass the outputs to other neurons for manipulation. Artificial neurons, or perceptrons, are the most basic model of neural networks. In at least one embodiment, a perceptron may receive one or more inputs representing various features of objects that the perceptron is being trained to recognize and classify, and assign a weight to each of these features based on their importance in defining the shape of the object.

[0064] Deep neural network (DNN) models consist of multiple layers of many connected perceptrons (e.g., nodes) that can be trained with large amounts of input data to solve complex problems quickly and with high accuracy. In one example, the first layer of a DNN model breaks down an input image of a car into its parts and looks for basic patterns such as lines and corners. The second layer assembles the lines to find higher-level patterns such as wheels, windshields, and rearview mirrors. The next layer identifies the type of vehicle, and the last few layers generate labels for the input image, identifying models that recognize specific car brands. Once a DNN is trained, it can be deployed and used to identify and classify objects or patterns in a process called inference. Examples of inference (the process by which a DNN extracts useful information from a given input) include recognizing handwritten digits on a check deposited into an ATM, recognizing an image of a friend in a photograph, providing movie recommendations, identifying and classifying different types of cars, pedestrians, and road hazards in a self-driving car, or translating human speech in near real-time.

[0065] During training, data flows through the DNN in the forward propagation phase until a prediction corresponding to the input is produced. If the neural network does not correctly label the input, the error between the correct label and the predicted label is analyzed, and the weights of each feature are adjusted in the backpropagation phase until the DNN correctly labels the input and other inputs in the training dataset. Training complex neural networks requires significant parallel computational power, including supported floating-point multiplication and addition. Inference is less computationally intensive than training; it is a latency-sensitive process where the trained neural network is applied to new inputs never seen before, such as classifying images, translating speech, and inferring new information.

[0066] Neural networks rely heavily on matrix mathematical operations, and complex multi-layered networks require significant floating-point performance and bandwidth to improve efficiency and speed. With thousands of processing cores optimized for matrix mathematical operations and delivering tens to hundreds of TFLOPS of performance, computing platforms can provide the performance required for deep neural network-based artificial intelligence and machine learning applications.

[0067] Figure 6 Components of an example system 600, which can be used to train and utilize machine learning in at least one embodiment, are illustrated. As will be discussed, various components can be provided by various combinations of computing devices and resources, or a single computing system, that can be under the control of a single entity or multiple entities. Furthermore, aspects can be triggered, initiated, or requested by different entities. In at least one embodiment, the training of the neural network can be guided by a vendor associated with vendor environment 606, while in at least one embodiment, the training of the neural network can be requested by a customer or other user who can access the vendor environment through client device 602 or other such resources. In at least one embodiment, training data (or data to be analyzed by the trained neural network) can be provided by a vendor, user, or third-party content provider 624. In at least one embodiment, client device 602 can be a vehicle or object that can navigate on behalf of a user, for example, the user can submit requests and / or receive instructions that aid in device navigation.

[0068] In at least one embodiment, a request can be submitted via at least one network 604 to be received by the vendor environment 606. In at least one embodiment, the client device can be any suitable electronic and / or computing device that enables a user to generate and send such requests, such as a desktop computer, laptop computer, computer server, smartphone, tablet computer, game console (portable or otherwise), computer processor, computing logic, and set-top box. One or more networks 604 can include any suitable network for sending requests or other such data, such as the Internet, intranet, Ethernet, cellular network, local area network (LAN), network providing direct wireless connectivity between nodes, etc.

[0069] In at least one embodiment, a request may be received to an interface layer 608, which in this example may forward data to a training and inference manager 610. This manager may be a system or service comprising hardware and software for managing services and requests consistent with data or content. In at least one embodiment, the manager may receive a request to train a neural network and may provide the requested data to a training manager 612. In at least one embodiment, if the request is not specified, the training manager 612 may select an appropriate model or network to use and may train the model using the associated training data. In at least one embodiment, the training data may be a batch of data received from a client device 602 or obtained from a third-party vendor 624 and stored in a training data repository 614. In at least one embodiment, the training manager 612 may be responsible for training the data, for example, by using a LARC-based method discussed herein. The network may be any suitable network, such as a recurrent neural network (RNN) or a convolutional neural network (CNN). Once the network has been trained and successfully evaluated, the trained network may be stored in a model repository 616, which may, for example, store different models or networks for users, applications, or services. In at least one embodiment, multiple models may exist for a single application or entity, such as multiple models may be utilized based on multiple different factors.

[0070] In at least one embodiment, at a subsequent point in time, a request for content (e.g., path determination) or data determined or influenced by at least partially trained neural networks can be received from client device 602 (or another such device). This request may include, for example, input data to be processed using the neural network to obtain one or more inference or other output values, classifications, or predictions. In at least one embodiment, although different systems or services may also be used, the input data may be received to interface layer 608 and directed to inference module 618. In at least one embodiment, if not already locally stored in inference module 618, inference module 618 may obtain an appropriate trained network, such as a trained deep neural network (DNN) as described herein, from model repository 616. Inference module 618 may feed data as input to the trained network and then generate one or more inferences as outputs. For example, this may include classification of input data instances. In at least one embodiment, the inference may then be sent to client device 602 for display to a user or for other communication with the user. In at least one embodiment, user context data may also be stored in user context data repository 622, which may include data about the user that can be used as network input to generate inference or determine data to be returned to the user after obtaining an instance. In at least one embodiment, relevant data, including at least some of the input or inference data, may be stored in a local database 620 for processing future requests. In at least one embodiment, a user may use an account or other information to access resources or features of the vendor environment. In at least one embodiment, user data may also be collected and used to further train the model to provide more accurate inference for future requests, if permitted and available. In at least one embodiment, requests to a machine learning application 626 executed on a client device 602 may be received via a user interface, and the results may be displayed via the same interface. The client device may include resources such as a processor 628 and a memory 630 for generating requests and processing results or responses, and at least one data storage element 632 for storing data for the machine learning application 626.

[0071] In at least one embodiment, processor 628 (or the processor of training manager 612 or inference module 618) will be a central processing unit (CPU). However, as mentioned above, resources in such an environment can utilize GPUs to process data for at least some types of requests. GPUs have thousands of cores and are designed to handle large amounts of parallel workloads, thus becoming popular in deep learning for training neural networks and generating predictions. While offline building with GPUs allows for faster training of larger, more complex models, offline prediction generation means that request-time input features cannot be used, or predictions must be generated for all features and stored in a lookup table for real-time service requests. If the deep learning framework supports CPU mode and the model is small and simple enough that the feedforward can be performed on the CPU with reasonable latency, then a service on a CPU instance can host the model. In this case, training can be done offline on the GPU and inference can be performed in real-time on the CPU. If the CPU approach is not feasible, the service can run on a GPU instance. However, because GPUs have different performance and cost characteristics than CPUs, running a service that offloads runtime algorithms to the GPU may require it to be designed differently from a CPU-based service.

[0072] In at least one embodiment, video data may be provided from client device 602 for enhancement in vendor environment 606. In at least one embodiment, the video data may be processed in client device 602 for enhancement. In at least one embodiment, the video data may be a stream from third-party content provider 624 and enhanced by third-party provider 624, vendor environment 606, or client device 602.

[0073] Figure 7An example system 700 is illustrated, which can be used to classify data or generate inference in at least one embodiment. In at least one embodiment, supervised training and unsupervised training can be used in at least one embodiment discussed herein. In at least one embodiment, a set of training data 702 (e.g., classified or labeled data) is provided as input to be used as training data. In at least one embodiment, the training data may include instances of at least one type of object for which a neural network is to be trained, and information identifying that type of object. In at least one embodiment, the training data may include a set of images, each containing a representation of an object type, wherein each image also contains a label, metadata, classification, or other information fragments identifying or associated with the object type represented in the respective image. Various other types of data may also be used as training data and may include text data, audio data, video data, etc. In at least one embodiment, the training data 702 is provided as training input to a training manager 704. In at least one embodiment, the training manager 704 may be a system or service including hardware and software, such as one or more computing devices executing a training application for training a neural network (or other model or algorithm, etc.). In at least one embodiment, the training manager 704 receives instructions or requests indicating the type of model to be used for training. In at least one embodiment, the model can be any suitable statistical model, network, or algorithm suitable for such purposes, such as artificial neural networks, deep learning algorithms, learned classifiers, Bayesian networks, etc. In at least one embodiment, the training manager 704 can select an initial model or other untrained model from an appropriate repository 706 and use training data 702 to train the model to generate a trained model 708 (e.g., a trained deep neural network) that can be used to classify similar types of data, or to generate other such inference. In at least one embodiment where training data is not used, the input data can still be trained according to the selection of an appropriate initial model by the training manager 704.

[0074] In at least one embodiment, the model can be trained in a variety of different ways, which may depend in part on the type of model chosen. In at least one embodiment, a set of training data can be provided to the machine learning algorithm, wherein the model is a model artifact created through a training process. In at least one embodiment, each instance of the training data contains the correct answer (e.g., a classification), which may be referred to as the target or target attribute. In at least one embodiment, the learning algorithm finds patterns in the training data that map input data attributes to targets, the answers to be predicted, and outputs a machine learning model that captures these patterns. In at least one embodiment, the machine learning model can then be used to obtain predictions for new data without a specified target.

[0075] In at least one embodiment, the training manager 704 can select from a set of machine learning models, including binary classification, multi-class, and regression models. In at least one embodiment, the type of model to be used may depend at least in part on the type of target to be predicted. In at least one embodiment, a machine learning model for a binary classification problem can predict binary outcomes, such as one of two possible classes. In at least one embodiment, a learning algorithm (such as logistic regression) can be used to train the binary classification model. In at least one embodiment, a machine learning model for a multi-class classification problem allows the generation of predictions for multiple classes, such as predicting one of more than two outcomes. Multinomial logistic regression can be useful for training multi-class models. Machine learning models for regression problems can predict numerical values. Linear regression is useful for training regression models.

[0076] In at least one embodiment, in order to train a machine learning model according to one embodiment, the training manager must determine the input training data source and other information, such as the name of the data attribute containing the target to be predicted, the required data transformation instructions, and training parameters to control the learning algorithm. In at least one embodiment, during training, the training manager 704 may automatically select an appropriate learning algorithm based on the target type specified in the training data source. In at least one embodiment, the machine learning algorithm may accept parameters for controlling certain attributes of the training process and the resulting machine learning model. These are referred to herein as training parameters. In at least one embodiment, if no training parameters are specified, the training manager may utilize known default values ​​to handle a wide range of machine learning tasks well. Examples of training parameters for which values ​​can be specified include maximum model size, maximum number of passes through the training data, shuffle type, regularization type, learning rate, and regularization amount. Default settings can be specified, with options for adjusting values ​​to fine-tune performance.

[0077] In at least one embodiment, the maximum model size is the total size (in bytes) of patterns created during model training. In at least one embodiment, by default, a model of a specified size can be created, such as a 100MB model. If the training manager cannot determine enough patterns to fill the model size, a smaller model can be created. If the training manager finds that the number of patterns exceeds what the specified size can accommodate, a maximum cutoff can be enforced by trimming the patterns that have the least impact on the quality of the learned model. Choosing a model size allows control over the trade-off between the model's predictive quality and its cost of use. In at least one embodiment, a smaller model may cause the training manager to remove many patterns to fit the maximum size limit, thus affecting the quality of predictions. In at least one embodiment, a larger model may be more costly than querying real-time predictions. In at least one embodiment, a larger input dataset does not necessarily result in a larger model, as the model stores patterns rather than input data. In at least one embodiment, if the patterns are few and simple, the resulting model will be small. Input data with a large number of original attributes (input columns) or derived features (output of data transformation) may find and store more patterns during training.

[0078] In at least one embodiment, the training manager 704 may perform multiple passes or iterations on the training data to attempt to discover patterns. In at least one embodiment, a default number of passes may exist, such as ten, while in at least one embodiment, a maximum number of passes may be set, such as up to one hundred passes. In at least one embodiment, there may be no maximum set, or there may be a set of convergence criteria or other factors that would trigger the termination of the training process. In at least one embodiment, the training manager 704 may monitor the quality of the patterns during training (e.g., for model convergence) and may automatically stop training when there are no more data points or patterns to discover. In at least one embodiment, datasets with only a few observations may require more data traversal to achieve sufficiently high model quality. Larger datasets may contain many similar data points, which can reduce the need for a large number of passes. A potential impact of choosing to pass more data is that model training may take longer and incur higher resource and system utilization costs.

[0079] In at least one embodiment, training data is shuffled before training or between training passes. In at least one embodiment, the shuffling is a random or pseudo-random shuffling used to generate truly random sorting, although there may be constraints to ensure that certain types of data are not grouped, or if such grouping exists, the shuffled data can be reshuffled, etc. In at least one embodiment, shuffling changes the sequence or arrangement of data used for training so that the training algorithm does not encounter groupings of similar types of data or a single type of data with too many consecutive observations. In at least one embodiment, a model can be trained to predict objects. In at least one embodiment, data may be categorized by object type before uploading. In at least one embodiment, the algorithm may then process the data alphabetically by object type, initially encountering only data of a specific object type. In at least one embodiment, the model will begin to learn a pattern for that type of object. In at least one embodiment, the model will then encounter only data for a second object type and will attempt to adjust the model to fit that object type, which may cause the pattern suitable for the first object type to degenerate. This abrupt switching between object types may result in a model that cannot learn how to accurately predict object types. In at least one embodiment, shuffling may be performed before dividing the training dataset into a training subset and an evaluation subset, thereby utilizing a relatively uniform data type distribution for both stages. In at least one embodiment, the training manager 704 may use, for example, a pseudo-random shuffling technique to automatically shuffle the data.

[0080] In at least one embodiment, when creating a machine learning model, the training manager 704 allows the user to specify settings or apply custom options. In at least one embodiment, the user can specify one or more evaluation settings to indicate a portion of the input data to be retained for evaluating the predictive quality of the machine learning model. In at least one embodiment, the user can specify a strategy that indicates which attributes and attribute transformations can be used for model training. In at least one embodiment, the user can also specify various training parameters that control the training process and certain attributes of the resulting model.

[0081] In at least one embodiment, once the training manager determines that model training is complete, for example by using at least one final criterion discussed herein, the trained model 708 can be provided to the classifier 714 for classifying (or otherwise generating inference to) the validation data 712. In at least one embodiment, this involves a logical transition between the model's training mode and its inference mode. In at least one embodiment, however, the trained model 708 will first be passed to an evaluator 710, which may include an application, process, or service executing on at least one computational resource (e.g., the CPU or GPU of at least one server) for evaluating the quality (or other aspects) of the trained model. In at least one embodiment, the model is evaluated to determine whether it will provide at least a minimum acceptable or threshold level of performance when predicting targets for new and future data. If not, the training manager 704 can continue training the model. In at least one embodiment, since future data instances will typically have unknown target values, it may be desirable to examine machine learning accuracy metrics on data with known target answers and use that evaluation as a proxy for predicting the accuracy of future data.

[0082] In at least one embodiment, a subset of the training data 702 provided for training is used to evaluate the model. This subset can be determined using the shuffling and splitting methods described above. In at least one embodiment, this evaluation data subset will be labeled with a target and can therefore serve as a resource for evaluating ground reality. It is useless to use the same data used for training to evaluate the predictive accuracy of a machine learning model, as this might produce a positive evaluation for a model that memorizes the training data rather than generalizes from it. In at least one embodiment, once training is complete, the trained model 708 is used to process the evaluation data subset, and the evaluator 710 can determine the accuracy of the model by comparing the ground reality data with the corresponding output (or prediction / observation) of the model. In at least one embodiment, the evaluator 710 can provide a summary or performance metric indicating the degree of match between the predicted and true values. In at least one embodiment, if the trained model does not meet at least a minimum performance criterion or other such accuracy threshold, the training manager 704 can be instructed to perform further training, or in some cases, to attempt to train a new or different model. In at least one embodiment, if the trained model 708 meets the relevant criteria, the trained model can be provided for use by the classifier 714.

[0083] In at least one embodiment, when creating and training a machine learning model, it is desirable to specify model settings or training parameters that will result in a model capable of making accurate predictions. In at least one embodiment, parameters include the number of passes to be performed (forward and / or backward), regularization or refinement, model size, and shuffling type. In at least one embodiment, selecting model parameter settings that produce the best predictive performance on evaluation data may lead to model overfitting. In at least one embodiment, overfitting occurs when the model stores patterns that appear in both training and evaluation data sources but fails to generalize patterns in the data. Overfitting often occurs when the training data includes all the data used in the evaluation. In at least one embodiment, an overfitted model may perform well during evaluation but may not make accurate predictions on new or other validation data. In at least one embodiment, to avoid selecting an overfitted model as the best model, the training manager may retain additional data to validate the model's performance. For example, the training dataset may be divided into two or more phases: 60% for training and 40% for evaluation or validation. In at least one embodiment, after selecting the model parameters best suited to the evaluation data, resulting in convergence to a subset of the validation data (e.g., half of the validation data), a second validation can be performed using the remaining validation data to ensure the model's performance. If this model meets the expectations of the validation data, then the model is not overfitting the data. In at least one embodiment, a test set or holdout set can be used to test the parameters. In at least one embodiment, using a second validation or testing step helps in selecting appropriate model parameters to prevent overfitting. However, taking more data from the training process for validation reduces the amount of data available for training. This can be problematic for smaller datasets, as there may not be enough data available for training. In at least one embodiment, one approach in this situation is to perform cross-validation, as described elsewhere herein.

[0084] In at least one embodiment, numerous metrics or insights are available for reviewing and evaluating the predictive accuracy of a given model. In at least one embodiment, an evaluation result includes a predictive accuracy metric for reporting the overall success of the model, as well as visualizations to help explore instances where the model's accuracy exceeds the predictive accuracy metric. The result may also provide the ability to view the impact of setting score thresholds (such as binary classification) and may generate alerts regarding the criteria used to examine the validity of the evaluation. The choice of metrics and visualizations may depend at least in part on the type of model being evaluated.

[0085] In at least one embodiment, once satisfactorily trained and evaluated, the trained machine learning model can be used to build or support a machine learning application. In one embodiment, building a machine learning application is an iterative process involving a series of steps. In at least one embodiment, one or more core machine learning questions can be constructed based on observations and the answers the model aims to predict. In at least one embodiment, data can then be collected, cleaned, and prepared to suit its use in training algorithms through the machine learning model. This data can be visualized and analyzed for integrity checks to verify data quality and understanding. This may be a situation where the raw data (e.g., input variables) and answer data (e.g., the target) are not represented in a way that can be used to train a highly predictive model. Therefore, it may be desirable to construct a more predictive input representation or feature from the raw variables. The resulting features can be fed into a learning algorithm to build a model and evaluate the quality of the model based on data retained from the model construction. The model can then be used to generate predictions of the target answer for new data instances.

[0086] In at least one embodiment, Figure 7 In system 700, after evaluation, a trained model 710 is provided to or made available to a classifier 714, which is capable of using the trained model to process validation data. In at least one embodiment, this may include data received from a user or an unclassified third party, such as a query image querying for information about what is represented in these images. In at least one embodiment, the validation data may be processed by the classifier using the trained model, and the resulting outcome 716 (e.g., classification or prediction) may be sent back to the appropriate source, or further processed or stored. In at least one embodiment, and where such use is permitted, these currently classified data instances may be stored in a training data repository, which may be used by the training manager for further training of the trained model 708. In at least one embodiment, the model will be trained continuously as new data becomes available; however, in at least one embodiment, the models will be trained periodically, such as daily or weekly, depending on factors such as the size of the dataset or the complexity of the model.

[0087] In at least one embodiment, the classifier 714 may include appropriate hardware and software for processing validation data 712 using a trained model. In at least one embodiment, the classifier will include one or more computer servers, each with one or more graphics processing units (GPUs) capable of processing data. In at least one embodiment, the GPUs may be configured and designed to be more desirable for processing machine learning data than CPUs or other such components. In at least one embodiment, the trained model may be loaded into GPU memory, and received data instances may be provided to the GPU for processing. GPUs may have significantly more cores than CPUs, and GPU cores may be less complex. In at least one embodiment, a given GPU may be able to process thousands of data instances simultaneously through different hardware threads. In at least one embodiment, the GPU may also be configured to maximize floating-point throughput, which can provide a significant additional processing advantage for large datasets.

[0088] In at least one embodiment, even when using GPUs, accelerators, and other such hardware to accelerate tasks such as model training or data classification using such models, such tasks can still require significant time, resource allocation, and cost. In at least one embodiment, if a machine learning model is to be trained using 700 passes, and the dataset includes 1,000,000 data instances to be used for training, each pass requires processing all one million instances. Different parts of the architecture can also be supported by different types of devices. In at least one embodiment, a set of servers can be used at a logically centralized location to perform training, as can be provided as a service, while the classification of the raw data can be performed by such a service or on client devices, among other such options. These devices can also be owned, operated, or controlled by the same or multiple entities.

[0089] In at least one embodiment, Figure 8An example neural network 800 that can be trained or otherwise utilized in at least one embodiment is illustrated. In at least one embodiment, the statistical model is an artificial neural network (ANN) comprising multiple node layers, including an input layer 802, an output layer 806, and multiple layers 804 of intermediate nodes, often referred to as “hidden” layers because inner layers and nodes are typically invisible or inaccessible in a neural network. In at least one embodiment, although several intermediate layers are shown for illustrative purposes only, it should be understood that there is no limit to the number of intermediate layers that can be utilized, and any limitation on the number of layers will generally be a factor of the resources or time required to process the model. In at least one embodiment, additional types of models, networks, algorithms, or processes may be used in addition to other numbers or options that may include nodes and layers. In at least one embodiment, validation data may be processed by layers of the network to generate a set of inference or inference scores, which may then be fed into a loss function 808.

[0090] In at least one embodiment, all nodes in a given layer are interconnected to all nodes in adjacent layers. In at least one embodiment, nodes in intermediate layers are then each connected to nodes in two adjacent layers. In at least one embodiment, in some models, nodes are also referred to as neurons or connected units, and the connections between nodes are called edges. Each node can perform a function for the received input, for example, by using a specified function. In at least one embodiment, nodes and edges can be assigned different weights during training, and the individual layers of a node can perform specific types of transformations on the received input, which can also be learned or adjusted during training. In at least one embodiment, learning can be supervised or unsupervised, which may depend at least in part on the type of information contained in the training dataset. In at least one embodiment, various types of neural networks can be utilized, such as convolutional neural networks (CNNs), which include many convolutional layers and a set of pooling layers and have proven beneficial for applications such as image recognition. CNNs are also easier to train than other networks because the number of parameters to be determined is relatively small.

[0091] In at least one embodiment, various tuning parameters can be used to train such a complex machine learning model. Selecting parameters, fitting the model, and evaluating the model are part of the model tuning process, often referred to as hyperparameter optimization. In at least one embodiment, this tuning may include introspection of the base model or data. In training or production settings, a robust workflow is crucial to avoid overfitting of hyperparameters, as described elsewhere in this document. Cross-validation and adding Gaussian noise to the training dataset are useful techniques to avoid overfitting to either dataset. For hyperparameter optimization, it may be necessary to keep the training and validation sets fixed. In at least one embodiment, hyperparameters can be tuned in several categories, such as data preprocessing (e.g., converting words to vectors), CNN architecture definitions (e.g., filter size, number of filters), stochastic gradient descent (SGD) parameters (e.g., learning rate), and regularization or refinement (e.g., dropout probability).

[0092] In at least one embodiment, during preprocessing, instances of the dataset can be embedded into a lower-dimensional space of a specific size. In at least one embodiment, the size of this space is a parameter to be tuned. In at least one embodiment, the CNN architecture incorporates many tuned parameters. The parameter of the filter size can represent the interpretation of information corresponding to the size of the instances to be analyzed. In computational linguistics, this is called the n-gram size. The example CNN uses three different filter sizes, which represent potentially different n-gram sizes. The number of filters for each filter size can correspond to the depth of the filters. Each filter attempts to learn something different from the structure of the instances, such as the sentence structure of text data. In the convolutional layers, the activation function can be rectified linear units, and the pooling type is set to max pooling. The results can then be concatenated into a one-dimensional vector, with the final layer fully connected to the two-dimensional output. This corresponds to binary classification, to which optimization functions can be applied. One such function is an implementation of the root mean square (RMS) propagation method of gradient descent, where example hyperparameters can include learning rate, batch size, maximum gradient normal, and epoch. Neural networks, regularization, can be a very important consideration. In at least one embodiment, the input data can be relatively sparse. In this scenario, the primary hyperparameters can be discarded at the penultimate layer, meaning a certain percentage of nodes will not "trigger" in each training epoch. The example training process can suggest different hyperparameter configurations based on feedback on the performance of previous configurations. The model can be trained using the suggested configurations, evaluated on a specified validation set, and performance can be reported. This process can be repeated, for example, by balancing exploration (learning more about different configurations) and development (leveraging prior knowledge to achieve better results).

[0093] Because CNN training can be parallelized and can leverage GPU-supported computational resources, various optimization strategies can be tried for different scenarios. Complex scenarios allow for tuning of the model architecture, preprocessing, and stochastic gradient descent parameters. This expands the model configuration space. In the basic case, only the preprocessing and stochastic gradient descent parameters are tuned. In complex scenarios, there are many more configuration parameters than in the basic approach. Joint space tuning can be performed using linear or exponential steps, iteratively through the model's optimization loop. Such tuning processes can be significantly less costly than tuning processes such as random search and grid search without incurring any noticeable performance penalty.

[0094] In at least one embodiment, backpropagation can be used to compute gradients for determining the weights of the neural network. Backpropagation is a form of differentiation, and as described above, gradient descent optimization algorithms can be used to adjust the weights applied to various nodes or neurons. The gradients of the relevant loss function can be used to determine the weights. Backpropagation can utilize the derivative of the loss function with respect to the output generated by the statistical model. As described above, each node can have an associated activation function that defines the output of each node. Various activation functions can be appropriately used, such as radial basis functions (RBF) and sigmoid functions, which can be used for data transformation by various support vector machines (SVMs). The activation functions of the intermediate layers of a node are referred to herein as inner product kernels. These functions can include, for example, recognition functions, step functions, sigmoid functions, ramp functions, etc. The activation functions can also be linear or nonlinear, and other such options.

[0095] In at least one embodiment, a training dataset is used to train an untrained neural network. In at least one embodiment, the training framework is PyTorch, Tensorflow, Boost, Caffe, Microsoft CognitiveToolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or another training framework. In at least one embodiment, the training framework trains the untrained neural network and enables it to be trained using the processing resources described herein to generate a trained neural network. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0096] In at least one embodiment, supervised learning is used to train an untrained neural network, wherein the training dataset comprises inputs paired with desired outputs for input, or wherein the training dataset comprises inputs with known outputs and the neural network is manually graded outputs. In at least one embodiment, the untrained neural network is trained in a supervised manner to process inputs from the training dataset and compare the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network. In at least one embodiment, the training framework adjusts the weights controlling the untrained neural network. In at least one embodiment, the training framework includes tools for monitoring the degree to which the untrained neural network converges to the model, such as a trained neural network adapted to generate correct answers, such as results, based on known input data, such as new data. In at least one embodiment, the training framework repeatedly trains the untrained neural network while adjusting the weights to improve the output of the untrained neural network using a loss function and tuning algorithms, such as stochastic gradient descent. In at least one embodiment, the training framework trains the untrained neural network until the untrained neural network reaches the desired accuracy. In at least one embodiment, the trained neural network can then be deployed to perform any number of machine learning operations.

[0097] In at least one embodiment, unsupervised learning is used to train an untrained neural network, wherein the untrained neural network attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network can learn groupings within the training dataset and can determine how each input relates to the untrained dataset. In at least one embodiment, unsupervised training can be used to generate self-organizing graphs, a type of trained neural network capable of performing operations useful for reducing the dimensionality of new data. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in a new dataset that deviate from the normal patterns of the new dataset.

[0098] In at least one embodiment, semi-supervised learning can be used, a technique in which the training dataset includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network to adapt to new data without forgetting the knowledge injected into the network during initial training.

[0099] Reasoning and training logic

[0100] Figure 9AThe diagram illustrates inference and / or training logic 915 for performing inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Provide details about reasoning and / or training logic 915.

[0101] In at least one embodiment, inference and / or training logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters, to configure neurons or layers of a neural network trained and / or used for inference in one or more aspects of the embodiments. In at least one embodiment, training logic 915 may include or be coupled to code and / or data storage 901 to store graphical code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graphical code loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, code and / or data storage 901 stores input / output data and / or weight parameters during forward propagation of the neural network trained or used in one or more embodiments, in conjunction with weight parameters and / or input / output data of each layer of the neural network. In at least one embodiment, any portion of the code and / or data storage 901 may be included in other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0102] In at least one embodiment, any portion of the code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 901 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (such as flash memory), or other memory. In at least one embodiment, whether the code and / or data storage 901 is internal or external to the processor, for example, or constitutes DRAM, SRAM, flash memory, or certain other memory types, the choice may depend on the available on-chip and off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used for inference and / or training the neural network, or some combination of these factors.

[0103] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, code and / or data storage 905 to store backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network used for training and / or inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, the code and / or data storage 905 stores weight parameters and / or input / output data of each layer of the neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 915 may include or be coupled to the code and / or data storage 905 to store graphical code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graphical code loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of the code and / or data storage 905 may be included in other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 905 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the choice of whether the code and / or data storage 905 is internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other memory type, may depend on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used for inference and / or training the neural network, or some combination of these factors.

[0104] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including processor L1, L2, or L3 caches or system memory.

[0105] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910, including integer and / or floating-point units, for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graphical code), the results of which may lead to activations (e.g., output values ​​of neural network layers or neurons) stored in activation storage 920, which are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, the activation stored in activation storage 920 is generated based on linear algebra and / or matrix-based mathematics performed by one or more ALUs 910 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 905 and / or code and / or data storage 901, along with other values, are used as operands, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, wherein any or all of these may be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip memory.

[0106] In at least one embodiment, one or more ALUs 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processor or other hardware logic device or the circuitry using them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 910 may be included in the execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be in the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included together with other on-chip or off-chip data memory, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be extracted and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0107] In at least one embodiment, the active memory 920 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 920 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 920 is internal or external to the processor may depend on the availability of on-chip and off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used for inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or some other memory type. In at least one embodiment, Figure 9A The inference and / or training logic 915 shown can be used with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU), or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9A The inference and / or training logic 915 shown can be used with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware such as field programmable gate array (“FPGA”) .

[0108] Figure 9B Inference and / or training logic 915 according to at least one or more embodiments is illustrated. In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, hardware logic, wherein computational resources are dedicated to or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, Figure 9B The inference and / or training logic 915 shown can be used with application-specific integrated circuits (ASICs), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU), or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9BThe inference and / or training logic 915 shown can be used with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field-programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graphical code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 9B In at least one embodiment shown, each of code and / or data storage 901 and code and / or data storage 905 is associated with dedicated computing resources (e.g., computing hardware 902 and computing hardware 906). In at least one embodiment, each of computing hardware 902 and computing hardware 906 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on information stored in code and / or data storage 901 and code and / or data storage 905, respectively, with the results stored in active storage 920.

[0109] In at least one embodiment, each of the code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of the neural network, such that activations obtained from a “store / computation pair 901 / 902” of the code and / or data storage 901 and computing hardware 902 are provided as input to a “store / computation pair 905 / 906” of the code and / or data storage 905 and computing hardware 906 to reflect the conceptual organization of the neural network. In at least one embodiment, each of the storage / computation pairs 901 / 902 and 905 / 906 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) performed after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906 may be included in the inference and / or training logic 915.

[0110] Data Center

[0111] Figure 10 An example data center 1000 is shown, in which at least one embodiment can be used. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0112] In at least one embodiment, such as Figure 10As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources (“nodes CR”) 1016(1)-1016(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 1016(1)-1016(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1016(1)-1016(N) may be servers having one or more of the aforementioned computing resources.

[0113] In at least one embodiment, the grouped computing resources 1014 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. The individual groups of node CRs within the grouped computing resources 1014 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0114] In at least one embodiment, resource coordinator 1012 may be configured or otherwise control one or more nodes CR1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may include a Software Design Infrastructure (“SDI”) management entity for data center 1000. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0115] In at least one embodiment, such as Figure 10As shown, framework layer 1020 includes job scheduler 1022, configuration manager 1024, resource manager 1026, and distributed file system 1028. In at least one embodiment, framework layer 1020 may include a framework of software 1032 supporting software layer 1030 and / or one or more applications 1042 supporting application layer 1040. In at least one embodiment, software 1032 or one or more applications 1042 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1020 may be, but is not limited to, a free and open-source software web application framework type, such as Apache Spark™ (hereinafter referred to as "Spark") which can utilize distributed file system 1028 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1022 may include Spark drivers to facilitate the scheduling of workloads supported by the various layers of data center 1000. In at least one embodiment, configuration manager 1024 may be able to configure different layers, such as software layer 1030 and framework layer 1020 including Spark and distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, resource manager 1026 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1028 and job scheduler 1022. In at least one embodiment, cluster or group computing resources may include grouped computing resources 1014 on data center infrastructure layer 1010. In at least one embodiment, resource manager 1026 may coordinate with resource coordinator 1012 to manage these mapped or allocated computing resources.

[0116] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least a portion of nodes CR1016(1)-1016(N), grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. One or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0117] In at least one embodiment, the application layer 1040 may include one or more applications 1042 that can be used by at least a portion of nodes CR1016(1)-1016(N), grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0118] In at least one embodiment, any of the configuration manager 1024, resource manager 1026, and resource coordinator 1012 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1000 and can prevent underutilization and / or poor performance of the data center.

[0119] In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1000. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1000, by using weight parameters calculated through one or more training techniques described herein.

[0120] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0121] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 10 In use, at least in part, the operation is inferred or predicted based on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0122] In at least one embodiment, such a component can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0123] Computer System

[0124] Figure 11 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof 1100 formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, the computer system 1100 may include, but is not limited to, components such as processor 1102, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, the computer system 1100 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon™ XScale™ and / or StrongARM™ Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0125] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0126] In at least one embodiment, computer system 1100 may include, but is not limited to, processor 1102, which may include, but is not limited to, one or more execution units 1108, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, but in another embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to processor bus 1110, which can transmit data signals between processor 1102 and other components in computer system 1100.

[0127] In at least one embodiment, processor 1102 may include, but is not limited to, a level-one (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache memory or multiple levels of internal cache memory. In at least one embodiment, the cache memory may reside external to processor 1102. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0128] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1102. In at least one embodiment, the processor 1102 may also include microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packaged instruction set 1109. In at least one embodiment, by including the packaged instruction set 1109 in the instruction set of the general-purpose processor 1102, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1102 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0129] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other storage device. In at least one embodiment, memory 1120 may store one or more instructions 1119 and / or data 1121 represented by data signals that can be executed by processor 1102.

[0130] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1116 may initiate data signals between processor 1102, memory 1120, and other components in computer system 1100, and bridge data signals between processor bus 1110, memory 1120, and system I / O 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 can be coupled to memory 1120 via high-bandwidth memory path 1118, and graphics / video card 1112 can be coupled to MCH 1116 via Accelerated Graphics Port (“AGP”) interconnect 1114.

[0131] In at least one embodiment, computer system 1100 may use system I / O 1122 as a proprietary hub interface bus to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, data storage 1124, a conventional I / O controller 1123 and keyboard interface 1125 containing user input, a serial expansion port 1127 (e.g., Universal Serial Bus (USB)), and a network controller 1134. Data storage 1124 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0132] In at least one embodiment, Figure 11 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 11An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, the device may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1100 are interconnected using a compute fast link (CXL) interconnect.

[0133] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. (The following is in conjunction with...) Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can... Figure 11 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0134] In at least one embodiment, the component can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0135] Figure 12 This is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0136] In at least one embodiment, system 1200 may include, but is not limited to, processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 uses a bus or interface coupling, such as an I2C bus, system management bus (“SMBus”), low pin count (LPC) bus, serial peripheral interface (“SPI”), high-definition audio (“HDA”) bus, serial advanced technology accessory (“SATA”) bus, universal serial bus (“USB”) (versions 1, 2, and 3), or universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 12 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 12 An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, Figure 12 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0137] In at least one embodiment, Figure 12 It may include a display 1224, a touch screen 1225, a touchpad 1230, a near field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash (“BIOS, FW Flash”) 1222, a DSP 1260, a drive (“SSD” or “HDD”) 1220 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”) 1250), a wireless LAN unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) 1255, and a camera (“USB 3.0 camera”) 1254 (e.g., USB). 3.0 camera) and / or low-power double data rate (“LPDDR”) memory cells (“LPDDR3”) 1215 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0138] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components discussed above. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1246, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1264 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250, Bluetooth unit 1252, and WWAN unit 1256 can be implemented as next-generation form factor (NGFF).

[0139] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 12 It is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network use cases described herein.

[0140] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0141] Figure 13 A computer system 1300 according to at least one embodiment is shown. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described throughout this disclosure.

[0142] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit (“CPU”) 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or one or more point-to-point communication protocols. In at least one embodiment, the computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1304 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1322 provides an interface to other computing devices and networks for receiving data from the computer system 1300 and transferring data to other systems.

[0143] In at least one embodiment, the computer system 1300 includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0144] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 13 It is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network use cases described herein.

[0145] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0146] Figure 14 A computer system 1400 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1400 includes, but is not limited to, a computer 1410 and a USB flash drive 1420. In at least one embodiment, the computer 1410 may include, but is not limited to, any number and type of one or more processors (not shown) and memory (not shown). In at least one embodiment, the computer 1410 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0147] In at least one embodiment, the USB stick 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1430 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1430 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0148] In at least one embodiment, the USB interface 1440 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0C receptacle for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0A connector. In at least one embodiment, the USB interface logic 1450 may include any amount and type of logic enabling the processing unit 1430 to connect to a device (e.g., computer 1410) via the USB connector 1440.

[0149] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 14 In use, at least in part, the operation is inferred or predicted based on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0150] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0151] Figure 15A An exemplary architecture is shown in which multiple GPUs 1510-1513 are communicatively coupled to multiple multi-core processors 1505-1506 via high-speed links 1540-1543 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 1540-1543 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0152] Furthermore, in one embodiment, two or more GPUs 1510-1513 are interconnected via high-speed links 1529-1530, which can be implemented using the same or different protocols / links as those used for high-speed links 1540-1543. Similarly, two or more multi-core processors 1505-1506 can be connected via high-speed link 1528, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, in Figure 15A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., through a common interconnect structure).

[0153] In one embodiment, each of the multi-core processors 1505-1506 is communicatively coupled to processor memory 1501-1502 via memory interconnects 1526-1527, and each of the GPUs 1510-1513 is communicatively coupled to GPU memory 1520-1523 via GPU memory interconnects 1550-1553. Memory interconnects 1526-1527 and 1550-1553 may use the same or different memory access technologies. For example, and not limitingly, processor memory 1501-1502 and GPU memory 1520-1523 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3DXPoint or Nano-RAM. In one embodiment, some portions of processor memory 1501-1502 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0154] As described below, although the various processors 1505-1506 and GPUs 1510-1513 can be physically coupled to specific memories 1501-1502 and 1520-1523 respectively, a unified memory architecture can be achieved, in which the same virtual system address space (also known as the "effective address" space) is distributed across the various physical memories. For example, processor memories 1501-1502 can each contain 64GB of system memory address space, while GPU memories 1520-1523 can each contain 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0155] Figure 15B Additional details are shown regarding the interconnection between a multi-core processor 1507 and a graphics acceleration module 1546 according to an exemplary embodiment. The graphics acceleration module 1546 may include one or more GPU chips integrated on a line card coupled to the processor 1507 via a high-speed link 1540. Alternatively, the graphics acceleration module 1546 may be integrated on the same package or chip as the processor 1507.

[0156] In at least one embodiment, the processor 1507 shown includes a plurality of cores 1560A-1560D, each having a translation back buffer 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components for executing instructions and processing data (not shown). Caches 1562A-1562D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 1556 may be included in caches 1562A-1562D and shared by the set of cores 1560A-1560D. For example, one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. Processor 1507 and graphics acceleration module 1546 are connected to system memory 1514, which may include Figure 15A The processor memory is 1501-1502.

[0157] Maintaining consistency of data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 is achieved through inter-core communication on the coherence bus 1564. For example, each cache may have associated cache coherence logic / circuit to communicate with the coherence bus 1564 in response to detected reads or writes to a specific cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 1564 to listen for cache accesses.

[0158] In one embodiment, proxy circuitry 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, allowing graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. Specifically, interface 1535 provides connectivity to proxy circuitry 1525 via high-speed link 1540 (e.g., PCIe bus, NVLink, etc.), and interface 1537 connects graphics acceleration module 1546 to link 1540.

[0159] In one embodiment, accelerator integrated circuit 1536 represents multiple graphics processing engines 1531, 1532, N of graphics acceleration module 1546 to provide cache management, memory access, context management, and interrupt management services. Graphics processing engines 1531, 1532, N may each include a separate graphics processing unit (GPU). Alternatively, graphics processing engines 1529, 1532, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and bit-block transfer engines. In at least one embodiment, graphics acceleration module 1546 may be a GPU with multiple graphics processing engines 1531-1532, N, or graphics processing engines 1531-1532, N may be a single GPU integrated on a common package, line card, or chip.

[0160] In one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 1514. The MMU 1539 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one embodiment, cache 1538 stores commands and data effectively accessed by graphics processing engines 1529-1532, N. In one embodiment, data stored in cache 1538 and graphics memories 1533-1534, M are consistent with core caches 1562A-1562D, 1556 and system memory 1514. As described above, this can be accomplished by proxy circuitry 1525 representing cache 1538 and memories 1533-1534, M (e.g., sending updates to cache 1538 related to modifications / accesses to cache lines on processor caches 1562A-1562D, 1556, and receiving updates from cache 1538).

[0161] A set of registers 1545 stores context data for threads executed by graphics processing engines 1531-1532, N, and context management circuitry 1548 manages the thread context. For example, context management circuitry 1548 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1548 can store the current register value to a designated area in memory (e.g., identified by a context indicator). Then, when returning to the context, it can restore the register value. In one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0162] In one implementation, virtual / effective addresses from graphics processing engine 1531 are translated by MMU 1539 into real / physical addresses in system memory 1514. One embodiment of accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. Graphics accelerator module 1546 may be dedicated to a single application executing on processor 1507, or it may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is proposed, in which the resources of graphics processing engines 1531-1532, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” that are allocated to different VMs and / or applications based on the processing needs and priorities associated with the VMs and / or applications.

[0163] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system for the graphics acceleration module 1546 and provides address translation and system memory caching services. Furthermore, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage the virtualization of graphics processing engines 1531-1532, N, interrupts, and memory management.

[0164] Because the hardware resources of graphics processing engines 1531-1532, N are explicitly mapped to the real address space visible to the host processor 1507, any host processor can directly process these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1536 is the physical separation of graphics processing engines 1531-1532, N, making them independent units in the system.

[0165] In at least one embodiment, one or more graphics memories 1533-1534, M are coupled to each graphics processing engine 1531-1532, N, respectively. Graphics memories 1533-1534, M store instructions and data processed by each graphics processing engine 1531-1532, N. Graphics memories 1533-1534, M may be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3DXPoint or Nano-RAM.

[0166] In one embodiment, to reduce data traffic on link 1540, a biasing technique is used to ensure that the data stored in graphics memories 1533-1534, M is the most frequently used data by graphics processing engines 1531-1532, N, and preferably data that is not used by cores 1560A-1560D (at least infrequently). Similarly, the biasing mechanism attempts to store the data required by the cores (and preferably not graphics processing engines 1531-1532, N) in caches 1562A-1562D, 1556 of the core and system memory 1514.

[0167] Figure 15C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1536 is integrated into the processor 1507. At least in this embodiment, the graphics processing engines 1531-1532, N communicate directly with the accelerator integrated circuit 1536 via high-speed link 1540 through interfaces 1537 and 1535 (again, any form of bus or interface protocol can be used). The accelerator integrated circuit 1536 can perform operations related to… Figure 15B The operation described herein is the same, but may have higher throughput due to its proximity to the coherence bus 1564 and caches 1562A-1562D, 1556. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1536 and a programming model controlled by graphics acceleration module 1546.

[0168] In at least one embodiment, graphics processing engines 1531-1532, N are dedicated to a single application or process within a single operating system. In at least one embodiment, a single application can pass requests from other applications to graphics processing engines 1531-1532, N, thereby providing virtualization within a VM / partition.

[0169] In at least one embodiment, graphics processing engines 1531-1532, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1531-1532, N to allow each operating system to access them. For a single-partition system without a hypervisor, graphics processing engines 1531-1532, N belong to the operating system. In at least one embodiment, the operating system can virtualize graphics processing engines 1531-1532, N to provide access to each process or application.

[0170] In at least one embodiment, the graphics acceleration module 1546 or a single graphics processing engine 1531-1532, N uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1514 and can be addressed using the translation technique described herein to convert effective addresses to real addresses. In at least one embodiment, the process handle, when registering its context with the graphics processing engines 15231-1532, N (i.e., calling system software to add the process element to the process element linked list), may be an implementation-specific value provided to the host process. In at least one embodiment, the lower 16 bits of the process handle may be an offset of the process element in the process element linked list.

[0171] Figure 15D An exemplary accelerator integration slice 1590 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1536. The application's effective address space 1582 in system memory 1514 stores process elements 1583. In one embodiment, process element 1583 responds to a GPU call 1581 from an application 1580 executing on processor 1507. Process element 1583 contains the processing state corresponding to application 1580. A job descriptor (WD) 1584 contained in process element 1583 may be a single job requested by the application or may contain pointers to job queues. In at least one embodiment, WD 1584 is a pointer to a job request queue in the application's address space 1582.

[0172] The graphics acceleration module 1546 and / or the various graphics processing engines 1531-1532, N can be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure for setting process states and sending WD1584 to the graphics acceleration module 1546 to initiate jobs in a virtualized environment may be included.

[0173] In at least one embodiment, a dedicated process programming model is specifically implemented. In this model, a single process owns either a graphics acceleration module 1546 or a single graphics processing engine 1531. Because the graphics acceleration module 1546 is owned by a single process, when the graphics acceleration module 1546 is allocated, the management program initializes the accelerator integrated circuit 1536 for the owned partition, and the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0174] During operation, the WD fetch unit 1591 in the accelerator integrated slice 1590 fetches the next WD 1584, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. Data from the WD 1584 can be stored in register 1545 and used by the illustrated MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548. For example, one embodiment of the MMU 1539 includes segment / page roaming circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. The interrupt management circuitry 1547 can handle interrupt events 1592 received from the graphics acceleration module 1546. When performing graphics operations, the MMU 1539 translates the effective address 1593 generated by the graphics processing engines 1531-1532,N into a real address.

[0175] In one embodiment, a set of identical registers 1545 is copied for each graphics processing engine 1531-1532, N, and / or graphics acceleration module 1546, and can be initialized by a hypervisor or operating system. Each of these duplicated registers can be included in the accelerator integration slice 1590. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0176] Table 1: Management Program Initialization Registers

[0177]

[0178] Example registers that can be initialized by the operating system are shown in Table 2.

[0179] Table 2 - Operating System Initialization Registers

[0180]

[0181] In one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531-1532, N. It contains all the information required for the graphics processing engine 1531-1532, N to complete its work, or it may be a pointer to a memory location of a queue of commands for tasks that the application sets to complete.

[0182] Figure 15E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1598 in which a list of process elements 1599 is stored. The hypervisor real address space 1598 can be accessed by a hypervisor 1596, which is a virtualized graphics acceleration module engine for an operating system 1595.

[0183] In at least one embodiment, the shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 1546. There are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions: time-slice sharing and graphics-oriented sharing.

[0184] In this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. For the graphics acceleration module 1546 to support virtualization through the hypervisor 1596, the graphics acceleration module 1546 can comply with the following: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 1546 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 1546 guarantees that application job requests are completed within a specified time, including any transition failures, or the graphics acceleration module 1546 provides the ability to pre-process jobs; 3) When operating in a directed shared programming model, the graphics acceleration module 1546 must guarantee fairness between processes.

[0185] In at least one embodiment, application 1580 requires operating system 1595 system calls using graphics acceleration module 1546 type, working descriptor (WD), authorization mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, graphics acceleration module 1546 type describes the target acceleration function for the system call. In at least one embodiment, graphics acceleration module 1546 type can be a system-specific value. In at least one embodiment, WD is specifically formatted for graphics acceleration module 1546 and can be a graphics acceleration module 1546 command, a valid address pointer to a user-defined structure, a valid address pointer to an instruction queue, or any other data structure describing the work to be performed by graphics acceleration module 1546. In one embodiment, AMR value is the AMR state to be used for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application setting the AMR. If the accelerator integrated circuit 1536 and graphics acceleration module 1546 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1596 may optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into process element 1583. In at least one embodiment, CSRP is one of registers 1545 containing the effective address of a region in the application's effective address space 1582, used by graphics acceleration module 1546 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job has been preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0186] Upon receiving a system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. The operating system 1595 then calls the hypervisor 1596, whose information is shown in Table 3.

[0187] Table 3 - Call parameters from OS to management program

[0188]

[0189] Upon receiving the hypervisor call, hypervisor 1596 verifies that operating system 1595 has been registered and granted permission to use graphics acceleration module 1546. Hypervisor 1596 then adds process element 1583 to the linked list of process elements of the corresponding graphics acceleration module 1546 type. The process element may include the information shown in Table 4.

[0190] Table 4: Process Element Information

[0191]

[0192]

[0193] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1590 registers 1545.

[0194] like Figure 15F As shown, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space for accessing physical processor memories 1501-1502 and GPU memories 1520-1523. In this implementation, operations performed on GPUs 1510-1513 utilize the same virtual / effective memory address space to access processor memories 1501-1502, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501, a second portion to second processor memory 1502, a third portion to GPU memory 1520, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each processor memory 1501-1502 and GPU memory 1520-1523, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0195] In one embodiment, one or more bias / coherence management circuits 1594A-1594E of the MMU 1539A-1539E ensure cache coherence between the caches of one or more host processors (e.g., 1505) and the GPUs 1510-1513, and implement biasing techniques that indicate the physical memory where certain types of data should be stored. Meanwhile... Figure 15F Several examples of bias / coherence management circuits 1594A-1594E are shown. The bias / coherence circuits can be implemented within the MMU of one or more host processors 1505, and / or within the accelerator integrated circuit 1536.

[0196] One embodiment allows GPU-attached memory 1520-1523 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without incurring the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU-attached memory 1520-1523 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 1505 software to set operands and access computation results without the overhead of conventional I / O DMA data copying. This conventional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory access. In at least one embodiment, the ability to access GPU-attached memory 1520-1523 without cache coherence overhead is critical to the execution time of offloading computations. For example, in situations with high streaming memory write traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1510-1513. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0197] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. A bias table can be used, for example, which may be a page-granular structure (i.e., controlled at the granularity of memory pages), where each GPU-attached memory page contains 1 or 2 bits. In at least one embodiment, the bias table can be implemented within the stolen memory range of one or more GPU-attached memories 1520-1523, with a bias-free cache (e.g., caching frequently / recently used entries of the bias table) in GPUs 1510-1513. Alternatively, the entire bias table can be maintained within the GPU.

[0198] In at least one embodiment, accessing the bias table entries associated with each access to GPU-attached memory 1520-1523 before actually accessing GPU memory results in the following operations: First, local requests from GPUs 1510-1513 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memory 1520-1523. Local requests from GPUs that find their pages in the host bias are forwarded to processor 1505 (e.g., via the high-speed link described above). In one embodiment, a request from processor 1505 that finds the requested page in the host processor bias completes the same request as a normal memory read. Alternatively, requests for GPU biased pages can be forwarded to GPUs 1510-1513. In at least one embodiment, if the GPU is not currently using the page, the GPU can switch the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0199] One mechanism for changing the bias state uses API calls (e.g., OpenCL), which in turn invoke the GPU's device driver, which in turn sends messages (or queued command descriptors) to the GPU instructing it to change the bias state, and, for certain transitions, performs a cache refresh operation in the host. In at least one embodiment, the cache refresh operation is used for transitions from host processor 1505 bias to GPU bias, but not for the reverse transition.

[0200] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that the host processor 1505 cannot cache. To access these pages, the processor 1505 can request access from the GPU 1510, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1505 and the GPU 1510, it is best to ensure that the GPU-biased pages are those needed by the GPU, not those needed by the host processor 1505, and vice versa.

[0201] The inference and / or training logic 915 is used to execute one or more implementations. The following will combine... Figure 9A and / or Figure 9B Provide details about reasoning and / or training logic 915.

[0202] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0203] Figure 16The document illustrates exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to those shown, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0204] Figure 16 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may also include an image processor 1615 and / or a video processor 1620, any of which can be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral logic or bus logic, including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I... 2 S / I 2 C controller 1640. In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more High Definition Multimedia Interface (HDMI) controllers 1650 and Mobile Industrial Processor Interface (MIPI) display interfaces 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660 including flash memory and a flash memory controller. In at least one embodiment, a memory interface for accessing SDRAM or SRAM memory devices may be provided via memory controller 1665. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0205] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in integrated circuit 1600 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0206] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0207] Figures 17A-17BExemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores are illustrated according to various embodiments described herein. In addition to those shown, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0208] Figures 17A-17B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 17A An exemplary graphics processor 1710 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 17B Further exemplary graphics processor 1740 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 17A The graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1710, 1740 may be... Figure 16 A variant of the 1610 graphics processor.

[0209] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D to 1715N-1 and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic, such that the vertex processor 1705 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for either the fragment or pixel shader program. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1715A-1715N use the primitive and vertex data generated by the vertex processor 1705 to generate a framebuffer for display on a display device. In at least one embodiment, one or more fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0210] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more cache memories 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-to-physical address mappings for the graphics processor 1710, including for vertex processors 1705 and / or fragment processors 1715A-1715N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B can be synchronized with other MMUs within the system, including with... Figure 16 One or more application processors 1605, graphics processors 1615, and / or video processors 1620 are associated with one or more MMUs, enabling each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0211] In at least one embodiment, the graphics processor 1740 includes Figure 17A The graphics processor 1710 includes one or more MMUs 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N-1 and 1755N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1755A-1755N and a tile unit 1758 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0212] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 may be integrated into an integrated circuit. Figure 17A and / or Figure 17B The method is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0213] In at least one embodiment, the component can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0214] Figures 18A-18B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 18A It shows that it can be included in Figure 16 The graphics core 1800 within the graphics processor 1610, in at least one embodiment, may be... Figure 17B The unified shader cores are 1755A and 1755N. Figure 18B A highly parallel general-purpose graphics processing unit 1830 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0215] In at least one embodiment, the graphics core 1800 includes a shared instruction cache memory 1802, texture units 1818, and cache / shared memory 1820, which are common to execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1800. Slices 1801A-1801N may include supporting logic, including local instruction cache memories 1804A-1804N, thread schedulers 1806A-1806N, thread dispatchers 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFU 1812A-1812N), floating-point units (FPU 1814A-1814N), integer arithmetic logic units (ALU 1816A-1816N), address calculation units (ACU 1813A-1813N), double-precision floating-point units (DPFPU1815A-1815N), and matrix processing units (MPU 1817A-1817N).

[0216] In at least one embodiment, the FPU 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1812A-1812N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0217] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in the graphics core 1800 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0218] In at least one embodiment, the component can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0219] Figure 18BA general-purpose processing unit (GPGPU) 1830 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a graphics processing unit array. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 to assign the execution threads associated with those commands to a group of compute clusters 1836A-1836H. In at least one embodiment, the compute clusters 1836A-1836H share cache memory 1838. In at least one embodiment, cache memory 1838 can be used as an advanced cache of cache memory within computing clusters 1836A-1836H.

[0220] In at least one embodiment, the GPGPU 1830 includes memory 1844A-1844B coupled to the computing cluster 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memory 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0221] In at least one embodiment, computing clusters 1836A-1836H each include a set of graphics cores, such as Figure 18A The graphics core 1800 may include various types of integer and floating-point logic units, which can perform computational operations within a precision range suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0222] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, the communication used for synchronization and data exchange by the compute clusters 1836A-1836H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU link 1840, enabling direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization among the multiple instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 1830 reside in a separate data processing system and communicate via a network device accessible via the host interface 1832. In at least one embodiment, GPU link 1840 may be configured to connect to a host processor, supplementing or replacing host interface 1832.

[0223] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment where the GPGPU 1830 is used for inference, the GPGPU may include fewer compute clusters 1836A-1836H compared to when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B can differ between inference and training configurations, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0224] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 may be used in the GPGPU 1830 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases as described herein.

[0225] In at least one embodiment, the component can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0226] Figure 19 This is a block diagram illustrating a computing system 1900 according to at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset assembly or may be integrated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that enables the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 may enable a display controller, which is included in one or more processors 1902, for providing output to one or more display devices 1910A. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0227] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to a memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may be one of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1912 form a computationally concentrated parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 1912 form a graphics processing subsystem capable of outputting pixels to one or more display devices 1910A coupled via an I / O hub 1907. In at least one embodiment, the one or more parallel processors 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B.

[0228] In at least one embodiment, system storage unit 1914 may be connected to I / O hub 1907 to provide a storage mechanism for computing system 1900. In at least one embodiment, I / O switch 1916 may be used to provide an interface mechanism to enable connectivity between I / O hub 1907 and other components, such as network adapter 1918 and / or wireless network adapter 1919 which may be integrated into one or more platforms, and various other devices that may be added via one or more add-on devices 1920. In at least one embodiment, network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1919 may include one or more Wi-Fi, Bluetooth, near field communication (NFC), or other network devices comprising one or more radios.

[0229] In at least one embodiment, the computing system 1900 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 1907. In at least one embodiment, for Figure 19 The communication paths that interconnect the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocols (e.g., NV-Link High-Speed ​​Interconnect or Interconnect Protocol).

[0230] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, a memory hub 1905, one or more processors 1902, and an I / O hub 1907 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1900 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system.

[0231] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in system diagram 1900 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0232] In at least one embodiment, the component can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0233] processor

[0234] Figure 20A A parallel processor 2000 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is according to exemplary embodiments. Figure 19 The variant of the 1912, which includes one or more parallel processors, is shown.

[0235] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 can be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices using a hub or switch interface (e.g., a memory hub 1905). In at least one embodiment, the connection between the memory hub 1905 and the I / O unit 2004 forms a communication link 1913. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, wherein the host interface 2006 receives commands for performing processing operations, and the memory crossbar switch 2016 receives commands for performing memory operations.

[0236] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to assign commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is correctly configured and in an active state before assigning tasks to processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and environment switching of threads executing on processing array 2012. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2012 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0237] In at least one embodiment, the processing cluster array 2012 may include up to "N" processing clusters (e.g., clusters 2014A, 2014B to 2014N). In at least one embodiment, each cluster 2014A-2014N of the processing cluster array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A-2014N of the processing cluster array 2012, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of the processing cluster array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0238] In at least one embodiment, the processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0239] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory.

[0240] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2014A-2014N of the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0241] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be executed via a scheduler 2010, which receives commands defining the processing tasks from a front end 2008. In at least one embodiment, the processing task may include an index of data to be processed, surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0242] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 may be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar switch 2016, which may receive memory requests from the processing cluster array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar switch 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition units 2020A, 2020B to 2020N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2022. In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding memory unit 2024B, and the Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0243] In at least one embodiment, memory cells 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2024A-2024N may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM). In at least one embodiment, rendering targets such as framebuffers or texture maps may be stored across memory cells 2024A-2024N, allowing partitioning cells 2020A-2020N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0244] In at least one embodiment, any of the clusters 2014A-2014N of the processing cluster array 2012 can process data to be written to any memory cell 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar switch 2016 can be configured to transfer the output of each cluster 2014A-2014N to any partition cell 2020A-2020N or another cluster 2014A-2014N, and the clusters 2014A-2014N can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with the memory interface 2018 via the memory crossbar switch 2016 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2016 has a connection to the memory interface 2018 for communication with the I / O unit 2004, and a connection to a local instance of the parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to the parallel processing unit 2002. In at least one embodiment, the memory crossbar switch 2016 may use a virtual channel to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0245] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2002 or the parallel processor 2000 can be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0246] Figure 20B This is a block diagram of a partitioning unit 2020 according to at least one embodiment. In at least one embodiment, the partitioning unit 2020 is... Figure 20AAn example of one of the partition units 2020A-2020N. In at least one embodiment, partition unit 2020 includes L2 cache memory 2021, frame buffer interface 2025, and raster operation unit (“ROP”) 2026. L2 cache memory 2021 is a read / write cache configured to perform load and store operations received from memory crossbar switch 2016 and ROP 2026. In at least one embodiment, L2 cache memory 2021 outputs read miss and urgent write-back requests to frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via frame buffer interface 2025. In at least one embodiment, frame buffer interface 2025 interacts with one of the memory cells in parallel processor memory (such as memory cells 2024A-2024N of FIG. 20 (e.g., within parallel processor memory 2022)).

[0247] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. The compression logic performed by ROP 2026 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0248] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., Figure 20A Clusters 2014A-2014N are used instead of partition units 2020. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2016 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 19 One or more display devices 1910) display, routed by processor 1902 for further processing, or by Figure 20A One of the processing entities within the parallel processor 2000 is routed for further processing.

[0249] Figure 20C This is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 20AAn instance of one of the processing clusters 2014A-2014N. In at least one embodiment, one or more processing clusters 2014 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issuing technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, Single Instruction Multiple Threading (SIMT) technology is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0250] In at least one embodiment, the operation of the processing cluster 2014 can be controlled by a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032... Figure 20A The scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2014 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2014 may include one or more instances of the graphics multiprocessor 2034. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data crossover switch 2040 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2040.

[0251] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0252] In at least one embodiment, instructions sent to the processing cluster 2014 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2034.

[0253] In at least one embodiment, the graphics multiprocessor 2034 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo the internal cache and use cache memory within the processing cluster 2014 (e.g., L1 cache memory 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access partition units (e.g., Figure 20A The L2 cache is located within partition units 2020A-2020N, ​​which are shared among all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2014 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache memory 2048.

[0254] In at least one embodiment, each processing cluster 2014 may include a memory management unit (“MMU”) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside in Figure 20A The memory interface 2018 is included. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of blocks and optionally to cache line indexes.

[0255] In at least one embodiment, MMU 2045 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034 or the L1 cache or the processing cluster 2014.

[0256] In at least one embodiment, physical addresses are processed to allocate surface data access locality in order to enable efficient request interleaving between partition units. In at least one embodiment, cache line indexes can be used to determine whether a request for a cache line is a hit or a miss.

[0257] In at least one embodiment, the processing cluster 2014 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs a processed task to a data crossbar switch 2040 to provide one or more processed tasks to another processing cluster 2014 for further processing or to store one or more processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2016. In at least one embodiment, a preROP 2042 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which may be associated with a partitioning unit (e.g., ...) described herein. Figure 20A The PreROP 2042 unit is located together with the partition units 2020A-2020N. In at least one embodiment, the PreROP 2042 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0258] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in a graphics processing cluster 2014 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0259] In at least one embodiment, the component can be used to generate enhanced video using one or more neural networks, such as generating higher frame rate video from lower frame rate video frames.

[0260] Figure 20D A graphics multiprocessor 2034 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2034 is coupled to a pipeline manager 2032 of a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline including, but not limited to, an instruction cache memory 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066. The one or more GPGPU cores 2062 and one or more load / store units 2066 are coupled to cache memory 2072 and shared memory 2070 via a memory and cache interconnect 2068.

[0261] In at least one embodiment, instruction cache memory 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache memory 2052 and dispatched for execution by instruction unit 2054. In one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread group to a different execution unit within one or more GPGPU cores 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2056 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by one or more load / store units 2066.

[0262] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2034 (e.g., GPGPU core 2062, load / store unit 2066). In at least one embodiment, register file 2058 is partitioned among each functional unit, such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is partitioned among different thread bundles being executed by graphics multiprocessor 2034.

[0263] In at least one embodiment, each of the GPGPU cores 2062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2034. The GPGPU cores 2062 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard floating-point algorithm or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0264] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0265] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network connecting each functional unit of the graphics multiprocessor 2034 to the register file 2058 and shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a cross-switch interconnect that allows the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfer between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2034. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2072, the thread executing on GPGPU core 2062 can also programmatically store data in shared memory.

[0266] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0267] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in a graphics multiprocessor 2034 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0268] In at least one embodiment, the component can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from lower frame rate video frames.

[0269] Figure 21 A multi-GPU computing system 11100 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 11100 may include a processor 11102 connected to a plurality of general-purpose graphics processing units (GPGPUs) 11106A-D via a host interface switch 11104.

[0270] In at least one embodiment, the host interface switch 11104 is a PCI fast switch device that connects processor 11102 to a PCI fast bus, through which processor 11102 can communicate with GPGPUs 11106A-D. GPGPUs 11106A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 11116. In at least one embodiment, the GPU-to-GPU links 11116 are connected to each of the GPGPUs 11106A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 11116 enable direct communication between each GPGPU 11106A-D without requiring communication via the host interface bus 11104 to which processor 11102 is connected. In at least one embodiment, through GPU-to-GPU traffic to the P2P GPU links 11116, the host interface bus 11104 can still be used for system memory access, or for communication with other instances of the multi-GPU computing system 11100, for example, via one or more network devices. Although in at least one embodiment, the GPGPU 11106A-D is connected to the processor 11102 via the host interface switch 11104, in at least one embodiment, the processor 11102 includes direct support for the P2PGPU link 11116 and can be directly connected to the GPGPU 11106A-D.

[0271] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This will be discussed below in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided together. In at least one embodiment, the inference and / or training logic 915 may be used in a multi-GPU computing system 11100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0272] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0273] Figure 22 This is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2200 is one of many processors integrated into a multi-core processing system.

[0274] In at least one embodiment, the graphics processor 2200 receives batches of commands via a ring interconnect 2202. In at least one embodiment, the incoming commands are interpreted by a command stream 2203 in a pipeline front-end 2204. In at least one embodiment, the graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via one or more graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, the command stream 2203 provides commands to the geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, the command stream 2203 provides commands to a video front-end 2234 coupled to a media engine 2237. In at least one embodiment, the media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing and a multi-format encoding / decoding (MFX) 2233 engine to provide hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate an execution thread for thread execution resources provided by at least one graphics core 2280A.

[0275] In at least one embodiment, the graphics processor 2200 includes features of scalable thread execution resources (sometimes referred to as core slices) having modular cores 2280A-2280N, each having multiple sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2200 may have any number of graphics cores 2280A to 2280N. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, the graphics processor 2200 is a low-power processor having a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes multiple graphics cores 2280A-2280N, each including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each of the first sub-cores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each of the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each sub-core 2250A-2250N and 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0276] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This will be discussed below in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in graphics processor 2200 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0277] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0278] Figure 23This is a block diagram illustrating the microarchitecture of a processor 2300 that may include logic circuitry for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2300 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2300 may include registers for storing packaged data, such as the 64-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms can operate with packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2300 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0279] In at least one embodiment, processor 2300 includes an ordered front end (“front end”) 2301 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2301 may include several units. In at least one embodiment, instruction prefetcher 2326 fetches instructions from memory and provides the instructions to instruction decoder 2328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2328 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2328 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2330 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2334 for execution. In at least one embodiment, when the trace cache 2330 encounters complex instructions, the microcode ROM 2332 provides the microinstructions required to complete the operation.

[0280] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2328. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2332. In at least one embodiment, the tracking cache 2330 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2332 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2332 has completed the micro-operation ordering of the instructions, the machine front end 2301 may resume fetching micro-operations from the tracking cache 2330.

[0281] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2303 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2303 includes, but is not limited to, an allocator / register renamer 2340, a memory microinstruction queue 2342, an integer / floating-point microinstruction queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2304, and a simple floating-point scheduler (“simple FP scheduler”) 2306. In at least one embodiment, the fast scheduler 2302, the slow / general-purpose floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to as “microinstruction schedulers 2302, 2304, 2306”. In at least one embodiment, the allocator / register renamer 2340 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2340 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2340 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2342 for memory operations and an integer / floating-point microinstruction queue 2344 for non-memory operations, preceding the memory scheduler 2346 and microinstruction schedulers 2302, 2304, and 2306. In at least one embodiment, the microinstruction schedulers 2302, 2304, and 2306 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2302 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2304 and the simple floating-point scheduler 2306 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2302, 2304, and 2306 arbitrate the scheduling port to schedule microinstructions for execution.

[0282] In at least one embodiment, execution block 2311 includes, but is not limited to, integer register file / branch network 2308, floating-point register file / branch network (“FP register file / branch network”) 2310, address generation units (“AGU”) 2312 and 2314, fast arithmetic logic units (“fast ALU”) 2316 and 2318, slow arithmetic logic unit (“slow ALU”) 2320, floating-point ALU (“FP”) 2322, and floating-point move unit (“FP move”) 2324. In at least one embodiment, integer register file / branch network 2308 and floating-point register file / bypass network 2310 are also referred to herein as “register files 2308, 2310”. In at least one embodiment, AGUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating-point ALU 2322, and floating-point movement unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324". In at least one embodiment, execution box b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0283] In at least one embodiment, register files 2308 and 2310 may be arranged between microinstruction schedulers 2302, 2304, and 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / tribute network 2308 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2310 performs floating-point operations. In at least one embodiment, each of register files 2308 and 2310 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2308 and 2310 can communicate data with each other. In at least one embodiment, integer register file / tribute network 2308 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2310 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0284] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324 can execute instructions. In at least one embodiment, register files 2308 and 2310 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2300 can be, but is not limited to, any number of execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324, and combinations thereof. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2322 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2316 and 2318. In at least one embodiment, the fast ALUs 2316 and 2318 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2320, because the slow ALU 2320 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by the AGUS 2312 and 2314. In at least one embodiment, the fast ALU 2316, fast ALU 2318, and slow ALU 2320 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2316, fast ALU 2318, and slow ALU 2320 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2322 and the floating-point movement unit 2324 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2322 and the floating-point movement unit 2324 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0285] In at least one embodiment, microinstruction schedulers 2302, 2304, and 2306 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2300, processor 2300 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0286] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0287] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into execution block 2311 and other memory or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2311. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2311 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0288] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0289] Figure 24 A deep learning application processor 2400 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2400 uses instructions, which, if executed by the deep learning application processor 2400, cause the deep learning application processor 2400 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2400 is an application-specific integrated circuit (ASIC). In at least one embodiment, the deep learning application processor 2400 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2400 includes, but is not limited to, processing clusters 2410(1)-2410(12), inter-chip links (“ICL”) 2420(1)-2420(12), inter-chip controllers (“ICC”) 2430(1)-2430(2), memory controllers (“Mem Ctrlr”) 2442(1)-2442(4), high-bandwidth memory physical layers (“HBM PHY”) 2444(1)-2444(4), management controller central processing unit (“management controller CPU”) 2450, serial peripheral interfaces, internal integrated circuits and general purpose input / output boxes (“SPI, I2C, GPIO”), peripheral component interconnect fast controllers and direct memory access blocks (“PCIe controllers and DMA”) 2470, and sixteen-channel peripheral component interconnect fast ports (“PCI Express x 16”) 2480.

[0290] In at least one embodiment, processing cluster 2410 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2400 can include any number and type of processing cluster 2400. In at least one embodiment, the inter-chip link 2420 is bidirectional. In at least one embodiment, the inter-chip link 2420 and the inter-chip controller 2430 enable multiple deep learning application processors 2400 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2400 can include any number (including zero) and type of ICL 2420 and ICC 2430.

[0291] In at least one embodiment, the HBM2 2440 provides a total of 32GB of memory. The HBM2 2440(i) is associated with both the memory controller 2442(i) and the HBM PHY 2444(i). In at least one embodiment, any number of HBM2 2440s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2442 and HBM PHY 2444. In at least one embodiment, any number and type of blocks can replace SPI, I2C, GPIO2460, PCIe controllers, and DMA 2470 and / or PCIe2480 to implement any number and type of communication standards in any technically feasible manner.

[0292] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor 2400 is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2400. In at least one embodiment, the deep learning application processor 2400 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2400.

[0293] In at least one embodiment, the processor 2400 may be used to execute one or more neural network use cases described herein.

[0294] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0295] Figure 25This is a block diagram of a neuromorphic processor 2500 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2500 may receive one or more inputs from a source external to the neuromorphic processor 2500. In at least one embodiment, these inputs may be transmitted to one or more neurons 2502 within the neuromorphic processor 2500. In at least one embodiment, the neurons 2502 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, thousands upon thousands of instances of neurons 2502, but any suitable number of neurons 2502 may be used. In at least one embodiment, each instance of a neuron 2502 may include a neuron input 2504 and a neuron output 2506. In at least one embodiment, a neuron 2502 may generate an output that can be transmitted to the inputs of other instances of the neuron 2502. In at least one embodiment, the neuron input 2504 and the neuron output 2506 may be interconnected via synapses 2508.

[0296] In at least one embodiment, neurons 2502 and synapses 2508 may be interconnected, enabling neuromorphic processor 2500 to operate to process or analyze information received by neuromorphic processor 2500.

[0297] In at least one embodiment, neuron 2502 may send an output pulse (or "trigger" or "peak") when the input received through neuron input 2504 exceeds a threshold. In at least one embodiment, neuron 2502 may sum or integrate the signal received at neuron input 2504. For example, in at least one embodiment, neuron 2502 may be implemented as a leaky integral-triggered neuron, wherein if the summation (referred to as "membrane potential") exceeds a threshold, neuron 2502 may use a transfer function such as a sigmoid or threshold function to generate an output (or "trigger"). In at least one embodiment, the leaky integral-triggered neuron may sum the signal received at neuron input 2504 to a membrane potential and may apply an attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, the leaky integral-triggered neuron may trigger if multiple input signals received at neuron input 2504 exceed a threshold quickly enough (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2502 may be implemented using circuitry or logic that receives input, integrates the input to a membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2502 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2506 when the result of applying the transfer function to neuron input 2504 exceeds a threshold. In at least one embodiment, once neuron 2502 is triggered, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2502 may resume normal operation after a suitable time period (or recovery period).

[0298] In at least one embodiment, neurons 2502 can be interconnected via synapses 2508. In at least one embodiment, synapses 2508 are operable to transmit signals from the output of a first neuron 2502 to the input of a second neuron 2502. In at least one embodiment, neurons 2502 can transmit information on more than one instance of synapses 2508. In at least one embodiment, one or more instances of neuron outputs 2506 can be connected via instances of synapses 2508 to instances of neuron inputs 2504 within the same neuron 2502. In at least one embodiment, an instance of neuron 2502 that produces an output to be transmitted on the instance of synapse 2508 may be referred to as a "presynaptic neuron". In at least one embodiment, an instance of neuron 2502 that receives input transmitted via an instance of synapse 2508 may be referred to as a "postsynaptic neuron". In at least one embodiment, regarding various instances of synapse 2508, since an instance of neuron 2502 can receive input from one or more instances of synapse 2508 and can also transmit output through one or more instances of synapse 2508, a single instance of neuron 2502 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0299] In at least one embodiment, neurons 2502 may be organized into one or more layers. Each instance of neuron 2502 may have a neuron output 2506, which can be fanned out to one or more neuron inputs 2504 via one or more synapses 2508.

[0300] In at least one embodiment, the neuron output 2506 of neuron 2502 in the first layer 2510 may be connected to the neuron input 2504 of neuron 2502 in the second layer 2512. In at least one embodiment, layer 2510 may be referred to as a "feedforward layer". In at least one embodiment, each instance of neuron 2502 in an instance of the first layer 2510 may fan out to each instance of neuron 2502 in the second layer 2512. In at least one embodiment, the first layer 2510 may be referred to as a "fully connected feedforward layer". In at least one embodiment, each instance of neuron 2502 in each instance of the second layer 2512 fan out to fewer than all instances of neuron 2502 in the third layer 2514. In at least one embodiment, the second layer 2512 may be referred to as a "sparsely connected feedforward layer". In at least one embodiment, neuron 2502 in the second layer 2512 may fan out to neurons 2502 in multiple other layers, including (the same) neurons 2502 in the second layer 2512. In at least one embodiment, the second layer 2512 may be referred to as a "recurrent layer". In at least one embodiment, the neuromorphic processor 2500 may be any suitable combination of recurrent layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0301] In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnect to connect the synapse 2508 to the neuron 2502.

[0302] In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2502 as needed, based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2508 may be connected to neurons 2502 using interconnect structures (such as on-chip networks) or via dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0303] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0304] Figure 26This is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2602 or processor cores 2607. In at least one embodiment, system 2600 is a processing platform integrated into a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0305] In at least one embodiment, system 2600 may include or be incorporated into a game console in a server-based gaming platform, including game and media game consoles, mobile game consoles, handheld game consoles, or online game consoles. In at least one embodiment, system 2600 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2600 may also include a wearable device, or be combined with or integrated into a wearable device, such as a smartwatch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphics interface generated by one or more graphics processors 2608.

[0306] In at least one embodiment, each of the one or more processors 2602 includes one or more processor cores 2607 to process instructions, which, when executed, perform operations on the system and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a specific instruction set 2609. In at least one embodiment, the instruction set 2609 may facilitate Complex Instruction Set Computing (CISC), Simplified Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2607 may process a different instruction set 2609, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor core 2607 may also include other processing devices, such as a digital signal processor (DSP).

[0307] In at least one embodiment, processor 2602 includes cache memory 2604. In at least one embodiment, processor 2602 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a Level 3 (L3) cache or a Last Level Cache (LLC)) (not shown), which can be shared among processor cores 2607 using known cache coherence techniques. In at least one embodiment, register file 2606 is additionally included in processor 2602, and processor 2602 may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2606 may include general-purpose registers or other registers.

[0308] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to transmit communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, the interface bus 2610, in one embodiment, may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2610 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, one or more processors 2602 include an integrated memory controller 2616 and a platform controller hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between memory devices and other components of the system 2600, while the platform controller hub (PCH) 2630 provides connectivity to I / O devices via a local I / O bus.

[0309] In at least one embodiment, memory device 2620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance serving as process memory. In at least one embodiment, memory device 2620 may operate as system memory of system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 execute an application or process. In at least one embodiment, memory controller 2616 is also coupled to an optional external graphics processor 2612, which may communicate with one or more graphics processors 2608 in processor 2602 to perform graphics and media operations. In at least one embodiment, display device 2611 may be connected to one or more processors 2602. In at least one embodiment, display device 2611 may include one or more internal display devices, such as in a mobile electronic device or notebook device, or an external display device connected via a display interface (e.g., a display port, etc.). In at least one embodiment, the display device 2611 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) applications or augmented reality (AR) applications.

[0310] In at least one embodiment, the platform controller hub 2630 enables peripheral devices to connect to the memory device 2620 and the processor 2602 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, a touch sensor 2625, and a data storage device 2624 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus (e.g., a peripheral component interconnect bus (e.g., PCI, PCI Express)). In at least one embodiment, the touch sensor 2625 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2626 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2628 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2634 is capable of enabling network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2610. In at least one embodiment, audio controller 2646 is a multi-channel high-definition audio controller. In at least one embodiment, system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, platform controller hub 2630 may also be connected to one or more Universal Serial Bus (USB) controllers 2642 to connect input devices, such as a combination of keyboard and mouse 2643, camera 2644, or other USB input devices.

[0311] In at least one embodiment, instances of the memory controller 2616 and the platform controller hub 2630 may be integrated to a discrete external graphics processor, such as external graphics processor 2612.

[0312] In at least one embodiment, the platform controller hub 2630 and / or memory controller 2616 may be external to one or more processors 2602. For example, in at least one embodiment, system 2600 may include an external memory controller 2616 and a platform controller hub 2630, which may be configured to communicate with a memory controller hub and a peripheral controller hub within a system chipset of one or more processors 2602.

[0313] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into graphics processor 2600. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs included in graphics processor 2612. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, except for... Figure 9A or Figure 9B The logic other than that shown is used to perform the task. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2600 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0314] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0315] Figure 27 This is a block diagram of a processor 2700 having one or more processor cores 2702A-2702N, an integrated memory controller 2714, and an integrated graphics processor 2708 according to at least one embodiment. In at least one embodiment, the processor 2700 may include cores attached to and including additional cores 2702N, indicated by dashed boxes. In at least one embodiment, each processor core 2702A-2702N includes one or more internal cache units 2704A-2704N. In at least one embodiment, each processor core may also access one or more shared cache units 2706.

[0316] In at least one embodiment, internal cache units 2704A-2704N and shared cache unit 2706 represent a cache memory hierarchy within processor 2700. In at least one embodiment, cache memory units 2704A-2704N may include at least one instruction-level and data cache within each processor core, and one or more levels of shared intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest-level cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the individual cache units 2706 and 2704A-2704N.

[0317] In at least one embodiment, the processor 2700 may further include a set of one or more bus controller units 2716 and a system agent core 2710. In at least one embodiment, one or more bus controller units 2716 manage a set of peripheral buses, such as one or more PCI or PCI express buses. In at least one embodiment, the system agent core 2710 provides management functions for various processor components. In at least one embodiment, the system agent core 2710 includes one or more integrated memory controllers 2714 to manage access to various external memory devices (not shown).

[0318] In at least one embodiment, one or more processor cores 2702A-2702N include support for concurrent multithreading. In at least one embodiment, system agent core 2710 includes components for coordinating and operating cores 2702A-2702N during multithreaded processing. In at least one embodiment, system agent core 2710 may further include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2702A-2702N and graphics processor 2708.

[0319] In at least one embodiment, processor 2700 further includes a graphics processor 2708 for performing graphics processing operations. In at least one embodiment, graphics processor 2708 is coupled to a shared cache unit 2706 and a system proxy core 2710, including one or more integrated memory controllers 2714. In at least one embodiment, system proxy core 2710 further includes a display controller 2711 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2711 may also be a separate module coupled to graphics processor 2708 via at least one interconnect, or it may be integrated into graphics processor 2708.

[0320] In at least one embodiment, a ring based on interconnect unit 2712 is used to couple the internal components of processor 2700. In at least one embodiment, optional interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2708 is coupled to ring interconnect 2712 via I / O link 2713.

[0321] In at least one embodiment, I / O link 2713 represents at least one of a variety of I / O interconnects, including in-circuit packaged I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 2718, such as an eDRAM module. In at least one embodiment, each of processor cores 2702A-2702N and graphics processor 2708 uses embedded memory module 2718 as a shared last-level cache.

[0322] In at least one embodiment, processor cores 2702A-2702N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2702A-2702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2702A-2702N execute a common instruction set, while one or more other cores of processor cores 2702A-2702N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 2702A-2702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are paired with one or more power-efficient cores with lower power consumption. In at least one embodiment, processor 2700 may be implemented on one or more chips or as a SoC integrated circuit.

[0323] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This will be discussed below in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the processor 2700. For example, in at least one embodiment, the training and / or inference techniques described herein may be embodied in the graphics processor 2612, one or more graphics cores 2702A-2702N, or... Figure 27 One or more ALUs in the other components. Furthermore, in at least one embodiment, the inference and / or training operations described herein can be used... Figure 9A or Figure 9B The logic is performed in a manner other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2700 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0324] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0325] Figure 28 This is a block diagram of the hardware logic of a graphics processor core 2800 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2800 is included within a graphics core array. In at least one embodiment, the graphics processor core 2800, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2800 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes.

[0326] In at least one embodiment, each graphics core 2800 may include a fixed function block 2830, also referred to as a sub-slice, coupled to a plurality of sub-cores 2801A-2801F, which includes module blocks of general and fixed function logic.

[0327] In at least one embodiment, the fixed-function block 2830 includes a geometry / fixed-function pipeline 2836, which, for example, may be shared by all sub-cores of the graphics processor 2800 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 2836 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0328] In at least one fixed embodiment, functional block 2830 further includes a graphics SoC interface 2837, a graphics microcontroller 2838, and a media pipeline 2839. In at least one fixed embodiment, the graphics SoC interface 2837 provides an interface between the graphics core 2800 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 2838 is a programmable subprocessor configurable to manage various functions of the graphics processor 2800, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2839 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2839 implements media operations via requests for computation or sampling logic within subcores 2801-2801F.

[0329] In at least one embodiment, the SoC interface 2837 enables the graphics core 2800 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2837 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2800 and the CPU within the SoC. In at least one embodiment, the SoC interface 2837 also implements power management control for the graphics core 2800 and enables interfacing between the clock domain of the graphics core 2800 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2837 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to the media pipeline 2839, or when a graphics processing operation is to be performed, they can be assigned to the geometry and fixed-function pipelines (e.g., geometry and fixed-function pipelines 2836 and 2814).

[0330] In at least one embodiment, the graphics microcontroller 2838 can be configured to perform various scheduling and management tasks on the graphics core 2800. In at least one embodiment, the graphics microcontroller 2838 can perform graphics and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2802A-2802F, 2804A-2804F in the sub-cores 2801A-2801F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2800 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2838 may also facilitate a low-power or idle state of the graphics core 2800, thereby providing the graphics core 2800 with the ability to save and restore registers across low-power state transitions within the graphics core 2800, independent of the operating system and / or the graphics driver software on the system.

[0331] In at least one embodiment, the graphics core 2800 may have up to N more or fewer modular sub-cores than the illustrated sub-cores 2801A-2801F. For each group of N sub-cores, in at least one embodiment, the graphics core 2800 may further include shared functional logic 2810, shared and / or cache memory 2812, geometry / fixed-function pipeline 2814, and additional fixed-function logic 2816 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2810 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 2800. In at least one fixed embodiment, the shared and / or cache memory 2812 may be the last-level cache of the N sub-cores 2801A-2801F within the graphics core 2800, and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, a geometry / fixed function pipeline 2814 may be included to replace the geometry / fixed function pipeline 2836 within the fixed function block 2830, and may include the same or similar logic units.

[0332] In at least one embodiment, the graphics core 2800 includes additional fixed-function logic 2816, which may include various fixed-function acceleration logics for use by the graphics core 2800. In at least one embodiment, the additional fixed-function logic 2816 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 2816, 2836, it is an additional geometry pipeline that can be included in the additional fixed-function logic 2816. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2816 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0333] In at least one embodiment, the additional fixed-function logic 2816 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementing optimizations for machine learning training or inference.

[0334] In at least one embodiment, each graphics subcore 2801A-2801F includes a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2801A-2801F includes multiple EU arrays 2802A-2802F, 2804A-2804F, thread dispatch and inter-thread communication (TD / IC) logic 2803A-2803F, 3D (e.g., texture) samplers 2805A-2805F, media samplers 2806A-2806F, shader processors 2807A-2807F, and shared local memory (SLM) 2808A-2808F. Each of the EU arrays 2802A-2802F and 2804A-2804F contains multiple execution units, which are general-purpose graphics processing units capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 2803A-2803F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2805A-2805F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 2806A-2806F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2801A-2801F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2801A-2801F may utilize shared local memory 2808A-2808F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0335] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into graphics processor 2810. For example, in at least one embodiment, the training and / or inference techniques described herein may use embedded graphics processor 2612, graphics microcontroller 2838, geometry and fixed-function pipelines 2814 and 2836, or... Figure 27 One or more ALUs in the other logic. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use, except... Figure 9A or Figure 9B The logic other than that shown is used to perform the task. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2800 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0336] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0337] Figures 29A-29B The diagram illustrates thread execution logic 2900 of an array of process elements including a graphics processor core, according to at least one embodiment. Figure 29A At least one embodiment is shown in which thread execution logic 2900 is used. Figure 29B Exemplary internal details of an execution unit according to at least one embodiment are shown.

[0338] like Figure 29AAs shown, in at least one embodiment, thread execution logic 2900 includes a shader processor 2902, a thread dispatcher 2904, an instruction cache 2906, a scalable execution unit array including multiple execution units 2908A-2908N, one or more samplers 2910, a data cache 2912, and a data port 2914. In at least one embodiment, the scalable execution unit array can be dynamically scaled, for example, based on the computational requirements of the workload, by enabling or disabling one or more execution units (e.g., any one of execution units 2908A, 2908B, 2908C, 2908D to 2908N-1 and 2908N). In at least one embodiment, the scalable execution units are interconnected via an interconnect structure linking to each execution unit. In at least one embodiment, the thread execution logic 2900 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 2906, data port 2914, sampler 2910, and execution units 2908A-2908N. In at least one embodiment, each execution unit (e.g., 2908A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2908A-2908N is scalable to include any number of individual execution units.

[0339] In at least one embodiment, execution units 2908A-2908N are primarily used to execute shader programs. In at least one embodiment, shader processor 2902 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2904. In at least one embodiment, thread dispatcher 2904 includes logic for arbitrating thread initialization celebrations from the graphics and media pipeline and for instantiating requested threads on one or more execution units 2908A-2908N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2904 can also handle runtime thread generation requests from executing shader programs.

[0340] In at least one embodiment, execution units 2908A-2908N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs in graphics libraries (e.g., Direct3D and OpenGL) to be executed with minimal translation. In at least one embodiment, the execution unit supports vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders). In at least one embodiment, each execution unit 2908A-2908N includes one or more arithmetic logic units (ALUs) capable of performing multiple-issue single-instruction multiple-data (SIMD) operations, and multithreaded operation enables an efficient execution environment despite higher latency memory access. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread states. In at least one embodiment, execution is multiple issues per clock cycle to a pipeline capable of integer, single-precision, and double-precision floating-point operations, SIMD branching functions, logical operations, a priori operations, and other operations. In at least one embodiment, while waiting for data from memory or a shared function, dependency logic within execution units 2908A-2908N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the latency associated with vertex shader operations, the execution unit can perform operations on a pixel shader, fragment shader, or another type of shader program (including different vertex shaders).

[0341] In at least one embodiment, each of the execution units 2908A-2908N operates on an array of data elements. In at least one embodiment, the plurality of data elements is an "execution size" or the number of instruction channels. In at least one embodiment, an execution channel is a logical unit for execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the plurality of channels may be independent of the plurality of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 2908A-2908N support integer and floating-point data types.

[0342] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as encapsulated data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit encapsulated data elements (quad-word (QW) size data elements), eight separate 32-bit encapsulated data elements (double-word (DW) size data elements), sixteen separate 16-bit encapsulated data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0343] In at least one embodiment, one or more execution units can be combined into a fused execution unit 2909A-2909N having thread control logic (2907A-2907N) for executing fused EUs. In at least one embodiment, multiple EUs can be merged into an EU group. In at least one embodiment, the number of EUs in a fused EU group can be configured to execute separate SIMD hardware threads. The number of EUs in a fused EU group can vary depending on the embodiments. In at least one embodiment, each EU can execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2909A-2909N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2909A includes a first EU 2908A, a second EU 2908B, and thread control logic 2907A shared by the first EU 2908A and the second EU 2908B. In at least one embodiment, thread control logic 2907A controls the threads executing on the fused graphics execution unit 2909A, thereby allowing each EU within the fused execution units 2909A-2909N to execute using a common instruction pointer register.

[0344] In at least one embodiment, one or more internal instruction caches (e.g., 2906) are included in the thread execution logic 2900 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 2912) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2910 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2910 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0345] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 2900 via thread creation and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2902 is invoked to further compute output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated on the rasterized objects. In at least one embodiment, the pixel processor logic within shader processor 2902 then executes the pixel or fragment shader program provided by the application programming interface (API). In at least one embodiment, to execute the shader program, shader processor 2902 dispatches threads to execution units (e.g., 2908A) via thread dispatcher 2904. In at least one embodiment, shader processor 2902 uses texture sampling logic in sampler 2910 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data are performed to calculate pixel color data for each geometric segment, or one or more pixels are discarded for further processing.

[0346] In at least one embodiment, data port 2914 provides a memory access mechanism for thread execution logic 2900 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2914 includes or is coupled to one or more cache memories (e.g., data cache 2912) to cache data for memory access via the data port.

[0347] like Figure 29BAs shown, in at least one embodiment, the graphics execution unit 2908 may include an instruction fetch unit 2937, a general-purpose register file array (GRF) 2924, an architecture register file array (ARF) 2926, a thread arbiter 2922, a send unit 2930, a branch unit 2932, a set of SIMD floating-point units (FPUs) 2934, and in at least one embodiment, a set of dedicated integer SIMD ALUs 2935. In at least one embodiment, the GRF 2924 and ARF 2926 include a set of general-purpose register files and architecture register files associated with each concurrent hardware thread that may be active in the graphics execution unit 2908. In at least one embodiment, the architecture state of each thread is maintained in the ARF 2926, while data used during thread execution is stored in the GRF 2924. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be stored in thread-specific registers in the ARF 2926.

[0348] In at least one embodiment, the graphics execution unit 2908 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and the number of registers per execution unit, wherein execution unit resources are logically allocated for executing multiple simultaneous threads.

[0349] In at least one embodiment, the graphics execution unit 2908 can jointly issue multiple instructions, each of which can be a different instruction. In at least one embodiment, the thread arbiter 2922 of the graphics execution unit thread 2908 can dispatch instructions to one of the sending unit 2930, the branching unit 2942, or the SIMD FPU 2934 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers in the GRF 2924, where each register can store 32 bytes and can be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread can access 4KB of the GRF 2924, although the embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In at least one embodiment, although the number of threads per execution unit may also vary depending on the embodiment, a maximum of seven threads can be executed simultaneously. In at least one embodiment where seven threads can access 4KB, the GRF 2924 can store a total of 28KB. In at least one embodiment, the flexible addressing mode can allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0350] In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are scheduled via a “send” instruction executed by message sending unit 2930. In at least one embodiment, branch instructions are dispatched to dedicated branch unit 2932 to facilitate SIMD divergence and eventual convergence.

[0351] In at least one embodiment, the graphics execution unit 2908 includes one or more SIMD floating-point units (FPUs) 2934 to perform floating-point operations. In at least one embodiment, one or more FPUs 2934 also support integer computation. In at least one embodiment, one or more FPUs 2934 can perform up to M 32-bit floating-point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating-point operations in SIMD. In at least one embodiment, at least one of the one or more FPUs provides extended mathematical capabilities to support high-throughput a priori mathematical functions and double-precision 64-bit floating-point operations. In at least one embodiment, a set of 8-bit integer SIMD ALUs 2935 is also present and can be specifically optimized to perform operations related to machine learning computations.

[0352] In at least one embodiment, an array of multiple instances of the graphics execution unit 2908 may be instantiated in a graphics sub-core group (e.g., a sub-slice). In at least one embodiment, the execution unit 2908 may execute instructions across multiple execution channels. In at least one embodiment, each thread executing on the graphics execution unit 2908 executes on a different channel.

[0353] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the execution logic 2900. Furthermore, in at least one embodiment, additional... Figure 9A or Figure 9B The logic other than that shown is used to perform the inference and / or training operations described herein. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of execution logic 2900 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0354] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0355] Figure 30 A parallel processing unit (“PPU”) 3000 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 3000 is configured with machine-readable code that, if executed by the PPU 3000, causes the PPU 3000 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 3000 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a set of instructions configured to be executed by the PPU 3000. In at least one embodiment, the PPU 3000 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as a liquid crystal display (“LCD”) device. In at least one embodiment, the PPU 3000 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 30 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture contemplated within the scope of this disclosure, which may be supplemented and / or replaced by any suitable processor.

[0356] In at least one embodiment, one or more PPU 3000s are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, the PPU 3000 is configured to accelerate deep learning systems and applications, including, but not limited to, the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analytics, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, etc.

[0357] In at least one embodiment, the PPU 3000 includes, but is not limited to, an input / output (“I / O”) unit 3006, a front-end unit 3010, a scheduler unit 3012, a job allocation unit 3014, a hub 3016, a crossbar (“Xbar”) 3020, one or more general-purpose processing clusters (“GPCs”) 3018, and one or more partitioning units (“memory partitioning units”) 3022. In at least one embodiment, the PPU 3000 is connected to a host processor or other PPU 3000 via one or more high-speed GPU interconnects (“GPU interconnects”) 3008. In at least one embodiment, the PPU 3000 is connected to a host processor or other peripheral device via an interconnect 3002. In one embodiment, the PPU 3000 is connected to local memory including one or more memory devices (“memory”) 3004. In at least one embodiment, the memory device 3004 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high-bandwidth memory (“HBM”) subsystems, and multiple DRAM dies are stacked within each device.

[0358] In at least one embodiment, the high-speed GPU interconnect 3008 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 3000s (“CPUs”) combined with one or more central processing units, supporting cache coherency between the PPUs 3000s and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 3008 transmits data and / or commands to other units of the PPU 3000, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components, via a hub 3016. Figure 30 Other components that may not be explicitly shown.

[0359] In at least one embodiment, the I / O unit 3006 is configured to access the host processor via the system bus 3002. Figure 30 (Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 3006 communicates directly with the host processor via system bus 3002 or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 3006 may communicate with one or more other processors (e.g., one or more PPUs 3000) via system bus 3002. In at least one embodiment, I / O unit 3006 implements a Peripheral Component Interconnect Express (“PCIe”) interface for communication via the PCIe bus. In at least one embodiment, I / O unit 3006 implements an interface for communicating with external devices.

[0360] In at least one embodiment, I / O unit 3006 decodes packets received via system bus 3002. In at least one embodiment, at least some packets represent commands configured to cause PPU 3000 to perform various operations. In at least one embodiment, I / O unit 3006 sends the decoded commands to various other units of PPU 3000 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 3010 and / or to hub 3016 or other units of PPU 3000, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 30 (Not explicitly shown in the text). In at least one embodiment, I / O unit 3006 is configured to route communication between various logical units of PPU 3000.

[0361] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 3000 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region of memory accessible (e.g., read / write) by both the host processor and the PPU 3000—a host interface unit can be configured to access a buffer in system memory connected to the system bus 3002 via memory requests transmitted through the system bus 3002 via the I / O unit 3006. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 3000, causing the front-end unit 3010 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 3000.

[0362] In at least one embodiment, a front-end unit 3010 is coupled to a scheduler unit 3012, which configures various GPCs 3018 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 3012 is configured to track status information related to the various tasks managed by the scheduler unit 3012, wherein the status information may indicate which GPC 3018 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, the scheduler unit 3012 manages multiple tasks executed on one or more GPCs 3018.

[0363] In at least one embodiment, a scheduler unit 3012 is coupled to a job allocation unit 3014 configured to dispatch tasks for execution on a GPC 3018. In at least one embodiment, the job allocation unit 3014 tracks multiple scheduled tasks received from the scheduler unit 3012 and manages a pool of pending tasks and an active task pool for each GPC 3018. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 32 time slots) containing tasks assigned to a particular GPC 3018 for processing; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by the GPC 3018, such that as one of the GPCs 3018 completes its execution, that task is evicted from the active task pool of the GPC 3018, and one of other tasks is selected from the pool of pending tasks and scheduled for execution on the GPC 3018. In at least one embodiment, if an active task is idle on GPC 3018, for example while waiting for data dependency resolution, the active task is evicted from GPC 3018 and returned to the task pool, while another task in the task pool is selected and scheduled to be executed on GPC 3018.

[0364] In at least one embodiment, the work allocation unit 3014 communicates with one or more GPCs 3018 via an XBar 3020. In at least one embodiment, the XBar 3020 is an interconnect network that couples a plurality of units of the PPU 3000 to other units of the PPU 3000, and can be configured to couple the work allocation unit 3014 to a specific GPC 3018. In at least one embodiment, other units of one or more PPUs 3000 can also be connected to the XBar 3020 via a hub 3016.

[0365] In at least one embodiment, tasks are managed by scheduler unit 3012 and assigned to one of GPCs 3018 by job allocation unit 3014. GPCs 3018 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPCs 3018, routed to different GPCs 3018 via XBar 3020, or stored in memory 3004. In at least one embodiment, results may be written to memory 3004 via partitioning unit 3022, which implements a memory interface for writing data to or reading data from memory 3004. In at least one embodiment, results may be transferred to another PPU 3004 or CPU via high-speed GPU interconnect 3008. In at least one embodiment, PPU 3000 includes, but is not limited to, U partitioning units 3022, which is equal to the number of separate and different storage devices 3004 coupled to PPU 3000. In at least one embodiment, the following is combined with… Figure 32 The partition unit 3022 is described in more detail.

[0366] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 3000. In one embodiment, multiple computing applications are executed concurrently by the PPU 3000, and the PPU 3000 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 3000, and the driver core outputs the tasks to one or more streams processed by the PPU 3000. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory. In at least one embodiment, combined with Figure 32 Threads and cooperative threads are described in more detail according to at least one embodiment.

[0367] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9BDetails regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 3000. In at least one embodiment, the PPU 3000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the PPU 3000. In at least one embodiment, the PPU 3000 can be used to perform one or more neural network use cases described herein.

[0368] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0369] Figure 31 A general processing cluster (“GPC”) 3100 according to at least one embodiment is shown.

[0370] In at least one embodiment, GPC 3100 is Figure 30 The GPC 3018. In at least one embodiment, each GPC 3100 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 3100 includes, but is not limited to, a pipeline manager 3102, a pre-raster operation unit (“PROP”) 3104, a raster engine 3108, a work assignment crossbar switch (“WDX”) 3116, a memory management unit (“MMU”) 3118, one or more data processing clusters (“DPC”) 3106, and any suitable combination of components.

[0371] In at least one embodiment, the operation of GPC 3100 is controlled by pipeline manager 3102. In at least one embodiment, pipeline manager 3102 manages the configuration of one or more DPCs 3106 to handle tasks assigned to GPC 3100. In at least one embodiment, pipeline manager 3102 configures at least one of one or more DPCs 3106 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 3106 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 3114. In at least one embodiment, pipeline manager 3102 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 3100, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 3104 and / or raster engine 3108, while other packets may be routed to DPC 3106 for processing by raw engine 3112 or SM 3114. In at least one embodiment, pipeline manager 3102 configures at least one of DPCs 3106 to implement a neural network model and / or computation pipeline.

[0372] In at least one embodiment, the PROP unit 3104 is configured to route data generated by the raster engine 3108 and DPC 3106 to the raster operation (“ROP”) unit in the partition unit 3022, in conjunction with the above. Figure 30 More detailed description. In at least one embodiment, the PROP unit 3104 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, the raster engine 3108 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 3108 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is passed to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and passed to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to the fine raster engine to generate properties of pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 3108 includes fragments that will be processed by any suitable entity (e.g., by the fragment shader implemented within the DPC 3106).

[0373] In at least one embodiment, each DPC 3106 included in GPC 3100 includes, but is not limited to, an M-pipeline controller (“MPC”) 3110; a primitive engine 3112; one or more SMs 3114; and any suitable combination thereof. In at least one embodiment, the MPC 3110 controls the operation of the DPC 3106, routing packets received from the pipeline manager 3102 to the appropriate units within the DPC 3106. In at least one embodiment, packets associated with vertices are routed to the primitive engine 3112, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be sent to the SM 3114.

[0374] In at least one embodiment, the SM 3114 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 3114 is multithreaded and configured to execute multiple threads (e.g., 31 threads) from a particular thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process a different dataset based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 3114 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process a different dataset based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. At least one embodiment of SM 3114 is described in more detail below.

[0375] In at least one embodiment, the MMU 3118 is integrated with the GPC 3100 and memory partitioning units (e.g., Figure 30 The MMU 3118 provides an interface between partition units 3022 and provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 3118 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0376] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 3100. In at least one embodiment, the GPC 3100 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or the GPC 3100. In at least one embodiment, the GPC 3100 can be used to perform one or more neural network use cases described herein.

[0377] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate higher frame rate video from frames of a lower frame rate video.

[0378] Figure 32 A memory partitioning unit 3200 of a parallel processing unit (“PPU”) according to at least one embodiment is illustrated. In at least one embodiment, the memory partitioning unit 3200 includes, but is not limited to, a raster operation (“ROP”) unit 3202; a secondary (“L2”) cache 3204; a memory interface 3206; and any suitable combination thereof. In at least one embodiment, the memory interface 3206 is coupled to memory. In at least one embodiment, the memory interface 3206 may implement a 32, 64, 128, or 1024-bit data bus, or a similar implementation for high-speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 3206, one memory interface 3206 per pair of partitioning units 3200, wherein each pair of partitioning units 3200 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high-bandwidth memory stack or graphics dual data rate version 5 synchronous dynamic random access memory (“GDDR5 SDRAM”).

[0379] In at least one embodiment, memory interface 3206 implements a high-bandwidth memory second-generation (“HBM2”) memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack and PPU reside on the same physical package, providing significant power savings and area savings compared to conventional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y equals 4, with each HBM2 stack including two 128-bit channels per die for a total of eight channels and a 1024-bit data bus width. In at least one embodiment, the memory supports Single Error Correction Double Error Detection (“SECDED”) error correction code (“ECC”) to protect data. In at least one embodiment, ECC provides higher reliability for data corruption-sensitive computing applications.

[0380] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partitioning unit 3200 supports unified memory to provide a single unified virtual address space for the central processing unit (“CPU”) and the PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses pages more frequently. In at least one embodiment, the high-speed GPU interconnect 3008 supports an address translation service that allows the PPU to directly access the CPU's page tables and provides full access to the CPU's memory through the PPU.

[0381] In at least one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the replication engine can generate page faults for addresses not mapped to page tables, and memory partitioning unit 3200 then servicees the page faults, mapping the addresses to page tables, after which the replication engine performs the transfer. In at least one embodiment, multiple replication engines operating on fixed (i.e., non-pageable) memory across multiple processors substantially reduce available memory. In at least one embodiment, in the event of a hardware page fault, an address can be passed to the replication engine regardless of whether a memory page resides, and the replication process is transparent.

[0382] According to at least one embodiment, from Figure 30Data in memory 3004 or other system memory is retrieved by memory partitioning unit 3200 and stored in L2 cache 3204, which is located on-chip and shared among various GPCs. In at least one embodiment, each memory partitioning unit 3200 includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in various units within a GPC. In at least one embodiment, each SM 3114 may implement a Level 1 (“L1”) cache, wherein the L1 cache is private memory dedicated to a specific SM 3114, and data is retrieved from L2 cache 3204 and stored in each L1 cache for processing within the functional units of the SM 3114. In at least one embodiment, L2 cache 3204 is coupled to memory interface 3206 and XBar 3020.

[0383] In at least one embodiment, ROP unit 3202 performs graphic raster operations related to pixel color, such as color compression, pixel blending, etc. In at least one embodiment, ROP unit 3202 performs depth testing in conjunction with raster engine 3108, receiving depth from the culling engine of raster engine 3018 for sample locations associated with pixel fragments. In at least one embodiment, depth is tested for the corresponding depth in the depth buffer at the sample location associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample location, ROP unit 3202 updates the depth buffer and sends the depth test result to raster engine 3108. It will be appreciated that the number of partition units 3200 may differ from the number of GPCs; therefore, each ROP unit 3202 may be coupled to each GPC in at least one embodiment. In at least one embodiment, ROP unit 3202 tracks packets received from different GPCs and determines which GPC to route the results generated by ROP unit 3202 to via XBar 3020.

[0384] Figure 33 A streaming multiprocessor (“SM”) 3300 according to at least one embodiment is illustrated. In at least one embodiment, the SM 3300 is Figure 31The SM 3300 includes, but is not limited to, an instruction cache 3302; one or more scheduler units 3304; a register file 3308; one or more processing cores (“cores”) 3310; one or more special function units (“SFUs”) 3312; one or more load / store units (“LSUs”) 3314; an interconnect network 3316; a shared memory / Level 1 (“L1”) cache 3318; and any suitable combination thereof. In at least one embodiment, a work allocation unit schedules tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 3300. In at least one embodiment, a scheduler unit 3304 receives tasks from the work allocation unit and manages the instruction scheduling of one or more thread blocks assigned to the SM 3300. In at least one embodiment, scheduler unit 3304 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 3304 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 3310, SFU 3312, and LSU 3314) in each clock cycle.

[0385] In at least one embodiment, a cooperative group can refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer and more efficient parallel decompositions. In at least one embodiment, a cooperative startup API supports synchronization between blocks of threads to execute parallel algorithms. In at least one embodiment, the application of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier (e.g., the `syncthreads()` function) across all threads in a thread block. However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of thread blocks and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block (i.e., as small as a single thread) and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing library and utility functions to be safely synchronized in their native environment without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0386] In at least one embodiment, the dispatch unit 3306 is configured to send instructions to one or more functional units, and the scheduler unit 3304 includes, but is not limited to, two dispatch units 3306 that enable two different instructions from the same thread bundle to be scheduled in each clock cycle. In at least one embodiment, each scheduler unit 3304 includes a single dispatch unit 3306 or additional dispatch units 3306.

[0387] In at least one embodiment, each SM 3300 includes, but is not limited to, a register file 3308 that provides a set of registers for functional units of the SM 3300. In at least one embodiment, the register file 3308 is partitioned between each functional unit, thereby allocating a dedicated portion of the register file 3308 for each functional unit. In at least one embodiment, the register file 3308 is partitioned between different thread bundles executed by the SM 3300, and the register file 3308 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM 3300 includes, but is not limited to, a plurality of L processing cores 3310. In at least one embodiment, the SM 3300 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3310. In at least one embodiment, each processing core 3310 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 3310 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores and 8 tensor cores.

[0388] According to at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 3310. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs matrix multiplication and accumulation operations D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0389] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core performs 32-bit floating-point accumulation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations to obtain a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform matrix operations on larger two-dimensional or higher-dimensional matrices composed of these smaller components. In at least one embodiment, APIs (such as the CUDA 9 C++ API) expose specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations to efficiently utilize the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16×16 matrix spanning all 32 thread bundle threads.

[0390] In at least one embodiment, each SM 3300 includes, but is not limited to, M SFUs 3312 that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, the SFUs 3312 include, but are not limited to, tree traversal units configured to traverse hierarchical tree data structures. In at least one embodiment, the SFUs 3312 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., a 2D array of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by a shader program executed by the SM 3300. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 3318. In at least one embodiment, according to at least one embodiment, the texture unit uses mip-maps (e.g., texture maps with different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 3300 includes, but is not limited to, two texture units.

[0391] In at least one embodiment, each SM 3300 includes, but is not limited to, N LSUs 3314 that implement load and store operations between the shared memory / L1 cache 3318 and the register file 3308. In at least one embodiment, each SM 3300 includes, but is not limited to, an interconnect network 3316 that connects each functional unit to the register file 3308, and the LSUs 3314 that connect to both the register file 3308 and the shared memory / L1 cache 3318. In at least one embodiment, the interconnect network 3316 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3308 and to connect the LSUs 3314 to memory locations in both the register file 3308 and the shared memory / L1 cache 3318.

[0392] In at least one embodiment, the shared memory / L1 cache 3318 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 3300 and the primitive engine, as well as between threads within the SM 3300. In at least one embodiment, the shared memory / L1 cache 3318 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM 3300 to the partition unit. In at least one embodiment, the shared memory / L1 cache 3318 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 3318, the L2 cache, and memory are backing storage.

[0393] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use shared memory or is used as a cache; for example, if shared memory is configured to use half its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 3318 enables the shared memory / L1 cache 3318 to be used as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration can be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a fixed-function graphics processing unit is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly allocates and distributes blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in computation to ensure each thread produces a unique result, using an SM 3300 to execute the program and perform computations, using a shared memory / L1 cache 3318 for communication between threads, and using an LSU 3314 to read and write global memory via the shared memory / L1 cache 3318 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, the SM 3300 writes commands to the scheduler unit 3304 that can be used to start new work on the DPC.

[0394] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), personal digital assistant (“PDA”), digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices (e.g., additional PPUs, memory, reduced instruction set computer (“RISC”) CPU, one or more memory management units (“MMU”), digital-to-analog converters (“DAC”), etc.).

[0395] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit (“iGPU”) included in the motherboard's chipset.

[0396] The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. (The following is in conjunction with...) Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the SM3300. In at least one embodiment, the SM 3300 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM 3300. In at least one embodiment, the SM 3300 can be used to perform one or more neural network use cases described herein.

[0397] In at least one embodiment, these components can be used to generate enhanced video using one or more neural networks, for example, to generate h...

Claims

1. A system-on-a-chip (SoC), comprising: Central Processing Unit (CPU); Memory; Peripheral component interconnection PCI communication bus; An upsampler comprising at least one neural network for inferring a higher resolution image from an input frame, wherein the higher resolution image is mixed with a previously inferred frame having a higher resolution. as well as Graphics processing unit (GPU), the GPU comprising: General Purpose Processing Cluster (GPC), wherein the GPC comprises multiple streaming multiprocessors (SMs), the multiple SMs including: Instruction cache; Dispatch unit; core; Load the LSU (Low Storage Unit); Shared memory; and L1 cache.

2. The SoC of claim 1, wherein the plurality of SMs further includes a register file.

3. The SoC of claim 1, wherein the plurality of SMs further comprises one or more special function units (SFUs).

4. The SoC of claim 1, wherein each of the plurality of SMs further includes one or more interconnects.

5. The SoC of claim 1, wherein the GPC further comprises a raster engine.

6. The SoC of claim 1, further comprising a hub for interconnecting with one or more GPUs.

7. The SoC of claim 1, wherein the GPU further includes an input / output I / O unit, the I / O unit being coupled to the PCI communication bus.

8. The SoC of claim 1, wherein the GPU further comprises a cross switch Xbar.

9. The SoC of claim 1, wherein the GPU further includes a memory partitioning unit.

10. A method comprising: An upsampler is executed using a SoC, the upsampler including at least one neural network for inferring a higher-resolution image from an input frame, wherein the higher-resolution image is blended with a previously inferred frame having a higher resolution. The SoC includes: Central Processing Unit (CPU); Memory; Peripheral component interconnection PCI communication bus; and Graphics processing unit (GPU), the GPU comprising: General Purpose Processing Cluster (GPC), wherein the GPC comprises multiple streaming multiprocessors (SMs), the multiple SMs including: Instruction cache; Dispatch unit; core; Load the LSU (Low Storage Unit); Shared memory; and L1 cache.

11. The method of claim 10, wherein the previous inference frame is inferred by the at least one neural network.

12. The method of claim 10, wherein the higher resolution image is mixed with the pixel values ​​of the previous inference frame.

13. The method of claim 10, wherein the GPU further comprises a scheduler unit.

14. The method of claim 10, wherein the GPU further comprises a raster engine.

15. The method of claim 10, wherein the SoC further includes a hub for engaging with one or more GPU interconnects.

16. The method of claim 10, wherein the SoC further includes a network interface.

17. The method of claim 10, wherein the SoC further comprises one or more display devices.

18. The method of claim 10, further comprising: The higher-resolution image is inferred from at least one neural network based at least in part on the lower-resolution input frame.

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