An iterative digital circuit static learning method and system for parallel computing

Abstract

This invention discloses an iterative static learning method, system, device, and medium for parallel computing of digital circuits. The method includes the following steps: S110, constructing an incremental learning database and a derivation relation database; S120, acquiring all learning tasks to be learned in the digital circuit; S130, independently deriving all learning tasks in the digital circuit based on the derivation relation database, and storing the generated derivation relations in the incremental learning database; S140, storing all derivation relations in the incremental learning database into the derivation relation database, and then clearing the incremental learning database; S150, determining whether the learning stop condition is met; if not, returning to S130; if yes, stopping learning and outputting the derivation relation database. This invention can acquire more new derivation relations, has no requirement on the order of processing learning tasks, saves computer memory, and supports parallelized accelerated operation.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, specifically to an iterative digital circuit static learning method, system, device, and medium for parallel computing. Background Technology

[0002] In the manufacturing process of digital circuit design, testers need to use test sets and automated testing equipment to detect defects in the actual manufactured chips, in order to avoid selling defective chips to consumers. The ATPG (Automatic Test Pattern Generation) algorithm mainly generates test sets based on fault model analysis of the circuit structure. However, its implementation involves many NPC (Non-deterministic Polynomial Complete) problems, often resulting in unsatisfactory performance or difficulty in finding high-quality test sets within a specified time. Therefore, it needs to be combined with heuristic algorithms to help trim the search space and reduce backtracking. Static learning, as one of the many heuristic algorithms required by the ATPG algorithm, can identify the derivation relationships between various logic gates in digital circuits. It can assist the ATPG algorithm in completing necessary assignment operations, efficiently trimming the search space and reducing backtracking. However, existing static learning methods, when deriving all learning tasks, have a final learning result that depends on the order in which the learning tasks are processed. The entire implementation has high memory requirements, and the output results after parallelization are unstable. Summary of the Invention

[0003] This invention provides an iterative digital circuit static learning method, system, device, and medium for parallel computing, to solve one or more technical problems existing in the prior art, and at least provide a beneficial option or create conditions.

[0004] Firstly, an iterative static learning method for digital circuits oriented towards parallel computing is provided, including:

[0005] Step 110: Construct an incremental learning database and an inference relation database;

[0006] Step 120: Obtain all the learning tasks that need to be learned in the digital circuit;

[0007] Step 130: Based on the derivation relation database, independently derive all the learning tasks in the digital circuit, and store the generated derivation relations in the incremental learning database;

[0008] Step 140: Store all derivation relations in the incremental learning database into the derivation relation database, and then clear the incremental learning database;

[0009] Step 150: Determine whether the learning stop condition is met; if not, return to step 130 above; if yes, stop learning and output the derived relation database.

[0010] Furthermore, any one of the learning tasks includes the labeling information of a single logic gate and the logic value output by the single logic gate.

[0011] Further, the step of independently deriving all learning tasks in the digital circuit based on the derivation relation database, and storing the generated derivation relations in the incremental learning database, includes:

[0012] For any of the learning tasks, locate the single logic gate recorded in the learning task in the digital circuit;

[0013] Based on the logic value output by the individual logic gate and the derivation relationship database, forward and backward derivation are performed in the digital circuit starting from the individual logic gate to obtain each effective logic gate and its output logic value.

[0014] Based on the individual logic gate and the logic values ​​output by each effective logic gate, a derivation relationship between each effective logic gate and the individual logic gate is generated and stored in the incremental learning database.

[0015] Furthermore, the logic values ​​output by each valid logic gate are obtained through forward derivation, and the first logic value input to each valid logic gate is a non-control value.

[0016] Furthermore, for any logic gate in the digital circuit,

[0017] The backward derivation of the logic gate is manifested as follows: based on the properties of the logic gate and the logic value of the logic gate output, the logic values ​​of all inputs of the logic gate are derived; or based on the properties of the logic gate, the logic value of the logic gate output and the logic values ​​of some inputs of the logic gate, the logic values ​​of other inputs of the logic gate are derived.

[0018] The forward derivation of the logic gate is manifested as follows: based on the properties of the logic gate and the current input logic value of the logic gate, the output logic value of the logic gate is derived.

[0019] Furthermore, generating the derivation relationship between the various valid logic gates and the individual logic gate based on the single logic gate and the logic values ​​output by each valid logic gate includes:

[0020] For any valid logic gate, an initial derivation relationship between the single logic gate and the valid logic gate is generated based on the single logic gate and the logic value output by the valid logic gate.

[0021] The initial derivation relationship is transformed using the inverse law to obtain the derivation relationship between the effective logic gate and the individual logic gate.

[0022] Furthermore, the stopping learning condition includes at least one of the following: the current iteration fails to learn a new derivation relation, the maximum number of iterations is reached, and the maximum number of derivation relations is reached.

[0023] Secondly, an iterative digital circuit static learning system for parallel computing is provided, including:

[0024] Build modules are used to construct incremental learning databases and inference relation databases;

[0025] The acquisition module is used to acquire all the learning tasks that need to be learned in the digital circuit.

[0026] The derivation module is used to independently derive all the learning tasks in the digital circuit according to the derivation relationship database, and store the generated derivation relationships in the incremental learning database;

[0027] The storage module is used to store all the derivation relations in the incremental learning database into the derivation relation database, and then clear the incremental learning database;

[0028] The judgment module is used to determine whether the learning stop condition is met; if not, the derivation module is run again; if yes, the output module is run.

[0029] The output module is used to stop learning and output the derived relation database.

[0030] Thirdly, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the iterative digital circuit static learning method for parallel computing as described in the first aspect.

[0031] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the iterative digital circuit static learning method for parallel computing as described in the first aspect.

[0032] The present invention has at least the following beneficial effects: by performing multiple derivations on each learning task through multiple iterations, the derivation relations stored in the previous N-1 derivations are queried and applied during the Nth derivation, where N is a positive integer. Furthermore, relying on digital circuits, more new derivation relations can be obtained, thereby effectively helping to improve the performance of ATPG. When performing an iterative derivation on all learning tasks, the derivation relations generated by the currently executed learning task will not be adopted by the learning tasks executed later, ensuring that all derivation relations generated in this iteration are completely independent of the order in which the learning tasks are processed, and supporting parallelized accelerated operation. Simultaneously, by storing only the newly learned derivation relations in each derivation process, computer memory resources can be saved. Attached Figure Description

[0033] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0034] Figure 1 This is a flowchart illustrating an iterative digital circuit static learning method for parallel computing in an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the structure of a simplified digital circuit in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the derivation process for characterizing a single learning task in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the first derivation process for characterization learning task A in the prior art;

[0038] Figure 5 This is a schematic diagram of the first derivation process for representing learning task B in the prior art;

[0039] Figure 6 This is a schematic diagram of the first derivation process for representing learning task C in the prior art;

[0040] Figure 7 This is a schematic diagram of the first derivation process for representing learning task D in the prior art;

[0041] Figure 8 This is a schematic diagram of the second derivation process for characterizing learning task A in the prior art;

[0042] Figure 9 This is a schematic diagram of the second derivation process for representing learning task B in the prior art;

[0043] Figure 10 This is a schematic diagram of the second derivation process for representing learning task C in the prior art;

[0044] Figure 11 This is a schematic diagram of the second derivation process for representing the learning task D in the prior art;

[0045] Figure 12 This is a schematic diagram of the composition of an iterative digital circuit static learning system for parallel computing in an embodiment of the present invention.

[0046] Figure 13 This is a schematic diagram of the hardware structure of the computer device in an embodiment of this disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0048] It should be noted that although functional modules are divided in the system diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the system or the order in the flowchart. The terms "first," "second," "third," "fourth," etc., used in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed and are inherent to these processes, methods, products, or apparatuses.

[0049] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating an iterative digital circuit static learning method for parallel computing provided by an embodiment of the present invention. The method includes the following:

[0050] Step S110: Construct an incremental learning database and an inference relation database;

[0051] Step S120: Obtain all learning tasks that need to be learned in the digital circuit;

[0052] Step S130: Based on the derivation relation database, independently derive all the learning tasks in the digital circuit, and store the generated derivation relations in the incremental learning database;

[0053] Step S140: Store all derivation relations in the incremental learning database into the derivation relation database, and then clear the incremental learning database;

[0054] Step S150: Determine whether the learning stop condition is met; if not, return to step S130 above; if yes, continue to step S160.

[0055] Step S160: Stop learning and output the derived relation database.

[0056] In this embodiment of the invention, the digital circuit mentioned in step S120 can be understood as a topology composed of several logic gates and the connection relationship between every two logic gates, wherein each logic gate has unique marking information to facilitate quick retrieval of the position and related connection information of the logic gate in the digital circuit; it should be noted that the several logic gates include, but are not limited to, one or more of the following logic gates: AND gate, OR gate, NOT gate, NAND gate, NOR gate, XOR gate, XNOR gate, selector, flip-flop, latch.

[0057] In step S120 above, the digital circuit is scanned and inspected to obtain all the logic gates that need to be learned. The tag information of the obtained individual logic gates and the logic value output by the individual logic gate (also known as the logic value of the output terminal of the individual logic gate, which is generally 0 or 1 in binary form) are encapsulated into a learning task output. According to the above encapsulation operation, all learning tasks corresponding to all logic gates can be generated. In order to facilitate the management of all learning tasks, the present invention constructs a learning task array to store all learning tasks.

[0058] In this embodiment of the invention, step S130 should be understood as follows: in the digital circuit, each learning task is individually derived using the derivation relation database, and each generated derivation relation is stored in the incremental learning database during the entire derivation process, thereby completing the derivation process for all learning tasks.

[0059] It should be noted that this invention can employ a single thread to derive each learning task serially, ensuring that all learning tasks are executed. Alternatively, it can employ multiple threads to derive multiple learning tasks independently in parallel, effectively improving processing efficiency while conserving memory. Furthermore, when at least two threads simultaneously attempt to access the learning task array to check for unexecuted tasks, configuring these threads to access the array sequentially ensures that no single learning task is executed repeatedly, preventing wasted computational resources and preventing any thread from accessing memory outside the learning task array. Of course, this invention can also be implemented using other parallel methods, which are not specifically limited here.

[0060] In this embodiment of the invention, taking any one of the learning tasks as an example, the derivation process of the learning task is explained as follows:

[0061] Step S131: According to the marking information of the individual logic gate recorded in the learning task, search for and locate the individual logic gate in the digital circuit;

[0062] Step S132: Using the single logic gate as the starting point, and using the derivation relation database and the logic value output by the single logic gate, perform forward and backward derivation in the digital circuit to obtain each valid logic gate and record the logic value output by each valid logic gate.

[0063] Step S133: Using the logic values ​​output by each valid logic gate and the logic value output by the single logic gate, generate corresponding derivation relationships between each valid logic gate and the single logic gate, and then store the derivation relationships in the incremental learning database.

[0064] In step S132 above, taking any logic gate in the digital circuit (hereinafter referred to as the first logic gate) as an example, the forward derivation principle and the backward derivation principle of the first logic gate are explained as follows:

[0065] (1) The first logic gate is deduced forward, specifically by using the current input logic value of the first logic gate and the properties of the first logic gate to directly deduce the output logic value of the first logic gate.

[0066] Assuming the first logic gate is a two-input, single-output AND gate, when the logic value of one or both inputs of the first logic gate is 0, it can be directly deduced that the logic value output by the first logic gate is 0; when the logic values ​​of both inputs of the first logic gate are 1, it can be directly deduced that the logic value output by the first logic gate is 1; however, when one input of the first logic gate is 1 and the logic value of the other input of the first logic gate is unknown, it is directly determined that the first logic gate cannot be deduced forward.

[0067] (2) The first logic gate is deduced backward, specifically by: using the logic value output by the first logic gate and the properties of the first logic gate, directly deriving the logic values ​​of all inputs of the first logic gate; or, using the logic values ​​of some inputs of the first logic gate, the logic values ​​output by the first logic gate and the properties of the first logic gate, deriving the logic values ​​of other inputs of the first logic gate.

[0068] Assuming the first logic gate is a two-input, single-output AND gate, when the output logic value of the first logic gate is 1, it can be directly deduced that the logic values ​​of both inputs of the first logic gate are 1; when the output logic value of the first logic gate is 0 and the logic value of one input of the first logic gate is 1, it can be directly deduced that the logic value of the other input of the first logic gate is 0; however, when the output logic value of the first logic gate is 0 and the logic values ​​of both inputs of the first logic gate are unknown or the logic value of one input of the first logic gate is 0, it is directly determined that the first logic gate cannot be further deduced.

[0069] In step S132 above, when a logic gate in the digital circuit (hereinafter referred to as the second logic gate) is identified as a valid logic gate, the following two conditions should be met simultaneously: First, the first input logic value of the second logic gate is a non-control value, that is, using the properties of the second logic gate and its first input logic value, the output logic value of the second logic gate cannot be directly derived by ignoring the other input logic values ​​of the second logic gate; Second, the output logic value of the second logic gate is obtained by forward derivation. It should be noted that the present invention can also set other conditions as the basis for judging a valid logic gate, and no specific limitations are made here.

[0070] More specifically, taking any one of the valid logic gates as an example, assuming the logic value of the output terminal s0 of the single logic gate is v0, and the output terminal s of the valid logic gate... r The logical value is v rThe implementation process of step S133 described above includes the following:

[0071] Step S133.1: Utilize the logic value output by the effective logic gate (i.e., s) r =v r The initial derivation relationship between the single logic gate and the effective logic gate is determined by the logic value output by the single logic gate (i.e., s0 = v0) and the logic value output by the single logic gate.

[0072] Step S133.2: Based on the inverse law, transform the initial derivation relationship to obtain the derivation relationship between the effective logic gate and the individual logic gate.

[0073] Step S133.3: Store the derivation relationship in the incremental learning database.

[0074] In this embodiment of the invention, with Figure 2 Based on the simplified digital circuit shown, where x represents the unknown logic value of the relevant port, logic gate G1 has two input terminals a and b and a single output terminal d, logic gate G2 has two input terminals b and c and a single output terminal e, logic gate G3 has two input terminals d and e and a single output terminal f, logic gate G4 has two input terminals f and e and a single output terminal g, logic gate G5 has two input terminals a and f and a single output terminal h, logic gate G6 has two input terminals f and g and a single output terminal i, and logic gate G7 has two input terminals h and i and a single output terminal j;

[0075] Assuming the single learning task to be learned in the simplified digital circuit is (G2 / e, 1), where G2 / e is the tagging information of logic gate G2, and the logic value output by logic gate G2 is e = 1, combined with... Figure 3 The derivation process shown for characterizing the single learning task, and the detailed implementation of steps S132 and S133 above, are as follows:

[0076] Starting from logic gate G2, we deduce S1 backward from logic gate G2 to obtain b=1 and c=1. Since the input terminal of logic gate G2 is actually the input terminal of the simplified digital circuit, we cannot continue to deduce backward. Here, S is an abbreviation for step.

[0077] By performing a forward derivation S2 on logic gate G1, we obtain d = 1. Then, by performing a forward derivation S3 on logic gate G3, we obtain f = 1. At this point, we can determine that logic gate G3 is a valid logic gate, and thus establish the initial derivation relationship between logic gates G2 and G3. Then, by performing an inverse transformation, the derivation relationship between logic gate G3 and logic gate G2 is obtained as follows: And store it in the incremental learning database;

[0078] Performing forward derivation S4 on logic gate G4 yields g = 1, and performing forward derivation S5 on logic gate G6 yields i = 0. At this point, logic gate G6 can be determined to be a valid logic gate, thus establishing the initial derivation relationship between logic gates G2 and G6. Then, by performing an inverse transformation, the derivation relationship between logic gate G6 and logic gate G2 is obtained as follows: And store it in the incremental learning database;

[0079] By performing forward derivation S6 on logic gate G7, we obtain j = 0. At this point, we can determine that logic gate G7 is a valid logic gate, and thus determine the initial derivation relationship between logic gate G2 and logic gate G7 as follows: Then, by performing an inverse transformation, the derivation relationship between logic gate G7 and logic gate G2 is obtained as follows: And store it in the incremental learning database.

[0080] It should be noted that when performing forward or backward derivation on any logic gate, the derivation relation database should be queried first and only if it already contains a derivation relation associated with that logic gate that can be directly invoked. This allows for the acquisition of derivation relations that cannot be obtained through forward or backward derivation. Of course, there are multiple execution orders for forward derivation, backward derivation, and applying stored derivation relations. This invention only proposes one such execution order, but it is not limited to the execution order proposed in this invention.

[0081] It should be noted that, in this invention, completing one round of derivation for all the learning tasks by executing the above step S130 is considered as completing one iteration operation. Then, by executing the above step S140, it can be ensured that the incremental learning database is only used to temporarily store the derivation relationship generated in the current iteration.

[0082] In this embodiment of the invention, the learning stop conditions mentioned in step S150 include, but are not limited to, at least one of the following: the current iteration fails to learn a new derivation relation, the maximum number of derivation relations is reached, and the maximum number of iterations is reached; wherein, the maximum number of derivation relations refers to the maximum storage capacity limited within the derivation relation database.

[0083] The following explanation addresses the issue of the current iteration failing to learn new derivation relationships: After executing step S130 above, the incremental learning database is queried first; if the incremental learning database is found to be empty, it indicates that the current iteration has failed to learn new derivation relationships, and step S140 above can be considered an invalid operation; if the incremental learning database is found to be non-empty, it indicates that the current iteration can still learn new derivation relationships.

[0084] In this embodiment of the invention, each learning task is deduced multiple times through multiple iterations. During the Nth derivation, the derivation relationships stored in the previous N-1 derivations are queried and applied, where N is a positive integer. By relying on digital circuits, more new derivation relationships can be obtained, thereby effectively helping to improve the performance of ATPG. When performing an iterative derivation on all learning tasks, the derivation relationships generated by the currently executed learning task will not be adopted by the learning tasks executed later, ensuring that all derivation relationships generated in this iteration are completely independent of the order of processing learning tasks and supporting parallelized accelerated operation. At the same time, only the newly learned derivation relationships are stored in each derivation process, which can save computer memory resources.

[0085] In contrast, existing static learning methods, with Figure 2 Using the simplified digital circuit shown as a benchmark, assuming that the four learning tasks to be learned in the simplified digital circuit are: A = (G2 / e, 1), B = (G3 / f, 0), C = (G4 / g, 1), and D = (G5 / h, 1), the following analysis is provided:

[0086] (1) When deriving the four learning tasks in the order of execution A→B→C→D:

[0087] First, by deriving learning task A, we can obtain three derivation relations as follows: and See Figure 4 Therefore, by further deriving learning task B, we can obtain the following derivation relationship: Furthermore, the derivation relationships generated by the learning task A are directly applied in this derivation process. See Figure 5 It can be seen that; further derivation of learning task C yields two derivation relationships as follows: and Furthermore, the derivation relationships generated by the learning task B are directly applied in this derivation process. See Figure 6 Therefore, by deriving the learning task D, we can obtain the following derivation relationship: Furthermore, the derivation relationship of the learning task A is directly applied in this derivation process. See Figure 7 It can be known that;

[0088] (2) When deriving the four learning tasks in the execution order of D→C→B→A:

[0089] Firstly, attempting to derive learning task D yields no derivation relationships; see [link / reference needed]. Figure 8 It can be seen that; further derivation of learning task C yields no derivation relationship, see [link to previous section]. Figure 9 It can be seen that further derivation of learning task B yields no derivation relationship; see [link to previous text]. Figure 10 It can be seen that, by deriving learning task A, three derivation relationships can be obtained as follows: and See Figure 11 It can be known that;

[0090] In other words, in the static learning methods proposed in the prior art, since the derivation relationship generated by the currently executed learning task will be adopted by the learning task executed later, when the order of processing the four learning tasks changes, the learning result obtained by performing an iterative derivation on the four learning tasks will also change. In order to obtain more derivation relationships, technicians need to analyze the digital circuit in advance to determine the processing order of all learning tasks. Furthermore, if the entire learning process is executed in parallel, it will lead to unstable output results, affecting the application of the static learning method in the ATPG algorithm.

[0091] Please refer to Figure 12 , Figure 12 This is a schematic diagram illustrating the composition of an iterative digital circuit static learning system for parallel computing provided in an embodiment of the present invention. The system includes:

[0092] Module 210 is used to build the inferential relational database and the incremental learning database;

[0093] Module 220 is used to acquire all the learning tasks that need to be learned in the digital circuit.

[0094] Derivation module 230 is used to derive all learning tasks individually in the digital circuit using the derivation relation database, and store the generated derivation relations in the incremental learning database;

[0095] Storage module 240 is used to store all inference relations in the incremental learning database into the inference relation database, and then perform a clearing operation on the incremental learning database;

[0096] The judgment module 250 is used to determine whether the learning stop condition is met; if not, the derivation module 230 is run again; if it is met, the output module 260 is run.

[0097] The output module 260 is used to end the entire learning process of the digital circuit and output the derivation relation database as the final learning result.

[0098] The content of the above method embodiments is applicable to this system embodiment. The functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are the same as those in the above method embodiments. Therefore, they will not be repeated here.

[0099] Furthermore, embodiments of the present invention also provide a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the iterative digital circuit static learning method for parallel computing described in the above embodiments. The computer-readable storage medium includes, but is not limited to, any type of disk (including floppy disks, hard disks, optical disks, CD-ROMs, and magneto-optical disks), ROM (Read-Only Memory), RAM (Random Access Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, magnetic cards, or optical cards. In other words, the storage device includes any medium on which a device (e.g., a computer, mobile phone, etc.) stores or transmits information in a readable form, and can be a read-only memory, a disk, or an optical disk, etc.

[0100] also, Figure 13 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of the present invention. The computer device includes components such as a processor 320, a memory 330, an input unit 340, and a display unit 350. Those skilled in the art will understand that... Figure 13The illustrated device structure is not intended to limit all devices and may include more or fewer components than shown, or combine certain components. The memory 330 can be used to store the computer program 310 and various functional modules. The processor 320 runs the computer program 310 stored in the memory 330, thereby performing various functional applications and data processing of the device. The memory can be internal memory or external memory, or include both internal and external memory. Internal memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or random access memory. External memory may include hard disks, floppy disks, USB flash drives, magnetic tapes, etc. The memory 330 disclosed in the embodiments of this invention includes, but is not limited to, these types of memory. The memory 330 disclosed in the embodiments of this invention is only an example and not a limitation.

[0101] Input unit 340 is used to receive signal input and user-input keywords. Input unit 340 may include a touch panel and other input devices. The touch panel can collect user touch operations on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch panel) and drive the corresponding connection device according to a pre-set program; other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as play control buttons, power buttons, etc.), trackballs, mice, joysticks, etc. Display unit 350 can be used to display user-input information or information provided to the user, as well as various menus of the terminal device. Display unit 350 may be in the form of a liquid crystal display, organic light-emitting diode, etc. Processor 320 is the control center of the terminal device, connecting various parts of the entire device through various interfaces and lines, performing various functions and processing data by running or executing software programs and / or modules stored in memory 330, and calling data stored in memory 330.

[0102] As one embodiment, the computer device includes a processor 320, a memory 330, and a computer program 310, wherein the computer program 310 is stored in the memory 330 and configured to be executed by the processor 320, and the computer program 310 is configured to perform the iterative digital circuit static learning method for parallel computing described in the above embodiment.

[0103] Although the description of this application has been quite detailed and particularly focused on several of the described embodiments, it is not intended to limit itself to any of these details or embodiments or any particular embodiment. Rather, it should be considered as effectively covering the intended scope of this application by referring to the appended claims and taking into account the prior art, which provides for a broad possible interpretation of these claims. Furthermore, the foregoing description of this application with respect to embodiments foreseeable by the inventors is intended to provide a useful description, and non-substantial modifications to this application that have not yet been foreseen may still represent equivalent modifications.

Claims

1. An iterative static learning method for digital circuits oriented towards parallel computing, characterized in that, include: Step 110: Construct an incremental learning database and an inference relation database; Step 120: Obtain all learning tasks that need to be learned in the digital circuit. Each learning task includes the tag information of a single logic gate and the logic value output by the single logic gate. Step 130: Based on the derivation relation database, independently derive all the learning tasks in the digital circuit, and store the generated derivation relations in the incremental learning database; Step 140: Store all derivation relations in the incremental learning database into the derivation relation database, and then clear the incremental learning database; Step 150: Determine whether the conditions for stopping learning are met; If not, return to step 130 above; if yes, stop learning and output the derived relation database. The step of independently deriving all learning tasks in the digital circuit based on the derivation relation database and storing the generated derivation relations in the incremental learning database includes: For any of the learning tasks, locate the single logic gate recorded in the learning task in the digital circuit; Based on the logic value output by the individual logic gate and the derivation relationship database, forward and backward derivation are performed in the digital circuit starting from the individual logic gate to obtain each effective logic gate and its output logic value. Based on the logic values ​​output by the individual logic gate and each effective logic gate, a derivation relationship between each effective logic gate and the individual logic gate is generated and stored in the incremental learning database; For any logic gate in the digital circuit, The backward derivation of the logic gate is manifested as follows: based on the properties of the logic gate and the logic value of the logic gate output, the logic values ​​of all inputs of the logic gate are derived; or based on the properties of the logic gate, the logic value of the logic gate output and the logic values ​​of some inputs of the logic gate, the logic values ​​of other inputs of the logic gate are derived. The forward derivation of the logic gate is manifested as: deriving the logic value output by the logic gate based on the properties of the logic gate and the current logic value input to the logic gate; The step of generating the derivation relationship between the various valid logic gates and the individual logic gate based on the logic values ​​output by the individual logic gate and the various valid logic gates includes: For any valid logic gate, an initial derivation relationship between the single logic gate and the valid logic gate is generated based on the single logic gate and the logic value output by the valid logic gate. The initial derivation relationship is transformed using the inverse law to obtain the derivation relationship between the effective logic gate and the individual logic gate.

2. The iterative digital circuit static learning method for parallel computing according to claim 1, characterized in that, The logic values ​​output by each valid logic gate are obtained by forward derivation, and the first logic value input to each valid logic gate is a non-control value.

3. The iterative digital circuit static learning method for parallel computing according to claim 1, characterized in that, The stopping learning conditions include at least one of the following: the current iteration fails to learn a new derivation relation, the maximum number of iterations is reached, and the maximum number of derivation relations is reached.

4. An iterative digital circuit static learning system for parallel computing, characterized in that, include: Build modules are used to construct incremental learning databases and inference relation databases; The acquisition module is used to acquire all learning tasks that need to be learned in the digital circuit. Any learning task among all learning tasks includes the tag information of a single logic gate and the logic value output by the single logic gate. The derivation module is used to independently derive all the learning tasks in the digital circuit according to the derivation relationship database, and store the generated derivation relationships in the incremental learning database; The storage module is used to store all the derivation relations in the incremental learning database into the derivation relation database, and then clear the incremental learning database; The judgment module is used to determine whether the conditions for stopping learning are met; If not, run the derivation module again; if yes, run the output module. The output module is used to stop learning and output the derived relation database; The step of independently deriving all learning tasks in the digital circuit based on the derivation relation database and storing the generated derivation relations in the incremental learning database includes: For any of the learning tasks, locate the single logic gate recorded in the learning task in the digital circuit; Based on the logic value output by the individual logic gate and the derivation relationship database, forward and backward derivation are performed in the digital circuit starting from the individual logic gate to obtain each effective logic gate and its output logic value. Based on the logic values ​​output by the individual logic gate and each effective logic gate, a derivation relationship between each effective logic gate and the individual logic gate is generated and stored in the incremental learning database; For any logic gate in the digital circuit, The backward derivation of the logic gate is manifested as follows: based on the properties of the logic gate and the logic value of the logic gate output, the logic values ​​of all inputs of the logic gate are derived; or based on the properties of the logic gate, the logic value of the logic gate output and the logic values ​​of some inputs of the logic gate, the logic values ​​of other inputs of the logic gate are derived. The forward derivation of the logic gate is manifested as: deriving the logic value output by the logic gate based on the properties of the logic gate and the current logic value input to the logic gate; The step of generating the derivation relationship between the various valid logic gates and the individual logic gate based on the logic values ​​output by the individual logic gate and the various valid logic gates includes: For any valid logic gate, an initial derivation relationship between the single logic gate and the valid logic gate is generated based on the single logic gate and the logic value output by the valid logic gate. The initial derivation relationship is transformed using the inverse law to obtain the derivation relationship between the effective logic gate and the individual logic gate.

5. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, The processor executes the computer program to implement the iterative digital circuit static learning method for parallel computing as described in any one of claims 1 to 3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the iterative digital circuit static learning method for parallel computing as described in any one of claims 1 to 3.

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