Pixel driving circuit, display panel

Abstract

The present disclosure provides a pixel driving circuit and a display panel, and belongs to the technical field of display. The pixel driving circuit comprises a driving transistor connected with a first node and a third node; a first transistor connected with a second node and configured to output a data voltage to the second node in response to a first scanning signal; a second transistor connected with the first node and the third node; a fifth transistor connected with the second node and configured to output a reference voltage to the second node in response to a first reset signal; a seventh transistor connected with the third node and a fourth node and configured to enable electrical communication between the third node and the fourth node in response to a light-emitting control signal; and a storage capacitor connected with the first node and the second node; and in a threshold voltage compensation stage, the first node is charged to VDD+Vth. The pixel driving circuit can simplify the pixel driving method.

Description

[0001] This application is a divisional application of the application with the application date of September 29, 2021, the Chinese application number of 202180002756.8, and the invention name of "Pixel driving circuit and pixel driving method, display panel". TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, in particular, to a pixel driving circuit and a display panel. BACKGROUND

[0003] Electroluminescent devices, such as organic electroluminescent diodes, have been widely used in the field of display. Among them, a pixel driving circuit for driving the electroluminescent device to emit light can be provided in a display device, and the pixel driving circuit usually includes a driving transistor for generating a driving current. In order to improve the display effect, the threshold voltage of the driving transistor can be compensated in some pixel driving circuits to overcome the display difference caused by the difference in threshold voltage of different driving transistors.

[0004] However, in the prior art, the threshold voltage of the driving transistor is usually compensated first, and then the data voltage is written to the pixel driving circuit; this leads to a relatively complex driving process of the pixel driving circuit. SUMMARY

[0005] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a pixel driving circuit and a display panel, and to simplify the pixel driving method.

[0006] According to one aspect of the present disclosure,

[0007] According to a first aspect of the present disclosure, a pixel driving circuit is provided, comprising:

[0008] a driving transistor connected to a first node and a third node;

[0009] a first transistor connected to a second node, for outputting a data voltage to the second node in response to a first scan signal;

[0010] a second transistor connected to the first node and the third node;

[0011] a fifth transistor connected to the second node, for outputting a reference voltage to the second node in response to a first reset signal;

[0012] a seventh transistor connected to the third node and a fourth node, for enabling electrical communication between the third node and the fourth node in response to a light-emitting control signal;

[0013] A storage capacitor is connected to the first node and the second node, and is used to store the data voltage and a threshold voltage of the driving transistor; in a threshold voltage compensation stage, the first node is charged to VDD+Vth; wherein VDD is a first power voltage, and Vth is the threshold voltage of the driving transistor.

[0014] According to an embodiment of the present disclosure, the pixel driving circuit further comprises a fourth transistor, a first electrode of the fourth transistor being used to load an initialization voltage, and a second electrode of the fourth transistor being connected to the first node.

[0015] According to an embodiment of the present disclosure, a channel region of the fifth transistor comprises a first sub-channel region and a second sub-channel region, and a conductorized second conductive wire is arranged to connect the first sub-channel region and the second sub-channel region in series; the first sub-channel region and the second sub-channel region are arranged along a row direction.

[0016] According to an embodiment of the present disclosure, the pixel driving circuit further comprises an eighth transistor, a first electrode of the eighth transistor being used to load an initialization voltage, and a second electrode of the eighth transistor being connected to the fourth node.

[0017] According to an embodiment of the present disclosure, the display panel is provided with a first reset wire;

[0018] The first reset wire overlaps with a channel region of the eighth transistor, so that the overlapping part is multiplexed as a gate electrode of the eighth transistor.

[0019] According to an embodiment of the present disclosure, a material of an active layer of the first transistor, the driving transistor, the fifth transistor, the seventh transistor and the eighth transistor is polycrystalline silicon semiconductor material.

[0020] According to an embodiment of the present disclosure, the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is located in a first gate layer of the display panel, and the second electrode plate is located in a second gate layer of the display panel; the second electrode plates arranged adjacent along a row direction are independently provided.

[0021] According to an embodiment of the present disclosure, the display panel is provided with a second gate layer, the second gate layer is provided with a power distribution wire extending along a row direction, and the power distribution wire is electrically connected to one or more first power voltage wires of the display panel.

[0022] According to an embodiment of the present disclosure, the display panel is provided with a second metal wiring layer, the second metal wiring layer is provided with a first power voltage wire, a data wire and a switching metal structure, and a pixel electrode of a light emitting element is connected to the switching metal structure through a via.

[0023] According to an embodiment of the present disclosure, a display panel is provided with a substrate, a driving circuit layer and a pixel layer which are stacked in sequence; a pixel driving circuit is arranged on the driving circuit layer; the pixel layer comprises a red light emitting element, a green light emitting element and a blue light emitting element; and a pixel electrode of the light emitting element is electrically connected with the pixel driving circuit.

[0024] According to a second aspect of the present disclosure, a display panel is provided, comprising the pixel driving circuit as described above.

[0025] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0026] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0027] Figure 1 A structural schematic diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0028] Figure 2 A structural schematic diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0029] Figure 3 A driving timing schematic diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0030] Figure 4 A structural schematic diagram of a polysilicon semiconductor layer of a display panel in an embodiment of the present disclosure.

[0031] Figure 5 A structural schematic diagram of a first gate layer of a display panel in an embodiment of the present disclosure.

[0032] Figure 6 A structural schematic diagram of a polysilicon semiconductor layer and a first gate layer of a display panel in an embodiment of the present disclosure.

[0033] Figure 7 A structural schematic diagram of a metal oxide semiconductor layer of a display panel in an embodiment of the present disclosure.

[0034] Figure 8 A structural schematic diagram of a second gate layer of a display panel in an embodiment of the present disclosure.

[0035] Figure 9A schematic diagram of a structure in which a metal oxide semiconductor layer and a second gate layer of a display panel are stacked in one embodiment of the present disclosure.

[0036] Figure 10 A schematic diagram of a structure in which a polycrystal semiconductor layer, a first gate layer, and a second gate layer of a display panel are stacked in one embodiment of the present disclosure.

[0037] Figure 11 A schematic diagram of a structure in which a polycrystal semiconductor layer, a first gate layer, and a second gate layer of a display panel are stacked in one embodiment of the present disclosure.

[0038] Figure 12 A schematic diagram of a structure of a first metal wiring layer of a display panel in one embodiment of the present disclosure.

[0039] Figure 13 A schematic diagram of a structure in which a polycrystal semiconductor layer, a first gate layer, a metal oxide semiconductor layer, a second gate layer, and a first metal wiring layer of a display panel are stacked in one embodiment of the present disclosure.

[0040] Figure 14 A schematic diagram of a structure of a first scan lead, a third scan lead, and a fifth metal wiring structure of a display panel in one embodiment of the present disclosure.

[0041] Figure 15 A schematic diagram of a structure of a first scan lead, a third scan lead, and a fifth metal wiring structure of a display panel in one embodiment of the present disclosure.

[0042] Figure 16 A schematic diagram of a structure of a second metal wiring layer of a display panel in one embodiment of the present disclosure.

[0043] Figure 17 A schematic diagram of a structure in which a first metal wiring layer and a second metal wiring layer of a display panel are stacked in one embodiment of the present disclosure.

[0044] Figure 18 A schematic diagram of a structure in which a second gate layer and a second metal wiring layer of a display panel are stacked in one embodiment of the present disclosure.

[0045] Figure 19 A schematic diagram of a structure in which a third electrode plate and a fourth electrode plate of a pixel driving circuit are stacked in one embodiment of the present disclosure.

[0046] Figure 20 A schematic diagram of a structure in which a polycrystal semiconductor layer, a first gate layer, a metal oxide semiconductor layer, a second gate layer, a first metal wiring layer, and a second metal wiring layer of a display panel are stacked in one embodiment of the present disclosure.

[0047] Figure 21A schematic diagram of a structure of a pixel electrode layer of a display panel in an embodiment of the present disclosure.

[0048] Figure 22 A schematic diagram of a structure of a polycrystal silicon semiconductor layer, a first gate layer, a metal oxide semiconductor layer, a second gate layer, a first metal wiring layer, a second metal wiring layer, and a pixel electrode layer of a display panel in an embodiment of the present disclosure.

[0049] Figure 23 A schematic diagram of a cross-sectional structure of a display panel in an embodiment of the present disclosure. Figure 12 at a position of a dashed line PQ shown.

[0050] Figure 24 A schematic diagram of a flow of a pixel driving method in an embodiment of the present disclosure.

[0051] Explanation of reference numerals:

[0052] 110, data writing unit; 120, threshold compensation unit; 130, light emitting control unit; 140, first reset unit; 150, second reset unit; 160, third reset unit; 170, light emitting element; M1, first transistor; M2, second transistor; M3, driving transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; M8, eighth transistor; Cst, storage capacitor; Gate_P, first scan signal; Gate_N, second scan signal; Re_P, first reset signal; Re_N, second reset signal; EM, light emitting control signal; Vref, reference voltage; Vdata, data voltage; Vinit, initialization voltage; VDD, first power voltage; VSS, second power voltage; GL1, first scan lead wire; GL2, second scan lead wire; GL21, first lead wire segment; GL22, second lead wire segment; GL3, third scan lead wire; RL1, first reset lead wire; RL2, second reset lead wire; RL21, third lead wire segment; RL22, fourth lead wire segment; RL3, third reset lead wire; EML, light emitting control lead wire; ViL, initialization signal lead wire; VRL, reference voltage lead wire; DataL, data lead wire; VDDL, first power voltage lead wire; N1, first node; N2, second node; N3, third node; N4, fourth node; H1, row direction; H2, column direction; F100, substrate substrate; F200, driving circuit layer; Buffer1, first buffer layer; Poly, polysilicon semiconductor layer; GI1, first gate insulating layer; Gate1, first gate layer; Buffer2, second buffer layer; Oxide, metal oxide semiconductor layer; GI2, second gate insulating layer; Gate2, second gate layer; ILD, interlayer dielectric layer; SD1, first metal wiring layer; PVX1, first passivation layer; PLN1, first planarization layer; SD2, second metal wiring layer; PVX2, second passivation layer; PLN2, second planarization layer; F300, pixel layer; F310, pixel electrode layer; F400, thin film packaging layer; F500, touch function layer; M1Act, channel region of first transistor; M2Act, channel region of second transistor; M3Act, channel region of third transistor; M4Act, channel region of fourth transistor; M5Act, channel region of fifth transistor; M6Act, channel region of sixth transistor; M7Act, channel region of seventh transistor; M8Act, channel region of eighth transistor; PL1, first conductive lead wire; PL2, second conductive lead wire; PL3, third conductive lead wire; PL4, fourth conductive lead wire; ML1, first metal wiring structure; ML2, second metal wiring structure; ML3, third metal wiring structure; ML4, fourth metal wiring structure; ML5, fifth metal wiring structure; ML6, sixth metal wiring structure; ML7, seventh metal wiring structure;ML8, eighth metal wiring structure; VDDGL, power distribution line; Hump1, first hump; Hump2, second hump; Hump3, third hump; Hump4, fourth hump; CP1, first electrode plate; CP2, second electrode plate; CP3, third electrode plate; CP4, fourth electrode plate; PR, pixel electrode of red light emitting element; PG, pixel electrode of green light emitting element; PB, pixel electrode of blue light emitting element; HA1, first bottom via region; HA2, second bottom via region; HA3, third bottom via region; HA4, fourth bottom via region; HA5, fifth bottom via region; HA6, sixth bottom via region; HA7, seventh bottom via region; HA8, eighth bottom via region; HA9, ninth bottom via region; HA10, tenth bottom via region; HA11, eleventh bottom via region; HA12, twelfth bottom via region; HA13, thirteenth bottom via region; HA14, fourteenth bottom via region; HA15, fifteenth bottom via region; HA16, sixteenth bottom via region; HA17, seventeenth bottom via region; HA18, eighteenth bottom via region; HA19, nineteenth bottom via region; HB1, first top via region; HB2, second top via region; HB3, third top via region; HB4, fourth top via region; HB5, fifth top via region; HB6, sixth top via region; HB7, seventh top via region; HB8, eighth top via region; HB9, ninth top via region; HB10, tenth top via region; HB11, eleventh top via region; HB12, twelfth top via region; HB13, thirteenth top via region; HB14, fourteenth top via region; HB15, fifteenth top via region; HB16, sixteenth top via region; HB17, seventeenth top via region; HB18, eighteenth top via region; HB19, nineteenth top via region; HAP, adapter via region; SubA, pixel driving region. DETAILED DESCRIPTION

[0053] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and description of these figures should be considered with reference to the detailed description. In addition, the drawings are not necessarily drawn to scale.

[0054] The terms "one", "a", "an", "the", and "at least one" are used to indicate that "one or more" of something is / are present; the terms "comprises", "comprising", "has", "having", "includes", "including", "contains", "containing" and variants thereof are used to indicate that a list of elements / components / etc. is not exclusive and that additional elements / components / etc. can be present; the term "first", "second", and "third" and the like are used merely as labels, and are not meant to impose numerical requirements on their objects.

[0055] In the display panel or pixel driving circuit of the present disclosure, the mutual overlap between two structures means that the two structures are stacked and intersected; that is, the two structures are located in different film layers of the display panel, and the orthographic projections of the two structures on the substrate overlap.

[0056] In the present disclosure, a transistor refers to an element including at least a gate, a drain, and a source, and has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to a region through which current mainly flows.

[0057] In the present disclosure, one of the drain and the source of a transistor is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor. In the case of using a transistor with opposite polarity, or in the case of changing the current direction in the operation of a circuit, the functions of the "source" and the "drain" are sometimes exchanged with each other. Therefore, in the present disclosure, in some cases, the first electrode can function as the source and the second electrode can function as the drain, and in other cases, the first electrode can function as the drain and the second electrode can function as the source.

[0058] In the present disclosure, unless otherwise specified, a via is a via in the conventional sense, and is not limited to the insulating film layer through which each via is formed or the conductive structure to which each via is connected.

[0059] The present disclosure provides a pixel driving circuit and a display panel using the same. Referring to Figure 1 The pixel driving circuit provided by the present disclosure comprises:

[0060] The driving transistor M3 is connected to the first node N1 and the third node N3, and is configured to output a driving current to the third node N3 under the control of the first node N1;

[0061] The storage capacitor Cst is connected to the first node N1 and the second node N2;

[0062] The data writing unit 110 is connected to the second node N2, and is configured to output a data voltage Vdata to the second node N2 in response to a first scan signal Gate_P;

[0063] The light emitting control unit 130 is connected to the third node N3 and the fourth node N4, and is configured to make the third node N3 and the fourth node N4 electrically connected in response to a light emitting control signal EM;

[0064] The first reset unit 140 is connected to the second node N2, and is configured to output a reference voltage Vref to the second node N2 in response to the light emitting control signal EM or a first reset signal Re_P;

[0065] The second reset unit 150 is connected to the first node N1, and is configured to output an initialization voltage Vinit to the first node N1 in response to a second reset signal Re_N.

[0066] In an embodiment of the present disclosure, the pixel driving circuit can further include a threshold compensation unit 120. The threshold compensation unit 120 is connected to the first node N1 and the third node N3, and is configured to make the first node N1 and the third node N3 electrically connected in response to a second scan signal Gate_N.

[0067] The pixel driving circuit provided by the present disclosure can be driven by the following pixel driving method: Figure 1 、 Figure 3 and Figure 24 ,

[0068] In step S110, in the reset stage T1, a first reset signal Re_P is loaded to the first reset unit 140 to load the reference voltage Vref to the second node N2; and a second reset signal Re_N is loaded to the second reset unit 150 to load the initialization voltage Vinit to the first node N1.

[0069] In step S120, in the data writing stage T2, a first scan signal Gate_P is loaded to the data writing unit 110 to load the data voltage Vdata to the second node N2; and a second scan signal Gate_N is loaded to the threshold compensation unit 120 to make the first node N1 and the third node N3 electrically connected until the current between the first node N1 and the third node N3 is zero, so as to write the threshold voltage of the driving transistor into the first node N1, and realize compensation of the threshold voltage of the driving transistor.

[0070] In step S130, in the light emitting stage T3, a light emitting control signal EM is loaded to the light emitting control unit 130 and the first reset unit 140 to make the third node N3 and the fourth node N4 electrically connected, and to load the reference voltage Vref to the second node N2.

[0071] It can be understood that, in the present disclosure, Figure 3In the illustrated timing diagram, the first reset signal Re_P, the first scan signal Gate_P, and the light-emitting control signal EM are active signals at a low level and are inactive base signals at a high level. The second reset signal Re_N and the second scan signal Gate_N are active signals at a high level and are inactive base signals at a low level. It can be understood that the high and low levels of the active signals in these signals can also be reversed to be able to realize the control of the corresponding unit.

[0072] In the pixel driving circuit and the driving method thereof provided in the present disclosure, in the reset stage, different reset signals can be used to control the first reset unit 140 and the second reset unit 150, respectively, so as to reset the second node N2 by using the reference voltage Vref and reset the first node N1 by using the initialization voltage Vinit. The reference voltage Vref is a positive voltage, which can be 3v, and the initialization voltage Vinit is a negative voltage, which can be -3v to -5v. In the data writing stage, the data voltage and the threshold voltage of the driving transistor can be written to the two ends of the storage capacitor, respectively, the first node N1 is charged to a voltage of VDD+Vth, and the second node N2 is written with the data voltage Data, so as to complete the data writing and the threshold voltage compensation of the driving transistor in the same stage, which can simplify the driving method of the pixel driving circuit. In the light-emitting stage, the first reset unit 140 can be controlled by the light-emitting control signal EM to reset the second node N2, and the voltage of the second node N2 changes from Data to Vref. According to the charge conservation principle, the voltage of the first node N1 jumps to VDD+Vth+Vref-Data, which realizes the pull-down (or pull-up) of the voltage of the first node N1, so that the driving transistor M3 can generate a driving current to drive the light-emitting element 170 to emit light.

[0073] In the following, the structure, principle and effect of the pixel driving circuit provided in the present disclosure are further explained and described in combination with the drawings.

[0074] Referring to Figure 23 The display panel provided in the present disclosure can include a substrate F100, a driving circuit layer F200 and a pixel layer F300 which are sequentially stacked. The pixel driving circuit provided in the present disclosure can be arranged in the driving circuit layer F200, and the light-emitting element 170 corresponding to the pixel driving circuit can be arranged in the pixel layer F300. One end of the light-emitting element 170 can be loaded with the second power voltage VSS, and the other end can be electrically connected to the fourth node of the pixel driving circuit. In this way, the pixel driving circuit can drive the corresponding light-emitting element 170 to emit light.

[0075] Referring to Figure 1In an embodiment of the present disclosure, the pixel driving circuit further comprises a third reset unit 160 connected to the fourth node N4, configured to output an initialization voltage Vinit to the fourth node N4 in response to a first reset signal Re_P. In this way, the pixel driving circuit can reset the first node N1, the second node N2 and the fourth node N4 at the same time at the reset stage, which can quickly eliminate the voltage difference between the cathode and the anode of the light emitting element 170, and avoid the smearing caused by the light emitting element 170 failing to stop emitting light in time.

[0076] Optionally, referring to Figure 2 The threshold compensation unit 120 comprises a second transistor M2 comprising a first electrode, a second electrode and a gate electrode, the first electrode is connected to the third node N3, the second electrode is connected to the first node N1, and the gate electrode is configured to load a second scan signal Gate_N. The active layer of the second transistor M2 is made of metal oxide semiconductor material. In this way, the second transistor M2 is an oxide transistor (Oxide-TFT), which has a low leakage current in the off state, so as to reduce the leakage of the first node N1, which is conducive to the potential holding of the storage capacitor Cst at the light emitting stage, and further reduces the flicker risk of the light emitting element 170 when driven at low frequency. In an embodiment of the present disclosure, the second transistor M2 is an N-type thin film transistor.

[0077] Further optionally, the gate electrode of the second transistor M2 comprises a first gate electrode and a second gate electrode both configured to load the second scan signal Gate_N, and the active layer of the second transistor M2 comprises a channel region. The first gate electrode, the channel region and the second gate electrode of the second transistor M2 are sequentially stacked. In this way, the channel region of the second transistor M2 is sandwiched between the first gate electrode and the second gate electrode, which can reduce the influence of floating body effect on the second transistor M2, and further reduce the leakage current of the second transistor M2 in the off state.

[0078] In an embodiment of the present disclosure, the pixel driving circuit is arranged on one side of the substrate F100. The first gate of the second transistor M2 is located on the side of the substrate F100 close to the channel region of the second transistor M2; the orthographic projection of the second gate of the second transistor M2 on the substrate F100 is located within the orthographic projection of the first gate of the second transistor M2 on the substrate F100. In other words, the first gate of the second transistor M2, the channel region of the second transistor M2, and the second gate of the second transistor M2 are sequentially arranged on the side of the substrate F100; the part of the active layer of the second transistor M2 overlapping with the second gate of the second transistor M2 serves as the channel region of the second transistor M2, and the channel region of the second transistor M2 is completely shielded by the first gate of the second transistor M2. In this way, the first gate of the second transistor M2 can shield the influence of external light on the channel region of the second transistor M2, and avoid the generation of photo-generated current in the channel region of the second transistor M2, thereby reducing the leakage current of the second transistor M2 in the off state.

[0079] Optionally, referring to Figure 3 , the second reset unit 150 includes a fourth transistor M4, the fourth transistor M4 includes a first electrode, a second electrode, and a gate, the first electrode is used to load an initialization voltage Vinit, the second electrode is connected to the first node N1, and the gate is used to load a second reset signal Re_N. The material of the active layer of the fourth transistor M4 is a metal oxide semiconductor material. In this way, the fourth transistor M4 is a metal oxide transistor, which has a low leakage current in the off state, thereby reducing the leakage of the first node N1, facilitating the potential holding of the storage capacitor Cst in the light-emitting stage, and further reducing the flicker risk of the light-emitting element 170 in low-frequency driving. In an embodiment of the present disclosure, the fourth transistor M4 is an N-type thin film transistor.

[0080] Further optionally, the gate of the fourth transistor M4 includes a first gate and a second gate both used to load the second reset signal Re_N, and the active layer of the fourth transistor M4 includes a channel region; the first gate, the channel region, and the second gate of the fourth transistor M4 are sequentially arranged in layers. In this way, the channel region of the fourth transistor M4 is sandwiched between the first gate and the second gate of the fourth transistor M4, which can reduce the influence of the floating body effect on the fourth transistor M4, and further reduce the leakage current of the fourth transistor M4 in the off state.

[0081] In an embodiment of the present disclosure, the pixel driving circuit is arranged on one side of the substrate F100. The first gate of the fourth transistor M4 is located on the side of the substrate F100 close to the channel region of the fourth transistor M4; the orthographic projection of the second gate of the fourth transistor M4 on the substrate F100 is completely located within the orthographic projection of the first gate of the fourth transistor M4 on the substrate F100.

[0082] In other words, the first gate of the fourth transistor M4, the channel region of the fourth transistor M4, and the second gate of the fourth transistor M4 are sequentially stacked on one side of the substrate F100; the portion of the active layer of the fourth transistor M4 that overlaps the second gate of the fourth transistor M4 serves as the channel region of the fourth transistor M4, and the channel region of the fourth transistor M4 is completely shielded by the first gate of the fourth transistor M4. In this way, the first gate of the fourth transistor M4 can shield the influence of external light on the channel region of the fourth transistor M4, and avoid the generation of photo-generated current in the channel region of the fourth transistor M4, thereby preventing the increase in leakage current of the fourth transistor M4 in the off state.

[0083] Optionally, the pixel driving circuit is disposed on one side of the substrate F100; the storage capacitor Cst includes at least two electrode plates that are stacked and insulated from each other, and the space between the two electrode plates is filled with an insulating medium. At least one of the electrode plates can be electrically connected to the first node N1, and at least one of the electrode plates can be electrically connected to the second node N2.

[0084] Further optionally, referring to Figure 23 The storage capacitor Cst includes a first electrode plate CP1, a second electrode plate CP2, a third electrode plate CP3, and a fourth electrode plate CP4 that are sequentially stacked on one side of the substrate F100, and an insulating medium is arranged between any two adjacent electrode plates; the first electrode plate CP1 and the third electrode plate CP3 are both electrically connected to the first node N1; the second electrode plate CP2 and the fourth electrode plate CP4 are both electrically connected to the second node N2. In this embodiment, the number of electrode plates of the storage capacitor Cst can be increased to increase the capacitance of the storage capacitor Cst, thereby reducing the influence of the leakage current of the first node N1 on the electromotive force at the first node N1, weakening or eliminating the flicker problem of the pixel driving circuit under low-frequency driving, and improving the display quality of the display panel using the pixel driving circuit.

[0085] Optionally, referring to Figure 23 The display panel using the pixel driving circuit further includes a first passivation layer PVX1 and a first planarization layer PLN1 that are sequentially stacked on the side of the third electrode plate CP3 away from the substrate F100, and the fourth electrode plate CP4 is arranged on the side of the first planarization layer PLN1 away from the substrate F100.

[0086] Referring to Figure 19The first planarization layer PLN1 at least includes a first portion SA1 and a second portion SA2. The first portion SA1 of the first planarization layer PLN1 is sandwiched between the third electrode plate CP3 and the fourth electrode plate CP4. The second portion SA2 of the first planarization layer PLN1 does not overlap with the third electrode plate CP3 and the fourth electrode plate CP4. The thickness of the first portion SA1 is less than the thickness of the second portion SA2. In other words, the display panel can reduce the distance between the third electrode plate CP3 and the fourth electrode plate CP4 at the first portion SA1 of the first planarization layer PLN1 by thinning the first portion SA1 of the first planarization layer PLN1, thereby improving the capacitance of the storage capacitor Cst.

[0087] Further optionally, the first planarization layer PLN1 can further include a third portion SA3 sandwiched between the first portion SA1 and the second portion SA2. The inner side edge SAE1 of the third portion SA3 can be completely located within the overlapping region of the third electrode plate CP3 and the fourth electrode plate CP4, and the outer side edge SAE2 of the third portion SA3 does not overlap with any one of the third electrode plate CP3 and the fourth electrode plate CP4. The thickness of the third portion SA3 of the first planarization layer PLN1 can be uniform, for example, the thickness is the same as that of the first portion SA1 or the second portion SA2, or can be non-uniform, for example, part of the thickness is the same as that of the first portion SA1 and the remaining part is the same as that of the second portion SA2. It can be understood that the thickness of the third portion SA3 of the first planarization layer PLN1 can also be in other states, for example, it can be in a gradual state, or in a stepped multiple mutation state, or in other regular or irregular states.

[0088] In one embodiment of the present disclosure, the third portion SA3 of the first planarization layer PLN1 can have the same thickness as the first portion SA1. In this way, both the first portion SA1 and the third portion SA3 of the first planarization layer PLN1 are thinned (both are thinning regions), so that the distance between the third electrode plate CP3 and the fourth electrode plate CP4 at any position of the overlapping region is reduced, which can maximize the capacitance value of the storage capacitor Cst. In addition, since the second portion SA2 is not overlapped with the third electrode plate CP3 and the fourth electrode plate CP4, i.e., the boundary of the thinning region of the first planarization layer PLN1 (i.e., the outer edge SAE2 of the third portion SA3) is outside the overlapping region of the third electrode plate CP3 and the fourth electrode plate CP4, this can avoid the boundary of the thinning region of the first planarization layer PLN1 being in the overlapping region of the third electrode plate CP3 and the fourth electrode plate CP4, thereby avoiding the deviation of the overlapping area between the overlapping region and the thinning region of the third electrode plate CP3 and the fourth electrode plate CP4 caused by process errors, and further avoiding the change of the capacitance value of the storage capacitor Cst caused by such deviation, which can ensure the uniformity of the storage capacitance value of the storage capacitor Cst of different drive circuits.

[0089] In another embodiment of the present disclosure, the third portion SA3 of the first planarization layer PLN1 can have the same thickness as the second portion SA2. In this way, both the second portion SA2 and the third portion SA3 of the first planarization layer PLN1 are not thinned, and the first portion SA1 of the first planarization layer PLN1 is thinned (is a thinning region). Since the thinned first portion SA1 is overlapped with the third electrode plate CP3 and the fourth electrode plate CP4, i.e., the boundary of the thinning region of the first planarization layer PLN1 (i.e., the inner edge SAE1 of the third portion SA3) is completely within the overlapping region of the third electrode plate CP3 and the fourth electrode plate CP4, this can avoid the boundary of the thinning region of the first planarization layer PLN1 being only partially in the overlapping region of the third electrode plate CP3 and the fourth electrode plate CP4, thereby avoiding the deviation of the overlapping area between the overlapping region and the thinning region of the third electrode plate CP3 and the fourth electrode plate CP4 caused by process errors, and further avoiding the change of the capacitance value of the storage capacitor Cst caused by such deviation, which can ensure the uniformity of the storage capacitance value of the storage capacitor Cst of different drive circuits.

[0090] In an embodiment of the present disclosure, the first portion SA1 of the first planarization layer PLN1 can have a thickness of zero to expose the first passivation layer PVX1. In this way, the first planarization layer PLN1 can have a hollowed-out shape at the position of the first portion SA1 to expose the first passivation layer PVX1, and the third electrode plate CP3 and the fourth electrode plate CP4 are isolated by the first passivation layer PVX1 at the hollowed-out portion. In other words, the first passivation layer PVX1 has the first portion SA1 sandwiched between the third electrode plate CP3 and the fourth electrode plate CP4, and the first planarization layer PLN1 has a hollowed-out portion to expose the first passivation layer PVX1; the hollowed-out portion of the first planarization layer PLN1 exposes at least part of the first portion SA1 of the first passivation layer PVX1. It can be understood that the third portion SA3 of the first planarization layer PLN1 can not have a hollowed-out shape at all, or can have a partially hollowed-out shape, or can have a completely hollowed-out shape. Therefore, the first portion SA1 of the passivation layer PVX1 can be partially located in the hollowed-out portion of the first planarization layer PLN1, or can be completely located in the hollowed-out portion of the first planarization layer PLN1.

[0091] Optionally, referring to Figure 2 The driving transistor M3 includes a first electrode, a second electrode, and a gate electrode, the first electrode is used to load a first power supply voltage VDD, the second electrode is connected to the third node N3, and the gate electrode is connected to the first node N1.

[0092] Optionally, referring to Figure 2 The data writing unit 110 can include:

[0093] The first transistor M1 includes a first electrode, a second electrode, and a gate electrode, the first electrode is used to load a data voltage Vdata, the second electrode is connected to the second node N2, and the gate electrode is used to load a first scan signal Gate_P.

[0094] Optionally, referring to Figure 2 The light emitting control unit 130 includes:

[0095] The seventh transistor M7 includes a first electrode, a second electrode, and a gate electrode, the first electrode is connected to the third node N3, the second electrode is connected to the fourth node N4, and the gate electrode is used to load a light emitting control signal EM.

[0096] Optionally, referring to Figure 2 The first reset unit 140 includes a fifth transistor M5 and a sixth transistor M6.

[0097] The fifth transistor M5 includes a first electrode, a second electrode, and a gate electrode, the first electrode is used to load a reference voltage Vref, the gate electrode is used to load a first reset signal Re_P, and the second electrode is connected to the second node N2.

[0098] The sixth transistor M6 comprises a first electrode, a second electrode and a gate electrode, the first electrode is used for loading a reference voltage Vref, the gate electrode is used for loading an emission control signal EM, and the second electrode is connected to the second node N2.

[0099] Optionally, referring to Figure 2 , the third reset unit 160 comprises:

[0100] The eighth transistor M8 comprises a first electrode, a second electrode and a gate electrode, the first electrode is used for loading an initialization voltage Vinit, the gate electrode is used for loading a first reset signal Re_P, and the second electrode is connected to the fourth node N4.

[0101] Optionally, the material of the active layer of the first transistor M1, the driving transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 is a polycrystalline semiconductor material, for example, can be a low-temperature polycrystalline semiconductor material. Further, the first transistor M1, the driving transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are P-type thin film transistors.

[0102] Optionally, referring to Figure 18 , the display panel comprises a data lead line DataL and a first power voltage lead line VDDL extending along the column direction H2. The data lead line DataL is electrically connected with the first electrode of the first transistor M1, and the first power voltage lead line VDDL is electrically connected with the first electrode of the driving transistor M3.

[0103] Referring to Figure 18The pixel driving circuit comprises a first metal wiring structure ML1 electrically connected with the first power voltage lead VDDL and insulated from the data lead DataL. Therefore, when the pixel driving circuit is working, the first power voltage VDD of constant voltage is loaded on the first metal wiring structure ML1. The orthogonal projection of the data lead DataL on the substrate F100 at least partially overlaps with the orthogonal projection of the first metal wiring structure ML1 on the substrate F100. In this way, the parasitic capacitance can be formed between the first metal wiring structure ML1 and the data lead DataL, thereby increasing the capacitance value of the parasitic capacitance of the data lead DataL. When the display panel is provided with a DEMUX (DE-Multiplexer) to drive multiple columns of pixel driving circuits, the data voltage Vdata of each column of pixel driving circuits will be pre-stored in the parasitic capacitance of the data lead DataL and written into the storage capacitor Cst after the first transistor M1 is turned on. In the present disclosure, since the parasitic capacitance of the data lead DataL is increased, the charge capacity of the data lead DataL is large, the proportion of lost charge when storing the charge forming the data voltage Vdata is smaller, and the storage capacitor Cst has stronger charging capacity in the data writing stage, thereby improving the charging rate of the storage capacitor Cst.

[0104] Optionally, referring to Figure 17 The pixel driving circuit further comprises a second metal wiring structure ML2. The second metal wiring structure ML2 is connected with the second electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6. Therefore, when the pixel driving circuit is working, the reference voltage Vref of constant voltage is loaded on the second metal wiring structure ML2. The orthogonal projection of the second metal wiring structure ML2 on the substrate F100 partially overlaps with the orthogonal projection of the data lead DataL on the substrate F100. In this way, the parasitic capacitance can be formed between the second metal wiring structure ML2 and the data lead DataL, thereby increasing the capacitance value of the parasitic capacitance of the data lead DataL. In this way, the charging rate of the storage capacitor Cst is improved.

[0105] In the present disclosure, referring to Figure 4, the row direction H1 has opposite first row direction H11 and second row direction H12. In the same pixel driving circuit, along the row direction H1, the channel region M3Act of the driving transistor M3 is located at the first row direction H11 side of the channel region M1Act of the first transistor M1; the channel region M1Act of the first transistor M1 is located at the second row direction H12 side of the channel region M3Act of the driving transistor M3. The column direction H2 has opposite first column direction H21 and second column direction H22. Along the column direction H2, the channel region M3Act of the driving transistor M3 is located at the first column direction H21 side of the channel region M1Act of the first transistor M1; the channel region M1Act of the first transistor M1 is located at the second column direction H22 side of the channel region M3Act of the driving transistor M3.

[0106] In one embodiment of the present disclosure, in the same pixel driving circuit, the first transistor M1 and the sixth transistor M6 are arranged in line along the first column direction H21, the seventh transistor M7 and the eighth transistor M8 are arranged in line along the first column direction H21, and the sixth transistor M6 and the seventh transistor M7 are arranged in line along the first row direction H11. Optionally, when the pixel driving circuit has the eighth transistor M8, the fifth transistor M5 and the eighth transistor M8 are arranged in line along the first row direction H11.

[0107] Figure 4 and Figure 7 The position of the channel region of each transistor in one embodiment is shown. Referring to FIG. 1, the channel region of the first transistor M1 is located at the first column direction H21 side of the channel region M3Act of the driving transistor M3; the channel region M3Act of the driving transistor M3 is located at the second column direction H22 side of the channel region M1Act of the first transistor M1. The channel region of the second transistor M2 is located at the second column direction H22 side of the channel region M1Act of the first transistor M1; the channel region M1Act of the first transistor M1 is located at the first column direction H21 side of the channel region M2Act of the second transistor M2. Figure 4 and Figure 7In an embodiment of the present disclosure, in the same pixel driving circuit, on the orthogonal projection of the column direction H2, the channel region M4Act of the fourth transistor M4, the channel region M2Act of the second transistor M2, the channel region M1Act of the first transistor M1, the channel region M3Act of the driving transistor M3, the channel region M6Act of the sixth transistor M6, and the channel region M5Act of the fifth transistor M5 are sequentially arranged along the first column direction H21. It can be understood that the channel region M4Act of the fourth transistor M4, the channel region M2Act of the second transistor M2, the channel region M1Act of the first transistor M1, the channel region M3Act of the driving transistor M3, the channel region M6Act of the sixth transistor M6, and the channel region M5Act of the fifth transistor M5 can not be arranged in a straight line along the first column direction H21. In the same pixel driving circuit, on the orthogonal projection of the row direction H1, the channel region M1Act of the first transistor M1, the channel region M4Act of the fourth transistor M4, the channel region M3Act of the driving transistor M3, and the channel region M7Act of the seventh transistor M7 are sequentially arranged along the first row direction H11, and the channel region M1Act of the first transistor M1, the channel region M4Act of the fourth transistor M4, the channel region M2Act of the second transistor M2, and the channel region M7Act of the seventh transistor M7 are sequentially arranged along the first row direction H11.

[0108] Referring to Figure 23 From the film layer structure, the display panel comprises a substrate F100, a driving circuit layer F200 and a pixel layer F300 which are sequentially stacked.

[0109] Optionally, the substrate F100 can be a substrate F100 of inorganic material or a substrate F100 of organic material. For example, in one embodiment of the present disclosure, the material of the substrate F100 can be a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate F100 can be Polymethyl methacrylate (PMMA), Polyvinylalcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Poly carbonate (PC), Polyethyleneterephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate F100 can also be a flexible substrate F100, for example, the material of the substrate F100 can be Polyimide (PI). The substrate F100 can also be a composite of multiple layers of materials, for example, in one embodiment of the present disclosure, the substrate F100 can include a Bottom Film, a pressure-sensitive adhesive layer, a first Polyimide layer, and a second Polyimide layer, which are sequentially stacked.

[0110] Optionally, referring to Figure 23 , the driving circuit layer F200 can include a first buffer layer Buffer1, a polysilicon semiconductor layer Poly, a first gate insulating layer GI1, a first gate layer Gate1, an interlayer dielectric layer ILD, a first metal wiring layer SD1, a first planarization layer PLN1, a second metal wiring layer SD2, and a second planarization layer PLN2, which are sequentially stacked on one side of the substrate F100. In one embodiment of the present disclosure, the driving circuit layer F200 can further include a first passivation layer PVX1 between the first metal wiring layer SD1 and the first planarization layer PLN1. Further, in one embodiment of the present disclosure, the driving circuit layer F200 can further include a second passivation layer PVX2 between the second metal wiring layer SD2 and the second planarization layer PLN2.

[0111] In an embodiment of the present disclosure, a metal oxide transistor can be arranged in the pixel driving circuit of the present disclosure, and the driving circuit layer F200 can further include a second buffer layer Buffer2, a metal oxide semiconductor layer Oxide, and an interlayer dielectric layer ILD arranged in sequence away from the substrate base plate on the side of the first gate layer Gate1. Further, the driving circuit layer can further include a second gate insulating layer GI2, a second gate layer Gate2, and an interlayer dielectric layer ILD arranged in sequence away from the substrate base plate on the side of the metal oxide semiconductor layer Oxide.

[0112] Optionally, the polysilicon semiconductor layer Poly can be provided with the active layer of the first transistor M1, the active layer of the driving transistor M3, the active layer of the fifth transistor M5, the active layer of the sixth transistor M6, and the active layer of the seventh transistor M7. Further optionally, the polysilicon semiconductor layer Poly can further be provided with the active layer of the eighth transistor M8 to form the eighth transistor M8 as the third reset unit 160. It can be understood that the active layer of any one of the above-mentioned first transistor M1, driving transistor M3, fifth transistor M5, sixth transistor M6, seventh transistor M7, and eighth transistor M8 can include a first electrode, a channel region, and a second electrode connected in sequence. Among them, the channel region of the transistor can maintain the semiconductor property, and the first electrode and the second electrode can be conductorized by doping or the like. Figure 4 In the middle, the position of the channel region of each transistor is shown.

[0113] Optionally, referring to Figure 4 , the polysilicon semiconductor layer Poly can further be provided with a conductorized first conductive lead PL1, and the channel region M1Act of the first transistor M1 and the channel region M6Act of the sixth transistor M6 are connected through the first conductive lead PL1. In this way, the first conductive lead PL1 can be reused as the second electrode of the first transistor M1 and the second electrode of the sixth transistor M6. Further, in one pixel driving circuit, the first conductive lead PL1 extends along the column direction H2.

[0114] In an embodiment of the present disclosure, referring to Figure 4 , the first electrode of the first transistor M1 is located on the side of the channel region M1Act of the first transistor M1 away from the channel region M6Act of the sixth transistor M6, which can have a first bottom via region HA1. The first bottom via region HA1 is electrically connected to the data lead DataL through a via, so that the Data loaded on the data lead DataL can be loaded to the first electrode of the first transistor M1.

[0115] In an embodiment of the present disclosure, referring to Figure 4 The first conductive lead PL1 can be part of the second node N2, which can have a second via hole area HA2 near one end of the channel region M6Act of the sixth transistor M6. The second via hole area HA2 is used to electrically connect the second electrode plate CP2 and the fourth electrode plate CP4 of the storage capacitor Cst through a via hole.

[0116] In an embodiment of the present disclosure, referring to Figure 4 The first electrode of the sixth transistor M6 and the first electrode of the fifth transistor M5 can be multiplexed, which are located on the side of the channel region M6Act of the sixth transistor M6 away from the channel region M1Act of the first transistor M1. The first electrode of the sixth transistor M6 can have a third via hole area HA3, which is used to electrically connect the reference voltage lead VrL through a via hole, so that the reference voltage Vref loaded on the reference voltage lead VrL can be loaded to the first electrodes of the sixth transistor M6 and the fifth transistor M5.

[0117] In an embodiment of the present disclosure, referring to Figure 4 The second electrode of the fifth transistor M5 can have a fourth via hole area HA4, which can be electrically connected to the first conductive lead PL1 through a via hole and other conductive structures, so that the second electrode of the fifth transistor M5 can be electrically connected to the second node N2.

[0118] Optionally, the channel region M5Act of the fifth transistor M5 includes a first sub-channel region and a second sub-channel region, and the polysilicon semiconductor layer Poly further includes a second conductive lead PL2 which is conductive and connects the first sub-channel region and the second sub-channel region in series. The first sub-channel region and the second sub-channel region both extend along the column direction H2 and are arranged along the row direction H1, and the second conductive lead PL2 connects one end of the first column direction H21 of the first sub-channel region and one end of the first column direction H21 of the second sub-channel region. Specifically, referring to Figure 4 The polysilicon semiconductor layer Poly is bent in a V shape between the first electrode of the fifth transistor M5 and the second electrode of the fifth transistor M5, which includes a first sub-channel region, a second conductive lead PL2 and a second sub-channel region connected in sequence, and the first sub-channel region and the second sub-channel region are respectively located on the two arms of the V-shaped bending structure. In this way, the length of the channel region M5Act of the fifth transistor M5 can be increased while the size of the pixel driving area SubA in the column direction H2 is reduced.

[0119] In an embodiment of the present disclosure, referring to Figure 4, the polysilicon semiconductor layer Poly can be further provided with a conductorized third conductive lead PL3, which can be reused as the first electrode of the driving transistor M3 and located on the side of the channel region M3Act of the driving transistor M3 close to the first conductive lead PL1. The third conductive lead PL3 can have a fifth bottom via region HA5 at the end thereof away from the channel region M3Act of the driving transistor M3, which is used to be electrically connected to the first power voltage lead VDDL through a via, so that the first power voltage VDD loaded on the first power voltage lead VDDL can be loaded to the first electrode of the driving transistor M3.

[0120] In an embodiment of the present disclosure, referring to Figure 4 , the polysilicon semiconductor layer Poly can be further provided with a conductorized fourth conductive lead PL4, which can be connected to the channel region M3Act of the driving transistor M3 to be reused as the second electrode of the driving transistor M3 and as part of the third node N3 of the pixel driving circuit. Optionally, the fourth conductive lead PL4 can extend along the column direction H2, and the end thereof located at the first column direction H21 can be connected to the channel region M7Act of the seventh transistor M7, so that the fourth conductive lead PL4 can be reused as the first electrode of the seventh transistor M7. The end of the fourth conductive lead PL4 located at the second column direction H22 can have a sixth bottom via region HA6, which is used to be connected to the second electrode of the second transistor M2 through a via.

[0121] In an embodiment of the present disclosure, referring to Figure 4 , the second electrode of the seventh transistor M7 is located on the side of the channel region M7Act of the seventh transistor M7 away from the fourth conductive lead PL4 and has a seventh bottom via region HA7. The seventh bottom via region HA7 is used to be electrically connected to the light emitting element 170 through a via. The second electrode of the seventh transistor M7 can be part of the fourth node N4 of the pixel driving circuit.

[0122] In an embodiment of the present disclosure, referring to Figure 4 , the pixel driving circuit is provided with an eighth transistor M8, the channel region M8Act of which is located on the side of the channel region M7Act of the seventh transistor M7 along the first column direction H21, and the second electrode of the seventh transistor M7 is reused as the second electrode of the eighth transistor M8. The first electrode of the eighth transistor M8 is located on the side of the channel region M8Act of the eighth transistor M8 away from the channel region M7Act of the seventh transistor M7 and has an eighth bottom via region HA8, which is used to be electrically connected to the initialization signal lead ViL through a via, so that the initialization voltage Vinit loaded on the initialization signal lead ViL can be loaded to the first electrode of the eighth transistor M8.

[0123] Referring to Figure 5 , the first gate layer Gate1 can be provided with a first scan lead GL1 for loading a first scan signal Gate_P, a first electrode plate CP1, a light emitting control lead EML for loading a light emitting control signal EM, and a first reset lead RL1 for loading a first reset signal Re_P. Optionally, the first scan lead GL1, the light emitting control lead EML, and the first reset lead RL1 extend along the row direction H1, and a plurality of pixel driving circuits arranged along the row direction H1 can share the same first scan lead GL1, the light emitting control lead EML, and the first reset lead RL1.

[0124] The first gate layer Gate1 can be provided with a gate of the first transistor M1, and the gate of the first transistor M1 is connected with the first scan lead GL1, so that the first transistor M1 can be turned on in response to the first scan signal Gate_P. In an embodiment of the present disclosure, referring to Figure 6 , a normal projection of a channel region Act of the first transistor M1 on the substrate F100 is located within a normal projection of the first scan lead GL1 on the substrate F100. In other words, the first scan lead GL1 can overlap with the channel region M1Act of the first transistor M1, so that the overlapping part is multiplexed as the gate of the first transistor M1.

[0125] The first gate layer Gate1 can be provided with a gate of the sixth transistor M6, and the gate of the sixth transistor M6 is connected with the light emitting control lead EML, so that the sixth transistor M6 can be turned on in response to the light emitting control signal EM. In an embodiment of the present disclosure, referring to Figure 6 , a normal projection of a channel region of the sixth transistor M6 on the substrate F100 is located within a normal projection of the light emitting control lead EML on the substrate F100. In other words, the light emitting control lead EML can overlap with the channel region M6Act of the sixth transistor M6, so that the overlapping part is multiplexed as the gate of the sixth transistor M6.

[0126] The first gate layer Gate1 can be provided with a gate of the seventh transistor M7, and the gate of the seventh transistor M7 is connected with the light emitting control lead EML, so that the seventh transistor M7 can be turned on in response to the light emitting control signal EM. In an embodiment of the present disclosure, referring to Figure 6 , a normal projection of a channel region of the seventh transistor M7 on the substrate F100 is located within a normal projection of the light emitting control lead EML on the substrate F100. In other words, the light emitting control lead EML can overlap with the channel region M7Act of the seventh transistor M7, so that the overlapping part is multiplexed as the gate of the seventh transistor M7.

[0127] The first gate layer Gate1 can be provided with a gate of the fifth transistor M5, and the gate of the fifth transistor M5 is connected with the first reset lead line RL1, so that the fifth transistor M5 can be turned on in response to the first reset signal Re_P. In an embodiment of the present disclosure, referring to Figure 6 , the first reset lead line RL1 can overlap with the channel region M5Act of the fifth transistor M5, so that the overlapping part is multiplexed as the gate of the fifth transistor M5. Exemplarily, the first sub-channel region and the second sub-channel region are located in the projection of the first reset lead line RL1 on the substrate substrate.

[0128] The first gate layer Gate1 can be provided with a gate of the eighth transistor M8, and the gate of the eighth transistor M8 is connected with the first reset lead line RL1, so that the eighth transistor M8 can be turned on in response to the first reset signal Re_P. In an embodiment of the present disclosure, referring to Figure 6 , the channel region Act of the eighth transistor M8 is located in the projection of the first reset lead line RL1 on the substrate F100. In other words, the first reset lead line RL1 can overlap with the channel region M8Act of the eighth transistor M8, so that the overlapping part is multiplexed as the gate of the eighth transistor M8.

[0129] The first electrode plate CP1 can cover the channel region M3Act of the driving transistor M3, so as to be multiplexed as the gate of the driving transistor M3. In this way, the first electrode plate CP1 can be part of the first node N1. In an embodiment of the present disclosure, referring to Figure 6 , the boundary of the first electrode plate CP1 on the side of the first row direction H11 is close to the fourth conductive lead line PL4, and the first electrode plate CP1 extends in the column direction H2 towards the first column direction H21 and the second column direction H22, so as to maximize the area of the first electrode plate CP1, thereby facilitating the increase of the capacitance value of the storage capacitor Cst.

[0130] In an embodiment of the present disclosure, referring to Figure 5 , the first electrode plate CP1 can have a thirteenth bottom via region HA13 for electrically connecting with the third electrode plate CP3 through a via. Further, the side of the first electrode plate CP1 close to L1 can be provided with a protruding part located on the side of the first column direction H21 of the third conductive lead line PL3; the thirteenth bottom via region HA13 is located in the protruding part.

[0131] Optionally, in the pixel driving area SubA, the first scan lead line GL1, the first electrode plate CP1, the light-emitting control lead line EML and the first reset lead line RL1 are sequentially arranged along the first column direction H21.

[0132] Optionally, the gate of the fourth transistor M4 includes a first gate of the fourth transistor M4 located in the first gate layer Gate1. See Figure 5 The first gate layer Gate1 can further be provided with a second reset lead RL2 for loading a second reset signal Re_N, the second reset lead RL2 being electrically connected with the first gate of the fourth transistor M4, so that the second reset signal Re_N can be loaded to the first gate of the fourth transistor M4, so that the fourth transistor M4 can be turned on in response to the second reset signal Re_N. Further, the second reset lead RL2 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same second reset lead RL2.

[0133] In an embodiment of the present disclosure, the fourth transistor M4 can be a metal oxide transistor. See Figure 7 The channel region M4Act of the fourth transistor M4 is located in the metal oxide semiconductor layer Oxide; and the orthographic projection of the channel region M4Act of the fourth transistor M4 on the first gate layer Gate1 can be completely located in the first gate of the fourth transistor M4. In this way, the first gate of the fourth transistor M4 can block the light from the side of the substrate from irradiating to the channel region M4Act of the fourth transistor M4, so as to avoid the light irradiation from increasing the leakage current of the fourth transistor M4 in the off state.

[0134] In an embodiment of the present disclosure, see Figure 11 The second reset lead RL2 can overlap with the channel region M4Act of the fourth transistor M4 located in the metal oxide semiconductor layer Oxide, to be reused as the first gate of the fourth transistor M4. See Figure 5 In the row direction H1, the second reset lead RL2 can include third lead segments RL21 and fourth lead segments RL22 arranged alternately and connected in sequence, the size of the third lead segment RL21 in the column direction H2 being greater than the size of the fourth lead segment RL22 in the column direction H2. The orthographic projection of the channel region M4Act of the fourth transistor M4 on the first gate layer Gate1 can be completely located in the third lead segment RL21, so that a part of the third lead segment RL21 can be used as the first gate of the fourth transistor M4.

[0135] Optionally, the gate of the second transistor M2 includes a first gate of the second transistor M2 located in the first gate layer Gate1. See Figure 5The first gate layer Gate1 can further be provided with a second scan lead GL2 for loading a second scan signal Gate_N. The second scan lead GL2 is electrically connected with the first gate of the second transistor M2, so that the second scan signal Gate_N can be loaded to the first gate of the second transistor M2, so that the second transistor M2 can be turned on in response to the second scan signal Gate_N. Further, the second scan lead GL2 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same second scan lead GL2.

[0136] In an embodiment of the present disclosure, the second transistor M2 can be a metal oxide transistor. Referring to Figure 7 The channel region M2Act of the second transistor M2 is located in the metal oxide semiconductor layer Oxide. The orthogonal projection of the channel region M2Act of the second transistor M2 on the first gate layer Gate1 can be completely located in the first gate of the second transistor M2. In this way, the first gate of the second transistor M2 can block the light from the side of the substrate substrate from irradiating the channel region M2Act of the second transistor M2, avoiding the light from causing the leakage current of the second transistor M2 in the off state to increase.

[0137] In an embodiment of the present disclosure, referring to Figure 11 The second scan lead GL2 can overlap with the channel region M2Act of the second transistor M2 arranged in the metal oxide semiconductor layer Oxide, to be reused as the first gate of the second transistor M2. For example, referring to Figure 5 Along the row direction H1, the second scan lead GL2 can include first lead segments GL21 and second lead segments GL22 arranged alternately and connected in sequence. The size of the first lead segment GL21 in the column direction H2 is greater than the size of the second lead segment GL22 in the column direction H2. For example, referring to Figure 11 The orthogonal projection of the channel region M2Act of the second transistor M2 on the first gate layer Gate1 can be completely located in the first lead segment GL21, so that a part of the first lead segment GL21 can be used as the first gate of the second transistor M2.

[0138] In an embodiment of the present disclosure, in the pixel driving area SubA, the second reset lead RL2, the second scan lead GL2, the first scan lead GL1, the first electrode plate CP1, the light-emitting control lead EML, and the first reset lead RL1 are arranged in the first column direction H21 in sequence.

[0139] In some embodiments of the present disclosure, referring to Figure 23The driving circuit layer F200 can include a second buffer layer Buffer2 and a metal oxide semiconductor layer Oxide which are sequentially stacked on one side of the first gate layer Gate1 away from the substrate F100. In this way, the pixel driving circuit of the present disclosure can be provided with a metal oxide transistor, and the channel region of the transistor is located in the metal oxide semiconductor layer Oxide.

[0140] Optionally, the fourth transistor M4 can be a metal oxide transistor, the active layer of the fourth transistor M4 is located in the metal oxide semiconductor layer Oxide, and includes a first electrode, a channel region M4Act and a second electrode which are sequentially connected. That is, the second electrode of the fourth transistor M4 and the first electrode of the fourth transistor M4 are located in the metal oxide semiconductor layer Oxide and on both sides of the channel region M4Act of the fourth transistor M4; the second electrode of the fourth transistor M4 and the first electrode of the fourth transistor M4 can be a conductive metal oxide, and the channel region M4Act of the fourth transistor M4 retains a semiconductor property.

[0141] Optionally, referring to Figure 7 , the first electrode of the fourth transistor M4, the channel region M4Act of the fourth transistor M4 and the second electrode of the fourth transistor M4 are arranged along the first column direction H21. The first electrode of the fourth transistor M4 has a ninth bottom via region HA9, and the ninth bottom via region HA9 is used to be electrically connected with the initialization signal lead ViL through a via, so that the initialization voltage Vinit can be loaded to the first electrode of the fourth transistor M4. The second electrode of the fourth transistor M4 has a tenth bottom via region HA10, and the tenth bottom via region HA10 is used to be electrically connected with the third electrode plate CP3 through a via.

[0142] In an embodiment of the present disclosure, two initialization signal leads ViL extending along the row direction H1 pass through one pixel driving area SubA, one initialization signal lead ViL is located at one end of the first column direction H21 of the pixel driving area, and the other initialization signal lead is located at one end of the second column direction H22 of the pixel driving area. In the pixel driving area SubA, the ninth bottom via region HA9 of the pixel driving circuit in the pixel driving area SubA can be electrically connected to the initialization signal lead ViL located at one end of the second column direction H22 through a via, and the eighth bottom via region HA8 of the pixel driving circuit in the pixel driving area SubA can be electrically connected to the initialization signal lead ViL located at one end of the first column direction H21 through a via. Correspondingly, two adjacent pixel driving areas SubA along the column direction H2 have an overlapping area, and the initialization signal lead ViL is arranged in the overlapping area, and the initialization signal lead ViL is shared by the pixel driving circuits in the two adjacent pixel driving areas SubA; that is, the initialization signal lead ViL is the initialization signal lead ViL located at one end of the first column direction H21 in the previous pixel driving area SubA, and is the initialization signal lead ViL located at one end of the second column direction H22 in the next pixel driving area SubA.

[0143] Optionally, the second transistor M2 can be a metal oxide transistor, the active layer of the second transistor M2 is located in the metal oxide semiconductor layer Oxide, and includes a first electrode, a channel region M2Act and a second electrode connected in sequence, that is, the second electrode of the second transistor M2 and the first electrode of the second transistor M2 are located on both sides of the channel region M2Act of the second transistor M2 in the metal oxide semiconductor layer Oxide; the second electrode of the second transistor M2 and the first electrode of the second transistor M2 can be a conductive metal oxide, and the channel region M2Act of the second transistor M2 retains a semiconductor property.

[0144] Optionally, referring to Figure 7 , the first electrode of the second transistor M2, the channel region M2Act of the second transistor M2 and the second electrode of the second transistor M2 are arranged along the second column direction H22. The second electrode of the second transistor M2 has an eleventh bottom via region HA11 for electrically connecting to the third electrode plate CP3 through a via. The first electrode of the second transistor M2 has a twelfth bottom via region HA12 for electrically connecting to the fourth conductive lead PL4 through a via.

[0145] In one embodiment of the present disclosure, in the pixel driving region SubA, the channel region M4Act of the fourth transistor M4 and the channel region M2Act of the second transistor M2 are located on the second column direction H22 side of the first scan lead GL1, and the channel region M4Act of the fourth transistor M4 is located on the second column direction H22 side of the channel region M2Act of the second transistor M2.

[0146] In some embodiments of the present disclosure, referring to Figure 23 , the driving circuit layer F200 can further be provided with a second gate insulating layer GI2 and a second gate layer Gate2 which are sequentially stacked on the side of the metal oxide semiconductor layer Oxide away from the substrate F100, and an interlayer dielectric layer ILD is located on the side of the second gate layer Gate2 away from the substrate.

[0147] Referring to Figure 8 , the second gate layer Gate2 can be provided with a second electrode plate CP2, and the second electrode plate CP2 partially overlaps the first electrode plate CP1. In one embodiment of the present disclosure, referring to Figure 10 , the second electrode plate CP2 has a notch exposing the thirteenth bottom via region HA13, so that the second electrode plate CP2 is completely not overlapped with the thirteenth bottom via region HA13 in the orthogonal projection of the first gate layer Gate1. In this way, the thirteenth bottom via region HA13 can be connected with the third electrode plate CP3 through the notch. Further, the notch is located on the second row direction H12 side of the second electrode plate CP2.

[0148] Referring to Figure 8 , the second electrode plate CP2 can have a seventeenth bottom via region HA17 for electrically connecting with a fourth electrode plate CP4 through a via. In this way, the storage capacitor Cst includes the first electrode plate CP1, the second electrode plate CP2, the third electrode plate CP3 and the fourth electrode plate CP4 which are sequentially stacked, the first electrode plate CP1 and the third electrode plate CP3 are electrically connected through the via, and the second electrode plate CP2 and the fourth electrode plate CP4 are electrically connected through the via. In one embodiment of the present disclosure, referring to Figure 8 , the second electrode plate CP2 has a fourth protruding portion Hump4, and the seventeenth bottom via region HA17 is arranged on the fourth protruding portion Hump4. Further, the fourth protruding portion Hump4 does not overlap the first electrode plate CP1. Exemplarily, the fourth protruding portion Hump4 is arranged on the first column direction H21 side of the second electrode plate CP2 and located on the second row direction H12 side, which can extend to overlap the channel region M6Act of the sixth transistor M6.

[0149] Optionally, the gate of the fourth transistor M4 includes a second gate of the fourth transistor M4 located on the second gate layer Gate2. Referring to Figure 8The second gate layer Gate2 can further be provided with a third reset lead line RL3 for loading a second reset signal Re_N. The third reset lead line RL3 is electrically connected with the second gate of the fourth transistor M4, so that the second reset signal Re_N can be loaded to the second gate of the fourth transistor M4, so that the fourth transistor M4 can be turned on in response to the second reset signal Re_N. Further, the third reset lead line RL3 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same third reset lead line RL3.

[0150] In an embodiment of the present disclosure, the fourth transistor M4 can be a metal oxide transistor, the channel region M4Act of the fourth transistor M4 is located in the metal oxide semiconductor layer Oxide, and the orthogonal projection of the channel region M4Act of the fourth transistor M4 on the second gate layer Gate2 can coincide with the second gate of the fourth transistor M4. Further, the third reset lead line RL3 can overlap with the channel region M4Act of the fourth transistor M4 located in the metal oxide semiconductor layer Oxide, to be reused as the second gate of the fourth transistor M4. For example, see Figure 9 and Figure 11 The third reset lead line RL3 extends along the row direction H1 and overlaps with the active layer of the fourth transistor M4; the part of the third reset lead line RL3 overlapping with the active layer of the fourth transistor M4 can be reused as the second gate of the fourth transistor M4; and the part of the active layer of the fourth transistor M4 overlapping with the third reset lead line RL3 can be the channel region M4Act of the fourth transistor M4.

[0151] In an embodiment of the present disclosure, the gate of the fourth transistor M4 includes the first gate of the fourth transistor M4 located in the first gate layer Gate1 and the second gate of the fourth transistor M4 located in the second gate layer Gate2, so that the fourth transistor M4 presents a double-gate structure, which can eliminate the influence of floating body effect and reduce the leakage current in the off state.

[0152] Optionally, the gate of the second transistor M2 includes the second gate of the second transistor M2 located in the second gate layer Gate2. See Figure 8 The second gate layer Gate2 can further be provided with a third scan lead line GL3 for loading a second scan signal Gate_N. The third scan lead line GL3 is electrically connected with the second gate of the second transistor M2, so that the second scan signal Gate_N can be loaded to the second gate of the second transistor M2, so that the second transistor M2 can be turned on in response to the second scan signal Gate_N. Further, the third scan lead line GL3 extends along the row direction H1, so that each pixel driving circuit arranged in the same row can share the same third scan lead line GL3.

[0153] In an embodiment of the present disclosure, the second transistor M2 can be a metal oxide transistor, the channel region M2Act of the second transistor M2 is located in the metal oxide semiconductor layer Oxide, and the orthogonal projection of the channel region M2Act of the second transistor M2 on the second gate layer Gate2 can coincide with the second gate of the second transistor M2. Further, referring to Figure 11 , the third scan lead line GL3 can overlap the channel region M2Act of the second transistor M2 located in the metal oxide semiconductor layer Oxide to be multiplexed as the second gate of the second transistor M2. Illustratively, the third scan lead line GL3 extends along the row direction H1 and overlaps the active layer of the second transistor M2; the portion of the third scan lead line GL3 overlapping the active layer of the second transistor M2 can be multiplexed as the second gate of the second transistor M2; and the portion of the active layer of the second transistor M2 overlapping the third scan lead line GL3 can be the channel region M2Act of the second transistor M2.

[0154] In an embodiment of the present disclosure, the gate of the second transistor M2 includes the first gate of the second transistor M2 located in the first gate layer Gate1 and the second gate of the second transistor M2 located in the second gate layer Gate2, so that the second transistor M2 has a dual-gate structure, which can eliminate the influence of floating body effect and reduce the leakage current in the off state.

[0155] Optionally, referring to Figure 8 , the second gate layer Gate2 can further be provided with a power distribution lead line VDDGL extending along the row direction H1, and the power distribution lead line VDDGL can be electrically connected with one or more first power voltage lead lines VDDL of the display panel. In this way, the wire conducting the first power voltage VDD can be gridded, reducing the voltage drop during transmission of the first power voltage VDD and improving the uniformity of the first power voltage VDD at different positions.

[0156] In an embodiment of the present disclosure, in the pixel driving area SubA, the power distribution lead line VDDGL is arranged between the third scan lead line GL3 and the second electrode plate CP2.

[0157] In an embodiment of the present disclosure, the power distribution lead line VDDGL extends along the row direction H1 and is electrically connected with each first power voltage lead line VDDL extending along the column direction H2.

[0158] Optionally, in the pixel driving area SubA, referring to Figure 8 and Figure 10The second gate layer Gate2 can further be provided with a first metal wiring structure ML1 extending along the column direction H2 and at least partially overlapping the first conductive lead PL1. The first metal wiring structure ML1 can be electrically connected with the first power voltage lead VDDL, so that the first metal wiring structure ML1 can be loaded with the first power voltage VDD. In this way, the first metal wiring structure ML1 can be loaded with a constant voltage signal, which can stabilize the voltage on the first conductive lead PL1 and avoid interference of other signals on the voltage on the first conductive lead PL1, especially interference of signals on the data lead DataL on the voltage on the first conductive lead PL1, and weaken the problem of vertical (column direction H2) crosstalk of the display panel. Furthermore, the first metal wiring structure ML1 and the data lead DataL can form a parasitic capacitance, which can further increase the parasitic capacitance of the data lead DataL, benefit the data lead DataL to keep the charge and improve the charging capacity of the storage capacitor Cst, and further improve the accuracy of Data written into the storage capacitor Cst, so that the display panel is more suitable for De-Mux driving.

[0159] In an embodiment of the present disclosure, the first metal wiring structure ML1 and the first conductive lead PL1 both extend along the column direction H2; the orthogonal projection of the first conductive lead PL1 on the row direction H1 is located within the orthogonal projection of the first metal wiring structure ML1 on the row direction H1. In this way, the width of the first metal wiring structure ML1 is greater than the width of the first conductive lead PL1, which can better shield the first conductive lead PL1. Further, in the column direction H2, the first metal wiring structure ML1 exposes the second bottom via area HA2 and covers other parts of the first conductive lead PL1.

[0160] In an embodiment of the present disclosure, referring to Figure 8 The first metal wiring structure ML1 has a fourteenth bottom via area HA14 for electrical connection with the first power voltage lead VDDL through a via. Further, one end of the second column direction H22 of the first metal wiring structure ML1 is connected with the power distribution lead VDDGL, so that the power distribution lead VDDGL is electrically connected with the first power voltage lead VDDL through the first metal wiring structure ML1.

[0161] Referring to Figure 12The first metal wiring layer SD1 can be provided with a third electrode plate CP3, an initialization signal lead line ViL and a reference voltage lead line VrL. The initialization signal lead line ViL extends along the row direction H1 and is used to load an initialization voltage Vinit. The reference voltage lead line VrL can extend along the row direction H1 and is used to load a reference voltage Vref. The third electrode plate CP3 can at least partially overlap the second electrode plate CP2 and is electrically connected to the first electrode plate CP1 through a via.

[0162] Optionally, referring to Figure 12 and Figure 13 , the initialization signal lead line ViL has an eighth top via region HB8 and a ninth top via region HB9. The eighth top via region HB8 and the eighth bottom via region HA8 can be directly connected through a via, so that the first electrode of the eighth transistor M8 is connected to the initialization signal lead line ViL through the via; the ninth top via region HB9 and the ninth bottom via region HA9 can be directly connected through a via, so that the first electrode of the fourth transistor M4 is connected to the initialization signal lead line ViL through the via.

[0163] Optionally, referring to Figure 12 and Figure 13 , the reference voltage lead line VrL has a third top via region HB3, and the third top via region HB3 and the third bottom via region HA3 can be directly connected through a via. Further, referring to Figure 12 and Figure 17 , the reference voltage lead line VrL has a first protruding part Hump1, which extends along the column direction H2 and can overlap the data lead line DataL located in the second metal wiring layer SD2. In this way, a larger parasitic capacitance is formed between the data lead line DataL and the reference voltage lead line VrL, which is beneficial to the driving of the display panel through the De-Mux method.

[0164] In an embodiment of the present disclosure, the reference voltage lead line VrL partially overlaps the first reset lead line RL1, and the first protruding part Hump1 extends along the second column direction H22 to overlap the third bottom via region HA3; the third top via region HB3 is located at one end of the first protruding part Hump1 along the second column direction H22.

[0165] Optionally, referring to Figure 12 and Figure 13 , the third electrode plate CP3 can have a thirteenth top via region HB13, and the thirteenth top via region HB13 and the thirteenth bottom via region HA13 can be directly connected through a via, so that the third electrode plate CP3 is connected to the first electrode plate CP1 through the via. In an embodiment of the present disclosure, the third electrode plate CP3 can be provided with a protruding part extending towards the second row direction H12, and the thirteenth top via region HB13 is arranged on the protruding part.

[0166] Optionally, referring to Figure 12 , the first metal wiring layer SD1 can be further provided with a second metal wiring structure ML2, which is arranged between the third electrode plate CP3 and the reference voltage lead VrL. The second metal wiring structure ML2 can have a second top via hole region HB2, a fourth top via hole region HB4 and a seventeenth top via hole region HB17. Referring to Figure 13 , the second top via hole region HB2 and the second bottom via hole region HA2 are directly connected by a via hole, the fourth top via hole region HB4 and the fourth bottom via hole region HA4 are directly connected by a via hole, and the seventeenth top via hole region HB17 and the seventeenth bottom via hole region HA17 are directly connected by a via hole. In this way, the second metal wiring structure ML2 electrically connects the second electrode of the first transistor M1, the second electrode of the fifth transistor M5, the second electrode of the sixth transistor M6 and the second electrode plate CP2 to each other as part of the second node N2 of the pixel driving circuit.

[0167] Further, referring to Figure 12 , the second metal wiring structure ML2 can further have an eighteenth bottom via hole region HA18. The eighteenth bottom via hole region HA18 is used to be electrically connected to the fourth electrode plate CP4 by a via hole. In this way, the second electrode plate CP2 and the fourth electrode plate CP4 can be electrically connected by the second metal wiring structure ML2, so that the second electrode plate CP2 and the fourth electrode plate CP4 are connected to the second node N2 of the pixel driving circuit.

[0168] Optionally, referring to Figure 12 , the first metal wiring layer SD1 can be further provided with a third metal wiring structure ML3. The third metal wiring structure ML3 has a projection on the substrate, which partially overlaps with the projection of the data lead DataL on the substrate and the projection of the third conductive lead PL3 on the substrate; in other words, the third metal wiring structure ML3 overlaps with the third conductive lead PL3 and the first metal wiring structure ML1. Referring to Figure 12 , the third metal wiring structure ML3 has a fifth top via hole region HB5, a fourteenth top via hole region HB14 and a sixteenth bottom via hole region HA16. Referring to Figure 13The fifth top via region HB5 and the fifth bottom via region HA5 are directly connected by a via, which makes the third metal wiring structure ML3 connected with the first electrode of the driving transistor M3 through the via. The fourteenth top via region HB14 and the fourteenth bottom via region HA14 are directly connected by a via, which makes the third metal wiring structure ML3 connected with the first metal wiring structure ML1 through the via. The sixteenth bottom via region HA16 is used for electrical connection with the first power voltage lead VDDL through a via, so that the first power voltage VDD loaded on the first power voltage lead VDDL is loaded to the first metal wiring structure ML1, the power distribution lead VDDGL and the first electrode of the driving transistor M3 through the third metal wiring structure ML3.

[0169] Optionally, referring to Figure 12 The first metal wiring layer SD1 can further be provided with a fourth metal wiring structure ML4, which has a first top via region HB1 and a fifteenth bottom via region HA15. Referring to Figure 13 The first top via region HB1 and the first bottom via region HA1 are directly connected by a via, and the fifteenth bottom via region HA15 is used for electrical connection with the data lead DataL through a via, so that the Data loaded on the data lead DataL is loaded to the first electrode of the first transistor M1 through the fourth metal wiring structure ML4. Further, the fourth metal wiring structure ML4 is located on one side of the third metal wiring structure ML3 in the second column direction H22.

[0170] Optionally, referring to Figure 12 The first metal wiring layer SD1 can further be provided with a fifth metal wiring structure ML5. The fifth metal wiring structure ML5 overlaps with the tenth bottom via region HA10 and the eleventh bottom via region HA11, and is connected with the third electrode plate CP3. The fifth metal wiring structure ML5 has a tenth top via region HB10 and an eleventh top via region HB11. Referring to Figure 13The tenth top via region HB10 and the tenth bottom via region HA10 are directly connected through a via, which makes the fifth metal wiring structure ML5 and the second electrode of the fourth transistor M4 connected through the via. The eleventh top via region HB11 and the eleventh bottom via region HA11 are directly connected through a via, which makes the fifth metal wiring structure ML5 and the second electrode of the second transistor M2 connected through the via. In this way, the second electrode of the fourth transistor M4 and the second electrode of the second transistor M2 are electrically connected to the third electrode plate CP3 and the first electrode plate CPI through the fifth metal wiring structure ML5, so that the second electrode of the fourth transistor M4 and the second electrode of the second transistor M2 are connected to the first node N1 of the pixel driving circuit through the fifth metal wiring structure ML5. Further, the fifth metal wiring structure ML5 extends in the column direction H2 as a whole, and the third metal wiring structure ML3 and the fourth metal wiring structure ML4 are located on the side of the second row direction H12 of the fifth metal wiring structure ML5.

[0171] Optionally, referring to Figure 14 The first scan lead GL1 overlaps with the fifth metal wiring structure ML5, that is, the orthographic projection of the first scan lead GL1 on the substrate F100 at least partially coincides with the orthographic projection of the fifth metal wiring structure ML5 on the substrate F100. In this way, although the second scan signal Gate_N affects the electromotive force of the third electrode plate CP3 (the first node N1) through the coupling effect of the fifth metal wiring structure ML5, the first scan signal Gate_P loaded on the first scan lead GL1 can exert an opposite coupling effect on the fifth metal wiring structure ML5, which makes the influence of the second scan signal Gate_N and the first scan signal Gate_P on the electromotive force of the first node N1 through the coupling effect cancel out, improving the accuracy of the electromotive force at the first node N1, and especially can improve the display accuracy of the pixel driving circuit under a low gray scale picture. Exemplarily, the display panel can be provided with a second scan lead GL2 or a third scan lead GL3 for loading the second scan signal Gate_N, and the second scan lead GL2 or the third scan lead GL3 overlaps with the fifth metal wiring structure ML5, and the first scan lead GL1 for loading the first scan signal Gate_P overlaps with the fifth metal wiring structure ML5.

[0172] It can be understood that the coupling capacitance formed by the overlap of the first scan lead GL1 and the fifth metal wiring structure ML5 is sized to be able to cancel out or as much as possible to cancel out the coupling effect of the second scan signal Gate_N on the fifth metal wiring structure ML5. In an embodiment of the present disclosure, referring to Figure 15The first scan lead GL1 can be provided with a second hump Hump2. A normal projection of the second hump Hump2 on the substrate F100 at least partially overlaps with a normal projection of the fifth metal wiring structure ML5 on the substrate F100. In other words, part or all of the second hump Hump2 can overlap with the fifth metal wiring structure ML5 to increase the overlapping area between the first scan lead GL1 and the fifth metal wiring structure ML5, and improve the coupling effect of the first scan lead GL1 on the fifth metal wiring structure ML5. Further, the second hump Hump2 can be located on the second column direction H22 side of the first scan lead GL1.

[0173] In an embodiment of the present disclosure, at least part of the region where the first scan lead GL1 overlaps with the fifth metal wiring structure ML5 can not overlap with the power distribution lead VDDGL, so as to overcome the shielding effect of the power distribution lead VDDGL on the first scan lead GL1.

[0174] In an embodiment of the present disclosure, the fifth metal wiring structure ML5 can be locally bent to avoid the twelfth bottom via region HA12.

[0175] Optionally, referring to Figure 12 The first metal wiring layer SD1 can further be provided with a sixth metal wiring structure ML6. The sixth metal wiring structure ML6 overlaps with the fourth conductive lead PL4 and the twelfth bottom via region HA12, and has a sixth top via region HB6 and a twelfth top via region HB12. Referring to Figure 13 The sixth top via region HB6 is directly connected with the sixth bottom via region HA6 through a via, which makes the sixth metal wiring structure ML6 connected with the fourth conductive lead PL4 through the via; and the twelfth top via region HB12 is directly connected with the twelfth bottom via region HA12 through a via, which makes the sixth metal wiring structure ML6 connected with the first electrode of the second transistor M2 through the via. In this way, the first electrode of the second transistor M2 is connected to the second electrode of the driving transistor M3 through the sixth metal wiring structure ML6, so that the sixth metal wiring structure ML6 can serve as part of the third node N3 of the pixel driving circuit. Further, the sixth metal wiring structure ML6 is located on the first row direction H11 side of the fifth metal wiring structure ML5.

[0176] Optionally, referring to Figure 12 The first metal wiring layer SD1 can further be provided with a seventh metal wiring structure ML7. The seventh metal wiring structure ML7 overlaps with a seventh bottom via region HA7, and has a seventh top via region HB7 and a nineteenth bottom via region HA19. Referring to Figure 13The seventh top via region HB7 and the seventh bottom via region HA7 are directly connected by a via hole, so that the seventh metal wiring structure ML7 is electrically connected with the second electrode of the seventh transistor M7. The nineteenth bottom via region HA19 is used to be connected with the light emitting element 170 by a via hole. Further, the seventh metal wiring structure ML7 is located between the third electrode plate CP3 and the reference voltage lead VrL, and extends along the row direction H1.

[0177] Referring to Figure 16 The second metal wiring layer SD2 can be provided with a data lead DataL and a first power voltage lead VDDL extending along the column direction H2, and a fourth electrode plate CP4. In an embodiment of the present disclosure, the data lead DataL, the first power voltage lead VDDL and the fourth electrode plate CP4 are arranged in sequence along the first row direction H11.

[0178] Optionally, referring to Figure 16 The data lead DataL has a fifteenth top via region HB15; referring to Figure 17 The fifteenth top via region HB15 and the fifteenth bottom via region HA15 are directly connected by a via hole. In this way, the data lead DataL is electrically connected with the first electrode of the first transistor M1 through the fourth metal wiring structure ML4.

[0179] Optionally, referring to Figure 16 The first power voltage lead VDDL has a sixteenth top via region HB16; referring to Figure 17 The sixteenth top via region HB16 and the sixteenth bottom via region HA16 are directly connected by a via hole. In this way, the first power voltage lead VDDL distributes the first power voltage VDD to the first metal wiring structure ML1 and the power distribution lead VDDGL through the third metal wiring structure ML3.

[0180] Optionally, referring to Figure 16 The first power voltage lead VDDL has a third protruding portion Hump3. The orthogonal projection of the third protruding portion Hump3 on the substrate F100 covers the orthogonal projection of the channel region M2Act of the second transistor M2 on the substrate F100 and the orthogonal projection of the channel region M4Act of the fourth transistor M4 on the substrate F100. In other words, the third protruding portion Hump3 covers the channel region M2Act of the second transistor M2 and the channel region M4Act of the fourth transistor M4, so as to shield the interference of external light and electromagnetic signals on the second transistor M2 and the fourth transistor M4, and especially avoid the light irradiation to the second transistor M2 and the fourth transistor M4, so as to avoid the increase of the leakage current of the second transistor M2 and the fourth transistor M4 in the off state.

[0181] Optionally, referring to Figure 16The fourth electrode plate CP4 has an eighteenth top via region HB18. Referring to Figure 17 The eighteenth top via region HB18 is directly connected with an eighteenth bottom via region HA18 through a via. In this way, the fourth electrode plate CP4 is electrically connected with the second electrode plate CP2 through the second metal wiring structure ML2. Further, referring to Figure 16 In the row direction H1, the eighteenth top via region HB18 is located at the second row direction H12 side of the fourth electrode plate CP4; in the column direction H2, the eighteenth top via region HB18 is located at the first column direction H21 side of the CP.

[0182] Optionally, referring to Figure 16 The second metal wiring layer SD2 can further be provided with an eighth metal wiring structure ML8. The eighth metal wiring structure ML8 at least partially overlaps with the seventh metal wiring structure ML7, wherein the eighth metal wiring structure ML8 has a nineteenth top via region HB19 and a transfer via region HAP. Referring to Figure 17 and Figure 20 The nineteenth top via region HB19 is directly connected with a nineteenth bottom via region HA19 through a via, so that the eighth metal wiring structure ML8 is electrically connected with the second electrode of the seventh transistor M7 through the seventh metal wiring structure ML7. The transfer via region HAP is used to be electrically connected with the pixel electrode of the light emitting element 170 through a via. In this way, the eighth metal wiring structure ML8 serves as a transfer metal structure of the pixel driving circuit. Further, the eighth metal wiring structure ML8 is located at the first row direction H11 side of the first power voltage lead VDDL and at the first column direction H21 side of the fourth electrode plate CP4. It can be understood that the shapes of the eighth metal wiring structures ML8 of the respective pixel driving circuits can or can not be the same.

[0183] Optionally, the pixel layer F300 can be provided on the side of the driving circuit layer F200 away from the substrate F100, and can include a pixel electrode layer F310. The pixel electrode layer F310 can be formed with pixel electrodes of light emitting elements, and each light emitting element can serve as a sub-pixel of the display panel of the present disclosure. The pixel electrode of the light emitting element can be connected with the transfer via region HAP through a via, so that the second electrode of the seventh transistor M7 is electrically connected with the light emitting element 170. The light emitting element can be an OLED (organic electroluminescent diode), an LED (light emitting diode), a Mini LED (mini light emitting diode), a Micro LED (micro light emitting diode), an OLED-QD (organic electroluminescent diode-quantum dot), or other types of electroluminescent devices.

[0184] In an embodiment of the present disclosure, the pixel layer includes red light emitting elements, green light emitting elements, and blue light emitting elements. Referring to Figure 21 and Figure 22The pixel electrodes in the pixel electrode layer F310 can include a pixel electrode PR of a red light-emitting element, a pixel electrode PG of a green light-emitting element, and a pixel electrode PB of a blue light-emitting element; each pixel electrode is connected with a transfer via hole area HAP of a corresponding pixel driving circuit.

[0185] The structure of the pixel layer F300 is exemplarily introduced as follows, taking the light-emitting element 170 as an OLED as an example. It can be understood that the structure of the pixel layer F300 can also be other structures, which can be provided according to the light-emitting element 170.

[0186] In the exemplary pixel layer F300, the pixel layer F300 includes a pixel electrode layer, a pixel definition layer, a support column layer, an organic light-emitting functional layer, and a common electrode layer which are sequentially stacked. The pixel electrode layer has a plurality of pixel electrodes in the display area of the display panel; the pixel definition layer has a plurality of through pixel openings in the display area, which are arranged one by one corresponding to the plurality of pixel electrodes, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode. The support column layer includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer away from the substrate substrate, so as to support a fine metal mask (FMM) in the evaporation process. The organic light-emitting functional layer at least covers the pixel electrode exposed by the pixel definition layer. The organic light-emitting functional layer can include an organic electroluminescent material layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Each film layer of the organic light-emitting functional layer can be prepared by an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation. The common electrode layer can cover the organic light-emitting functional layer in the display area. In this way, the pixel electrode, the common electrode layer, and the organic light-emitting functional layer located between the pixel electrode and the common electrode layer form an organic electroluminescent diode, and any one organic electroluminescent diode can serve as a sub-pixel of the display panel.

[0187] In some embodiments, the pixel layer can further include a light extraction layer located on the side of the common electrode layer away from the substrate substrate, so as to enhance the light extraction efficiency of the organic light-emitting diode.

[0188] Optionally, referring to Figure 23The display panel can further include a thin film encapsulation layer F400. The thin film encapsulation layer is arranged on the surface of the pixel layer away from the substrate, and can include inorganic encapsulation layers and organic encapsulation layers arranged alternately. The inorganic encapsulation layer can effectively block moisture and oxygen from the outside, so as to avoid water and oxygen from invading the organic light-emitting functional layer and causing material degradation. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers, so as to achieve planarization and weaken the stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer arranged sequentially on the side of the pixel layer away from the substrate.

[0189] Optionally, referring to Figure 23 The display panel can further include a touch function layer F500 arranged on the side of the thin film encapsulation layer away from the substrate, for realizing the touch operation of the display panel.

[0190] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure following the general principles thereof and including such departures from the present disclosure that come within known use or custom in the art. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A pixel driving circuit, characterized in that, include: A driving transistor includes a first electrode, a second electrode, and a gate, wherein the first electrode is used to apply a first power supply voltage, the second electrode is connected to a third node, and the gate is connected to the first node; The first transistor includes a first electrode, a second electrode, and a gate. The first electrode is used to load a data voltage, the second electrode is connected to a second node, and the gate is used to load a first scan signal. The second transistor connects the first node and the third node; The fifth transistor, connected to the second node, is used to output a reference voltage to the second node in response to the first reset signal; The seventh transistor, connecting the third node and the fourth node, is used to electrically connect the third node and the fourth node in response to a light emission control signal; A storage capacitor is connected to the first node and the second node. The storage capacitor is used to store the data voltage and the threshold voltage of the driving transistor. During the threshold voltage compensation phase, the first node is charged to VDD+Vth. Wherein, VDD is the first power supply voltage and Vth is the threshold voltage of the driving transistor. The pixel driving circuit is disposed on one side of the substrate of the display panel; the display panel includes data leads and a first power supply voltage lead extending along the column direction, the data leads being connected to the first electrode of the first transistor, and the first power supply voltage lead being electrically connected to the first electrode of the driving transistor; the pixel driving circuit includes a first metal wiring structure, the first metal wiring structure being electrically connected to the first power supply voltage lead and insulated from the data leads; the orthographic projection of the data leads on the substrate overlaps at least partially with the orthographic projection of the first metal wiring structure on the substrate; the display panel also includes power distribution leads extending along the row direction, the power distribution leads being integral with the first metal wiring structure.

2. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit further includes a fourth transistor, the first electrode of which is used to apply an initialization voltage, and the second electrode of which is connected to the first node.

3. The pixel driving circuit according to claim 1, characterized in that, The channel region of the fifth transistor includes a first subchannel region and a second subchannel region, and a conductive second conductive lead that connects the first subchannel region and the second subchannel region in series; the first subchannel region and the second subchannel region are arranged in the row direction.

4. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit further includes an eighth transistor, the first electrode of which is used to apply an initialization voltage, and the second electrode of which is connected to the fourth node.

5. The pixel driving circuit according to claim 4, characterized in that, The display panel is equipped with a first reset lead; The first reset lead overlaps with the channel region of the eighth transistor, such that the overlapping portion is reused as the gate of the eighth transistor.

6. The pixel driving circuit according to claim 4, characterized in that, The active layers of the first transistor, the driving transistor, the fifth transistor, the seventh transistor, and the eighth transistor are made of polycrystalline silicon semiconductor material.

7. The pixel driving circuit according to claim 1, characterized in that, The storage capacitor includes a first electrode plate and a second electrode plate. The first electrode plate is located in the first gate layer of the display panel, and the second electrode plate is located in the second gate layer of the display panel. The second electrode plates are arranged independently and are adjacent to each other along the row direction.

8. The pixel driving circuit according to claim 7, characterized in that, The display panel is provided with a second gate layer, and the second gate layer is provided with power distribution leads extending in the row direction. The power distribution leads are electrically connected to one or more first power supply voltage leads of the display panel.

9. The pixel driving circuit according to claim 1, characterized in that, The display panel is provided with a second metal wiring layer, and the second metal wiring layer is also provided with a transition metal structure. The pixel electrode of the light-emitting element is connected to the transition metal structure through a via.

10. The pixel driving circuit according to claim 1, characterized in that, The display panel comprises a substrate, a driving circuit layer, and a pixel layer stacked sequentially; the pixel driving circuit is disposed on the driving circuit layer; the pixel layer includes a red light-emitting element, a green light-emitting element, and a blue light-emitting element; the pixel electrode of the light-emitting element is electrically connected to the pixel driving circuit.

11. A display panel, characterized in that, Includes the pixel driving circuit according to any one of claims 1 to 10.

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