A sampling synchronization method for multiple digital oscilloscopes

Abstract

The application discloses a sampling synchronization method of multiple digital oscilloscopes, which mainly comprises two steps of clock synchronization and trigger synchronization; in the clock synchronization part, a master device crystal oscillator provides a source clock and outputs a synchronization clock signal to a slave device, the slave device obtains a transmission delay time of the synchronization clock signal through an internal counter and performs phase compensation to realize sampling clock synchronization; in the trigger synchronization part, the master and slave devices set the same trigger depth, the slave device establishes a trigger system through FIFO read-write enable signals and intermediate control signals FIFO_MID generated by the master device, read-write operations of trigger data are realized, then FPGA performs delay processing on the collected data, compensates for the determinate delay of edge detection and the indeterminate delay of a transmission path, and finally, timing adjustment is performed on the slave trigger signal FIFO_MID to complete trigger synchronization; when the digital oscilloscopes connected in series complete the sampling clock synchronization and the trigger synchronization in turn, the sampling synchronization of the multiple digital oscilloscopes is finally realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of digital oscilloscope, more specifically, relates to a sampling synchronization method of multiple digital oscilloscopes. BACKGROUND

[0002] Digital oscilloscope (DSO) is a kind of high-speed and high-precision measuring instrument, which is widely used in various complex electronic measurement fields. Compared with analog oscilloscope, it has the ability to store waveform data and process data, and the trigger mode is more abundant and the capture ability for complex waveforms is stronger. With the progress of electronic technology, the size of electronic equipment is becoming more and more different, and the test environment is becoming more and more complex. Therefore, in order to improve the adaptability of test instruments to different test environments, the demand for portable and small digital oscilloscopes is increasing. In order to reduce the size and weight of the equipment, this small digital oscilloscope often designs a small number of channels, which is not suitable for test scenarios that require simultaneous measurement of multiple signals. Therefore, in order to improve the test capability of small digital oscilloscope, a method of synchronizing multiple digital oscilloscopes to realize synchronous precise sampling must be designed. SUMMARY

[0003] The purpose of the present application is to overcome the shortcomings of the prior art and provide a sampling synchronization method of multiple digital oscilloscopes, which realizes the synchronization of multiple device data acquisition, storage and display through clock synchronization and trigger synchronization, and achieves high-precision index of multiple device synchronous trigger.

[0004] In order to achieve the above-mentioned purpose of the application, the sampling synchronization method of multiple digital oscilloscopes comprises the following steps:

[0005] (1) There are M digital oscilloscopes in the system that need to be sampled synchronously, and each digital oscilloscope is connected in series;

[0006] (2) Sampling clock synchronization of master and slave devices;

[0007] (2.1) The first digital oscilloscope is used as the master device, and the second digital oscilloscope is used as the slave device, and the digital oscilloscope acquisition process is performed;

[0008] (2.1.1) The internal crystal oscillator of the master device provides a 10MHz clock source for the clock chip, and at the same time, a 10MHz synchronization clock signal is output separately;

[0009] (2.1.2), the master and slave device internal circuit design is same, both designed with bidirectional input and output function of clock interface A and B, 10MHz synchronous clock signal through the FPGA clock programming control circuit in the master device to the clock interface B, the interface through the coaxial line and slave device clock interface A connected;

[0010] (2.1.3), 10MHz synchronous clock signal through the FPGA clock programming control circuit in the slave device to the clock circuit of slave device, the circuit constantly adjust the phase of slave device crystal oscillator, make it with 10MHz synchronous clock signal phase equal, adjust the crystal oscillator for slave device clock chip provides 10MHz clock source;

[0011] (2.1.4), the master and slave device with respective clock source through the same clock chip generates ADC sampling clock, start data collection, analog signal through the ADC transmission to the FPGA internal FIFO memory with the same path;

[0012] (2.2), to estimate the process, calculate the transmission delay time ΔT of synchronous clock signal from the master device crystal oscillator to the slave device crystal oscillator clk ;

[0013] (2.2.1), the signal generator generates 10MHz test signal, with equal length of coaxial connection line is connected to the clock interface A of master device and clock interface B of slave device, and into the FPGA in each device, this transmission time is recorded as T1 and T2, T1=T2;

[0014] (2.2.2), the test signal in the master device is transmitted to the clock circuit through the FPGA clock programming control module, the clock circuit constantly adjusts the phase of the master device crystal oscillator, so that it is equal to the phase of the test signal, the transmission time is recorded as Tclk; The adjusted crystal oscillator is transmitted to the clock interface A of the slave device according to the transmission path of (2.1.2), and finally transmitted to the FPGA inside the slave device, the transmission time is recorded as Tnet;

[0015] (2.2.3), the slave device starts the FPGA internal counter, and uses the FPGA internal wiring tool to make the path of the test signal to the counter the same as the transmission path of the clock signal in the FPGA clock programming control circuit. The counter starts counting after detecting the test signal output by the signal generator, and stops counting after detecting the synchronous clock signal. The counting time is: T=T1+Tclk+Tnet-T2=Tclk+Tnet;

[0016] (2.2.4), from the transmission path of the synchronous clock signal in (2.1.2) and (2.1.3) and the FPGA internal wiring layout in (2.2.3), it can be known that the transmission delay ΔT of the synchronous clock signal from the master device crystal oscillator to the slave device crystal oscillatorclk = Tclk+ Tnet, i.e. ΔT clk = T;

[0017] (2.3), master-slave sampling clock skew correction;

[0018] Let ΔT clk_min be the phase difference between the nearest rising edges of the master-slave sampling clock, T be the sampling clock period, N be the number of the maximum complete sampling clock periods contained by ΔT clk , and ΔT clk = ΔT clk min + NT delay the ADC sampling clock phase difference of the slave device until the master-slave device sampling clock phase is consistent, at which time the sampling clock of the master-slave device is synchronized;

[0019] (3), master-slave device trigger synchronization;

[0020] (3.1), the trigger source of the master device is set to the self-analog channel mode, the trigger source of the slave device is set to the external trigger channel mode, and the master-slave device is set to the same trigger depth;

[0021] (3.2), set the trigger condition of the master device, and the FPGA of the master device generates the FIFO read-write enable signal for data storage and reading according to the trigger condition;

[0022] (3.2.1), the master device generates the intermediate control signal FIFO_MID according to the FIFO read-write enable signal, and the specific generation process is as follows: when the rising edge of the FIFO write enable signal is detected, FIFO_MID is pulled high, when the falling edge of the FIFO read enable signal is detected, FIFO_MID is pulled low, and remains unchanged at other times;

[0023] (3.2.2), FIFO_MID enters the slave device through the connection cable of the master-slave device, and the FPGA of the slave device generates the FIFO read-write enable signal for data storage and reading of the slave device according to FIFO_MID; when the FPGA of the slave device detects the rising edge of FIFO_MID, the FIFO write enable signal of the slave device is pulled high, at which time the collected data is written into the FIFO of the slave device, until the length of the written data is equal to the pre-trigger depth, then the FIFO read enable signal of the slave device is pulled high, at which time the FIFO simultaneously performs the write and read operations of the collected data;

[0024] When the FPGA of the slave device detects the falling edge of FIFO_MID, the FIFO read enable signal of the slave device is pulled low, the FIFO stops reading data, and starts writing the collected data into the post-trigger storage area until the post-trigger storage area is full of data, then the write enable of the slave device is pulled low and the read enable is pulled high, the collected data after being full is taken out for subsequent processing, and the trigger process of the slave device is completed;

[0025] (3.3), trigger point offset correction;

[0026] The FPGA of the slave device performs delay processing on the collected data taken out, compensates for the delay of edge detection and transmission path, and adjusts the delay value through the upper computer until the trigger point position returns to the ideal trigger position;

[0027] (3.4), timing adjustment is performed on the slave trigger signal FIFO_MID to make it away from the metastable state interval of the slave processing clock;

[0028] The optimal delay value is determined in the following steps: the delay of the slave trigger signal is just away from the metastable state interval, the data transmission is from misalignment to alignment as the starting point delay0, then the delay value is increased to data from alignment to misalignment as the ending point delay1, and the optimal delay value is (delay0+delay1) / 2, then the FPGA calls the internal IDELAYE2 resource to independently adjust the delay of the slave trigger signal, and thus the trigger synchronization of the master and slave devices is completed.

[0029] (4), after the synchronization of the first and second digital oscilloscopes is completed, the second digital oscilloscope is set as the master device, the third digital oscilloscope is set as the slave device, and then the synchronization of steps (2) and (3) is completed, and then the synchronization of all digital oscilloscopes is completed in this way;

[0030] (5), after the synchronization of all digital oscilloscopes is completed, an arbitrary digital oscilloscope is selected as the master device, and the remaining digital oscilloscopes are slave devices, so as to form a multi-channel data acquisition system.

[0031] The application purpose of the application is achieved in this way:

[0032] The application is a kind of sampling synchronization method of multiple digital oscilloscopes, which mainly includes two steps of clock synchronization and trigger synchronization; in the clock synchronization part, the master device crystal oscillator provides a source clock and outputs a synchronization clock signal to the slave device, the slave device obtains the transmission delay time of the synchronization clock signal through an internal counter and performs phase compensation to realize sampling clock synchronization; in the trigger synchronization part, the master and slave devices set the same trigger depth, the slave device establishes a trigger system through the FIFO read-write enable signal and the intermediate control signal FIFO_MID generated by the master device, realizes the read-write operation of the trigger data, then the FPGA performs delay processing on the collected data, compensates the deterministic delay of edge detection and the uncertain delay of the transmission path, and finally adjusts the timing of the slave trigger signal FIFO_MID to complete the trigger synchronization. The digital oscilloscopes connected in series complete sampling clock synchronization and trigger synchronization in turn, and finally realize the sampling synchronization of multiple digital oscilloscopes.

[0033] Meanwhile, the application also has the following beneficial effects:

[0034] (1) The method can accurately realize the clock synchronization and trigger synchronization of the master and slave devices by calculating and compensating the transmission delay time, ensure the consistency of multiple digital oscilloscopes at the sampling and triggering time, and improve the synchronization accuracy compared with the traditional multi-machine synchronization method; higher synchronization accuracy can eliminate the sampling error caused by inconsistent clock and trigger, and provide more accurate and reliable data;

[0035] (2) The method supports the connection of multiple digital oscilloscopes, which can be combined according to actual scene requirements to achieve the purpose of expanding the number of channels; it can also expand the application range of digital oscilloscopes in high-speed multi-signal test scenes, solve the problem of relatively small number of channels, realize larger range of signal acquisition and analysis, and meet the complex experiment or test requirements;

[0036] (3) The multi-machine synchronization function is an important basis for subsequent multi-machine data splicing development, which can interval splice the multi-machine sampling data, improve the highest sampling rate of the digital oscilloscope by using the TIADC scheme, and further improve the acquisition performance of the digital oscilloscope. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a flow chart of the sampling synchronization method of multiple digital oscilloscopes of the application;

[0038] Figure 2 is a schematic diagram of the connection of multiple digital oscilloscopes;

[0039] Figure 3 is a clock circuit structure diagram of the slave device;

[0040] Figure 4is a clock signal transmission path delay schematic diagram. DETAILED DESCRIPTION

[0041] The specific embodiments of the present application are described below with reference to the accompanying drawings, so that those skilled in the art can better understand the present application. It should be particularly noted that in the following description, when the detailed description of the known functions and designs may obscure the main content of the present application, these descriptions will be omitted here.

[0042] EMBODIMENT

[0043] Figure 1 is a flow chart of a sampling synchronization method of a plurality of digital oscilloscopes of the present application.

[0044] In this embodiment, as shown in the figure, the sampling synchronization method of the plurality of digital oscilloscopes of the present application comprises the following steps: Figure 1

[0045] S1, set M digital oscilloscopes in the system to be sampled synchronously, and connect each digital oscilloscope in series in turn, as shown in the figure; Figure 2

[0046] S2, sampling clock synchronization of master and slave devices;

[0047] S2.1, take the first digital oscilloscope as the master device, and take the second digital oscilloscope as the slave device, and perform digital oscilloscope acquisition process;

[0048] S2.1.1, the internal crystal oscillator of the master device provides a 10MHz clock source for the clock chip, and at the same time, a 10MHz synchronization clock signal is separately output;

[0049] S2.1.2, the internal circuits of the master and slave devices are designed to be the same, and both are designed to have a clock interface A and B with bidirectional input and output functions, and the clock circuit design structure diagram and the clock signal transmission path in the acquisition mode are as shown in the figure, the 10MHz synchronization clock signal is transmitted to the clock interface B through the FPGA clock programming control circuit in the master device, and the interface is connected with the clock interface A of the slave device through a coaxial line; Figure 3

[0050] S2.1.3, the 10MHz synchronization clock signal is transmitted to the clock circuit of the slave device through the FPGA clock programming control circuit in the slave device, and the clock circuit is composed of a voltage optimization circuit, a phase-locked controller and a voltage-controlled oscillator VCO, the structure continuously adjusts the phase of the slave device crystal oscillator to make it equal to the phase of the synchronization clock signal, and the adjusted crystal oscillator provides a 10MHz clock source for the clock chip of the slave device;

[0051] ​​​S2.1.4, the master and slave devices generate the sampling clock of ADC with the same clock chip through the respective clock sources, start data collection, and transmit the analog signal to the internal FIFO memory of FPGA through the same path of ADC;

[0052] S2.2, perform an estimation process to calculate the transmission delay time ΔT of the synchronization clock signal from the master device crystal oscillator to the slave device crystal oscillator clk ;

[0053] S2.2.1, start the signal generator to generate a 10MHz test signal, connect the same length coaxial connection line to the clock interface A of the master device and the clock interface B of the slave device respectively, and enter the FPGA in each device, the transmission time is recorded as T1 and T2, T1=T2, and the signal transmission path delay is as shown in Figure 4 ;

[0054] S2.2.2, the test signal in the master device is transmitted to the clock circuit through the FPGA clock programming control module, the clock circuit continuously adjusts the phase of the master device crystal oscillator to be equal to the phase of the test signal, and the transmission time is recorded as Tclk; the adjusted crystal oscillator is transmitted to the clock interface A of the slave device according to the transmission path of S2.1.2, and finally transmitted to the internal FPGA of the slave device, and the transmission time is recorded as Tnet;

[0055] S2.2.3, the slave device starts the internal counter of FPGA, and uses the internal wiring tool of FPGA to make the path of the test signal to the counter the same as the transmission path of the clock signal in the FPGA clock programming control circuit, the counter starts counting after detecting the test signal output by the signal generator, and stops counting after detecting the synchronization clock signal, and the counting time is: T=T1+Tclk+Tnet-T2=Tclk+Tnet;

[0056] S2.2.4, according to the synchronization clock signal transmission path in S2.1.2 and S2.1.3 and the internal FPGA wiring layout in S2.2.3, the transmission delay ΔT of the synchronization clock signal from the master device crystal oscillator to the slave device crystal oscillator is clk =Tclk+Tnet, that is, ΔT clk =T;

[0057] S2.3, master-slave sampling clock skew correction;

[0058] The sampling clock phase adjustment can be adjusted inside the clock chip HMC7044 or ADC. HMC7044 provides an analog adjustment scheme for the output clock, with an adjustment step of 25ps and a maximum adjustment of 600ps. This design uses ADC clock delay adjustment with a coarse adjustment step of 1.13ps, a maximum adjustment of 289ps, a fine adjustment step of 19fs, and a maximum adjustment of 4.9ps. Considering the adjustment accuracy, the ADC internal adjustment scheme is selected;

[0059] Let ΔT clk_min be the phase difference between the nearest rising edges of the master and slave sampling clocks, T be the sampling clock period, N be the number of complete sampling clock periods contained in ΔT clk , and ΔT clk be the number of complete sampling clock periods contained in ΔT clk_min + NT delay the slave device's ADC sampling clock phase difference until the master and slave device sampling clock phases are consistent, and the master and slave device sampling clock synchronization is completed;

[0060] S3, trigger synchronization of the master and slave devices;

[0061] S3.1, the trigger source of the master device is set to the self-analog channel mode, the trigger source of the slave device is set to the external trigger channel mode, and the master and slave devices are set to the same trigger depth;

[0062] S3.2, set the master device trigger condition, and the FPGA of the master device generates the FIFO read-write enable signal for data storage and reading according to the trigger condition;

[0063] S3.2.1, the master device generates the intermediate control signal FIFO_MID according to the FIFO read-write enable signal, and the specific generation process is as follows: when the rising edge of the FIFO write enable signal is detected, FIFO_MID is pulled high, when the falling edge of the FIFO read enable signal is detected, FIFO_MID is pulled low, and at other times, it remains unchanged;

[0064] S3.2.2, FIFO_MID enters the slave device through the connection cable of the master and slave devices, and the FPGA of the slave device generates the FIFO read-write enable signal for data storage and reading of the slave device according to FIFO_MID; when the FPGA of the slave device detects the rising edge of FIFO_MID, the FIFO write enable signal of the slave device is pulled high, at this time, the collected data starts to be written into the FIFO of the slave device, until the length of the written data is equal to the pre-trigger depth, then the FIFO read enable signal of the slave device is pulled high, at this time, the FIFO simultaneously performs the write and read operations of the collected data;

[0065] When the FPGA of the slave device detects the falling edge of FIFO_MID, the FIFO read enable signal of the slave device is pulled low, the FIFO stops reading data, and the collected data is written into the post-trigger storage area until the post-trigger storage area is full of data, then the write enable is pulled low and the read enable is pulled high, and the collected data after writing is taken out for subsequent processing, and the slave device trigger process is completed;

[0066] S3.3, trigger point offset correction;

[0067] The slave control signal has a certain delay compared with the master control signal, including the certain beat delay caused by edge detection and the uncertain delay caused by transmission path. Since the clock circuit is synchronized before the trigger process, the sampling points of the master and slave devices have been synchronized, so the delay of the slave trigger signal means that the trigger point will enter the FIFO earlier than the trigger signal, which will cause the deviation of the trigger points of the master and slave devices and the offset of the slave trigger point relative to the normal case, so the delay must be corrected to synchronize the trigger points of the master and slave devices and appear at the ideal trigger position;

[0068] The beat delay is fixed and known, the beat clock is 320MHz, and the delay caused by each beat is 1 / 320MHz=3.125ns. The number of beats is two, which is the number of edges detected by the master and the slave, so the collected data of the slave also needs to be beat twice. The uncertain delay caused by the transmission path is adjusted by the IDelayE2 statement integrated in the FPGA to adjust the delay of the collected data. The corresponding port configuration value is modified in the host software to dynamically adjust the delay value until the trigger point position returns to the ideal trigger position.

[0069] S3.4, timing adjustment of the slave trigger signal FIFO_MID to make it away from the metastable state interval of the slave processing clock;

[0070] When the total delay of the slave trigger signal transmission is close to the processing clock period, it may not meet the setup and hold time requirements of the slave processing clock, resulting in metastability. Once metastability occurs, the signal may not take effect for one or even multiple cycles, which will cause timing chaos of the trigger signal in the collection mode and error reading and writing control of the FIFO, which is displayed as different trigger point positions after each power-on on the waveform. In order to make the transmission signal away from the metastable state interval of the slave processing clock, it needs to be properly delayed in time.

[0071] The optimal delay value is determined by the following steps: delaying the FIFO_MID signal to just away from the metastable interval, the data transmission from misaligned to aligned as the starting point delay0, then increasing the delay value to data just from aligned to misaligned as the end point delay1, and the optimal delay value is (delay0+delay1) / 2, then the FPGA calls the internal IDELAYE2 resource to independently adjust the delay of the slave trigger signal, and the master-slave device trigger synchronization is completed.

[0072] S4, after the synchronization of the first and second digital oscilloscopes is completed, the second digital oscilloscope is set as the master device, the third digital oscilloscope is set as the slave device, and the synchronization is completed according to steps (2) and (3), and then the synchronization of all digital oscilloscopes is completed in this way;

[0073] S5, after the synchronization of all digital oscilloscopes is completed, an arbitrary digital oscilloscope is selected as the master device, and the remaining digital oscilloscopes are all slave devices, so as to form a multi-channel data acquisition system.

[0074] Although the above describes the specific embodiments of the present application in detail, so as to facilitate the understanding of the present application by the skilled in the art, it should be clear that the present application is not limited to the scope of the specific embodiments, and for the ordinary skilled in the art, all kinds of changes are obvious within the spirit and scope of the present application limited and determined by the appended claims, and all kinds of application and creation using the concept of the present application are included in the protection.

Claims

1. A sampling synchronization method for multiple digital oscilloscopes, characterized in that, Includes the following steps: (1) Suppose there are M digital oscilloscopes in the system that need to be sampled synchronously. Each digital oscilloscope is connected in series. The trigger port and clock interface on the synchronous transmission module of the previous digital oscilloscope are connected to the trigger port and clock interface on the synchronous receiving module of the next digital oscilloscope. That is, the trigger port of the synchronous transmission module is connected to the trigger port of the synchronous receiving module, and the clock interface of the synchronous transmission module is connected to the clock interface of the synchronous receiving module, and so on. (2) Sampling clock synchronization between master and slave devices; (2.1) The first digital oscilloscope is used as the master device, and the second digital oscilloscope is used as the slave device. Perform digital oscilloscope acquisition process; (2.1.1) The internal crystal oscillator of the main device provides a 10MHz clock source for the clock chip, and at the same time outputs a separate 10MHz synchronous clock signal; (2.1.2) The internal circuit design of the master and slave devices is the same. Both are designed with clock interfaces A and B with bidirectional input and output functions. The 10MHz synchronous clock signal is transmitted to clock interface B through the FPGA clock programming control circuit in the master device. This interface is connected to the clock interface A of the slave device through a coaxial cable. (2.1.3) The 10MHz synchronous clock signal is transmitted to the clock circuit of the slave device through the FPGA clock programming control circuit in the slave device. The circuit continuously adjusts the phase of the crystal oscillator of the slave device to make it equal to the phase of the 10MHz synchronous clock signal. The adjusted crystal oscillator provides a 10MHz clock source for the clock chip of the slave device. (2.1.4) The master and slave devices generate the sampling clock of the ADC through the same clock chip with their own clock source and start data acquisition. The analog signal is transmitted to the internal FIFO memory of the FPGA through the ADC along the same path. (2.2) Perform the estimation process and calculate the transmission delay ΔT of the synchronization clock signal from the master device crystal oscillator to the slave device crystal oscillator. clk ; (2.2.1) Start the signal generator to generate a 10MHz test signal, and connect it to the clock interface A of the master device and the clock interface B of the slave device with coaxial cables of equal length, and enter the FPGA in each device. This transmission time is recorded as T1 and T2, T1=T2. (2.2.2) The test signal in the master device is transmitted to the clock circuit through the FPGA clock programming control module. The clock circuit continuously adjusts the phase of the master device crystal oscillator to make it equal to the phase of the test signal. This transmission time is recorded as Tclk. The adjusted crystal oscillator is transmitted to the clock interface A of the slave device according to the transmission path (2.1.2), and finally transmitted to the slave device FPGA. The transmission time is recorded as Tnet. (2.2.3) Start the FPGA internal counter from the device, and use the FPGA internal routing tool to make the path of the test signal to the counter the same as the transmission path of the clock signal in the FPGA clock programming control circuit. The counter starts counting after detecting the test signal output by the signal generator and stops counting after detecting the synchronous clock signal. The counting time is: T=T1+Tclk+Tnet-T2= Tclk+Tnet. (2.2.4) From the synchronous clock signal transmission path in (2.1.2) and (2.1.3) and the FPGA internal wiring layout in (2.2.3), it can be seen that the transmission delay ΔT of the synchronous clock signal from the master device crystal oscillator to the slave device crystal oscillator is... clk =Tclk+Tnet, i.e., ΔT clk =T; (2.3) Master-slave sampling clock skew correction; Let ΔT clk_min The phase difference between the most recent rising edges of the master and slave sampling clocks, where T is the sampling clock period and N is ΔT. clk The maximum number of complete sampling clock cycles included, based on ΔT clk =ΔT clk_min +NT delays the phase difference of the ADC sampling clock of the slave device until the sampling clock phases of the master and slave devices are consistent, at which point the sampling clock synchronization of the master and slave devices is completed; (3) Triggering synchronization of master and slave devices; (3.1) The trigger source of the master device is set to its own simulated channel mode, the trigger source of the slave device is set to the external trigger channel mode, and the master and slave devices are set to the same trigger depth; (3.2) Set the master device trigger conditions. The FPGA of the master device generates FIFO read / write enable signals to control data storage and reading according to the trigger conditions; (3.2.1) The master device generates the intermediate control signal FIFO_MID together with the FIFO read and write enable signal. The specific generation process is as follows: when the rising edge of the FIFO write enable signal is detected, FIFO_MID is pulled high; when the falling edge of the FIFO read enable signal is detected, FIFO_MID is pulled low; otherwise, it remains unchanged. (3.2.2) FIFO_MID enters the slave device through the connection cable between the master and slave devices. The FPGA of the slave device generates a FIFO read / write enable signal to control the data storage and reading of the slave device based on FIFO_MID. When the FPGA of the slave device detects the rising edge of FIFO_MID, it pulls up the FIFO write enable signal of the slave device. At this time, it starts writing the acquired data to the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth. Then it pulls up the FIFO read enable signal of the slave device. At this time, the FIFO performs both writing and reading operations of the acquired data. When the FPGA of the slave device detects the falling edge of FIFO_MID, it pulls the FIFO read enable signal of the slave device low, the FIFO stops reading data, and starts writing the acquired data into the post-trigger memory area. This continues until the post-trigger memory area is full. Then, the slave device write enable is pulled low and the read enable is pulled high to retrieve the acquired data after it is full for subsequent processing, thus completing the slave device triggering process. (3.3) Trigger point offset correction; The FPGA of the device performs delay processing on the acquired data to compensate for the delay of edge detection and transmission path. This delay value is adjusted by the host computer until the trigger point position returns to the ideal trigger position. (3.4) Adjust the timing of the slave trigger signal FIFO_MID to keep it away from the metastable range of the slave processing clock; The optimal delay value is determined by the following steps: Delay the FIFO_MID signal until it is just away from the metastable range, with the data transmission going from misaligned to aligned as the starting point delay0. Then increase the delay value until the data goes from aligned to misaligned as the ending point delay1. The optimal delay value is (delay0+delay1) / 2. Then the FPGA calls the internal IDELAYE2 resource to independently adjust the delay of the slave trigger signal, thus completing the master-slave device trigger synchronization. (4) After the first and second digital oscilloscopes are synchronized, set the second digital oscilloscope as the master device and the third digital oscilloscope as the slave device, and then complete the synchronization according to steps (2) and (3). Then, in this way, complete the synchronization of all digital oscilloscopes. (5) After all digital oscilloscopes are synchronized, one digital oscilloscope can be selected as the master device and the rest of the digital oscilloscopes are slave devices, thus forming a multi-channel data acquisition system.

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