A test circuit and device with power-on protection

Abstract

The application provides a test circuit and device with power-on protection, wherein a power supply circuit is connected with a delay circuit, so that the power supply circuit is turned on, and the power supply circuit is used to perform power-on test on a mainboard, and the current limiting effect is realized while the power supply circuit supplies power to the mainboard, thereby replacing the linear power supply, reducing the detection cost, avoiding the problem of excessive current caused by the abnormal mainboard, and improving the detection success rate. Meanwhile, the current limiting protection circuit is connected with the power-on protection circuit, and whether the mainboard has a short circuit problem is judged. When the power-on protection circuit detects that the mainboard has a short circuit, the power supply circuit is controlled to be disconnected, so that the power supply to the mainboard is stopped. When the power-on protection circuit does not detect that the mainboard has a short circuit, the delay circuit controls the power supply circuit to directly supply power to the mainboard from the power supply after a period of time, so that the mainboard can be used for subsequent test on other modules, and the automatic control of the current limiting time of the circuit is realized, and the operation efficiency of the debugging process is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of test circuit, in particular to a test circuit with power-on protection and device. BACKGROUND

[0002] When a mainboard which has not been debugged is powered on for the first time, the mainboard may be damaged due to short circuit or abnormal device, etc. To this end, two methods are usually used to protect the mainboard from power-on. One is to use a linear power supply with current limiting protection function to supply power to the mainboard, but this method requires the use of a linear power supply with current limiting protection, which has high testing cost. In addition, during the debugging process, the current limiting value of the linear power supply needs to be set first, and after the test mainboard is powered on without abnormality, the current limiting value of the linear power supply needs to be set again to make the mainboard work normally, which causes the debugging process to be troublesome. The other is to use a multimeter or a tooling board with short circuit test function to test whether the mainboard has short circuit, and then power on the mainboard after no short circuit problem is found. The test principle of this method is to use the impedance between the power supply network and the GND (ground) network of the mainboard when the mainboard is not powered on to determine whether the mainboard is short-circuited. However, some abnormal devices or circuits may not show short circuit phenomenon when the mainboard is not powered on, and may show short circuit phenomenon only after the mainboard is powered on. Therefore, this method cannot exclude the failure caused by such abnormal devices or circuits. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a test circuit with power-on protection and device, which improves the testing efficiency and accuracy.

[0004] To solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0005] A test circuit with power-on protection, comprising a delay circuit, a power supply circuit, a current limiting protection circuit and a power-on protection circuit.

[0006] The input end of the delay circuit is used to connect a power supply, and the output end of the delay circuit is connected to the first control end of the power supply circuit. The input end of the power supply circuit is used to connect the power supply.

[0007] The first output end of the power supply circuit is connected to the input end of the current limiting protection circuit and the first input end of the power-on protection circuit, respectively. The second output end of the power supply circuit is used to connect the mainboard to be tested.

[0008] The first output end of the current limiting protection circuit is used to connect the mainboard to be tested. The second output end of the current limiting protection circuit is connected to the second input end of the power-on protection circuit, and the output end of the power-on protection circuit is connected to the second control end of the power supply circuit.

[0009] To solve the above technical problems, another technical solution adopted by the present application is:

[0010] A test device with power-on protection, comprising the test circuit with power-on protection.

[0011] The present application has the beneficial effects that: the first control end of the power supply circuit is connected through the delay circuit, so as to turn on the power supply circuit, so that the power supply first passes through the first input end and the first output end of the power supply circuit to perform power-on test on the mainboard. The first output end of the power supply circuit is connected to the input end of the current limiting protection circuit, and the first output end of the current limiting protection circuit is connected to the mainboard to be tested, so that the power supply to the mainboard is realized while the current limiting effect is realized, the linear power supply is replaced, the detection cost is reduced, the problem of excessive current caused by abnormal mainboard is avoided, and the detection success rate is improved. The first output end of the power supply circuit is connected to the first input end of the power-on protection circuit, so as to turn on the power-on protection circuit; at the same time, the second output end of the current limiting protection circuit is connected to the second input end of the power-on protection circuit, so as to judge whether the mainboard has a short circuit problem. When the power-on protection circuit detects that the mainboard has a short circuit, the output end of the power-on protection circuit is connected to the second control end of the power supply circuit, so as to control the power supply circuit to disconnect the power supply part of the first input end and the first output end, so as to stop the power supply to the mainboard. When the power-on protection circuit does not detect that the mainboard has a short circuit, the delay circuit controls the power supply circuit to turn on the second input end and the second output end after a period of time, so that the power supply is directly supplied to the mainboard by the power supply without passing through the current limiting protection circuit, so as to supply the mainboard for subsequent test of other modules. In this way, the automatic control of the current limiting time of the circuit is realized, and the operation efficiency of the debugging process is improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A structure diagram of the test circuit with power-on protection is provided for the embodiment of the present application;

[0013] Figure 2 A structure diagram of the power supply circuit is provided for the embodiment of the present application;

[0014] Figure 3 A circuit principle diagram of the test circuit with power-on protection is provided for the embodiment of the present application;

[0015] Figure 4 A test flow chart of the test circuit with power-on protection is provided for the embodiment of the present application;

[0016] LABEL EXPLANATION:

[0017] 1, delay circuit; 1r, input terminal of the delay circuit; 1c, output terminal of the delay circuit; 2, power supply circuit; 21k, first control terminal of the power supply circuit; 22k, second control terminal of the power supply circuit; 21r, first input terminal of the power supply circuit; 22r, second input terminal of the power supply circuit; 21c, first output terminal of the power supply circuit; 22c, second output terminal of the power supply circuit; 3, current limiting protection circuit; 3r, input terminal of the current limiting protection circuit; 31c, first output terminal of the current limiting protection circuit; 32c, second output terminal of the current limiting protection circuit; 4, power-on protection circuit; 41r, first input terminal of the power-on protection circuit; 42r, second input terminal of the power-on protection circuit; 4c, output terminal of the power-on protection circuit; 5, mainboard to be tested. DETAILED DESCRIPTION

[0018] To make the technical contents of the present application, the purposes and effects achieved more clear, the following will be described in detail in combination with the embodiments and the accompanying drawings.

[0019] Please refer to Figure 1 The embodiment of the present application provides a test circuit with power-on protection, which comprises a delay circuit, a power supply circuit, a current limiting protection circuit and a power-on protection circuit.

[0020] The input terminal of the delay circuit is used for connecting a power supply, and the output terminal of the delay circuit is connected with the first control terminal of the power supply circuit.

[0021] The first output terminal of the power supply circuit is connected with the input terminal of the current limiting protection circuit and the first input terminal of the power-on protection circuit respectively, and the second output terminal of the power supply circuit is used for connecting the mainboard to be tested.

[0022] The first output terminal of the current limiting protection circuit is used for connecting the mainboard to be tested, the second output terminal of the current limiting protection circuit is connected with the second input terminal of the power-on protection circuit, and the output terminal of the power-on protection circuit is connected with the second control terminal of the power supply circuit.

[0023] From the above description, the beneficial effects of the present application are that: the power supply circuit is connected with the delay circuit, the power supply circuit is connected with the current limiting protection circuit, so as to turn on the power supply circuit, so that the power supply is first tested by the power supply circuit and the current limiting protection circuit, and the current limiting effect is realized while the power supply supplies power to the mainboard, the linear power supply is replaced, the detection cost is reduced, the problem of excessive current caused by abnormal mainboard is avoided, and the detection success rate is improved. At the same time, the power supply circuit and the current limiting protection circuit are connected with the power-on protection circuit, and whether the mainboard has a short circuit problem is judged. When the power-on protection circuit detects that the mainboard has a short circuit, the power supply is controlled to be disconnected, so that the power supply to the mainboard is stopped. When the power-on protection circuit does not detect that the mainboard has a short circuit, the delay circuit controls the power supply circuit to supply power to the mainboard directly from the power supply after a period of time, so that the mainboard can be tested by other modules subsequently. In this way, the automatic control of the current limiting time of the circuit is realized, and the operation efficiency of the debugging process is improved.

[0024] Further, the power supply circuit comprises a NAND unit, a NAND unit and a switch unit;

[0025] The input end of the NAND unit is connected with the output end of the delay circuit as the first control end of the power supply circuit, the output end of the NAND unit is connected with the first input end of the NAND unit, and the second input end of the NAND unit is connected with the output end of the power-on protection circuit as the second control end of the power supply circuit;

[0026] The output end of the NAND unit is connected with the control end of the switch unit, the input end of the switch unit is used for connecting the power supply as the input end of the power supply circuit, the first output end of the switch unit is connected with the input end of the current limiting protection circuit and the first input end of the power-on protection circuit as the first output end of the power supply circuit, and the second output end of the switch unit is used for connecting the mainboard to be tested as the second output end of the power supply circuit.

[0027] From the above description, the level signal of the delay circuit is first processed by the NAND unit, and the two input ends of the NAND unit are connected with the NAND unit and the power-on protection circuit respectively, that is, the feedback signals of the NAND unit and the power-on protection circuit are judged by the NAND unit, the NAND unit can output high level and low level at the same time, and the switch unit is turned on when the NAND unit receives high level signals from the NAND unit and the power-on protection circuit. When the NAND unit receives low level signals from the NAND unit or the power-on protection circuit, the switch unit is turned off, so as to control the switch unit to turn on different power supply circuits and realize different power supply modes to meet different needs of power-on debugging and testing.

[0028] Further, the NAND unit comprises a first NAND chip and a second NAND chip;

[0029] The input end of the first NOT gate chip is connected with the output end of the delay circuit as the first control end of the power supply circuit, the output end of the first NOT gate chip is connected with the first input end of the NAND gate unit and the input end of the second NOT gate chip respectively; and the output end of the second NOT gate chip is connected with the first input end of the NAND gate unit.

[0030] As can be seen from the above description, when the delay circuit supplies power to the first NOT gate chip, before reaching the flip threshold of the first NOT gate chip, the first NOT gate chip outputs high level and the second NOT gate chip outputs low level, so as to control the NAND gate unit to simultaneously output high level and low level; when the feedback signal of the power-on protection circuit is high level, the high level output by the NAND gate unit turns on the first output end of the switch unit to supply current limiting power, so as to exclude the problem of abnormal mainboard device; after reaching the flip threshold of the first NOT gate chip, the first NOT gate chip outputs low level and the second NOT gate chip outputs high level, so that the low level output by the NAND gate unit disconnects the first output end of the switch unit, and the high level output turns on the second output end of the switch unit to supply test power, so as to supply test power for subsequent test of other modules of the mainboard. When the feedback signal of the power-on protection circuit is low level, the first output end of the switch unit is disconnected to stop power supply, so as to realize power-on protection. While realizing the current limiting effect of the current limiting protection circuit, the delay circuit and the NAND gate unit automatically control the on time of the current limiting protection circuit, that is, automatically control the current limiting time, so as to simplify the operation process of power-on test.

[0031] Further, the NAND gate unit comprises a first NAND gate chip, a second NAND gate chip, a first transistor and a second transistor.

[0032] The output end of the first NOT gate chip is connected with the first input end of the first NAND gate chip.

[0033] The output end of the second NOT gate chip is connected with the first input end of the second NAND gate chip.

[0034] The output ends of the first NAND gate chip and the second NAND gate chip are connected with the control end of the switch unit.

[0035] The second input ends of the first NAND gate chip and the second NAND gate chip are connected with the collector of the first transistor, and the collector of the first transistor is also used for connecting a pull-up resistor.

[0036] The base of the first transistor is connected with the output end of the power-on protection circuit as the second control end of the power supply circuit; and the emitter of the first transistor is grounded.

[0037] The base of the first transistor is also connected to the collector of the second transistor, the emitter of the second transistor and the base of the second transistor are all used to connect the pull-up resistor.

[0038] As described above, the first NAND chip and the second NAND chip control the first NAND chip and the second NAND chip respectively, and the second input terminals of the first NAND chip and the second NAND chip are also connected to the output terminal of the power-on protection circuit. The signal logic of the first NAND chip, the second NAND chip and the power-on protection circuit is judged through the first NAND chip and the second NAND chip, so as to generate high level and low level to control whether the first output terminal and the second output terminal of the switch unit are powered, so as to control whether the power supply circuit is directly powered by the power supply to the mainboard for the next test stage. At the same time of detecting whether the short circuit occurs in the circuit, the abnormal problem of the device is excluded based on the current limiting protection circuit, and the accuracy of determining the abnormal mainboard is improved.

[0039] Further, the switch unit comprises a first MOS tube and a second MOS tube.

[0040] The source of the first MOS tube and the second MOS tube is used as the input terminal of the power supply circuit to connect the power supply.

[0041] The gate of the first MOS tube is connected to the output terminal of the first NAND chip, and the gate of the second MOS tube is connected to the output terminal of the second NAND chip.

[0042] The drain of the first MOS tube is used as the first output terminal of the power supply circuit to connect the input terminal of the current limiting protection circuit and the first input terminal of the power-on protection circuit.

[0043] The drain of the second MOS tube is used as the second output terminal of the power supply circuit to connect the mainboard to be tested.

[0044] As described above, the first MOS tube is connected to the current limiting protection circuit, and the second MOS tube is directly connected to the mainboard to be tested. When the first MOS tube is turned on and the second MOS tube is turned off, the power supply is used to perform power-on test through the current limiting protection circuit and the power-on protection circuit. When the second MOS tube is turned on and the first MOS tube is turned off, the power supply directly supplies power to the mainboard to be tested to enter the subsequent test stage. When the first MOS tube and the second MOS tube are both turned off, the power supply cannot supply power to the mainboard to be tested, indicating that the mainboard has abnormal factors, and the power-on test is ended to avoid damage to the mainboard after power-on. In this way, the circuit with current limiting function and the direct power-on test circuit are turned on respectively, the current limiting protection is realized, and the current limiting time is automatically controlled for the mainboard power-on, the operation process of the mainboard test is simplified, and the test efficiency is improved.

[0045] Further, the current-limiting protection circuit comprises a first resistor, a second resistor, a third transistor and a fourth transistor;

[0046] The input end of the first resistor is connected to the first output end of the power supply circuit as the input end of the current-limiting protection circuit, and is also connected to the emitter of the third transistor.

[0047] The output end of the first resistor is connected to the base of the third transistor and the emitter of the fourth transistor respectively, and is connected to the second input end of the power-on protection circuit as the second output end of the current-limiting protection circuit.

[0048] The collector of the third transistor is connected to one end of the second resistor and the base of the fourth transistor respectively, and the other end of the second resistor is grounded.

[0049] The collector of the fourth transistor is connected to the first output end of the current-limiting protection circuit.

[0050] As can be seen from the above description, the first resistor, the third transistor and the fourth transistor play a current-limiting role to prevent the problem of excessive current caused by abnormal motherboard, realize current-limiting protection, replace linear power supply with current-limiting protection function, and reduce test cost.

[0051] Further, the power-on protection circuit comprises a differential amplification unit and a detection unit.

[0052] The first input end of the differential amplification unit is connected to the first input end of the power supply circuit as the first input end of the power-on protection circuit.

[0053] The second input end of the differential amplification unit is connected to the second output end of the current-limiting protection circuit as the second input end of the power-on protection circuit.

[0054] The output end of the differential amplification unit is connected to the input end of the detection unit, and the output end of the detection unit is connected to the second control end of the power supply circuit.

[0055] As can be seen from the above description, the differential amplification unit is used to amplify the sampling voltage of the power supply current of the motherboard to be tested, so as to input the detection unit for short circuit detection. When the detection unit judges that the motherboard has a short circuit problem, the output signal controls the power supply circuit to disconnect the power supply to protect the motherboard. In this way, the power-on protection function is realized.

[0056] Further, the differential amplification unit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a first operational amplifier.

[0057] One end of the third resistor is connected to the second output end of the current limiting protection circuit as the second input end of the power-on protection circuit, the other end of the third resistor is connected to the inverting input end of the first operational amplifier and one end of the fourth resistor respectively, and the output end of the first operational amplifier and the other end of the fourth resistor are both connected to the input end of the detection unit;

[0058] The non-inverting input end of the first operational amplifier is connected to one end of the fifth resistor and one end of the sixth resistor respectively, and the other end of the fifth resistor is grounded.

[0059] The other end of the sixth resistor is connected to the first output end of the power supply circuit as the first input end of the power-on protection circuit.

[0060] As can be seen from the above description, the differential amplification unit is used for amplifying the sampling voltage of the power supply current of the mainboard to be tested, and the amplification multiple of the sampling voltage is determined by the third resistor and the fourth resistor.

[0061] Further, the detection unit comprises a comparator.

[0062] The non-inverting input end of the comparator is connected to the output end of the differential amplification unit, and the inverting input end of the comparator is used for inputting a preset voltage value.

[0063] The output end of the comparator is connected to the second control end of the power supply circuit.

[0064] As can be seen from the above description, the detection unit compares the amplified sampling voltage of the power supply current of the mainboard with the preset voltage value, so as to judge whether the mainboard has a short circuit problem, when the mainboard has a short circuit problem, the comparator outputs a high level to disconnect the power supply through the second control end of the power supply circuit, so as to protect the mainboard, that is, to realize the power-on protection.

[0065] Another embodiment of the present application provides a test device with power-on protection, comprising the test circuit with power-on protection.

[0066] As described above, the beneficial effects of this invention are as follows: By connecting the power supply circuit to the delay circuit, and the power supply circuit to the current limiting protection circuit, the power supply circuit is turned on, allowing the power supply to first power on the motherboard through the power supply circuit and the current limiting protection circuit. While the power supply is supplying power to the motherboard, it simultaneously limits the current, replacing the linear power supply, reducing testing costs, and avoiding excessive current caused by motherboard malfunctions, thus improving the testing success rate. Simultaneously, both the power supply circuit and the current limiting protection circuit are connected to the power-on protection circuit to determine if there is a short circuit on the motherboard. When the power-on protection circuit detects a short circuit, it controls the power supply to disconnect, thus stopping power supply to the motherboard. When the power-on protection circuit does not detect a short circuit, after a certain period, the delay circuit controls the power supply circuit to directly supply power to the motherboard from the power supply, allowing the motherboard to subsequently perform tests on other modules. This achieves automated control of the circuit current limiting time, improving the efficiency of the debugging process.

[0067] This invention provides a test circuit and device with power-on protection, which can be applied to motherboard test fixtures. It replaces linear power supplies with current-limiting functions, saving testing costs while automating current-limiting time control, improving motherboard testing efficiency, and effectively eliminating problems caused by motherboard component malfunctions, thus improving the accuracy of motherboard testing. Specific embodiments are described below:

[0068] Please refer to Figures 1 to 4 Embodiment 1 of the present invention is as follows:

[0069] A test circuit with power-on protection includes a delay circuit 1, a power supply circuit 2, a current limiting protection circuit 3, and a power-on protection circuit 4; as shown... Figure 1 As shown, specifically, the input terminal 1r of the delay circuit 1 is connected to the power supply VCC, the output terminal 1c of the delay circuit 1 is connected to the first control terminal 21k of the power supply circuit 2, and the input terminal 2r of the power supply circuit 2 is connected to the power supply VCC; the first output terminal 21c of the power supply circuit 2 is connected to the input terminal 3r of the current limiting protection circuit 3 and the first input terminal 41r of the power-on protection circuit 4; the second output terminal 22c of the power supply circuit 2 is connected to the motherboard 5 under test; the first output terminal 31c of the current limiting protection circuit 3 is connected to the motherboard 5 under test; the second output terminal 32c of the current limiting protection circuit 3 is connected to the second input terminal 42r of the power-on protection circuit 4, and the output terminal 4c of the power-on protection circuit 4 is connected to the second control terminal 22k of the power supply circuit 2.

[0070] like Figure 2 as well as Figure 3 As shown, the following provides a detailed description of one circuit structure of the aforementioned delay circuit 1, power supply circuit 2, current limiting protection circuit 3, and power-on protection circuit 4.

[0071] In the embodiment, the delay circuit 1 comprises a resistor R7, a resistor R8 and a capacitor C1; specifically, one end of the resistor R7 is connected to the power supply VCC, the other end of the resistor R7 is connected to one end of the resistor R8 and one end of the capacitor C1 respectively, the other end of the resistor R8 and the other end of the capacitor C1 are both grounded; wherein the other end of the resistor R7 is also connected to the input end of the NAND gate unit U1 as the output end of the delay circuit 1.

[0072] It should be noted that in the delay circuit 1, the power supply VCC charges the capacitor C1 through the resistor R7 and discharges the capacitor C1 through the resistor R8.

[0073] The power supply circuit 2 comprises a NAND gate unit U1, a NAND gate unit U2 and a switch unit K; specifically, the input end of the NAND gate unit U2 is connected to the output end 1r of the delay circuit 1 as the first control end 21k of the power supply circuit 2, the output end of the NAND gate unit U2 is connected to the first input end of the NAND gate unit U1, the second input end of the NAND gate unit U1 is connected to the output end 4c of the power-on protection circuit 4 as the second control end 21k of the power supply circuit 2.

[0074] The output end of the NAND gate unit U1 is connected to the control end of the switch unit K; the input end of the switch unit K is connected to the power supply VCC as the input end 2r of the power supply circuit 2; the first output end of the switch unit K is connected to the input end 3r of the current limiting protection circuit 3 and the first input end 41r of the power-on protection circuit 4 as the first output end 21c of the power supply circuit 2; the second output end of the switch unit U1 is connected to the to-be-tested mainboard 5 as the second output end 22c of the power supply circuit 2.

[0075] In some embodiments, the NAND gate unit U2 comprises a first NAND gate chip U2A and a second NAND gate chip U2B; specifically, the input end of the first NAND gate chip U2A is connected to the output end 1c of the delay circuit 1 as the first control end 21k of the power supply circuit 2, the output end of the first NAND gate chip U2A is connected to the first input end of the NAND gate unit U1 and the input end of the second NAND gate chip U2B respectively; the output end of the second NAND gate chip U2B is connected to the first input end of the NAND gate unit U1.

[0076] In some embodiments, the NAND gate unit U1 comprises a first NAND gate chip U1A, a second NAND gate chip U1B, a first transistor Q1 and a second transistor Q2; specifically, an output end of the first NAND gate chip U1A is connected with a first input end of the first NAND gate chip U1A; an output end of the second NAND gate chip U1B is connected with a first input end of the second NAND gate chip U1B; output ends of the first NAND gate chip U1A and the second NAND gate chip U1B are both connected with a control end of the switch unit (Q1 & Q2); second input ends of the first NAND gate chip U1A and the second NAND gate chip U1B are both connected with a collector of the first transistor Q1, and the collector of the first transistor Q1 is further used for connecting the pull-up resistor R12; a base of the first transistor Q1 is connected with an output end 4c of the power-on protection circuit 4 as a second control end 21k of the power supply circuit 2; an emitter of the first transistor Q1 is grounded; a base of the first transistor Q1 is further connected with a collector of the second transistor Q2, and an emitter of the second transistor Q2 and the base of the second transistor Q2 are both used for connecting the pull-up resistors R11 and R12.

[0077] In the embodiment, the emitter of the second transistor Q2 is connected with the pull-up resistor R11, the base of the second transistor Q2 is connected with the pull-up resistor R12, and the collector of the second transistor Q2 is further connected with the pull-down resistor R13.

[0078] In an alternative implementation, the NAND gate unit U1 and the NAND gate unit U2 can be realized by a NAND gate circuit composed of discrete components.

[0079] In some embodiments, the switch unit K comprises a first MOS transistor Q1 and a second MOS transistor Q3; specifically, sources of the first MOS transistor Q3 and the second MOS transistor Q4 are used for connecting a power supply VCC as an input end 2r of the power supply circuit 2; a gate of the first MOS transistor Q3 is connected with an output end of the first NAND gate chip U1A, and a gate of the second MOS transistor Q3 is connected with an output end of the second NAND gate chip U1B; a drain of the first MOS transistor Q3 is connected with an input end 3r of the current-limiting protection circuit 3 and a first input end 41r of the power-on protection circuit 4 as a first output end 21c of the power supply circuit 2; a drain of the second MOS transistor Q4 is used for connecting the mainboard 5 to be tested as a second output end 22c of the power supply circuit 2.

[0080] It should be noted that the first MOS transistor Q3 and the second MOS transistor Q4 are P-type MOS transistors.

[0081] In some embodiments, the current-limiting protection circuit 4 comprises a first resistor R1, a second resistor R2, a third transistor Q5 and a fourth transistor Q6; specifically, an input end of the first resistor R1 is connected to the first output end 21c of the power supply circuit 2 as the input end 3r of the current-limiting protection circuit 3, and the input end of the first resistor R1 is also connected to an emitter of the third transistor Q5; an output end of the first resistor R1 is connected to a base of the third transistor Q5 and an emitter of the fourth transistor Q6, respectively; the output end of the first resistor R1 is connected to the second input end 42r of the power-on protection circuit 4 as the second output end 32c of the current-limiting protection circuit 3; a collector of the third transistor Q5 is connected to one end of the second resistor R2 and a base of the fourth transistor Q6, respectively, and the other end of the second resistor R2 is grounded; a collector of the fourth transistor Q6 is used as the first output end 31c of the current-limiting protection circuit 3 for connecting the mainboard 5 to be tested.

[0082] In an alternative embodiment, the current-limiting protection circuit can be implemented by a current-limiting switch IC chip.

[0083] In some embodiments, the power-on protection circuit 4 comprises a differential amplification unit U3 and a detection unit U4; specifically, a first input end of the differential amplification unit U3 is connected to the first input end 21r of the power supply circuit 2 as the first input end 41r of the power-on protection circuit 4; a second input end of the differential amplification unit U3 is connected to the second output end 32c of the current-limiting protection circuit 3 as the second input end 42r of the power-on protection circuit 4; an output end of the differential amplification unit U3 is connected to an input end of the detection unit U4, and an output end of the detection unit U4 is connected to the second control end 22k of the power supply circuit 2.

[0084] In an alternative embodiment, the differential amplification unit U3 comprises a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a first operational amplifier U3A; specifically, one end of the third resistor R3 is connected to the second output end 32c of the current-limiting protection circuit 3 as the second input end 42r of the power-on protection circuit 4, and the other end of the third resistor R3 is connected to an inverting input end of the first operational amplifier U3A and one end of the fourth resistor R4, respectively; an output end of the first operational amplifier U3A and the other end of the fourth resistor R4 are both connected to the input end of the detection unit U4; a non-inverting input end of the first operational amplifier U3A is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, respectively, and the other end of the fifth resistor R5 is grounded; the other end of the sixth resistor R6 is connected to the first output end 21c of the power supply circuit 2 as the first input end 41r of the power-on protection circuit 4.

[0085] In an alternative embodiment, the detection unit U4 comprises a comparator U4A; specifically, the non-inverting input terminal of the comparator U4A is connected to the output terminal of the differential amplification unit U3; the inverting input terminal of the comparator U4A is used to input a preset voltage value Vref; and the output terminal of the comparator U4A is connected to the second control terminal 22k of the power supply circuit 2.

[0086] In the embodiment, the detection unit U4 further comprises a pull-up resistor R9 and a resistor R10; specifically, the output terminal of the comparator U4A is further connected to one end of the pull-up resistor R9 and the resistor R10, and the other end of the resistor R10 is connected to the second control terminal 22k of the power supply circuit 2.

[0087] In an alternative embodiment, the preset voltage value Vref can be obtained by dividing the power supply VCC through a resistor, or obtained by a reference voltage source.

[0088] As shown in Figure 4 the working principle of the test circuit with power supply protection is specifically as follows:

[0089] After the power supply VCC is powered on, the power supply VCC charges the capacitor C1 through the resistor R7, before reaching the flip threshold of the first NAND chip U2A, the first NAND chip U2A outputs a high level, the second NAND chip U2B outputs a low level, and the collector of the first transistor Q1 outputs a high level, at this time, the first NAND chip U1A outputs a low level, and the second NAND chip U1B outputs a high level, so as to control the first MOS Q3 to be in a conductive state, and the second MOS Q4 to be in a cut-off state.

[0090] When the first MOS Q3 is conductive, the power supply VCC supplies power to the mainboard to be tested through the first MOS Q3, the first resistor R1 and the fourth transistor Q6; wherein the first resistor R1, the third transistor Q5 and the fourth transistor Q6 have a current limiting effect, which prevents the current from being too large due to the abnormality of the mainboard, and the current limiting value is specifically U be (the voltage between the emitter and the base of the third transistor Q5) / R1.

[0091] At the same time, the sampling voltage of the power supply current of the mainboard to be tested (the sampling voltage of the power supply current = the power supply current of the current limiting protection circuit x R1) is processed by the differential amplification unit U3 for voltage amplification, and the voltage amplification factor is specifically R4 / R3, and the amplified voltage value V is obtained. The voltage value V is input into the comparator U4A of the detection unit U4 and compared with the preset voltage value Vref:

[0092] (1) When the power supply current of the mainboard to be tested exceeds the preset value, the voltage V of the same phase input end of the comparator U4A of the detection unit U4 is greater than the voltage Vref of the reverse input end, the output end of the comparator U4A outputs a high level, the first triode Q1 is turned on, at this time, the collector of the first triode Q1 outputs a low level, that is, the base of the second triode Q2 inputs a low level, the second triode Q2 is turned on. At this time, the collector of the first triode Q1 outputs a low level, and the first non-inverting gate chip U1A and the second non-inverting gate chip U1B both output a high level, so the first MOS tube Q3 and the second MOS tube Q4 are both cut off, the power supply VCC cannot supply power to the mainboard to be tested, and the overcurrent protection function is realized. Since there is no current supply to the mainboard to be tested at this time, the current on the resistor R1 is always 0, causing the output voltage value V of the differential amplification unit to continuously be lower than the preset voltage value Vref, the voltage V of the same phase input end of the comparator U4A of the detection unit U4 is less than the voltage Vref of the reverse input end, and the output end of the comparator U4A outputs a low level. Because the first triode Q1 and the second triode Q2 are continuously turned on, the collector of the first triode Q1 is always in a low level state, and the first MOS tube Q3 and the second MOS tube Q4 are continuously maintained in a closed state.

[0093] (2) When the power supply current of the mainboard to be tested does not exceed the preset value, the voltage V of the same phase input end of the comparator U4A of the detection unit U4 is less than the voltage Vref of the reverse input end, the output end of the comparator U4A outputs a low level, the first triode Q1 remains in a cut-off state, the collector of the first triode Q1 continuously outputs a high level, the first MOS tube Q3 continues to be turned on, and the second MOS tube Q4 continues to be cut off.

[0094] After the power-up time T, the power-up protection circuit does not detect that the mainboard to be tested has an overcurrent condition, indicating that the mainboard is normal and excluding device abnormalities and other problems. At the same time, the power supply VCC charges the capacitor C1 through the resistor R7 to reach the flip threshold of the first non-inverting gate chip U2A, the first non-inverting gate chip U2A outputs a low level, the second non-inverting gate chip U2B outputs a high level, the first NAND gate chip U1A outputs a high level at this time, the second NAND gate chip U1B outputs a low level, so as to control the first MOS tube Q3 to be in a cut-off state and the second MOS tube Q4 to be in a turned-on state, and the power supply VCC directly supplies power to the mainboard to be tested for testing of other circuit modules in the mainboard to be tested.

[0095] Embodiment two of the application is:

[0096] A test device with power-up protection, comprising the test circuit with power-up protection of embodiment one.

[0097] In summary, the application provides a test circuit and device with power-on protection, which connects the NAND gate unit and the NAND gate unit through the delay circuit, thereby turning on the first MOS tube, and the second MOS tube is in the off state, so that the power supply first tests the mainboard through the current limiting protection circuit, so that the power supply supplies power to the mainboard while realizing the current limiting effect, replacing the linear power supply and reducing the detection cost. At the same time, the current of the current limiting protection circuit is input into the detection unit and compared with the preset voltage value after voltage amplification by the differential amplification unit, thereby avoiding the problem of excessive current caused by abnormal mainboard, improving the success rate of abnormal mainboard determination, and detecting whether the mainboard has a short circuit problem. When the mainboard has a short circuit, the first MOS tube is turned off by the NAND gate unit and the NAND gate unit, thereby stopping the power supply to the mainboard, realizing the protection effect. When the mainboard does not have a short circuit, the output signal of the NAND gate unit changes after a period of time, thereby turning on the second MOS tube, and the first MOS tube is in the off state, so that the power supply directly supplies power to the mainboard. The mainboard is used for subsequent testing of other modules, so as to realize the automatic control of the current limiting time of the circuit, and improve the operation efficiency of the debugging process.

[0098] The above is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent transformation or direct or indirect application in the related technical field based on the content of the specification and drawings is also included in the patent protection scope of the application.

Claims

1. A test circuit having power-on protection, characterized by, The power supply circuit comprises a NAND gate unit, a NAND gate unit and a switch unit. The input end of the NAND gate unit is connected with the output end of the delay circuit as the first control end of the power supply circuit, and the output end of the NAND gate unit is connected with the first input end of the NAND gate unit. The output end of the NAND gate unit is connected with the control end of the switch unit. The input end of the switch unit is connected with the power supply as the input end of the power supply circuit. The first output end of the switch unit is connected with the input end of the current-limiting protection circuit and the first input end of the power-on protection circuit as the first output end of the power supply circuit. The second output end of the switch unit is connected with the to-be-tested motherboard as the second output end of the power supply circuit. The current-limiting protection circuit comprises a first resistor, a second resistor, a third transistor and a fourth transistor. The input end of the first resistor is connected with the first output end of the power supply circuit as the input end of the current-limiting protection circuit. The output end of the first resistor is connected with the base of the third transistor and the emitter of the fourth transistor. The collector of the third transistor is connected with one end of the second resistor and the base of the fourth transistor. The collector of the fourth transistor is connected with the to-be-tested motherboard as the first output end of the current-limiting protection circuit. The NAND gate unit comprises a first NAND gate chip and a second NAND gate chip. The input end of the first NAND gate chip is connected with the output end of the delay circuit as the first control end of the power supply circuit.

2. The test circuit with power-on protection of claim 1, wherein, The output end of the first NAND gate chip is connected with the first input end of the NAND gate unit and the input end of the second NAND gate chip. The output end of the second NAND gate chip is connected with the first input end of the NAND gate unit.

3. The test circuit having power-on protection of claim 2, wherein, The NAND gate unit comprises a first NAND gate chip, a second NAND gate chip, a first transistor and a second transistor. The output end of the first NAND gate chip is connected with the first input end of the first NAND gate chip. The first transistor is connected with the output end of the first NAND gate chip. The second transistor is connected with the output end of the second NAND gate chip. The output end of the second NAND gate chip is connected to the first input end of the second NAND gate chip; The output ends of the first NAND gate chip and the second NAND gate chip are connected to the control end of the switch unit; The second input ends of the first NAND gate chip and the second NAND gate chip are connected to the collector of the first transistor, and the collector of the first transistor is also used for connecting the pull-up resistor; The base of the first transistor is connected to the output end of the power-on protection circuit as the second control end of the power supply circuit; and the emitter of the first transistor is grounded. The base of the first transistor is also connected to the collector of the second transistor, and the emitter of the second transistor and the base of the second transistor are used for connecting the pull-up resistor.

4. The test circuit having power-on protection of claim 3, wherein, The switch unit comprises a first MOS transistor and a second MOS transistor; The sources of the first MOS transistor and the second MOS transistor are used for connecting the power supply as the input end of the power supply circuit; The gate of the first MOS transistor is connected to the output end of the first NAND gate chip, and the gate of the second MOS transistor is connected to the output end of the second NAND gate chip; The drain of the first MOS transistor is connected to the input end of the current-limiting protection circuit and the first input end of the power-on protection circuit as the first output end of the power supply circuit; The drain of the second MOS transistor is used for connecting the mainboard to be tested as the second output end of the power supply circuit.

5. The test circuit having power-on protection of claim 1, wherein, The power-on protection circuit comprises a differential amplification unit and a detection unit; The first input end of the differential amplification unit is connected to the first input end of the power supply circuit as the first input end of the power-on protection circuit; The second input end of the differential amplification unit is connected to the second output end of the current-limiting protection circuit as the second input end of the power-on protection circuit; The output end of the differential amplification unit is connected to the input end of the detection unit, and the output end of the detection unit is connected to the second control end of the power supply circuit.

6. The test circuit having power-on protection of claim 5, wherein, The differential amplification unit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a first operational amplifier; One end of the third resistor is connected to the second input end of the power-on protection circuit as the second output end of the current-limiting protection circuit, and the other end of the third resistor is connected to the inverting input end of the first operational amplifier and one end of the fourth resistor, respectively; the output end of the first operational amplifier and the other end of the fourth resistor are both connected to the input end of the detection unit; The non-inverting input end of the first operational amplifier is connected to one end of the fifth resistor and one end of the sixth resistor, respectively; and the other end of the fifth resistor is grounded; The other end of the sixth resistor is connected to the first output end of the power supply circuit as the first input end of the power-on protection circuit.

7. The test circuit having power-on protection of claim 5, wherein, The detection unit comprises a comparator; The non-inverting input end of the comparator is connected to the output end of the differential amplification unit; and the inverting input end of the comparator is used for inputting a preset voltage value; The output end of the comparator is connected to the second control end of the power supply circuit.

8. A test device with power-on protection, characterized by The test circuit with power-on protection comprises the test circuit with power-on protection according to any one of claims 1-7.

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