A calibration circuit and calibration method for a two-step multi-phase clock time-to-digital converter

Abstract

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

Description

Technical Field

[0001] This invention relates to the field of time-to-digital conversion technology, and in particular to a correction circuit and correction method for a two-step multiphase clock-to-digital converter. Background Technology

[0002] A time-to-digital converter (TDC) is a high-precision time measurement module. Time signals are typically measured using clock signals. A two-step multiphase clock time-to-digital converter divides the measured time signal T into two distinct steps, generating the final digital signal by seamlessly connecting the data converted between two coarse and fine quantization steps.

[0003] Please see Figure 1 As shown, the Z_CNT signal represents the time signal T arriving at the coarse quantization module, and the Z_MOD signal represents the time signal T arriving at the fine quantization module. Ideally, the falling edge of Z_CNT coincides with the rising edge of Z_MOD, and the rising edge of Z_CNT coincides with the falling edge of Z_MOD. The master clock CLK... <0> Divided into 2 Q Equal parts, CLK<0:2 Q-1 Used for fine-tuning modules, CLK < 2 Q-3 >、CLK<2 Q-2 >、CLK<3*2 Q-3 >and CLK<2 Q-1 > indicates a lag in the master clock CLK <0> Clock signals at 45°, 90°, 135°, and 180°. Assume the first step is coarse quantization of P bits, the second step is fine quantization of Q bits, coarse and fine quantization are performed in parallel, and the coarse quantization count is based on the clock of the fine quantization.

[0004] In a two-step multiphase clock-to-digital converter (CD-to-digital converter) architecture, the input signal is fed into a coarse quantization unit for measurement, while the quantization error is fed into a fine quantization unit for precise measurement. The two-step multiphase clock-to-digital converter uses the master clock CLK. <0> Coarse quantization is achieved by counting the time signal T, while CLK < 1:2 is detected at the flip edge of the time signal T. Q The -1> level state is used to achieve fine quantization. The main principle of fine quantization is to use the phase difference between different CLK values ​​to reduce the original coarse quantization resolution Tclk to Tclk / 2. Q Please see. Figure 2 As shown, at the falling edge of the time signal T, if CLK < 1:2 Q The level of -1> is <000…00>, indicating that the falling edge of the time signal T is located at CLK. <0> With CLK <1> If CLK < 1:2, then the refinement value is 0; if CLK < 1:2 QThe level of -1> is <100…00>, indicating that the falling edge of the current time signal T is located at CLK. <1> With CLK <2> If CLK < 0:2, then the value is 1; and so on, if CLK < 0:2 Q The level of -1> is <000…01>, indicating that the falling edge of the current time signal T is located at CLK<2. Q >With CLK <0> Between, the fine value is 2 Q -1. Please refer to Figure 3 As shown, t1 is the fine quantization value after level recognition and decoding at the Tstart terminal, t2 is the fine quantization value after level recognition and decoding at the Tstop terminal, and N*Tclk is the coarse quantization count value, that is: T=N*TCLK+(Tclk-t1)+(t2-Tclk)=N*TCLK-t1+t2.

[0005] In two-step multiphase clock-time digital converters (CD-DC), D flip-flops play a crucial role. As memory devices with two stable states, they are the most basic logic units for constructing various sequential circuits. D flip-flops are commonly used as counters in the coarse quantization module of CD-DCs, updating on the edge of the clock signal. However, when a D flip-flop is in a metastable state, its output state may become unstable or unpredictable. Metastability means that the D flip-flop cannot reach a definite state within a specified time period. Once a D flip-flop enters a metastable state, it is impossible to predict its output level or when it will stabilize at a definite level.

[0006] To avoid metastability in D flip-flops, the following methods are used in the prior art to reduce the bit error rate: (1) adding a filter circuit to the input of the D flip-flop, or using multi-stage flip-flops to increase stability; (2) calibrating the coarse and fine quantizer data synchronously to solve the bit error problem. For example, patent document CN114265301A discloses a data synchronization calibration method applied to a two-step time-to-digital converter. In order to solve the problem of how to synchronize the coarse and fine quantization values ​​to obtain the final time-to-digital converter data in a coarse quantizer that uses a dual-counting mechanism, this patent document provides a method to select the rising edge of any phase clock in the N-phase driving clock of the fine quantizer using a selector to latch the data results of the first coarse counter counting on the positive edge and the second coarse counter counting on the negative edge to obtain a pair of latched values; then compare the two latched values ​​through a comparator, and return the comparison result to the state machine. The state machine determines whether the current coarse and fine quantizer data are synchronized based on the comparison result; select the driving clock of the next phase as the latch clock of the holding module and the control signal of the synchronizer by controlling the selector until the comparator returns a result of 1, thus completing the calibration.

[0007] At the beginning and end of the time signal T, due to the propagation delay mismatch between coarse and fine quantization and the metastability of the D flip-flop, the actual counting result of the coarse quantization counter may count one more or one less. To address the metastability problem of the D flip-flop, the methods described above not only introduce additional filtering circuits or ring oscillators into the two-step multiphase clock-to-digital converter, but also fail to correct the propagation delay mismatch error caused by coarse and fine quantization. To address the propagation delay mismatch problem between coarse and fine quantization, overquantization by one bit is used in fine quantization to achieve error correction. However, this traditional method also means increased requirements for fine quantization design, i.e., at the cost of doubling the area or doubling the conversion time. Therefore, how to simultaneously solve the coarse quantization counting error caused by the metastability of the D flip-flop and the propagation delay mismatch has become an urgent problem to be solved. Summary of the Invention

[0008] This invention provides a correction circuit and method for a two-step multiphase clock-time digital converter, which solves the problem of coarse quantization counting error caused by metastability and propagation delay mismatch of D flip-flops in the prior art, and realizes the correction of metastability error and propagation delay mismatch error of D flip-flops.

[0009] In a first aspect, the present invention provides a correction circuit for a two-step multiphase clock-time-to-digital converter, including a selection module and a correction module;

[0010] The selection module selects the correct clock signal based on the main clock level state at the flip edge of the fine quantization signal, and the selection module inputs the correct clock signal into the correction module.

[0011] The correction module receives the correct clock signal, performs correction, and generates two sets of digital calibration control codes to perform correction operations on the coarse quantization count value of the coarse quantization signal using the digital calibration control codes. The correction operations include: hold, increment by one, increment by two, decrement by one, or decrement by two.

[0012] In conjunction with the first aspect, in one embodiment of the present invention, the selection module includes: a double-edge D flip-flop D0, a logic submodule SUB1, and a transmission gate switch submodule SUB2;

[0013] The double-edge D flip-flop D0 is based on the signal CLK<2. Q-1 The level is identified by the fine-tuning signal Z_MOD; the Z_MOD signal is input to the clock terminal of the dual-edge D flip-flop D0, and the CLK<2 signal... Q-1 The data input of the double-edge D flip-flop D0 is used to output the signal J from the Q input of the double-edge D flip-flop D0. The terminal outputs signal J_INV, where CLK<2.Q-1 Lags behind the master clock by 180°;

[0014] The logic submodule SUB1 generates signals SET1, SET2, B, and B_INV based on the fine-tuning signal;

[0015] The transmission gate switch submodule SUB2 is based on the signal CLK<2 Q-1 The signals J, J_INV, B, and B_INV select the correct clock signal input to the calibration module.

[0016] In conjunction with the first aspect, in one embodiment of the present invention, the logic submodule SUB1 includes: a delay inverter I00, a general inverter I0, an AND gate G1, an AND gate G2, an XNOR gate G3, and a general inverter I1;

[0017] The input terminal of the delay inverter I00 and the second input terminal of the XNOR gate G3 are connected to the signal Z_MOD. The signal Z_MOD is inverted by the delay inverter I00 to generate the signal Z_MOD_DELAY. The signal Z_MOD_DELAY is connected to the first input terminal of the XNOR gate G3. The XNOR gate G3 outputs signal A and is connected to the ordinary inverter I1 to generate signal A_INV. The signal A and the signal A_INV are connected to the transmission gate switch submodule SUB2.

[0018] The input terminal of the ordinary inverter I0 and the second input terminal of the AND gate G2 are connected to the signal Z_MOD. The signal Z_MOD is inverted by the ordinary inverter I0 to generate the signal Z_MOD_INV, which is then connected to the second input terminal of the AND gate G1. The first input terminal of the AND gate G1 and the first input terminal of the AND gate G2 are connected to the output signal A of the XOR gate G3. The AND gates G1 and G2 output set signals SE1 and SE2 respectively, which are connected to the correction module.

[0019] In conjunction with the first aspect, in one embodiment of the present invention, the transmission gate switch submodule SUB2 includes a first-stage transmission gate switch S11, a first-stage transmission gate switch S12, a general inverter I2, a second-stage transmission gate switch S21, and a second-stage transmission gate switch S22.

[0020] The input terminals of the first-stage transmission gate switch S11 and the first-stage transmission gate switch S12 are both connected to the signal CLK<2. Q-2>, the signal J and the signal J_INV serve as the switching control signals for the first-stage transmission gate switch S11 and the first-stage transmission gate switch S12; the signal CLK<2 Q-2 Lag behind the master clock by 90°;

[0021] The output terminal of the first-stage transmission gate switch S12 is connected to the input terminal of the ordinary inverter I2. The common terminal of the first-stage transmission gate switch S11 and the ordinary inverter I2 is connected to signal B. Signal B is connected to the input terminal of the second-stage transmission gate switch S21.

[0022] The signals A and A_INV output by the logic submodule SUB1 serve as the switching control signals for the second-stage transmission gate switch S21 and the second-stage transmission gate switch S22. The input terminal of the second-stage transmission gate switch S22 is connected to a constant high-level signal.

[0023] The common terminal of the second-stage transmission gate switch S21 and the second-stage transmission gate switch S22 is connected to signal C. Signal C is the correct clock signal corresponding to the level at the edge of the fine-quantization signal, and signal C is input to the correction module.

[0024] In conjunction with the first aspect, in one embodiment of the present invention, the correction module includes: a first trigger submodule TRI1, a pulse submodule SUB3, and a second trigger submodule TRI2;

[0025] The first trigger submodule TRI1 generates a digital calibration control code Mstart based on the fine quantization signal, the coarse quantization signal, the master clock signal, and the correct clock signal. <1> and digital calibration control code Mstop <1> The first trigger submodule TRI1 generates a fine quantization signal synchronization signal Z_MOD_DTRI based on the fine quantization clock, and the first trigger submodule TRI1 generates a coarse quantization clock synchronization signal Z_CNT_DTR based on the coarse quantization signal.

[0026] The pulse submodule SUB3 is based on the fine-quantization clock synchronization signal Z_MOD_DTRI, the coarse-quantization clock synchronization signal Z_CNT_DTR, and the clock signal CLK<2 which lags the master clock by 45°. Q-3 > and a clock signal CLK<3*2 that lags the master clock by 135° Q-3 Generates pulse signal L;

[0027] The second trigger submodule TRI2 generates two digital calibration control codes based on the pulse signal L, the signal J output by the double-edge D flip-flop D0 of the selection module, and the set signals SE1 and SE2 output by the logic submodule SUB1 of the selection module. The two digital calibration control codes are digital calibration control codes Mstart. <0> and digital calibration control code Mstop <0> .

[0028] In conjunction with the first aspect, in one embodiment of the present invention, the first trigger submodule TRI1 includes a rising edge D flip-flop D1, a rising edge D flip-flop D2, a double-edge D flip-flop D3, and a holding module L1;

[0029] The data terminal of the rising edge trigger D1 is connected to the fine quantization signal, and the clock terminal is connected to the signal C output by the selection module, so that the fine quantization signal and the signal C are clock-synchronized to generate a fine quantization clock synchronization signal Z_MOD_DTRI. The signal C is the correct clock signal corresponding to the level at the edge of the fine quantization signal.

[0030] The data terminal of the rising edge trigger D2 is connected to the coarse quantization signal, and the clock terminal is connected to the main clock signal CLK. <0> So that the coarse quantization signal is synchronized with the master clock signal CLK. <0> Perform clock synchronization to generate a coarse-quantized clock synchronization signal Z_CNT_DTRI;

[0031] The data terminal of the dual-edge flip-flop D3 is connected to the signal Z_MOD_DTRI output from the Q terminal of the rising-edge flip-flop D1, and the clock terminal is connected to the signal Z_CNT_DTRI output from the Q terminal of the rising-edge flip-flop D2, so that the fine-quantization clock synchronization signal Z_MOD_DTRI can perform level recognition on the coarse-quantization clock synchronization signal Z_CNT_DTRI. The terminal outputs the digital calibration control code Mstop. <1> The Q output of the dual-edge flip-flop D3 is signal MN1;

[0032] The hold module L1 is connected to the signal MN1 output from the Q terminal of the double-edge trigger D3. Based on the fine-tuning signal and the signal Z_MOD_INV generated by the selection module, the hold module L1 outputs the digital calibration control code Mstart. <1> ;

[0033] The holding module L1 includes a delay inverter I01, a transmission gate switch S31, and a capacitor C1;

[0034] The input terminal of the delay inverter I01 is connected to the Q terminal of the double-edge flip-flop D3, and the output terminal of the inverter I01 is connected to the positive terminal of the capacitor C1 through the transmission gate switch S31. The negative terminal of the capacitor C1 is grounded.

[0035] The transmission gate switch S31 is controlled by the fine-tuning signal and the signal Z_MOD_INV generated by the logic submodule SUB1 of the selection module;

[0036] The common terminal of the transmission gate switch S31 and the capacitor C1 serves as the output terminal of the holding module L1, outputting the digital calibration control code Mstart. <1> .

[0037] In conjunction with the first aspect, in one embodiment of the present invention, the pulse submodule includes an XOR gate G4, an OR gate G5, and an AND gate G6;

[0038] The fine-quantization clock synchronization signal Z_MOD_DTRI and the coarse-quantization clock synchronization signal Z_CNT_DTRI generated by the first trigger submodule TRI1 generate signal E through the XOR gate G4;

[0039] The clock signal CLK<2 Q-3 >and the clock signal CLK<3*2 Q-3 The clock signal CLK<2 is generated by the OR gate G5. Q-3 >and the clock signal CLK<3*2 Q-3 > indicates a lag in the master clock signal CLK <0> 45° and 135°;

[0040] The signal E and the signal F generate a pulse signal L through the AND gate G6, and the pulse signal L is connected to the second trigger submodule TRI2.

[0041] In conjunction with the first aspect, in one embodiment of the present invention, the second trigger submodule TRI2 includes rising edge D flip-flop D4, rising edge D flip-flop D5, XNOR gate G7, XNOR gate G8, and holding module L2;

[0042] The data terminal of the rising edge trigger D4 is connected to the rising edge trigger D4. The clock input of the rising edge flip-flop D4 is connected to the output pulse signal L of the pulse submodule SUB3, and the set input of the rising edge flip-flop D4 is connected to the set signal SE1 output by the selection module, so as to count the number of pulses of the pulse signal L near the time signal Tstop. When the number of pulses is 1, the Q input of the rising edge flip-flop D4 outputs a low level, and when the number of pulses is 2, the Q input of the rising edge flip-flop D4 outputs a high level.

[0043] The data terminal of the rising edge trigger D5 is connected to the rising edge trigger D5. The clock input of the rising edge trigger D5 is connected to the pulse signal L output by the pulse submodule SUB3, and the set input of the rising edge trigger D5 is connected to the set signal SE2 output by the selection module, so as to count the number of pulses of the pulse signal L near the time signal Tstart. When the number of pulses is 1, the Q input of the rising edge trigger D5 outputs a low level, and when the number of pulses is 2, the Q input of the rising edge trigger D5 outputs a high level.

[0044] The two inputs of the XOR gate G7 are respectively connected to the Q terminal of the rising edge flip-flop D4 and the output signal J of the selection module. The XOR gate G7 outputs the digital calibration control code Mstop. <0> ;

[0045] The two inputs of the XOR gate G8 are respectively connected to the Q terminal of the rising edge flip-flop D5 and the output signal J of the selection module, and the XOR gate G8 outputs the digital calibration control code MN0.

[0046] The holding module L2 is connected to the output of the XOR gate G8, and outputs the digital calibration control code Mstart based on the fine quantization signal and the signal Z_MOD_INV generated by the selection module. <0> ;

[0047] The holding module L2 includes a delay inverter I02, a transmission gate switch S32, and a capacitor C2;

[0048] The input terminal of the delay inverter I02 is connected to the output terminal of the XOR gate G8, and the output terminal of the inverter I02 is connected to the positive terminal of the capacitor C2 through the transmission gate switch S32. The negative terminal of the capacitor C2 is grounded.

[0049] The transmission gate switch S32 is controlled by the fine-tuning signal and the signal Z_MOD_INV generated by the selection module;

[0050] The common terminal of the transmission gate switch S32 and the capacitor C2 serves as the output terminal of the holding module L2, outputting the digital calibration control code Mstart. <0> .

[0051] Secondly, the present invention provides a calibration method for a two-step multiphase clock-time digital converter, comprising:

[0052] The correct clock signal C corresponding to the master clock level state at which the Z_MOD edge is selected is input into the calibration module.

[0053] The calibration module receives the correct clock signal and generates two sets of digital calibration control codes;

[0054] Based on two sets of digital calibration control codes, the coarse quantization count result corresponding to the coarse quantization signal is corrected by holding, incrementing by one, incrementing by two, decrementing by one, or decrementing by two.

[0055] In conjunction with the second aspect, in one embodiment of the present invention, the coarse quantization count result corresponding to the coarse quantization signal is maintained, incremented by one, incremented by two, decremented by one, or decremented by two according to two sets of digital calibration control codes, including:

[0056] The digital calibration control code Mstart<1:0> generated by the calibration module is 11, which increments the coarse quantization count result by one.

[0057] The digital calibration control code Mstart<1:0> generated by the calibration module is 00, which reduces the coarse quantization count result by one.

[0058] The digital calibration control code Mstart<1:0> generated by the calibration module is 10 or 01, and no compensation is made for the coarse quantization count results;

[0059] The digital calibration control code Mstop<1:0> generated by the calibration module is 11, which increments the coarse quantization count result by one.

[0060] The digital calibration control code Mstop<1:0> generated by the calibration module is 00, which reduces the coarse quantization count result by one.

[0061] The digital calibration control code Mstop<1:0> generated by the calibration module is 10 or 01, so there is no need to compensate for the coarse quantization count results;

[0062] Where 1 represents a high level and 0 represents a low level; the correction module generates digital calibration control codes Mstart<1:0> and Mstop<1:0> to resolve the metastability error and transmission delay mismatch error of the D flip-flops at the Tstart and Tstop terminals of the time signal T. The compensation results formed by the digital calibration control codes Mstart<1:0> and Mstop<1:0> are accumulated and transmitted to the coarse quantization module for hold, increment, decrement, and subtraction operations.

[0063] One or more technical solutions provided in this invention have at least the following technical effects or advantages:

[0064] This invention selects the correct clock signal corresponding to the fine quantization signal in the fine quantizer through a selection module and inputs it to the correction module. The correction module generates a calibration signal, which, through a digital calibration control code generated by a logic module, performs hold, increment, increment, decrement, and decrement operations on the coarse quantization count value generated by the coarse quantizer. This effectively solves the problem of coarse quantization count error caused by metastability and propagation delay mismatch in the prior art, and realizes the correction of metastability error and propagation delay mismatch error of the D flip-flop. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments of the present invention or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is a diagram illustrating the signal characteristics of a traditional two-step multiphase clock-to-digital converter.

[0067] Figure 2 Quantization schematic diagram of a traditional two-step multiphase clock-to-digital converter;

[0068] Figure 3 Timing diagram for quantization analysis of a traditional two-step time-to-digital converter;

[0069] Figure 4 A block diagram illustrating the correction circuit principle of a two-step multiphase clock-to-digital converter provided in this embodiment of the invention;

[0070] Figure 5 A correction circuit diagram of a two-step multiphase clock-to-digital converter provided for an embodiment of the present invention;

[0071] Figure 6 A diagram illustrating the selection module provided in an embodiment of the present invention;

[0072] Figure 7 Timing diagram for signal analysis of a two-step multiphase clock-time digital converter provided in an embodiment of the present invention;

[0073] Figure 8 A diagram illustrating a calibration module provided in an embodiment of the present invention;

[0074] Figure 9 A flowchart illustrating a calibration method for a two-step multiphase clock-time digital converter provided in an embodiment of the present invention;

[0075] Figure 10 Timing diagram for metastability error analysis of D flip-flops provided in embodiments of the present invention;

[0076] Figure 11 A timing diagram for total error analysis provided in an embodiment of the present invention;

[0077] Figure 12 The timing diagram for total error calibration at the Tstart terminal of the two-step multiphase clock-time digital converter provided in this embodiment of the invention;

[0078] Figure 13 The timing diagram for total error calibration at the Tstop terminal of the two-step multiphase clock-time digital converter provided in this embodiment of the invention is shown. Detailed Implementation

[0079] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0080] Please see Figure 4 and Figure 5 , Figure 4 This invention provides a block diagram of a correction circuit for a two-step multiphase clock-to-digital converter. Figure 5 This invention provides a calibration circuit diagram for a two-step multiphase clock-time digital converter. The two-step multiphase clock-time digital converter includes: a fine quantization module for generating fine quantization values, a coarse quantization module for generating coarse quantization values, a calibration circuit module for generating coarse quantization count calibration codes, and a logic module for processing the coarse quantization count values. The calibration circuit for the two-step multiphase clock-time digital converter includes a selection module and a calibration module. The selection module selects the signal CLK<2 at the edge of the fine quantization signal Z_MOD. Q-1 The correct clock signal corresponding to the level state is selected by the selection module and input into the calibration module. The calibration module receives the correct clock signal and generates a digital calibration control code, which is then input into the logic module. The logic module obtains a modulation signal with different numbers of small pulses based on the digital calibration control code. The number of pulses includes two, three, four, one, or zero. The modulation signal is ANDed with the counting clock of the coarse quantization module and then input to the clock terminal of the coarse quantization module counter to complete the operation of holding, incrementing, decrementing, or subtracting the coarse quantization count value.

[0081] This invention, without increasing the number of fine-tuning bits, not only effectively solves the -Tclk+Tsetup-Tclk-Thold transmission delay mismatch error, but also solves the error caused by the metastability of the D flip-flop. The invention mainly includes the following steps: First, the signal CLK<2 is selected at the edge of the fine-tuning signal Z_MOD using the selection module. Q-1 The correct clock signal corresponding to the level state is input to the calibration module, which then generates a digital calibration control code. This code can perform hold, increment, increment by two, decrement by one, and decrement by two operations on the coarse quantization count value. This invention is primarily applied to two-step multi-phase clock-to-digital conversion scenarios.

[0082] Please see Figure 6 , Figure 6 This is an illustration of a selection module provided in an embodiment of the present invention. The selection module includes: a double-edge D flip-flop D0, a logic submodule SUB1, and a transmission gate switch submodule SUB2; the double-edge D flip-flop D0 is based on the signal CLK<2. Q-1 The level is identified by the fine-tuning signal Z_MOD; the Z_MOD signal is input to the clock terminal of the double-edge D flip-flop D0, and the CLK signal is <2. Q-1 The input is the data terminal of the double-edge D flip-flop D0. The Q terminal of the double-edge D flip-flop D0 outputs signal J, and through the Q terminal, it outputs signal J_INV. Signal CLK<2 Q-1 Lags the master clock by 180°; Logic submodule SUB1 generates signals SE1, SE2, B, and B_INV based on fine-tuning signals; Transmission gate switch submodule SUB2 is based on signal CLK<2 Q-1 > Select the correct clock signal input to the calibration module using signals J, J_INV, B, and B_INV.

[0083] Among them, the aforementioned double-edge D flip-flop D0 is used to determine whether the flip edge of signal Z_MOD is located at signal CLK<2. Q-1 A high or low level signal Z_MOD is the fine quantization signal arriving at the fine quantization module. In practice, Figure 6 The flip-flop D0 in the diagram belongs to the level recognition unit of the fine quantization module. For ease of analysis and understanding, this embodiment of the invention categorizes flip-flop D0 as the selection module of the correction circuit. Since CLK < 2... Q-1 Lagging master clock CLK <0> 180°, therefore it can be determined simultaneously that the flip edge of signal Z_MOD is located at the master clock CLK. <0> The high or low level of the signal determines the opposite outcome. When the toggling edge of signal Z_MOD is located at signal CLK<2... Q-1A high level indicates that the Z_MOD signal's toggle edge is located at the master clock CLK. <0> When the level is low, it indicates that signal J jumps to a high level, switch S11 of the transmission gate submodule SUB2 is turned on, S12 is closed, and CLK < 2. Q-2 The signal is transmitted to the clock input of the correction module trigger D1 via switches S11 and S21. Ideally, the rising edge of signal C should be located at the master clock CLK at this time. <0> The rising edge of signal C and the topping edge of signal Z_MOD are at least Tclk / 4 apart, thus avoiding metastability of D flip-flop D1. When the topping edge of signal Z_MOD is located at CLK<2... Q-1 A low level indicates that the Z_MOD signal's toggle edge is located at the master clock CLK. <0> When the signal is high, it indicates that signal J transitions to low, switch S11 of the transmission gate submodule SUB2 is closed, S12 is turned on, and CLK < 2. Q-2 The signal is transmitted to the clock input of the correction module trigger D1 via switches S12 and S21. Ideally, the rising edge of signal C should be located at the master clock CLK at this time. <0> The low-level interval is in the middle, so the rising edge of signal C and the topping edge of signal Z_MOD are at least Tclk / 4 apart, thus avoiding the metastability of D flip-flop D1.

[0084] The aforementioned logic submodule SUB1 includes: a delay inverter I00, a general-purpose inverter I0, an AND gate G1, an AND gate G2, a XNOR gate G3, and a general-purpose inverter I1. The input of the delay inverter I00 and the second input of the XNOR gate G3 are connected to the signal Z_MOD. The signal Z_MOD is inverted by the delay inverter I00 to generate the signal Z_MOD_DELAY. The signal Z_MOD_DELAY is connected to the first input of the XNOR gate G3. The XNOR gate G3 outputs signal A, which is then connected to the general-purpose inverter I1 to generate signal A_INV. The signal A_INV is connected to the transmission gate switch submodule SUB2; the input of the ordinary inverter I0 and the second input of the AND gate G2 are connected to the signal Z_MOD. After the signal Z_MOD is inverted by the ordinary inverter I0, the signal Z_MOD_INV is generated and connected to the second input of the AND gate G1. The first input of the AND gate G1 and the first input of the AND gate G2 are connected to the output signal A of the XOR gate G3. The AND gates G1 and G2 output set signals SE1 and SE2 respectively, which are connected to the calibration module. Since the beginning and end of the time signal T need to be calibrated, the correct clock signal needs to be input to the calibration module after the beginning and end transitions of the time signal T, that is, the correct clock signal needs to be input to the calibration module after the falling edge and rising edge of the signal Z_MOD. In addition, the first-stage control signals J and J_INV of the transmission gate switch submodule SUB2 are obtained by identifying the level of signal Z_MOD. Due to the delay of the dual-edge D flip-flop, signals J and J_INV are delayed relative to signal Z_MOD, assuming this delay is td. In order to obtain the correct clock signal C, the second-stage switch S21 of the transmission gate switch submodule SUB2 needs to be turned on after signal J transitions, and the second-stage switch S22 needs to be turned off after signal J transitions. Therefore, the second-stage control signal A needs to become high after signals J and J_INV transition, and the second-stage control signal A_INV needs to become low after signals J and J_INV transition. To achieve this function, the logic submodule SUB1 uses a delay inverter I00, an XNOR gate G3, and an inverter I1 to generate switch control signals A and A_INV. The delay of the delay inverter I00 is tc, and the delay relationship needs to satisfy Tclk / 8>tc>td. The Tclk / 8 limitation is mainly that the rising edge of the control signal C and the flip edge of the signal Z_MOD are at least Tclk / 8 apart to avoid metastability of the flip-flop D1.

[0085] The aforementioned transmission gate switch submodule SUB2 includes a first-stage transmission gate switch S11, a first-stage transmission gate switch S12, a general inverter I2, a second-stage transmission gate switch S21, and a second-stage transmission gate switch S22; the input terminals of both the first-stage transmission gate switch S11 and the first-stage transmission gate switch S12 are connected to the signal CLK<2.Q-2 >, signals J and J_INV serve as the switching control signals for the first-stage transmission gate switch S11 and the first-stage transmission gate switch S12; signal CLK<2 Q-2 The clock lags the master clock by 90°. The output of the first-stage transmission gate switch S12 is connected to the input of the ordinary inverter I2. The common terminal of the first-stage transmission gate switch S11 and the ordinary inverter I2 is connected to signal B, which is connected to the input of the second-stage transmission gate switch S21. Signals A and A_INV output from logic submodule SUB1 serve as the switching control signals for the second-stage transmission gate switches S21 and S22. The input of the second-stage transmission gate switch S22 is connected to a constant high-level signal. The common terminal of the second-stage transmission gate switches S21 and S22 is connected to signal C, which is the correct clock signal corresponding to the level at the edge of the fine-quantization signal. Signal C is input to the correction module. To obtain the correct clock signal C, the second-stage switch S21 of the transmission gate switch submodule SUB2 needs to be turned on after the signal J transitions, and the second-stage switch S22 needs to be turned off after the signal J transitions. Therefore, the first-stage control signal A needs to become high after the transitions of signals J and J_INV. In addition, to ensure that the rising edge of the clock signal C occurs after the toggle edge of Z_MOD, signal C remains high until the Z_MOD transition. This is achieved by controlling switch S21 to be off before the Z_MOD transition via signals A and A_INV, and on before the Z_MOD transition. Therefore, signal C remains high until the Z_MOD transition. For ease of understanding, Figure 7 Demonstrates when the Z_MOD flip edge is at the master clock CLK <0> A high-level timing signal, C remains high before the Z_MOD edge transition, and after the Z_MOD transition, C outputs a clock CLK < 2. Q-2 The signal is the inverted phase of the signal. Similarly, it can be concluded that in other cases, the C signal is correct and will not cause calibration errors.

[0086] Please see Figure 8 , Figure 8The diagram illustrates a calibration module provided in an embodiment of the present invention. The calibration module includes: a first trigger submodule TRI1, a pulse submodule SUB3, and a second trigger submodule TRI2. The first trigger submodule TRI1 generates a digital calibration control code Mstart based on a fine quantization signal, a coarse quantization signal, a master clock signal, and a correct clock signal. <1> and digital calibration control code Mstop <1> The first trigger submodule TRI1 generates a fine-quantization clock synchronization signal Z_MOD_DTRI based on the fine-quantization signal, and the first trigger submodule TRI1 generates a coarse-quantization clock synchronization signal Z_CNT_DTR based on the coarse-quantization signal; the pulse submodule SUB3 generates a clock synchronization signal CLK<2 based on the fine-quantization clock synchronization signal Z_MOD_DTRI, the coarse-quantization clock synchronization signal Z_CNT_DTR, and a clock signal CLK<2 that lags the master clock by 45°. Q-3 > and a clock signal CLK<3*2 that lags the master clock by 135° Q-3 The second trigger submodule TRI2 generates a pulse signal L; based on the pulse signal L, the signal J output by the double-edge D flip-flop D0 of the selection module, and the set signals SE1 and SE2 output by the logic submodule SUB1 of the selection module, it generates two digital calibration control codes, namely the digital calibration control code Mstart. <0> and digital calibration control code Mstop <0> .

[0087] The first trigger submodule TRI1 includes rising-edge D flip-flops D1 and D2, double-edge D flip-flops D3, and a holding module L1. The data terminal of rising-edge flip-flop D1 receives a fine-tuning signal, and its clock terminal receives signal C output from the selection module. This allows the fine-tuning signal and signal C to be clock-synchronized to generate a fine-tuning clock synchronization signal Z_MOD_DTRI. Signal C is the correct clock signal corresponding to the level at the edge of the fine-tuning signal. The data terminal of rising-edge flip-flop D2 receives a coarse-tuning signal, and its clock terminal receives the main clock signal CLK. <0> So that the coarse quantization signal is synchronized with the master clock signal CLK <0> Clock synchronization is performed to generate a coarse-quantized clock synchronization signal Z_CNT_DTRI. The data input of the dual-edge flip-flop D3 is connected to the signal Z_MOD_DTRI output from the Q input of the rising-edge flip-flop D1, and the clock input is connected to the signal Z_CNT_DTRI output from the Q input of the rising-edge flip-flop D2. This allows the fine-quantized clock synchronization signal Z_MOD_DTRI to perform level identification with the coarse-quantized clock synchronization signal Z_CNT_DTRI. The dual-edge flip-flop D3... Terminal output digital calibration control code Mstop <1> The Q output of the dual-edge flip-flop D3 is signal MN1; the holding module L1 is connected to the signal MN1 output from the Q output of the dual-edge flip-flop D3, and the holding module L1 outputs the digital calibration control code Mstart based on the fine-tuning signal and the signal Z_MOD_INV generated by the selection module. <1> The aforementioned holding module L1 includes a delay inverter I01, a transmission gate switch S31, and a capacitor C1. The input of the delay inverter I01 is connected to the Q terminal of a double-edge flip-flop D3, and the output of the inverter I01 is connected to the positive terminal of capacitor C1 through the transmission gate switch S31. The negative terminal of capacitor C1 is grounded. The transmission gate switch S31 is controlled by the signal Z_MOD_INV generated by the logic submodule SUB1 of the fine quantization signal and selection module. The common terminal of the transmission gate switch S31 and capacitor C1 serves as the output of the holding module L1, outputting the digital calibration control code Mstart. <1> In this embodiment of the invention, the rising edge of the clock input signal C of flip-flop D1 and the toggling edge interval of the data input signal Z_MOD are forced to be greater than Tclk / 8 by a selection module, thus avoiding metastability of flip-flop D1. In the actual coarse quantization module, the coarse quantization signal, after clock synchronization, is synchronized with the main clock CLK. <0> The result is ANDed and then transmitted to the counter for coarse quantization counting. Figure 8Flip-flop D2 in the original text is the clock synchronization unit of the coarse quantization module. However, for ease of analysis and understanding, this embodiment of the invention classifies flip-flop D2 as the correction module of the correction circuit. Because the edges of signal Z_CNT are random, flip-flop D2 will exhibit metastability. Furthermore, the propagation delays of signals Z_CNT and Z_MOD in the circuit layout are mismatched. To address these two issues, this embodiment of the invention summarizes the correction circuit by analyzing the error results. Since signal Z_CNT and the master clock signal CLK... <0> Clock synchronization is achieved through flip-flop D2, and the toggling edge of signal Z_CNT_DTRI must coincide with the master clock CLK. <0> The rising edges overlap, therefore the topping edge of signal Z_CNT_DTRI is separated from the topping edge of signal Z_CNT_DTRI by Tclk / 4, which avoids the metastability of D flip-flop D3. The D3 flip-flop identifies that the Z_CNT_DTRI level at the topping edge of signal Z_CNT_DTRI can generate the signal Mstop. <1> And MN1. Since the subsequent calibration compensation operation is performed after the time signal T is quantized, the calibration code formed for the error at the Tstop end will overwrite the calibration code at the Tstart end. Therefore, it is necessary to save the calibration code at the Tsart end. Before the signal Z_MOD changes from low to high, the level state of the signal MN1 is formed by the error calibration of the time signal Tstart end by the first trigger submodule TRI1. In order to save the calibration code at the Tsart end, this invention mainly implements this function through the delay-based holding module L1. When Z_MOD is low, the holding module L1 transmits the signal MN1; when Z_MOD is high, the holding module L1 holds the signal Mstart. <1> The delay inverter I01 of L1 pushes the transition time of MN1 to after the rising edge of Z_MOD. When Z_MOD transitions from low to high, the holding module L1 holds the signal Mstart. <1> .

[0088] The pulse submodule mentioned above includes an XOR gate G4, an OR gate G5, and an AND gate G6; the fine-quantization clock synchronization signal Z_MOD_DTRI and the coarse-quantization clock synchronization signal Z_CNT_DTRI generated by the first trigger submodule TRI1 generate signal E through the XOR gate G4; the clock signal CLK<2 Q-3 >and clock signal CLK<3*2 Q-3 The signal F is generated through OR gate G5, and the clock signal CLK < 2. Q-3 >and clock signal CLK<3*2 Q-3> indicates a lag in the master clock signal CLK <0> 45° and 135°; signals E and F generate pulse signal L through AND gate G6, and pulse signal L is connected to the second trigger submodule TRI2. To generate the correct digital calibration control code subsequently, an intermediate pulse signal L needs to be introduced. Signal L counts the number of pulses within the high-level range of signal E near the Tstart and Tstop terminals. Analysis shows that the input signals Z_CNT_DTRI, Z_MOD_DTRI, and CLK<2 of the pulse submodule... Q-3 >and signal CLK<3*2 Q-3 The interval between the flip edges of each pair should be at least Tclk / 8 to avoid errors caused by race conditions in the logic circuit.

[0089] The second trigger submodule TRI2 mentioned above includes rising-edge D flip-flop D4, rising-edge D flip-flop D5, XOR gate G7, XOR gate G8, and holding module L2; the data terminal of rising-edge flip-flop D4 is connected to the rising-edge flip-flop D5. The clock input of rising edge flip-flop D4 is connected to the output pulse signal L of pulse submodule SUB3, and the set input of rising edge flip-flop D4 is connected to the set signal SE1 output of selection module to count the number of pulses of pulse signal L near the time signal Tstop. When the number of pulses is 1, the Q input of rising edge flip-flop D4 outputs a low level; when the number of pulses is 2, the Q input of rising edge flip-flop D4 outputs a high level. The data input of rising edge flip-flop D5 is connected to the clock input of rising edge flip-flop D5. The clock input of rising edge flip-flop D5 is connected to the pulse signal L output by pulse submodule SUB3, and the set input of rising edge flip-flop D5 is connected to the set signal SE2 output by selection module. This counts the number of pulses of pulse signal L near the time signal Tstart. When the number of pulses is 1, the Q input of rising edge flip-flop D5 outputs a low level; when the number of pulses is 2, the Q input of rising edge flip-flop D5 outputs a high level. The two inputs of XOR gate G7 are connected to the Q input of rising edge flip-flop D4 and the output signal J of selection module, respectively. XOR gate G7 outputs the digital calibration control code Mstop. <0> The two inputs of the XOR gate G8 are connected to the Q input of the rising edge flip-flop D5 and the output signal J of the selection module, respectively. The XOR gate G8 outputs the digital calibration control code MN0. The holding module L2 is connected to the output of the XOR gate G8. Based on the control of the fine quantization signal and the signal Z_MOD_INV generated by the selection module, it outputs the digital calibration control code Mstart. <0> The aforementioned holding module L2 includes a delay inverter I02, a transmission gate switch S32, and a capacitor C2. The input of the delay inverter I02 is connected to the output of the XOR gate G8, and the output of the inverter I02 is connected to the positive terminal of the capacitor C2 through the transmission gate switch S32. The negative terminal of the capacitor C2 is grounded. The transmission gate switch S32 is controlled by the fine-tuning signal and the signal Z_MOD_INV generated by the selection module. The common terminal of the transmission gate switch S32 and the capacitor C2 serves as the output of the holding module L2, outputting the digital calibration control code Mstart. <0> The subsequent calibration and compensation operation occurs after the time signal T has been quantized. Since the number of small pulses formed near the Tstart terminal of the pulse signal L is either zero or one, the number of pulses is uncertain. If the initial value of the output Q of flip-flop D4 is uncertain, then the final value of the output Q of flip-flop D4 will also be uncertain, thus the calibration code at the Tstop terminal may be incorrect. Similarly, since the number of small pulses formed near the Tstop terminal of the pulse signal L is either zero or one, the number of pulses is uncertain. If the initial value of the output Q of flip-flop D5 is uncertain, then the final value of the output Q of flip-flop D5 will also be uncertain, thus the calibration code at the Tstart terminal may be incorrect. To solve this problem, set signals SE1 and SE2 are used to set flip-flops D4 and D5 to 1. The set signal SE1, generated by the selection module, is high for a short period after the rising edge of the time signal T. By controlling the delay inverter I00, it is ensured that the small pulses of the pulse signal L occur before the falling edge of SE1. This method ensures that the output Q of D4 remains high when the Tstop terminal arrives. Similarly, the set signal SE2 generated by the selection module is high for a short period of time after the falling edge of the time signal T. By controlling the delay inverter I00 to ensure that the small pulse of the pulse signal L is before the falling edge of SE2, this method can ensure that the output terminal Q of D5 remains high when the Tstart terminal arrives.In addition, the set signal SE2 and the pulse signal will overwrite the calibration code at the Tstart terminal, so it is necessary to save the calibration code at the Tstart terminal. This embodiment of the invention mainly implements this function through a delay-based holding module L2. When Z_MOD is low, the holding module L2 transmits the signal MN2; when Z_MOD is high, the holding module L2 holds the signal Mstart. <0> The delay inverter I02 of L2 pushes the transition time of MN2 to after the rising edge of Z_MOD. When Z_MOD transitions from low to high, the latch signal Mstart of module L2 is held. <0> .

[0090] In summary, when Mstart<1:0> is 11, the coarse quantization count result is incremented by one; when Mstart<1:0> is 00, the coarse quantization count result is decremented by one; when Mstart<1:0> is 10 or 01, no compensation is performed on the coarse quantization count result. Similarly, when Mstop<1:0> is 11, the coarse quantization count result is incremented by one; when Mstop<1:0> is 00, the coarse quantization count result is decremented by one; and when Mstop<1:0> is 10 or 01, no compensation is performed on the coarse quantization count result. The quantization error compensation results from Tstart and Tstop are accumulated and transmitted to the coarse quantization module for hold, increment, increment by two, decrement by one, and decrement by two operations.

[0091] Compared to other calibration methods, this invention not only effectively solves the errors caused by transmission delay mismatch and D flip-flop metastability, but also avoids doubling the conversion time. Furthermore, it can calibrate the Tstart and Tstop terminals of the time signal T, achieving full-time domain calibration. Theoretically, this novel correction circuit can not only correct errors caused by D flip-flop metastability, but also transmission delay mismatch errors within the range of -Tclk+Tset to Tclk-Thold, where Tset is the setup time of the clock-synchronized D2 flip-flop and Thold is the hold time of the clock-synchronized D2 flip-flop.

[0092] Please see Figure 9 , Figure 9 This invention provides a flowchart of a calibration method for a two-step multiphase clock-time digital converter, which includes the following steps:

[0093] The selection module is based on the signal CLK<2 at the flip edge of the finer signal Z_MOD. Q-1 The correct clock signal is input to the correction module to select the level of the signal.

[0094] The calibration module receives the correct clock signal and generates a digital calibration control code, which is then input into the logic module.

[0095] The logic module obtains modulation signals with different numbers of small pulses based on the digital calibration control code. The number of pulses includes: two, three, four, one, or zero.

[0096] The modulated signal and the counting clock of the coarse quantization module are ANDed together and then input to the clock terminal of the coarse quantization module counter to perform operations such as holding, incrementing, decrementing, or subtracting the coarse quantization count value.

[0097] The digital calibration control code described above in this embodiment of the invention performs operations such as holding, incrementing, incrementing, decrementing, or subtracting from the coarse quantization count result, including: If Mstart<1:0> is 11 in the digital calibration control code generated by the calibration module, the coarse quantization count result is compensated by incrementing by one; if Mstart<1:0> is 00 in the digital calibration control code generated by the calibration module, the coarse quantization count result is compensated by decrementing by one; if Mstart<1:0> is 10 or 01 in the digital calibration control code generated by the calibration module, no compensation is performed on the coarse quantization count result; if Mstop<1:0> is 11 in the digital calibration control code generated by the calibration module, the coarse quantization count result is compensated by incrementing by one; if Mstop<1:0> is 00 in the digital calibration control code generated by the calibration module, the coarse quantization count result is compensated by decrementing by one; if Mstop<1:0> is 10 or 01 in the digital calibration control code generated by the calibration module, no compensation is required for the coarse quantization count result; the quantization error compensation results at the Tstart and Tstop ends of the digital calibration control code generated by the calibration module are accumulated and transmitted to the coarse quantization module for holding, incrementing, incrementing, decrementing, or subtracting operations.

[0098] In the traditional structure of a two-step multiphase clock-time digital converter, Z_CNT is clock-synchronized by a D flip-flop to generate Z_CNT_DTRI, which is then input to the counter of the coarse quantization module for coarse quantization counting. This can reduce the repeated counting caused by the start and end of Z_CNT. However, this structure will have two problems in actual transmission.

[0099] The first problem is the coarse quantization error caused by the metastability of the D flip-flop; please refer to [link / reference]. Figure 10 As shown, at the end of the time signal T, due to the randomness of the Z_CNT edge, the D flip-flop exhibits metastability. When the Z_CNT edge is within the setup and hold time of the D flip-flop, an uncertain value appears at the output of the D flip-flop, the clock synchronization may fail, and the coarse quantization count value may have three results: undercounting by one, overcounting by one, or counting correctly.

[0100] Please see Figure 10 As shown in (a), if Z_CNT_DTRI toggles to 0 on the rising edge of the clock when the falling edge of Z_CNT is within the hold time of the D flip-flop, the coarse quantization count will be counted one less time. Please refer to [link to relevant documentation]. Figure 10As shown in (b), if Z_CNT_DTRI toggles to 0 on the rising edge of the next clock cycle when the falling edge of Z_CNT is within the hold time of the D flip-flop, the coarse quantization count value is correct; please refer to [link to relevant documentation]. Figure 10 As shown in (c), if Z_CNT_DTRI toggles to 0 on the rising edge of the next clock cycle when the falling edge of Z_CNT is within the setup time of the D flip-flop, the coarse quantization count value is correct; please refer to [link to relevant documentation]. Figure 10 As shown in (d), when the falling edge of Z_CNT is within the setup time of the D flip-flop, if Z_CNT_DTRI flips to output 0 on the rising edge of the second subsequent clock, the coarse quantization count value will be counted by one more.

[0101] The second problem is the error in the coarse quantization result caused by the different delays in the transmission of the time signal T to the coarse quantization module and the fine quantization module. Ideally, the edges of Z_MOD and Z_CNT should coincide. However, in reality, due to the problem of transmission delay mismatch, the edges of Z_MOD and Z_CNT deviate. Therefore, the delay mismatch on the transmission path will affect the coarse and fine quantization results, thus limiting the overall conversion accuracy to the accuracy of coarse quantization. Let Terror1 = τ2 - τ1, Terror2 = τ4 - τ3, where τ1 and τ2 are the propagation delay times of the rising edge of Z_CNT and the falling edge of Z_MOD, respectively, and τ3 and τ4 are the propagation delay times of the falling edge of Z_CNT and the rising edge of Z_MOD. If we consider both the metastability of the D flip-flop and the transmission delay mismatch of the coarse and fine quantization signals, please refer to [link to relevant documentation]. Figure 11 The timing diagram shown is for transmission delay errors in the range of Tclk-Thold>Terror>-Tclk+Tset.

[0102] Near the Tstart end, please refer to Figure 11 As shown in (a), when Z_CNT_DTRI toggles on the rising edge of the clock at the Z_MOD edge, the coarse quantization count is incremented by one; near the Tstart pin, please refer to [reference needed]. Figure 11 As shown in (b), when Z_CNT_DTRI toggles on the rising edge of the second clock cycle following the clock cycle of Z_MOD, the coarse quantization count is reduced by 1; near the Tstop pin, please refer to [link to relevant documentation]. Figure 11 As shown in (c), when Z_CNT_DTRI toggles on the rising edge of Z_MOD, the coarse quantization count is counted one less; near the Tstop end, please refer to [reference needed]. Figure 11 As shown in (d), when Z_CNT_DTRI toggles on the rising edge of the second clock cycle following the clock cycle of Z_MOD, the coarse quantization count is increased by 1. ① indicates correct clock synchronization, and ② indicates incorrect clock synchronization.

[0103] By analyzing the error scenarios caused by the two problems, it can be seen that at the beginning and end of the time signal T, the actual counting result of the coarse quantization counter may count 1 more or less.

[0104] Using the edge of the fine quantization signal Z_MOD as a reference, when Terror1 and Terror2 are within the error range of -Tclk+Tset—Tclk-Thold, the edge of the coarse quantization signal Z_CNT lies within the range from Thold after the rising edge of the clock preceding the Z_MOD edge to Tset before the rising edge of the clock following the Z_MOD edge. Therefore, the edge of Z_CNT_DTRI may lie at the rising edge of the clock preceding the Z_MOD edge, the rising edge of the clock following the Z_MOD edge, or the second-to-last rising edge of the clock following the Z_MOD edge. The clock in question refers to the master clock CLK. <0> The corresponding clock position.

[0105] To explain the working principle of the calibration module, Figure 12 and Figure 13 The timing sequence of the calibration modules at the Tstart and Tstop ends is shown respectively.

[0106] Please see Figure 12 As shown in (ac), when the Z_MOD edge is at the master clock CLK <0> When the signal is high, J is low, switch S11 is off, switch S12 is on, and CLK < 2. Q-2 The inverted signal is transmitted to signal C.

[0107] Please continue reading. Figure 12 As shown in (a), if Z_CNT_DTRI toggles on the rising edge of the clock at the falling edge of Z_MOD, the coarse quantization count is over-counted by 1. Analysis shows that when the falling edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 1, and MN1 is also 1. At this time, a pulse exists at L, causing flip-flop D5 to jump from 1 to 0, and MN0 to 0. MN1 is then transmitted to Mstart via the delay inverter I01. <1> Mstart <1> It becomes 0; MN2 is transmitted to Mstart through the XOR gate G8 and the inverter I02. <0> Mstart <0> When Z_MOD jumps to a high level, hold module L1 and hold module L2 maintain their outputs, Mstart<1:0> is 00, and the coarse quantization count is decremented by one to compensate.

[0108] Please continue reading. Figure 12As shown in (b), if Z_CNT_DTRI toggles on the rising edge of the clock following the Z_MOD edge, the coarse quantization count is correct. In this case, analysis shows that when the falling edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 0, and MN1 is 0. At this time, a pulse exists in L, causing flip-flop D5 to jump from 1 to 0, and MN0 to 0. MN1 is then transmitted to Mstart via the delay inverter I01. <1> Mstart <1> It becomes 1; MN2 is transmitted to Mstart through the XOR gate G8 and the delay inverter I02. <0> Mstart <0> When Z_MOD jumps to high, hold module L1 and hold module L2 maintain their outputs, Mstart<1:0> is 10, and no coarse quantization count compensation is performed.

[0109] Please continue reading. Figure 12 As shown in (c), if Z_CNT_DTRI toggles on the second rising edge of the clock following the Z_MOD edge, the coarse quantization count is undercounted by 1. Analysis shows that when the falling edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 0, and MN1 is also 0. At this time, there are two pulses in L, causing flip-flop D5 to jump from 1 to 0 and then back to 1, while MN0 is 1. MN1 is then transmitted to Mstart via the delay inverter I01. <1> Mstart <1> It becomes 1; MN2 is transmitted to Mstart through the XOR gate G8 and the delay inverter I02. <0> Mstart <0> It becomes 1. When Z_MOD jumps to a high level, hold module L1 and hold module L2 maintain the output, Mstart<1:0> is 11, and the coarse quantization count is incremented by one to compensate.

[0110] Please see Figure 12 As shown in (df), when the Z_MOD edge is at the master clock CLK <0> When the level is low, J is high, switch S11 is on, switch S12 is off, and CLK < 2. Q-2 >Transmitted to signal C.

[0111] Please continue reading. Figure 12As shown in (d), if Z_CNT_DTRI toggles on the rising edge of the clock at the falling edge of Z_MOD, the coarse quantization count is over-counted by 1. Analysis shows that when the falling edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 1, and MN1 is also 1. At this time, there are two pulses in L, and the D5 flip-flop jumps from 1 to 0 and then back to 1, so MN0 is 1. MN1 is then transmitted to Mstart via the delay inverter I01. <1> Mstart <1> It becomes 0; MN2 is transmitted to Mstart through the XOR gate G8 and the inverter I02. <0> Mstart <0> When Z_MOD jumps to a high level, hold module L1 and hold module L2 maintain their outputs, Mstart<1:0> is 00, and the coarse quantization count is decremented by one to compensate.

[0112] Please continue reading. Figure 12 As shown in (e), if Z_CNT_DTRI toggles on the rising edge of the clock following the Z_MOD edge, the coarse quantization count is correct. In this case, analysis shows that when the falling edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 1, and MN1 is also 1. At this time, a pulse exists in L, causing flip-flop D5 to jump from 1 to 0, and MN0 to 0. MN1 is then transmitted to Mstart via the delay inverter I01. <1> Mstart <1> It becomes 0; MN2 is transmitted to Mstart through the XOR gate G8 and the delay inverter I02. <0> Mstart <0> When Z_MOD jumps to high level, hold module L1 and hold module L2 maintain output, Mstart<1:0> is 01, and no coarse quantization count compensation is performed.

[0113] Please continue reading. Figure 12 As shown in (f), if Z_CNT_DTRI toggles on the second rising edge of the clock following the Z_MOD edge, the coarse quantization count is undercounted by 1. Analysis shows that when the falling edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 0, and MN1 is 0. At this time, a pulse exists in L, causing flip-flop D5 to jump from 1 to 0, and MN0 becomes 0. MN1 is then transmitted to Mstart via the delay inverter I01. <1> Mstart <1> It becomes 1; MN2 is transmitted to Mstart through the XOR gate G8 and the delay inverter I02. <0> Mstart <0> It becomes 1. When Z_MOD jumps to a high level, hold module L1 and hold module L2 maintain the output, Mstart<1:0> is 11, and the coarse quantization count is incremented by one to compensate.

[0114] Please see Figure 13As shown in (ac), when the Z_MOD edge is at the master clock CLK <0> When the signal is high, J is low, switch S11 is off, switch S12 is on, and CLK < 2. Q-2 The inverted signal is transmitted to signal C.

[0115] Please continue reading. Figure 13 As shown in (a), if Z_CNT_DTRI toggles on the rising edge of the clock at the Z_MOD edge, the coarse quantization count is underestimated by 1. Analysis shows that when the rising edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 0, and Mstop... <1> When L is 1, a pulse exists, causing flip-flop D4 to transition from 1 to 0. The output Q of flip-flop D4 is then transmitted to Mstop after being XORed by G7. <0> Mstop <0> It becomes 1. Mstart<1:0> is 11, and the coarse quantization count is incremented by one to compensate.

[0116] Please continue reading. Figure 13 As shown in (b), if Z_CNT_DTRI toggles on the rising edge of the clock following the Z_MOD edge, the coarse quantization count is correct. In this case, analysis shows that when the Z_MOD_DTRI rising edge arrives, the Z_CNT_DTRI signal level is 1, and Mstop... <1> When L is 0, a pulse exists, causing flip-flop D4 to transition from 1 to 0. The output Q of flip-flop D4 is then transmitted to Mstop after being XORed by G7. <0> Mstop <0> It becomes 1. Mstart<1:0> is 01, and no compensation is made for the coarse quantization count.

[0117] Please continue reading. Figure 13 As shown in (c), if Z_CNT_DTRI toggles on the second rising edge of the clock following the Z_MOD edge, the coarse quantization count is over-counted by 1. Analysis shows that in this case, when the Z_MOD_DTRI rising edge arrives, the Z_CNT_DTRI signal level is 1, and Mstop... <1> When L is 0, there are two pulses. Flip-flop D4 changes from 1 to 0 and then back to 1. The output Q of flip-flop D4 is transmitted to Mstop after being XORed by G7. <0> Mstop <0> It becomes 0. Mstart<1:0> is 00, and the coarse quantization count is reduced by one to compensate.

[0118] Please see Figure 13 As shown in (df), when the Z_MOD edge is at the master clock CLK <0> When the level is low, J is high, switch S11 is on, switch S12 is off, and CLK < 2. Q-2 >Transmitted to signal C.

[0119] Please continue reading. Figure 13As shown in (d), if Z_CNT_DTRI toggles on the rising edge of the clock at the Z_MOD edge, the coarse quantization count is underestimated by 1. Analysis shows that when the rising edge of Z_MOD_DTRI arrives, the Z_CNT_DTRI signal level is 0, and Mstop... <1> When L is 1, there are two pulses. Flip-flop D4 changes from 1 to 0 and then back to 1. The output Q of flip-flop D4 is transmitted to Mstop after being XORed by G7. <0> Mstop <0> It becomes 1. Mstart<1:0> is 11, and the coarse quantization count is incremented by one to compensate.

[0120] Please continue reading. Figure 13 As shown in (e), if Z_CNT_DTRI toggles on the rising edge of the clock following the Z_MOD edge, the coarse quantization count is correct. In this case, analysis shows that when the Z_MOD_DTRI rising edge arrives, the Z_CNT_DTRI signal level is 0, and Mstop... <1> When L is 1, a pulse exists, causing flip-flop D4 to transition from 1 to 0. The output Q of flip-flop D4 is then transmitted to Mstop after being XORed by G7. <0> Mstop <0> It becomes 0. Mstart<1:0> is 10, so no compensation is made for the coarse quantization count.

[0121] Please continue reading. Figure 13 As shown in (f), if Z_CNT_DTRI toggles on the second rising edge of the clock following the Z_MOD edge, the coarse quantization count is over-counted by 1. For this situation, analysis shows that when the Z_MOD_DTRI rising edge arrives, the Z_CNT_DTRI signal level is 1, and Mstop... <1> When L is 0, a pulse exists, causing flip-flop D4 to transition from 1 to 0. The output Q of flip-flop D4 is then transmitted to Mstop after being XORed by G7. <0> Mstop <0> It becomes 0. Mstart<1:0> is 00, and the coarse quantization count is reduced by one to compensate.

[0122] Based on the analysis of the above twelve scenarios, the correction circuit proposed in this invention can accurately correct transmission delay errors and D flip-flop metastability errors, and can correct two-step time-to-digital converters with transmission delay mismatch errors within the range of -Tclk+Tset to Tclk-Thold. When Mstart<1:0> is 00, the coarse quantization count result is decremented by one; when Mstart<1:0> is 10 or 01, no compensation is performed on the coarse quantization count result; when Mstart<1:0> is 11, the coarse quantization count result is incremented by one. When Mstop<1:0> is 00, the coarse quantization count result is decremented by one; when Mstop<1:0> is 10 or 01, no compensation is performed on the coarse quantization count result; when Mstop<1:0> is 11, the coarse quantization count result is incremented by one. The quantization error compensation results at Tstart and Tstop are accumulated and transmitted to the coarse quantization module for hold, increment, increment, decrement, and decrement operations.

[0123] In parallel two-step time-to-digital conversion, coarse quantization should be implemented using a counter, while fine quantization should be implemented using a delay chain or similar structure. Since three clock signals with different phases are required during calibration, a multi-phase clock level identification structure is recommended for fine quantization. After each quantization cycle, a processing circuit can be integrated within the chip to process the calibration results. Specifically, the four calibration values ​​(Mstart<1:0>, Mstop<1:0>) are ANDed with positive level pulses and then ORed to generate modulation signals. The coarse quantization clock synchronization signal and the main clock CLK are then... <0> The modulation signal and the coarse counting signal are then ANDed to generate a coarse quantization clock signal. Finally, the output signal is input to the clock terminal of the coarse quantization module counter to complete the processing of the correction circuit results.

[0124] The methods, apparatus, or modules of this invention can be implemented in a computer-readable program code manner. The controller can be implemented in any suitable manner, for example, as a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, transmission gate switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. The memory controller can also be implemented as part of the memory's control logic. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code manner, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, transmission gate switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the devices included within it for implementing various functions can also be considered structures within the hardware component. Alternatively, the device used to implement various functions can be viewed as either a software module implementing the method or a structure within a hardware component.

[0125] Some modules in the apparatus of this invention can be described in the general context of computer-executable instructions, such as program modules, which are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc., that perform a specific task or implement a specific abstract data type. This invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0126] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A correction circuit for a two-step multiphase clock-to-digital converter, characterized in that, Includes a selection module and a calibration module; The selection module selects the correct clock signal based on the main clock level state at the flip edge of the fine quantization signal, and the selection module inputs the correct clock signal into the correction module. The selection module includes: a double-edge D flip-flop D0, a logic submodule SUB1, and a transmission gate switch submodule SUB2; The double-edge D flip-flop D0 is based on the signal CLK<2. Q-1 The level is identified by the fine-tuning signal Z_MOD; the Z_MOD signal is input to the clock terminal of the dual-edge D flip-flop D0, and the CLK<2 signal... Q -1 The data input of the double-edge D flip-flop D0 is used to output the signal J from the Q input of the double-edge D flip-flop D0. The terminal outputs signal J_INV, where CLK<2. Q-1 Lags behind the master clock by 180°; The logic submodule SUB1 generates signals SE1, SE2, A, and A_INV based on the fine-tuning signal; The transmission gate switch submodule SUB2 is based on the signal CLK<2 Q-1 > The signal J, the signal J_INV, the signal A, and the signal A_INV select the correct clock signal input to the calibration module; The correction module receives the correct clock signal, performs correction, and generates two sets of digital calibration control codes to perform correction operations on the coarse quantization count value of the coarse quantization signal using the digital calibration control codes. The correction operations include: hold, increment by one, increment by two, decrement by one, or decrement by two.

2. The correction circuit for a two-step multiphase clock-to-digital converter according to claim 1, characterized in that, The logic submodule SUB1 includes: a delay inverter I00, a general inverter I0, an AND gate G1, an AND gate G2, an XOR gate G3, and a general inverter I1; The input terminal of the delay inverter I00 and the second input terminal of the XNOR gate G3 are connected to the signal Z_MOD. The signal Z_MOD is inverted by the delay inverter I00 to generate the signal Z_MOD_DELAY. The signal Z_MOD_DELAY is connected to the first input terminal of the XNOR gate G3. The XNOR gate G3 outputs signal A and is connected to the ordinary inverter I1 to generate signal A_INV. The signal A and the signal A_INV are connected to the transmission gate switch submodule SUB2. The input terminal of the ordinary inverter I0 and the second input terminal of the AND gate G2 are connected to the signal Z_MOD. The signal Z_MOD is inverted by the ordinary inverter I0 to generate the signal Z_MOD_INV, which is then connected to the second input terminal of the AND gate G1. The first input terminal of the AND gate G1 and the first input terminal of the AND gate G2 are connected to the output signal A of the XOR gate G3. The AND gates G1 and G2 output set signals SE1 and SE2 respectively, which are connected to the correction module.

3. The correction circuit for a two-step multiphase clock-to-digital converter according to claim 1, characterized in that, The transmission gate switch submodule SUB2 includes a first-stage transmission gate switch S11, a first-stage transmission gate switch S12, a general inverter I2, a second-stage transmission gate switch S21, and a second-stage transmission gate switch S22. The input terminals of the first-stage transmission gate switch S11 and the first-stage transmission gate switch S12 are both connected to the signal CLK<2. Q-2 >, the signal J and the signal J_INV serve as the switching control signals for the first-stage transmission gate switch S11 and the first-stage transmission gate switch S12; the signal CLK<2 Q-2 Lag behind the master clock by 90°; The output terminal of the first-stage transmission gate switch S12 is connected to the input terminal of the ordinary inverter I2. The common terminal of the first-stage transmission gate switch S11 and the ordinary inverter I2 is connected to signal B. Signal B is connected to the input terminal of the second-stage transmission gate switch S21. The signals A and A_INV output by the logic submodule SUB1 serve as the switching control signals for the second-stage transmission gate switch S21 and the second-stage transmission gate switch S22. The input terminal of the second-stage transmission gate switch S22 is connected to a constant high-level signal. The common terminal of the second-stage transmission gate switch S21 and the second-stage transmission gate switch S22 is connected to signal C. Signal C is the correct clock signal corresponding to the level at the edge of the fine-quantization signal, and signal C is input to the correction module.

4. The correction circuit for a two-step multiphase clock-to-digital converter according to claim 1, characterized in that, The correction module includes: a first trigger submodule TRI1, a pulse submodule SUB3, and a second trigger module TRI2; The first trigger submodule TRI1 generates a digital calibration control code Mstart based on the fine quantization signal, the coarse quantization signal, the master clock signal, and the correct clock signal. <1> and digital calibration control code Mstop <1> The first trigger submodule TRI1 generates a fine-grained clock synchronization signal Z_MOD_DTRI based on the fine-grained signal, and the first trigger submodule TRI1 generates a coarse-grained clock synchronization signal Z_CNT_DTR based on the coarse-grained signal. The pulse submodule SUB3 is based on the fine-quantization clock synchronization signal Z_MOD_DTRI, the coarse-quantization clock synchronization signal Z_CNT_DTR, and the clock signal CLK<2 which lags the master clock by 45°. Q-3 > and a clock signal CLK<3*2 that lags the master clock by 135° Q-3 Generates pulse signal L; The second trigger submodule TRI2 generates two digital calibration control codes based on the pulse signal L, the signal J output by the double-edge D flip-flop D0 of the selection module, and the set signals SE1 and SE2 output by the logic submodule SUB1 of the selection module. The two digital calibration control codes are digital calibration control codes Mstart. <0> and digital calibration control code Mstop <0> .

5. The correction circuit for a two-step multiphase clock-to-digital converter according to claim 4, characterized in that, The first trigger submodule TRI1 includes a rising edge D flip-flop D1, a rising edge D flip-flop D2, a double-edge D flip-flop D3, and a holding module L1; The data terminal of the rising edge D flip-flop D1 is connected to the fine quantization signal, and the clock terminal is connected to the signal C output by the selection module, so that the fine quantization signal and the signal C are clock-synchronized to generate a fine quantization clock synchronization signal Z_MOD_DTRI. The signal C is the correct clock signal corresponding to the main clock level where the edge of the fine quantization signal is located. The data terminal of the rising-edge D flip-flop D2 is connected to the coarse quantization signal, and the clock terminal is connected to the main clock signal CLK. <0> So that the coarse quantization signal is synchronized with the master clock signal CLK. <0> Perform clock synchronization to generate a coarse-quantized clock synchronization signal Z_CNT_DTRI; The data terminal of the double-edge D flip-flop D3 is connected to the signal Z_MOD_DTRI output from the Q terminal of the rising-edge D flip-flop D1, and the clock terminal is connected to the signal Z_CNT_DTRI output from the Q terminal of the rising-edge D flip-flop D2, so that the fine-quantization clock synchronization signal Z_MOD_DTRI can perform level recognition on the coarse-quantization clock synchronization signal Z_CNT_DTRI. The terminal outputs the digital calibration control code Mstop. <1> The Q output of the dual-edge D flip-flop D3 is signal MN1; The holding module L1 includes a delay inverter I01, a transmission gate switch S31, and a capacitor C1; The input terminal of the delay inverter I01 is connected to the Q terminal of the double-edge D flip-flop D3, and the output terminal of the inverter I01 is connected to the positive terminal of the capacitor C1 through the transmission gate switch S31. The negative terminal of the capacitor C1 is grounded. The transmission gate switch S31 is controlled by the fine-tuning signal and the signal Z_MOD_INV generated by the logic submodule SUB1 of the selection module; The common terminal of the transmission gate switch S31 and the capacitor C1 serves as the output terminal of the holding module L1, outputting the digital calibration control code Mstart. <1> .

6. The correction circuit for a two-step multiphase clock-to-digital converter according to claim 4, characterized in that, The pulse submodule includes an XOR gate G4, an OR gate G5, and an AND gate G6; The fine-quantization clock synchronization signal Z_MOD_DTRI and the coarse-quantization clock synchronization signal Z_CNT_DTRI generated by the first trigger submodule TRI1 generate signal E through the XOR gate G4; The clock signal CLK<2 Q-3 >and the clock signal CLK<3*2 Q-3 The clock signal CLK<2 is generated by the OR gate G5. Q-3 >and the clock signal CLK<3*2 Q-3 > indicates a lag in the master clock signal CLK <0> 45° and 135°; The signal E and the signal F generate a pulse signal L through the AND gate G6, and the pulse signal L is connected to the second trigger submodule TRI2.

7. The correction circuit for a two-step multiphase clock-to-digital converter according to claim 4, characterized in that, The second trigger submodule TRI2 includes rising edge D flip-flop D4, rising edge D flip-flop D5, XOR gate G7, XOR gate G8, and holding module L2; The data terminal of the rising-edge D flip-flop D4 is connected to the rising-edge D flip-flop D4. The clock input of the rising edge D flip-flop D4 is connected to the output pulse signal L of the pulse submodule SUB3, and the set input of the rising edge D flip-flop D4 is connected to the set signal SE1 output by the selection module, so as to count the number of pulses of the pulse signal L near the time signal Tstop. When the number of pulses is 1, the Q input of the rising edge D flip-flop D4 outputs a low level, and when the number of pulses is 2, the Q input of the rising edge D flip-flop D4 outputs a high level. The data terminal of the rising-edge D flip-flop D5 is connected to the rising-edge D flip-flop D5. The clock input of the rising edge D flip-flop D5 is connected to the pulse signal L output by the pulse submodule SUB3, and the set input of the rising edge D flip-flop D5 is connected to the set signal SE2 output by the selection module, so as to count the number of pulses of the pulse signal L near the time signal Tstart. When the number of pulses is 1, the Q input of the rising edge D flip-flop D5 outputs a low level, and when the number of pulses is 2, the Q input of the rising edge D flip-flop D5 outputs a high level. The two inputs of the XOR gate G7 are respectively connected to the Q terminal of the rising-edge D flip-flop D4 and the output signal J of the selection module. The XOR gate G7 outputs the digital calibration control code Mstop. <0> ; The two inputs of the XOR gate G8 are respectively connected to the Q terminal of the rising edge D flip-flop D5 and the output signal J of the selection module, and the XOR gate G8 outputs the digital calibration control code MN0. The holding module L2 includes a delay inverter I02, a transmission gate switch S32, and a capacitor C2; The input terminal of the delay inverter I02 is connected to the output terminal of the XOR gate G8, and the output terminal of the inverter I02 is connected to the positive terminal of the capacitor C2 through the transmission gate switch S32. The negative terminal of the capacitor C2 is grounded. The transmission gate switch S32 is controlled by the fine-tuning signal and the signal Z_MOD_INV generated by the selection module; The common terminal of the transmission gate switch S32 and the capacitor C2 serves as the output terminal of the holding module L2, outputting the digital calibration control code Mstart. <0> .

8. A calibration method for a two-step multiphase clock-time digital converter, applied to the calibration circuit of a two-step multiphase clock-time digital converter as claimed in any one of claims 1-7, characterized in that, include: The correct clock signal C corresponding to the master clock level state at which the Z_MOD edge is selected is input into the calibration module. The calibration module receives the correct clock signal and generates two sets of digital calibration control codes; Based on two sets of digital calibration control codes, the coarse quantization count result corresponding to the coarse quantization signal is corrected by holding, incrementing by one, incrementing by two, decrementing by one, or decrementing by two.

9. A calibration method for a two-step multiphase clock-to-digital converter according to claim 8, characterized in that, Based on two sets of digital calibration control codes, the coarse quantization count result corresponding to the coarse quantization signal is maintained, incremented by one, incremented by two, decremented by one, or decremented by two, including: The digital calibration control code Mstart<1:0> generated by the calibration module is 11, which compensates for the coarse quantization count result by one. The digital calibration control code Mstart<1:0> generated by the calibration module is 00, which reduces the coarse quantization count result by one. The digital calibration control code Mstart<1:0> generated by the calibration module is 10 or 01, and no compensation is made for the coarse quantization count results; The digital calibration control code Mstop<1:0> generated by the calibration module is 11, which increments the coarse quantization count result by one. The digital calibration control code Mstop<1:0> generated by the calibration module is 00, which reduces the coarse quantization count result by one. The digital calibration control code Mstop<1:0> generated by the calibration module is 10 or 01, so there is no need to compensate for the coarse quantization count results; Where 1 represents a high level and 0 represents a low level; the correction module generates digital calibration control codes Mstart<1:0> and Mstop<1:0> to resolve the metastability error and transmission delay mismatch error of the D flip-flops at the Tstart and Tstop terminals of the time signal T. The compensation results formed by the digital calibration control codes Mstart<1:0> and Mstop<1:0> are accumulated and transmitted to the coarse quantization module for hold, increment, decrement, and subtraction operations.

Images