Inner loop resistance high order compensation circuit based on on-chip loop high order compensation

Abstract

The application discloses a kind of inner loop resistance high-order compensation circuits based on on-chip loop high-order compensation, belongs to voltage reference circuit field, and only uses the voltage reference circuit of CMOS to realize the adjustment of reference source by resistance array, and realizes low power consumption and low temperature coefficient by the resistance high-order compensation of inner loop, to switch power supply circuit as typical application in harsh environment, the inner loop resistance high-order compensation of the topology structure proposed can significantly reduce temperature coefficient, realizes work under wide temperature range.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of voltage reference circuit, in particular to a kind of inner loop resistance high-order compensation circuit based on on-chip loop high-order compensation. BACKGROUND

[0002] Voltage reference source provides stable voltage reference for other circuits, which is not affected by process, voltage, temperature (PVT) changes, and is widely used in switching power supply, analog-to-digital converter, linear voltage regulator circuit, etc. With the development of information age, especially in the field of space exploration, energy exploration, it requires the working equipment to work normally in a wider temperature range, some of which reach above 200℃ or below 60℃. This poses a challenge to the design of reference circuit. Currently, the mainstream design can mainly cover the temperature working range of-40℃ to 125℃, while at higher or lower temperatures, the temperature curve becomes very poor. The temperature coefficient of the existing voltage reference source for high-temperature working temperature is generally above 100ppm / ℃, and the power consumption is relatively large, about 100μW. Therefore, a voltage reference circuit with wider application range and lower temperature coefficient is needed.

[0003] To meet the above needs, high-order compensation can achieve low temperature coefficient. Compared with general reference circuits, high-order compensation compensates for the high-order terms of the reference source temperature function, eliminates the first-order derivative coefficient and even higher-order coefficient of the output voltage with respect to temperature, and achieves lower temperature coefficient. High-order compensation needs to achieve lower temperature coefficient according to the complementarity of the temperature characteristic curves of different devices. To achieve this purpose, more loops are usually introduced, which increases the overall power consumption and also increases the layout area.

[0004] To meet the needs of wider application range and PVT influence, many designs use bipolar transistor integrated CMOS to reduce the influence of PVT. However, under advanced process, the temperature characteristics of the bipolar transistor are severely deteriorated, which is not suitable for wide temperature range. SUMMARY

[0005] The present application provides a kind of inner loop resistance high-order compensation circuit based on on-chip loop high-order compensation, which realizes the voltage reference circuit of only using CMOS by resistance array to adjust the reference source, and realizes low power consumption and low temperature coefficient by the resistance high-order compensation of inner loop.

[0006] The present application provides a kind of inner loop resistance high-order compensation circuit based on on-chip loop high-order compensation, which includes: starting circuit and bias circuit, for the power-on start of circuit and providing bias voltage;

[0007] Operational amplifier circuit, for realizing the locking voltage of input same direction end and reverse end;

[0008] The operational amplifier circuit comprises a first N-type transistor MN1, a second N-type transistor MN2, a fifth N-type transistor MN5, a third P-type transistor MP3, a fourth P-type transistor MP4, a loop compensation resistor R1, and a loop compensation capacitor C1; the ZTC-MOS high-order compensation is achieved by using the virtual short characteristic of the operational amplifier, wherein the first N-type transistor MN1 and the second N-type transistor MN2 form a differential pair, the loop compensation resistor R1 and the loop compensation capacitor C1 are loop compensation resistors and capacitors, the third P-type transistor MP3 and the fourth P-type transistor MP4 are current mirror loads, and the fifth N-type transistor MN5 is a tail current source, which is used to define the current value of the operational amplifier circuit;

[0009] The resistance and ZTC-MOS compensation circuit comprises a MNx, a first P-type transistor MP1, a second P-type transistor MP2, a first adjusting resistor Ra1, a second adjusting resistor Ra2, and a third adjusting resistor Ra3; the gate end of the MNx and the Ra1 are connected to the two input ends of the operational amplifier, the gate end voltage of the MNx is defined by the first adjusting resistor Ra1, the MNx is provided with current values by the first P-type transistor MP1 and the second P-type transistor MP2, the voltage reference source with low temperature drift coefficient output is realized by high-order compensation between the first adjusting resistor Ra1 and the MNx, and the source-drain end voltage of the MNx and the output voltage reference value are adjusted by the second adjusting resistor Ra2 and the third adjusting resistor Ra3.

[0010] The resistance array trimming circuit is used to realize eight-bit precision trimming of the first adjusting resistor Ra1, the second adjusting resistor Ra2, and the third adjusting resistor Ra3 by three trimming points and a three-to-eight decoder and a resistance switch array, so as to weaken the influence of PVT.

[0011] In one embodiment of the present application, in the starting circuit and biasing circuit, the starting circuit comprises a sixth N-type transistor MN6, a seventh N-type transistor MN7 and a seventh P-type transistor MP7, the biasing circuit comprises a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth P-type transistor MP5, a sixth P-type transistor MP6 and a biasing adjusting resistor R2, wherein the source terminal of the seventh P-type transistor MP7 is connected to a power supply, the gate terminal and the drain terminal of the seventh P-type transistor MP7 are short-circuited and connected to the gate terminal of the sixth N-type transistor MN6 and the drain terminal of the seventh N-type transistor MN7, the gate terminal of the sixth N-type transistor MN6 starts to charge and turn on at the start, the source terminal of the sixth N-type transistor MN6 provides a bias voltage for the fourth N-type transistor MN4 and the fifth N-type transistor MN5 at the start to accelerate the start, and the seventh N-type transistor MN7 turns on after the circuit is started to avoid the continuous rise of the voltage at the source terminal of the sixth N-type transistor MN6, the third N-type transistor MN3, the fourth N-type transistor MN4, the fifth P-type transistor MP5 and the sixth P-type transistor MP6 are connected in a current source mode, and the biasing point of the biasing circuit is adjusted by the biasing adjusting resistor R2 to provide a gate voltage bias for the fifth N-type transistor MN5.

[0012] In one embodiment of the present application, the operational amplifier circuit comprises a first N-type transistor MN1, a second N-type transistor MN2, a fifth N-type transistor MN5, a third P-type transistor MP3, a fourth P-type transistor MP4, a loop compensation resistor R1 and a loop compensation capacitor C1, and is used for high-order compensation of the ZTC-MOS by using the virtual short characteristic of the operational amplifier, wherein the first N-type transistor MN1 and the second N-type transistor MN2 form a differential pair, the loop compensation resistor R1 and the loop compensation capacitor C1 are loop compensation resistance and capacitance, the third P-type transistor MP3 and the fourth P-type transistor MP4 are current mirror loads, and are used for double-ended input to single-ended output, and the fifth N-type transistor MN5 is a tail current source and is used for defining the current value of the operational amplifier circuit.

[0013] The inner loop resistance high-order compensation circuit based on the on-chip loop high-order compensation of the embodiment of the present application has the following beneficial effects:

[0014] (1) The high-order compensation structure based on the positive and negative temperature coefficient resistance in the loop is proposed, the advantages of high-order compensation and low temperature coefficient are realized, and the increase of power consumption caused by adding an extra loop is avoided.

[0015] (2) The configurable compensation method based on the resistance array in the loop is realized, the stable voltage output in a wider temperature range is realized, and the influence of the adverse environmental temperature change on the circuit is dynamically compensated through adaptive adjustment in a wider temperature range.

[0016] (3) The resistance array trimming structure is adopted to effectively weaken the influence of PVT and solve the influence of large resistance fluctuation in the process on the circuit.

[0017] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the attendant drawings or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0018] The foregoing and / or additional aspects and advantages of the application are achieved by providing an on-chip loop high-order compensation based inner loop resistance high-order compensation circuit structure according to an embodiment of the application.

[0019] Figure 1 An inner loop high-order compensation schematic diagram is provided according to an embodiment of the application.

[0020] Figure 2 An inner loop high-order compensation schematic diagram is provided according to an embodiment of the application.

[0021] Figure 3 A source-drain current I of an MNx tube in a wide temperature range of -65°C to 225°C is provided according to an embodiment of the application. DS And a cadence simulation curve of resistance values of Ra1, Ra2 and Ra3 changing with temperature;

[0022] Figure 4 An eight-bit precision trimming schematic diagram is provided according to an embodiment of the application, in which a three-bit trimming point is used to control a resistance switch array through a three-to-eight decoder.

[0023] Figure 5 Trimming and non-trimming cadence simulation results and process corner cadence simulation results are provided according to an embodiment of the application.

[0024] Figure 6 A reference voltage value and an output voltage temperature coefficient value are output by 200 times of Monte Carlo cadence simulation according to an embodiment of the application.

[0025] Figure 7 A cadence simulation result of a power supply rejection ratio of a structure reference voltage output at different temperatures is provided according to an embodiment of the application. DETAILED DESCRIPTION

[0026] Embodiments of the application are described in detail below with reference to the attached drawings, which show by way of example, embodiments in which like reference numerals refer to like elements or elements having similar functions. The embodiments described below are exemplary and are intended to be illustrative of the application and are not to be construed as limiting the application.

[0027] Figure 1A high-order compensation circuit structure of an inner loop resistance based on a high-order compensation of an on-chip loop is provided according to an embodiment of the present application.

[0028] As shown in the figure, the high-order compensation circuit of the inner loop resistance based on the high-order compensation of the on-chip loop comprises the following steps: Figure 1

[0029] A starting circuit and a biasing circuit are used for starting up the circuit and providing a biasing voltage;

[0030] An operational amplifier circuit is used for locking the voltages of the input same direction terminal and the input reverse terminal;

[0031] The operational amplifier circuit comprises a first N-type transistor MN1, a second N-type transistor MN2, a fifth N-type transistor MN5, a third P-type transistor MP3, a fourth P-type transistor MP4, a loop compensation resistor R1, and a loop compensation capacitor C1, and is used for high-order compensation of the ZTC-MOS by using the virtual short characteristic of the operational amplifier, wherein the first N-type transistor MN1 and the second N-type transistor MN2 form a differential pair, the loop compensation resistor R1 and the loop compensation capacitor C1 are loop compensation resistance and capacitance, the third P-type transistor MP3 and the fourth P-type transistor MP4 are current mirror loads, the fifth N-type transistor MN5 is a tail current source, and the operational amplifier circuit is used for double-end input to single-end output and defining the current value of the operational amplifier circuit;

[0032] The resistance and ZTC-MOS compensation circuit comprises an MNx, a first P-type transistor MP1, a second P-type transistor MP2, a first adjusting resistor Ra1, a second adjusting resistor Ra2, and a third adjusting resistor Ra3, the gate terminal of the MNx and the Ra1 are connected to the two input terminals of the operational amplifier, the gate terminal voltage of the MNx is defined by the first adjusting resistor Ra1, the current value of the MNx is provided by the first P-type transistor MP1 and the second P-type transistor MP2, the voltage reference source with low temperature drift coefficient is realized by high-order compensation between the first adjusting resistor Ra1 and the MNx, and the source-drain terminal voltage of the MNx and the output voltage reference value are adjusted by the second adjusting resistor Ra2 and the third adjusting resistor Ra3;

[0033] The resistance array trimming circuit is used for realizing eight-bit precision trimming of the first adjusting resistor Ra1, the second adjusting resistor Ra2, and the third adjusting resistor Ra3 by three trimming points, a three-to-eight decoder, and a resistance switch array, and weakening the influence of PVT.

[0034] ​In one embodiment of the present application, in the starting circuit and the biasing circuit, the starting circuit comprises a sixth N-type transistor MN6, a seventh N-type transistor MN7 and a seventh P-type transistor MP7, the biasing circuit comprises a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth P-type transistor MP5, a sixth P-type transistor MP6 and a biasing adjusting resistor R2, wherein the source end of the seventh P-type transistor MP7 is connected to a power supply, the gate end and the drain end of the seventh P-type transistor MP7 are short-circuited and connected to the gate end of the sixth N-type transistor MN6 and the drain end of the seventh N-type transistor MN7, the gate end of the sixth N-type transistor MN6 starts to charge until the sixth N-type transistor MN6 is turned on during starting, the source end of the sixth N-type transistor MN6 provides a bias voltage for the fourth N-type transistor MN4 and the fifth N-type transistor MN5 during power-on, and the starting is accelerated; after the circuit is started, the seventh N-type transistor MN7 is turned on to avoid continuous rise of the source end voltage of the sixth N-type transistor MN6, the third N-type transistor MN3, the fourth N-type transistor MN4, the fifth P-type transistor MP5 and the sixth P-type transistor MP6 are connected in a current source mode, and the biasing point of the biasing circuit is adjusted through the biasing adjusting resistor R2 to provide a gate voltage bias for the fifth N-type transistor MN5.

[0035] The operational amplifier circuit comprises a first N-type transistor MN1, a second N-type transistor MN2, a fifth N-type transistor MN5, a third P-type transistor MP3, a fourth P-type transistor MP4, a loop compensation resistor R1 and a loop compensation capacitor C1, and is used for high-order compensation of the ZTC-MOS by using the virtual short characteristic of the operational amplifier, wherein the first N-type transistor MN1 and the second N-type transistor MN2 form a differential pair, the loop compensation resistor R1 and the loop compensation capacitor C1 form a loop compensation resistor-capacitor, the third P-type transistor MP3 and the fourth P-type transistor MP4 form a current mirror load, and the fifth N-type transistor MN5 is a tail current source, which is used for double-ended input to single-ended output and for defining the current value of the operational amplifier circuit.

[0036] As shown in Figure 1 , the starting and biasing of the circuit are realized by the starting circuit and the biasing circuit, and the OTA operational amplifier with five transistors is used to realize the locking of the same direction and reverse direction input voltages. The unit1 and the unit2 are a positive temperature coefficient resistor and a negative temperature coefficient resistor respectively, and the overall temperature coefficient of the Ra1 resistor is designed to provide a gate voltage for the MNx transistor, and the MNx transistor is provided with a drain bias through the resistors Ra2 and Ra3, so that the final VREF output is a ZTC voltage. The V REF The expression of the output voltage is shown in formula (1):

[0037]

[0038] The V GS is the gate-source voltage of the MNx, and the V DSLet I be the drain-source voltage of MNx. DS Let MNx be the drain-source current. It can be observed that the value of the reference voltage is affected by the resistance and I. DS Impact. This design is being implemented through I DS Mutual compensation between the resistor and the resistor achieves high-order compensation, resulting in a low temperature coefficient. The principle is as follows: Figure 2 As shown, by selecting a suitable resistor Ra1, Ra1, which is composed of resistors with positive and negative temperature coefficients, and the selected I... DS The curves compensate for each other, specifically by using an operational amplifier to make Ral provide gate bias for MNx, while the current I of MP2 is mirrored by MP1. DS This makes the voltage of Ra1 I. DS The product of Ra1 and I, since Ra1 and I DS The temperature coefficients are set to be complementary, which enables the final output VREF to achieve a low temperature coefficient within the selected temperature range.

[0039] Figure 3 (a) and (b) show the results of using Cadence software to test the MNx transistor at different V values. GS Its output current I DS With temperature change (V) DS The voltage is set to 0.3V, and a curve showing the resistance changing with temperature with positive and negative temperature coefficients is selected. In this invention, V is selected. GS When I is 661mV DS In this case, the temperature coefficient function curve of the MNx transistor is extracted using MATLAB software, and then high-order compensation is performed by adjusting the ratio of positive and negative temperature coefficient resistors to its curve. This invention takes a silicon-free N+ polycrystalline resistor (positive temperature coefficient) and a high polycrystalline silicon resistor (negative temperature coefficient) as examples, and achieves high-order compensation with the I... DS Complementary temperature characteristic curves. Simulation verification based on 0.18-μm BCD process yields the following results: Figure 3 As shown in (c). Resistors Ra1, Ra2, and Ra3 adopt... Figure 3 The resistor ratio in (c) provides bias voltage for transistor MNx, ultimately achieving a low temperature coefficient and wide temperature range voltage reference output.

[0040] Figure 4The trimming schematic diagram of the resistance switching array, since the resistance is greatly affected by the environment in the general process, the error range is generally fluctuated by plus or minus 20% to 40%, so the resistance value has great fluctuation under different PVT environments, and the resistance needs to be trimmed to realize stable output under different PVT. The positive and negative temperature coefficient resistances of Ra1, Ra2 and Ra3 are trimmed by three three-eight decoders, wherein the minimum unit of unit1.1 to unit1.4 is 1kΩ, the maximum unit is 8kΩ, and unit1.0 is the set resistance value. The resistance of the unit2 module is set to be consistent with the unit1 module. The resistance value in the range of 1kΩ to 15kΩ is adjusted and compensated by the three-eight decoder through three control ends, so as to reduce the influence of PVT on the performance of the reference source chip circuit of the application.

[0041] Figure 5 The cadence simulation results under the trimming and untrimming 0.18μm BCD process environment, cadence simulation results and process angle Cadence simulation results can be found that the output voltage of the result (a) after trimming through the resistance switching array is obviously more stable than the result (b) without trimming. The results after trimming under different process angles are completed, and the fluctuation is within an acceptable range. After trimming and in the temperature range of-65℃ to 225℃, the simulation temperature coefficient result under the 0.18μm BCD process environment is 1.49ppm / ℃ under the TT process angle, 3.90ppm / ℃ under the FF process angle and 4.27ppm / ℃ under the SS process angle. It can be found that the temperature coefficient can reach a very low level, and compared with the temperature coefficient (7.74ppm / ℃ under the TT process angle) provided by the single ZTC-MOS, it is further improved.

[0042] Figure 6 is the Monte Carlo simulation result of the reference voltage output value in the application, the output voltage mean is 508.303mV, and the standard deviation is 478μV. (b) is the Monte Carlo simulation result of the temperature coefficient, the output temperature coefficient mean is 3.38ppm / ℃, and the standard deviation is 1.7ppm / ℃. (c) is the detail diagram of 50 simulation results in Monte Carlo. Eight test points are selected in the range of-65℃ to 225℃ for Monte Carlo simulation. The overall low temperature coefficient is achieved, and the overall circuit power consumption is only 36.9μW.

[0043] Figure 7 is the cadence simulation result of the power supply rejection ratio of the structure reference voltage output under different temperatures, which reaches the optimal value of 94dB@1kHz at 225℃, and reaches the worst case of 83dB@1kHz at-65℃. The power supply rejection ratio expression of the application is shown as formula (2):

[0044]

[0045] Wherein rox, ro2 are the output impedance of MNx and MP2 respectively, gmx, gm2 are the transconductance of transistor MNx and MP2 respectively. It can be obviously found from the expression that the addition of the resistor Ra3 further increases the power supply rejection ratio of the application, and improves the stability of the reference output.

[0046] According to the inner loop resistance high-order compensation circuit based on on-chip loop high-order compensation provided by the embodiment of the application, a wide temperature and low temperature coefficient inner loop resistance high-order compensation circuit is provided, and the circuit is applied to a switching power supply circuit in a harsh environment as a typical application. The inner loop resistance high-order compensation of the topology structure can significantly reduce the temperature coefficient and realize operation in a wide temperature range.

[0047] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or N embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0048] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "N" is at least two, for example, two, three, etc., unless otherwise specifically limited.

Claims

1. An inner loop resistance high order compensation circuit based on on-chip loop high order compensation, characterized in that, The application relates to a voltage reference source, which comprises the following parts: a starting circuit and a biasing circuit, which are used for starting and providing a biasing voltage; an operational amplifier circuit, which is used for locking the input same direction end and reverse end voltage; the operational amplifier circuit comprises a differential pair tube composed of a first N-type transistor MN1 and a second N-type transistor MN2, a tail current source composed of a fifth N-type transistor MN5, a current mirror load composed of a third P-type transistor MP3 and a fourth P-type transistor MP4, and a loop compensation resistor R1 and a loop compensation capacitor C1, wherein the loop compensation resistor and capacitor are used for high-order compensation of the temperature coefficient between the first adjusting resistor Ra1 and the MNx by using the virtual short characteristic of the operational amplifier; the source ends of the first N-type transistor MN1 and the second N-type transistor MN2 are connected to each other and to the drain end of the fifth N-type transistor MN5, the gate ends of the first N-type transistor MN1 and the second N-type transistor MN2 are used as the same direction input end and the reverse input end of the operational amplifier circuit respectively, and are connected to one end of the first adjusting resistor Ra1 and the gate end of the MNx respectively; one end of the loop compensation resistor R1 is connected to one end of the loop compensation capacitor C1, the other end of the loop compensation resistor R1 is connected to the drain end of the first N-type transistor MN1, and the other end of the loop compensation capacitor C1 is connected to the drain end of the second N-type transistor MN2; the drain end and the gate end of the third P-type transistor MP3 are connected to the drain end of the first N-type transistor MN1, the drain end of the fourth P-type transistor MP4 is connected to the drain end of the second N-type transistor MN2, the source ends of the third P-type transistor MP3 and the fourth P-type transistor MP4 are connected to the power supply voltage, and the gate ends are connected to form a current mirror load, which is used for realizing the conversion of the double-end input of the differential pair tube gate end of the operational amplifier circuit into the single-end output at the second N-type transistor MN2 drain end and the fourth P-type transistor MP4 drain end of the operational amplifier circuit; the source end of the fifth N-type transistor MN5 is connected to the ground, the gate end is connected to the starting circuit and the biasing circuit, and the drain end is connected to the source of the differential pair tube, which is used for defining the current value of the operational amplifier circuit; the resistor and ZTC-MOS compensation circuit comprises the MNx, the first P-type transistor MP1, the second P-type transistor MP2, the first adjusting resistor Ra1, the second adjusting resistor Ra2 and the third adjusting resistor Ra3; the gate end of the MNx and the Ra1 are connected to the two gate input ends of the differential pair tube of the operational amplifier circuit, the gate end voltage of the MNx is defined through the first adjusting resistor Ra1, the current value of the MNx is provided through the first P-type transistor MP1 and the second P-type transistor MP2, the voltage reference source with low temperature drift coefficient output is realized through the high-order compensation between the first adjusting resistor Ra1 and the MNx, and the source-drain end voltage of the MNx and the output voltage reference value are adjusted through the second adjusting resistor Ra2 and the third adjusting resistor Ra3. The resistance array trimming circuit is used for trimming the first adjusting resistance Ra1, the second adjusting resistance Ra2 and the third adjusting resistance Ra3 through three-bit trimming points and through a three-eight decoder and a resistance switch array, and realizes the eight-bit precision trimming of the first adjusting resistance Ra1, the second adjusting resistance Ra2 and the third adjusting resistance Ra3, and realizes the weakening of the influence of PVT.

2. The on-chip loop high-order compensation based inner loop resistance high-order compensation circuit according to claim 1, wherein, In the starting circuit and the biasing circuit, the starting circuit comprises a sixth N-type transistor MN6, a seventh N-type transistor MN7 and a seventh P-type transistor MP7, and the biasing circuit comprises a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth P-type transistor MP5, a sixth P-type transistor MP6 and a biasing adjusting resistance R2. The source of the seventh P-type transistor MP7 is connected to a power supply, the gate and the drain of the seventh P-type transistor MP7 are shorted and connected to the gate of the sixth N-type transistor MN6 and the drain of the seventh N-type transistor MN7. When starting, the gate of the sixth N-type transistor MN6 starts to charge until the sixth N-type transistor MN6 is turned on. The source of the sixth N-type transistor MN6 provides a bias voltage for the fourth N-type transistor MN4 and the fifth N-type transistor MN5 during power-on, so as to accelerate the starting. When the circuit is started completely, the seventh N-type transistor MN7 is turned on, so as to avoid the continuous rise of the voltage at the source of the sixth N-type transistor MN6. The third N-type transistor MN3, the fourth N-type transistor MN4, the fifth P-type transistor MP5 and the sixth P-type transistor MP6 are connected in a current source mode, and the biasing point of the biasing circuit is adjusted through the biasing adjusting resistance R2, so as to provide a gate voltage bias for the fifth N-type transistor MN5.

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