Cantilevered power planes provide return current paths for high-speed signals

Abstract

The present invention provides novel tools and techniques for implementing cantilevered power planes to provide return current paths for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler. The plurality of layers includes power, ground, and signal layers, each disposed on or above the substrate core, with each signal layer disposed between a power layer and a ground layer, each of the power layer and the ground layer providing a return path for high-frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layers. The AC coupler is coupled to each of the power and ground layers, with no portion of any power layer near an edge of the substrate core being anchored to the substrate core.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure relates generally to methods, systems, and apparatus for implementing semiconductor technology, and more particularly, to methods, systems, and apparatus for implementing cantilevered power planes to provide return current paths for high-speed signals. Background Art

[0004] For a typical semiconductor package in which the substrate's buildup includes ground, power, and signal layers for ground connection, power supply, and signal, respectively, the return path is carried only along the ground layer. This requires that the ground layer (or, in some cases, an additional ground layer) be formed adjacent to the signal layer (excluding the dielectric layer between adjacent pairs of ground, power, and signal layers). The additional layers result in additional costs for manufacturing the semiconductor package.

[0005] Therefore, there is a need for more robust and scalable solutions for implementing semiconductor technology, and more particularly, there is a need for methods, systems, and apparatus for implementing cantilevered power planes to provide return current paths for high-speed signals. Summary of the Invention

[0006] The technology of the present disclosure relates generally to tools and techniques for implementing semiconductor technology, and more particularly to methods, systems, and apparatus for implementing cantilevered power planes to provide return current paths for high-speed signals.

[0007] In one aspect, a semiconductor package includes a semiconductor substrate comprising a core layer; a first plurality of layers disposed on or over the core layer; and at least one alternating current ("AC") coupler. The first plurality of layers includes: one or more first power layers disposed on or over the core layer; one or more first ground layers disposed on or over the core layer; one or more first signal layers disposed on or over the core layer, each of the one or more first signal layers disposed between a nearest power layer of the one or more first power layers and a nearest ground layer of the one or more first ground layers, each of the nearest power layer and the nearest ground layer providing a return path for a high-frequency signal carried by each signal layer; and a plurality of first dielectric layers, each dielectric layer disposed between and in contact with two of the one or more first power layers, the one or more first ground layers, or the one or more first signal layers. The at least one AC coupler is coupled to each of at least one of the one or more first power layers and at least one of the one or more first ground layers, and no portion of any of the one or more first power layers is anchored to the core layer within a first distance from an edge of the core layer, wherein the first distance is half the distance between the edge of the core layer and the nearest edge of a semiconductor chip or one of a mounting base of the chip mounted on or above the semiconductor substrate.

[0008] In some embodiments, each of the at least one AC coupler is configured to reduce noise signals carried by each of the at least one first power layer to which it is coupled. In some examples, the at least one AC coupler is disposed on or above the first plurality of layers. In some cases, each of the at least one AC coupler comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more dielectric materials, one or more structures having dielectric substructures, and / or the like. Alternatively or additionally, at least a portion of the at least one AC coupler is disposed within the first plurality of layers. In some cases, each of the at least a portion of the at least one AC coupler comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more vias, one or more dielectric materials, one or more structures having dielectric substructures, and / or the like. In some examples, the nearest power layer and the nearest ground layer to each signal layer each provide a return path for high-frequency signals carried by each signal layer based on magnetic induction.

[0009] According to some embodiments, the first plurality of layers further includes a solder resist layer as the uppermost layer among the other layers in the first plurality of layers. In some cases, the semiconductor package further includes: the semiconductor chip mounted on or above the uppermost layer in the first plurality of layers; and at least one decoupling capacitor mounted on or above the uppermost layer in the first plurality of layers in proximity to the semiconductor chip, the at least one decoupling capacitor coupled to the uppermost power layer in the one or more first power layers and the ground layer in the one or more first ground layers, the at least one decoupling capacitor configured to reduce or prevent rapid power supply fluctuations.

[0010] In some embodiments, the core layer includes a top surface and a bottom surface. The first plurality of layers are disposed on or above the top surface of the core layer. In some cases, the semiconductor package further includes a second plurality of layers disposed on or below the bottom surface of the core layer, at least one signal anchor disposed on or below a bottommost layer of the second plurality of layers that is farthest from the core layer, and at least one ground anchor disposed on or below the bottommost layer of the second plurality of layers. In some examples, the second plurality of layers include: one or more second power layers disposed on or below the core layer; one or more second ground layers disposed on or below the core layer; one or more second signal layers disposed on or below the core layer, each of the one or more second signal layers disposed between a nearest power layer among the one or more second power layers and a nearest ground layer among the one or more second ground layers, the nearest power layer and the nearest ground layer each providing a return path for a high-frequency signal carried by each signal layer; and a plurality of second dielectric layers, each dielectric layer disposed between and in contact with two of the power layers among the one or more second power layers, the ground layers among the one or more second ground layers, or the signal layers among the one or more second signal layers. In some examples, the at least one signal anchor is connected to the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer and through the core layer, thereby anchoring the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer to the core layer. In some cases, the at least one ground anchor is connected to the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer and through the core layer, thereby anchoring the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer to the core layer.

[0011] In some examples, the at least one AC coupler is coupled to two or more of the at least one of the one or more first power layers, the at least one of the one or more first ground layers, the at least one of the one or more second power layers, or the at least one of the one or more second ground layers, and no portion of any of the one or more first power layers and the one or more second power layers near the edge of the core layer is anchored to the core layer. In some cases, the ground layer of the one or more first ground layers is at least one of the uppermost layer of the first plurality of layers and the lowermost layer of the first plurality of layers, and the ground layer of the one or more second ground layers is at least one of the uppermost layer of the second plurality of layers and the lowermost layer of the second plurality of layers.

[0012] According to some embodiments, the first plurality of layers include: a first ground layer among the one or more first ground layers, which is disposed on or above the core layer; a first dielectric layer among the one or more first dielectric layers, which is on the first ground layer; a first power layer among the one or more first power layers, which is disposed on the first dielectric layer; a second dielectric layer among the one or more first dielectric layers, which is on the first power layer; a first signal layer among the one or more first signal layers, which is disposed on the second dielectric layer; a third dielectric layer among the one or more first dielectric layers, which is on the first signal layer; a second ground layer among the one or more first ground layers, which is disposed on the third dielectric layer; and the one or more first a fourth dielectric layer among the dielectric layers, which is disposed on the second ground layer; a second signal layer among the one or more first signal layers, which is disposed on the fourth dielectric layer; a fifth dielectric layer among the one or more first dielectric layers, which is disposed on the second signal layer; a second power layer among the one or more first power layers, which is disposed on the fifth dielectric layer; a sixth dielectric layer among the one or more first dielectric layers, which is disposed on the second power layer; a third signal layer among the one or more first signal layers, which is disposed on the sixth dielectric layer; a seventh dielectric layer among the one or more first dielectric layers, which is disposed on the third signal layer; and a third ground layer among the one or more first ground layers, which is disposed on the seventh dielectric layer. In some cases, the first power layer and the second ground layer each provide a return path for high-frequency signals carried by the first signal layer. In some examples, the second ground layer and the second power layer each provide a return path for high-frequency signals carried by the second signal layer. In some cases, the second power layer and the third ground layer each provide a return path for high-frequency signals carried by the third signal layer.

[0013] On the other hand, a method includes: forming a first plurality of layers disposed on or above a core layer of a semiconductor substrate, comprising: forming a first ground layer of one or more first ground layers on the core layer; forming a first dielectric layer of one or more first dielectric layers on the first ground layer; forming a first power layer of one or more first power layers on the first dielectric layer; forming a second dielectric layer of the one or more first dielectric layers on the first power layer; forming a first signal layer of one or more first signal layers on the second dielectric layer; forming a third dielectric layer of the one or more first dielectric layers on the first signal layer; and forming a second ground layer of the one or more first ground layers on the third dielectric layer, wherein the first power layer and the second ground layer each provide a return path for a high-frequency signal carried by the first signal layer. The method further includes mounting at least one alternating current (“AC”) coupler on or over the first plurality of layers and coupling the at least one AC coupler to each of at least one of the one or more first power layers and at least one of the one or more first ground layers, with no portion of any of the one or more first power layers being anchored to the core layer within a first distance from an edge of the core layer, the first distance being half the distance between the edge of the core layer and a nearest edge of a semiconductor chip or one of a mounting for the chip mounted on or over the semiconductor substrate.

[0014] In some embodiments, each of the at least one AC coupler is configured to reduce noise signals carried by each of the at least one power layer to which it is coupled. In some examples, each of the at least one AC coupler comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more dielectric materials, or one or more structures having a dielectric substructure, and / or the like. Alternatively or additionally, at least a portion of the at least one AC coupler is disposed within the first plurality of layers. In some cases, each of the at least a portion of the at least one AC coupler comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more vias, one or more dielectric materials, or one or more structures having a dielectric substructure, and / or the like.

[0015] According to some embodiments, the method further includes: forming a solder resist layer as the topmost layer among the other layers in the first plurality of layers; mounting the semiconductor chip on or above the topmost layer in the first plurality of layers; and mounting at least one decoupling capacitor on or above the topmost layer in the first plurality of layers close to the semiconductor chip, the at least one decoupling capacitor being coupled to the topmost power layer in the one or more first power layers and the ground layer in the one or more first ground layers, the at least one decoupling capacitor being configured to reduce or prevent rapid power supply fluctuations.

[0016] In some embodiments, forming the first plurality of layers further includes: forming a fourth dielectric layer of the one or more first dielectric layers on the second ground layer; forming a second signal layer of the one or more first signal layers on the fourth dielectric layer; forming a fifth dielectric layer of the one or more first dielectric layers on the second signal layer; forming a second power layer of the one or more first power layers on the fifth dielectric layer; forming a sixth dielectric layer of the one or more first dielectric layers on the second power layer; forming a third signal layer of the one or more first signal layers on the sixth dielectric layer; forming a seventh dielectric layer of the one or more first dielectric layers on the third signal layer; and forming a third ground layer of the one or more first ground layers on the seventh dielectric layer. In some examples, the second ground layer and the second power layer each provide a return path for high-frequency signals carried by the second signal layer. In some cases, the second power layer and the third ground layer each provide a return path for high-frequency signals carried by the third signal layer.

[0017] According to some embodiments, the core layer includes a top surface and a bottom surface. The first plurality of layers is disposed on or above the top surface of the core layer. In some examples, the method further includes forming a second plurality of layers disposed on or below the core layer, comprising: rotating the semiconductor package so that the bottom surface of the core layer faces upward; forming a first ground layer of one or more second ground layers on or above the bottom surface of the core layer; forming a first dielectric layer of one or more second dielectric layers on the first ground layer; forming a first power layer of one or more second power layers on the first dielectric layer; forming a second dielectric layer of the one or more second dielectric layers on the first power layer; forming a first signal layer of one or more second signal layers on the second dielectric layer; forming a third dielectric layer of the one or more second dielectric layers on the first signal layer; and forming a second ground layer of the one or more second ground layers on the third dielectric layer. In some cases, the first power layer and the second ground layer each provide a return path for a high-frequency signal carried by the first signal layer.

[0018] In some embodiments, the at least one AC coupler is coupled to two or more of the at least one of the one or more first power layers, the at least one of the one or more first ground layers, the at least one of the one or more second power layers, or at least one of the one or more second ground layers, and any portion of the one or more first power layers and any of the one or more second power layers near the edge of the core layer is not anchored to the core layer.

[0019] According to some embodiments, the method further includes: when the semiconductor package is rotated so that the first plurality of layers face upward and the second plurality of layers face downward, forming a solder resist layer as the lowest layer farthest from the core layer among the other layers in the second plurality of layers; forming at least one first solder anchor as at least one signal anchor on or above the lowest layer in the second plurality of layers, the at least one signal anchor being connected to the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer and through the core layer using corresponding at least one anchor path, thereby connecting all the signal anchors near the edge of the core layer to the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers. anchoring the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers to the core layer; forming at least one second solder anchor on or above the lowest layer of the second plurality of layers as at least one ground anchor, the at least one ground anchor being connected to the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer and through the core layer using corresponding at least one anchor via, thereby anchoring the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer to the core layer.

[0020] In some embodiments, each of the at least one anchor via is formed by a process comprising one of: forming a hole through all interposers in the first and second multiple layers and filling the hole with a conductive material, wherein the at least one signal anchor or the at least one ground anchor, respectively, is formed to be in contact with the conductive material; or forming a hole through each interposer in the first and second multiple layers and filling the hole with a conductive material after each interposer is formed and before the next interposer is formed, and repeating the hole formation and hole filling until all of the at least one anchor vias are formed in all interposers, wherein the at least one signal anchor or the at least one ground anchor, respectively, is formed to be in contact with the conductive material; and / or the like.

[0021] Various modifications and additions may be made to the embodiments discussed without departing from the scope of the invention. For example, although the embodiments described above refer to particular features, the scope of the invention also includes embodiments having different combinations of features and embodiments that do not include all of the above features.

[0022] The details of one or more aspects of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the techniques described in this disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] A further understanding of the nature and advantages of certain embodiments may be achieved by reference to the remainder of the specification and drawings, in which like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to designate one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0024] Figure 1 is a schematic diagram illustrating a side view of an example of a configuration of a semiconductor package having a return current path only along an adjacent ground plane.

[0025] Figure 2A and 2B are schematic diagrams illustrating side views of various non-limiting examples of semiconductor packages having a power plane that provides a return current path for high-speed signals in accordance with various embodiments.

[0026] Figure 3A and 3B are schematic diagrams illustrating side and top views of a non-limiting example of a semiconductor package for implementing a cantilevered power plane to provide a return current path for high-speed signals in accordance with various embodiments.

[0027] Figure 4 is a schematic diagram illustrating a side cross-sectional view of a non-limiting example of a semiconductor package for implementing a cantilevered power plane to provide a return current path for high-speed signals in accordance with various embodiments.

[0028] Figures 5A to 5E is a flow chart illustrating a method for implementing a cantilevered power plane to provide a return current path for high-speed signals, according to various embodiments. DETAILED DESCRIPTION

[0029] Overview

[0030] Various embodiments provide tools and techniques for implementing semiconductor technology, and more particularly, provide methods, systems, and apparatus for implementing cantilevered power planes to provide return current paths for high-speed signals.

[0031] In various embodiments, a semiconductor package includes a semiconductor substrate including a core layer; a first plurality of layers disposed on or over the core layer; and at least one alternating current ("AC") coupler. The first plurality of layers includes: one or more first power layers disposed on or over the core layer; one or more first ground layers disposed on or over the core layer; one or more first signal layers disposed on or over the core layer, each of the one or more first signal layers disposed between a nearest power layer of the one or more first power layers and a nearest ground layer of the one or more first ground layers, the nearest power layer and the nearest ground layer each providing a return path for a high-frequency signal carried by each signal layer; and a plurality of first dielectric layers, each dielectric layer disposed between and in contact with two of the one or more first power layers, the one or more first ground layers, or the one or more first signal layers. At least one AC coupler is coupled to each of at least one of the one or more first power layers and at least one of the one or more first ground layers, and no portion of any of the one or more first power layers is anchored to the core layer within a first distance from an edge of the core layer, the first distance being half the distance between the edge of the core layer and the nearest edge of the semiconductor chip or one of the mounting bases for the chip mounted on or above the semiconductor substrate.

[0032] In various aspects described herein, various examples of semiconductor packages and methods for implementing cantilevered power planes to provide return current paths for high-speed signals are provided. This allows a power layer (or power plane) (together with a ground layer or ground plane) to serve as a return path for high-frequency (or high-speed) signals carried on a signal layer without significant crosstalk (e.g., due to the presence of a power ball or the like anchoring the power layer to the edge of a substrate base or core layer). An AC coupler anchors the ground layer and the power layer and any portion of any power layer near the edge of the substrate core is not anchored to the substrate core. The AC coupler can also be used to reduce noise signals carried by any of the power layers to which it is coupled. Due to these features, cost savings can be achieved (because fewer layers are used, etc.) while achieving the desired performance of the semiconductor chip without excessive signal degradation (e.g., crosstalk caused by a power ball or the like).

[0033] These and other aspects of a semiconductor package and method for implementing a cantilevered power plane to provide a return current path for high-speed signals are described in more detail with respect to the figures.

[0034] The following detailed description describes several embodiments in more detail to enable those skilled in the art to practice such embodiments. The described examples are for illustration only and are not intended to limit the scope of the invention.

[0035] In the following description, for the sake of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be understood by those skilled in the art that other embodiments of the present invention may be practiced without some of these details. In other examples, some structures and devices are shown in block diagram form. Several embodiments are described herein, and although various features are attributed to different embodiments, it will be understood that features described with respect to one embodiment may also be combined with other embodiments. However, by the same notation, a single feature or several features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0036] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and the like should be understood as being modified in all instances by the term "about." In this application, unless expressly stated otherwise, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. Furthermore, the use of the term "comprising" and other forms such as "comprising" should be considered non-exclusive. Furthermore, unless expressly stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

[0037] Some embodiments

[0038] We now turn to the embodiments illustrated by the drawings. Figure 1 5 illustrate some features of methods, systems, and apparatus for implementing semiconductor technology and more particularly, illustrate methods, systems, and apparatus for implementing a cantilevered power plane to provide a return current path for high-speed signals, as described above. Figure 1 The methods, systems, and apparatus described in connection with Figures 5 and 5A refer to examples of different embodiments including various components and steps, which may be considered alternatives or may be used in combination with each other in various embodiments. Figure 1 The descriptions of the illustrated methods, systems, and apparatus presented in Figures 5 to 5 are for illustration only and should not be considered to limit the scope of the different embodiments.

[0039] Refer to the pictures, Figure 1 is a schematic diagram illustrating a side view of an example 100 of a configuration of a semiconductor package having a return current path only along an adjacent ground plane.

[0040] like Figure 1, the semiconductor package 105 includes a ground layer 125 for every other layer of the substrate, wherein a power layer 130 is disposed between the uppermost ground layer 125 and the next uppermost ground layer 125, and wherein a signal layer 135 is sandwiched or disposed between two of the other ground layers 125 (e.g., in a "G / S / G stack" or "G / S / G arrangement" or the like). Although Figure 1 Not shown in , but each neighboring pair of these layers is represented by a Figure 4 The dielectric layer is sandwiched by way of the first and second pluralities of layers 420 and 460 shown in FIG. 1 , or the like. The semiconductor package 105 further includes a semiconductor chip 150 mounted on or over an uppermost layer (in this case, the uppermost ground layer 125).

[0041] Figure 1 Also shown in FIG. 1 is that only the ground layer 125 adjacent to the signal layer 135 serves as the current carried by each of the signal layers 135 (by Figure 1 The return path (denoted by the "i" in Figure 1 The "i'" mark in Figure 2B 、 3A This results in additional layers (in this case, 9 non-dielectric layers) compared to the 8 non-dielectric layers shown in 4 or similar.

[0042] Figure 2A and 2B (collectively referred to as “ FIG. 2 ”) are schematic diagrams illustrating side views of various non-limiting examples 200 and 200 ′ of semiconductor packages having a power plane that provides a return current path for high-speed signals according to various embodiments.

[0043] like Figure 2A As shown in the non-limiting example 200 of Figure 1 The semiconductor package 105 of the present invention includes one or more ground layers 225, one or more power layers 230, and one or more signal layers 235. Each of the one or more signal layers 235 is disposed between the nearest power layer in the one or more first power layers 230 and the nearest ground layer in the one or more first ground layers 225 (e.g., in a "G / S / P stack" or "G / S / P arrangement" or the like). Although Figure 2A Not shown in , but each neighboring pair of these layers is represented by a Figure 4 The dielectric layer is sandwiched by way of the first and second pluralities of layers 420 and 460 shown in FIG. 2 or the like. The semiconductor package 205a further includes a semiconductor chip 250 mounted on or over the uppermost layer (in this case, the uppermost ground layer 225).

[0044] Figure 2AIt is also shown that the nearest power layer 230 and the nearest ground layer 225 each provide a return path (indicated by "i" in FIG. 2) for the high frequency signal carried by each signal layer 235. Figure 2A As shown below regarding Figure 4 This enables high frequency (or high speed) signals to be routed between ground and power layers (or planes) instead of only between ground planes (e.g. Figure 1 ), thereby potentially reducing substrate layer count. That is, for an equal number of signal layers, a G / S / P arrangement requires fewer substrate layers than a G / S / G arrangement.

[0045] refer to Figure 2B , semiconductor package 205b is similar (if not identical) to semiconductor package 205a in at least the layers 225 to 235 and their relative order within the layers, and semiconductor chip 250 or the like. In some cases, as in Figure 4 In the first plurality of layers 420 , the ground layer 225 is disposed as the lowermost layer.

[0046] In some approaches, each of the one or more ground layers 225, the one or more power layers 230, and the one or more signal layers 235 (or portions thereof) near the edge of the substrate base or core layer can be anchored (e.g., anchored to the substrate base or core layer, for example) using an anchoring ball 290a (also referred to as "ground ball 290a" or "ground anchor 290a" or the like), an anchoring ball 290b (also referred to as "power ball 290b" or "power anchor 290b" or the like), and an anchoring ball 290c (also referred to as "signal ball 290c" or "signal anchor 290c" or the like), respectively. Figure 4 substrate base or core layer 410 or the like). However, the presence of power balls or anchors in high frequency (or high speed) signals increases crosstalk between high speed signals, which can offset any cost savings of using the power plane as a return path. As used herein, "anchored" or "anchored" may refer to a particular layer (e.g., a power layer, signal layer, or ground layer, etc.) being mechanically coupled to a corresponding anchor or anchor ball using a conductive path passing through an intervening layer between the particular layer and the corresponding anchor or anchor ball, while being electrically isolated (using a dielectric or non-conductive material) between the conductive path and intervening layers of a non-same type (e.g., for a signal layer, the conductive layer is electrically connected to the intervening signal layer, but is electrically isolated from the intervening power and ground layers; and the same is true for the power and ground layers; and so on). Because the conductive path passes through and is part of the substrate core layer, the particular layer is also mechanically "anchored" to the substrate core layer.

[0047] Figure 3A and 3B(collectively referred to as “ FIG. 3 ”) are schematic diagrams illustrating side and top views, respectively, of a non-limiting example 300 of a semiconductor package for implementing a cantilevered power plane to provide a return current path for high-speed signals in accordance with various embodiments.

[0048] like Figure 3A and 3B As shown in the non-limiting example 300 of Figure 4 The semiconductor package 405 includes one or more ground layers 325, one or more power layers 330, and one or more signal layers 335. Each of the one or more signal layers 335 is disposed between the nearest power layer in the one or more first power layers 330 and the nearest ground layer in the one or more first ground layers 325. Figure 3A Not shown in , but each neighboring pair of these layers is represented by a Figure 4 The dielectric layer is sandwiched in the manner of the first and second plurality of layers 420 and 460 shown in FIG. 1 , or the like.

[0049] Semiconductor package 305 further includes a semiconductor chip 350 mounted on or over the uppermost layer (in this case, uppermost ground layer 325 ) and a decoupling capacitor 395 disposed (or mounted) on or over uppermost ground layer 325 and coupling uppermost ground layer 325 and a nearest power layer 330 .

[0050] Different from Figure 2B In the semiconductor package 205b in the non-limiting example 300 of FIG. 3 , the semiconductor package 305 removes all power balls from the high frequency (or high speed) signal field (or does not include the power balls during manufacturing), and includes at least one AC coupler 355 (similar to Figure 4 AC coupler 455 or the like) to anchor the substrate core or substrate base or core layer 310 (e.g. Figure 3A and 3B3 and 4. In some embodiments, the power layer 330 and the ground layer 325 (or portions thereof) are located near the edge of the substrate base or core layer, with none of the power layers (or portions thereof) near the edge of the substrate base or core layer being anchored to the substrate base or core layer (thereby resulting in a "cantilevered" power layer in that the power layer is anchored to the substrate base or core layer 310 proximate a portion of the semiconductor chip 350 (e.g., anchored to a middle portion of the substrate base or core layer 310) but not anchored to the substrate layer 310 near the edge of the substrate layer 310). As used herein, "anchored" or "anchored" may refer to a particular layer (e.g., a signal layer or a ground layer, etc.) being mechanically coupled to a corresponding anchor or anchor ball using a conductive path through an intervening layer between the particular layer and the corresponding anchor or anchor ball, while being electrically isolated (using a dielectric or non-conductive material) between the conductive path and an intervening layer of a different type (e.g., for a signal layer, the conductive layer is electrically connected to the intervening signal layer but is electrically isolated from the intervening power and ground layers; and similarly for the ground layer; etc.). Because the conductive pathway passes through and is part of the substrate core layer, the particular layer is also mechanically "anchored" to the substrate core layer. On the other hand, "unanchored" may refer to a power layer not being mechanically coupled to a power anchor or power ball using a conductive pathway passing through an intervening layer between the power layer and the power anchor or power ball (indeed, in these embodiments, no power anchor or power ball exists). As used herein, "near an edge of a substrate base or core layer" may refer to an area extending from the edge defined by half the distance between the edge of the substrate base or core layer and the nearest edge of a semiconductor chip (or chip mount) mounted on or over the semiconductor substrate. For example, with reference to Figure 3B , "near" the left edge of the substrate core layer may be defined by an area or the like extending from the leftmost edge of layer 345 (which corresponds to the size of substrate core 310) to a portion of layer 345 between AC coupler 355 and decoupling capacitor 395. However, the ground layer 325 and the signal layer 335 (or portions thereof) near the edge of the substrate base or core layer 310 may be anchored (e.g., to the substrate base or core layer 310 or the like) using anchoring balls 390a (also referred to as "ground ball 390a" or "ground anchor 390a" or the like) and anchoring balls 390c (also referred to as "signal ball 390c" or "signal anchor 390c" or the like), respectively, because the ground ball or anchor 390a and the signal ball or anchor 390c do not significantly affect the signals (unlike the power ball, which increases crosstalk between high frequency (or high speed) signals). Similar to Figure 4 The anchoring balls 490 in the embodiment of the present invention can be arranged in a second plurality of layers ( Figure 3A Not shown, but Figure 4 3. Above or below the lowest layer farthest from the substrate base or core layer 310 in FIG. 3.

[0051] In this way, the power layer (or power plane) 330 can be used (along with the ground layer 325) as a return path for high frequency (or high speed) signals carried on the signal layer 335 without significant crosstalk (e.g., due to the presence of power balls (e.g., power balls) anchoring the power layer to the edge of the substrate base or core layer). Figure 2B ) or the like. Thus, cost savings can be achieved (by using fewer layers, etc.) while achieving the desired performance of the semiconductor chip without excessive signal degradation (e.g., crosstalk caused by power balls or the like).

[0052] These and other functions of the example 300 (and its components) are described herein with respect to Figure 4 and 5 are described in more detail.

[0053] Figure 4 is a schematic diagram illustrating a side cross-sectional view of a non-limiting example 400 of a semiconductor package for implementing a cantilevered power plane to provide a return current path for high-speed signals in accordance with various embodiments.

[0054] like Figure 4 As shown in the non-limiting example 400 of , a semiconductor package 405 includes a substrate core layer or substrate base layer 410, one or more vias 415 (including through-hole (“TH”) vias, conductive vias and / or dielectric vias or the like), a first plurality of layers 420 disposed on (the top surface of) the substrate base or core layer 410, and a second plurality of layers 460 disposed on (the bottom surface of) the substrate base or core layer 410.

[0055] In some embodiments, the first plurality of layers 420 include, but are not limited to: one or more first ground layers 425 (e.g., Figure 4 L1, L5 and L8 or the like), which are disposed on or above the substrate base or core layer 410; one or more first power supply layers 430 (e.g. Figure 4 L3 and L7 or the like), which are disposed on or above the substrate base or core layer 410; and one or more first signal layers 435 (e.g. Figure 44, and L6 (or the like) are disposed on or over a substrate base or core layer 410, with each of the one or more first signal layers 435 disposed between a nearest power layer in the one or more first power layers 430 and a nearest ground layer in the one or more first ground layers 425, the nearest power layer 430 and the nearest ground layer 425 each providing a return path for high-frequency signals carried by each signal layer 435. The first plurality of layers 420 further includes, but is not limited to, a plurality of first dielectric layers 440, each of which is disposed between and in contact with a power layer 430 in the one or more first power layers 430, a ground layer 425 in the one or more first ground layers 425, or a signal layer 435 in the one or more first signal layers 435. In some cases, each dielectric layer may include, but is not limited to, one of the following: a single layer having a uniform dielectric material throughout the single layer, a composite dielectric layer comprising multiple layers of different dielectric layers, a composite dielectric layer comprising multiple layers of the same dielectric layer and a conductive layer disposed between pairs of dielectric layers, a composite dielectric layer comprising multiple layers of different dielectric layers and a conductive layer disposed between pairs of dielectric layers, or a composite dielectric layer comprising multiple layers of the same dielectric layer and multiple layers of different dielectric layers and a conductive layer disposed between pairs of (same and / or different) dielectric layers, and / or the like. In some cases, the conductive layers disposed between the dielectric layers may be made of the same or different conductive materials.

[0056] As used herein, a “power layer” may refer to one of the following: (i) a layer having one or more conductive traces that are communicatively coupled, directly or indirectly, to a power source or power supply (e.g., a “composite power layer” or the like), the one or more conductive traces having any suitable shape or size (length, width, thickness, etc.) and separated from other conductive traces by dielectric or non-conductive material or the like; or (ii) a layer (e.g., a “power plane” or the like) comprising conductive material and dielectric or non-conductive material throughout, the dielectric or non-conductive material being in the form of non-conductive traces that separate areas of adjacent conductive areas that are communicatively coupled to different power supply sources (e.g., for supplying different voltage and / or current requirements to components, etc.) and / or separate areas around pathways connecting components / conductive traces on layers other than the (power) layer; and / or the like. Similarly, a “signal layer” may refer to one of the following: (1) a layer having one or more conductive traces that are communicatively coupled directly or indirectly to a signal source or repeater (e.g., a “composite signal layer” or the like), the one or more conductive traces having any suitable shape or size (length, width, thickness, etc.) and separated from other conductive traces by dielectric or non-conductive material or the like; or (2) a layer (e.g., a “signal plane” or the like) comprising conductive material and dielectric or non-conductive material throughout, the dielectric or non-conductive material being in the form of non-conductive traces that separate areas of adjacent conductive areas that are communicatively coupled to different signal sources or repeaters and / or separate areas around pathways connecting components / conductive traces on layers other than the (signal) layer; and / or the like. Similarly, a "ground layer" may refer to one of the following: (a) a layer having one or more conductive traces that are directly or indirectly communicatively coupled to circuit ground (e.g., a "composite ground layer" or the like), the one or more conductive traces having any suitable shape or size (length, width, thickness, etc.) and separated from other conductive traces by a dielectric or non-conductive material or the like; or (b) a layer (e.g., a "ground plane" or the like) including conductive material and dielectric or non-conductive material throughout, the dielectric or non-conductive material being in the form of non-conductive traces that separate areas around vias connecting components / conductive traces on layers other than the (ground) layer; and / or the like. In some embodiments, the conductive traces (or non-conductive traces) need not be straight lines. For example, the conductive traces or non-conductive traces may each include, but are not limited to, one or more traces that are each at least one of the following: straight lines, curved lines, patterned lines, zigzag lines, meandering lines, thick lines, thin lines, or combinations thereof. In some cases, conductive traces (or non-conductive traces) on a layer do not need to be vertically aligned with similar lines on other layers.

[0057] According to some embodiments, the first plurality of layers 420 includes, but is not limited to: a first ground layer (e.g., Figure 4L8 or the like in ), which is disposed on or above the substrate base or core layer 410; a first dielectric layer in one or more first dielectric layers 440, which is on the first ground layer 425; a first power layer in one or more first power layers 430 (e.g. Figure 4 L7 or the like in ), which is disposed on the first dielectric layer 440; a second dielectric layer in one or more first dielectric layers 440, which is on the first power layer 430; a first signal layer in one or more first signal layers 435 (e.g. Figure 4 L6 or the like in the one or more first dielectric layers 440 ), which is disposed on the second dielectric layer 440 ; a third dielectric layer in the one or more first dielectric layers 440 , which is on the first signal layer 435 ; a second ground layer in the one or more first ground layers 425 (e.g. Figure 4 L5 or the like in ), which is disposed on the third dielectric layer 440; a fourth dielectric layer in the one or more first dielectric layers 440, which is on the second ground layer 425; a second signal layer in the one or more first signal layers 435 (e.g. Figure 4 L4 or the like in the one or more first dielectric layers 440 ), which is disposed on the fourth dielectric layer 440 ; a fifth dielectric layer in the one or more first dielectric layers 440 , which is on the second signal layer 435 ; a second power layer in the one or more first power layers 430 (e.g. Figure 4 L3 or the like in the one or more first dielectric layers 440 ), which is disposed on the fifth dielectric layer 440 ; a sixth dielectric layer in the one or more first dielectric layers 440 , which is on the second power layer 430 ; a third signal layer in the one or more first signal layers 435 (e.g. Figure 4 L2 or the like in the one or more first dielectric layers 440), which is disposed on the sixth dielectric layer 440; a seventh dielectric layer in the one or more first dielectric layers 440, which is on the third signal layer 435; and a third ground layer in the one or more first ground layers 425 (e.g., Figure 4 L1 or the like in ), which is disposed on the seventh dielectric layer 440.

[0058] Because the impedance between the power supply and the ground layer (or plane) is determined by , where ω represents frequency and C represents capacitance. Therefore, at high frequencies (e.g., kHz, MHz, etc.), the impedance approaches zero, thereby providing a return path along the ground and power layers for high-frequency signals carried by the signal layers. Therefore, as used herein, "high-frequency signals" may refer to signals having a frequency of 1 kHz or greater. In some examples, the nearest power layer and the nearest ground layer to each signal layer each provide a return path for the high-frequency signals carried by each signal layer based on magnetic induction. For example, the first power layer 430 (L7) and the second ground layer 425 (L5) each provide a return path for the high-frequency signals carried by the first signal layer 435 (L6). Similarly, the second ground layer 425 (L5) and the second power layer 430 (L3) each provide a return path for the high-frequency signals carried by the second signal layer 435 (L4). Similarly, the second power layer 430 (L3) and the third ground layer 425 (L1) each provide a return path for the high-frequency signals carried by the third signal layer 435 (L2). This enables high frequency (or high speed) signals to be routed between ground and power layers (or planes) rather than just between ground planes, thereby potentially reducing substrate layer count.

[0059] In some examples, although not shown, the first plurality of layers 420 further includes additional signal, power, ground, and / or dielectric layers, wherein each additional signal layer is disposed between an additional power layer on one side and an additional ground layer on the other side, wherein a dielectric layer is disposed between each of two adjacent ones of the signal, power, or ground layers. The adjacent power and ground layers disposed on either side of the signal layer each provide a return path for the high-frequency signals carried by the signal layer in the manner described above. Alternatively, also not shown, the first plurality of layers may include fewer layers while maintaining the G / S / P arrangement.

[0060] In some embodiments, the first plurality of layers 420 further includes a solder resist layer 445 as the uppermost layer among the other layers in the first plurality of layers 420. In some cases, the semiconductor package 405 further includes, but is not limited to: a semiconductor chip or die 450 of a chip mounted on or over the uppermost layer of the first plurality of layers (in this case, the solder resist layer 445 or the like); at least one decoupling capacitor ( Figure 44 , wherein the at least one decoupling capacitor is coupled to the uppermost power layer (e.g., but not limited to, L3 or the like) of the one or more first power layers 430 and the ground layer (e.g., but not limited to, L1 or the like) of the one or more first ground layers 425, and the at least one decoupling capacitor is configured to reduce or prevent rapid power supply fluctuations, thereby maintaining the power integrity of any power supplied to the semiconductor chip via the at least one power layer (e.g., by absorbing energy from the power supply, whether steady or fluctuating (including low amplitude fluctuations, high amplitude fluctuations, low frequency fluctuations, high frequency fluctuations, etc.) via the at least one power layer and then discharging it at a (stable) predetermined rate), and the like.

[0061] In some cases, at least one AC coupler 455 is coupled to at least one of the one or more first power layers and each of at least one of the one or more first ground layers, with any portion of any of the one or more first power layers not anchored to the substrate base or core layer near (or within a first distance from) an edge of the substrate base or core layer (thereby resulting in a "cantilevered" power layer in that the power layer is anchored to the substrate base or core layer 410 proximate to a portion of the semiconductor chip or die 450 (e.g., anchored to a middle portion of the substrate base or core layer 410) but not anchored to the substrate layer 410 near an edge of the substrate layer 410), the first distance being defined by half the distance between the edge of the core layer and the nearest edge of one of the semiconductor chip or a mount for the chip mounted on or above the semiconductor substrate. In some embodiments, each of the at least one AC coupler 455 is configured to reduce noise signals carried by each of the at least one first power layers to which it is coupled. In some examples, at least one AC coupler 455 is disposed on or above first plurality of layers 420. In some cases, at least one AC coupler 455 each includes, but is not limited to, one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more dielectric materials, or one or more structures with dielectric substructures, and / or the like. Alternatively or in addition, at least a portion of at least one AC coupler 455 is disposed within first plurality of layers 420 ( Figure 4 (not shown in FIG. 4 ). In some cases, at least a portion of at least one AC coupler 455 each includes, but is not limited to, one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more vias, one or more dielectric materials, or one or more structures with dielectric substructures, and / or the like.

[0062] In some examples, the second plurality of layers 460 include, but are not limited to: one or more second ground layers 465 (e.g., Figure 4 L9, L12 and L16 or the like in FIG), which are disposed on or below the substrate base or core layer 410; one or more second power layers 470 (eg Figure 4 L10 and L14 or the like in FIG), which are disposed on or below the substrate base or core layer 410; one or more second signal layers 475 (eg Figure 4 L11, L13 and L15 or the like in (or similar thereto), which are disposed on or below the substrate base or core layer 410, each of the one or more second signal layers 475 is disposed between the nearest power layer in the one or more second power layers 470 and the nearest ground layer in the one or more second ground layers 465, the nearest power layer 470 and the nearest ground layer 465 each providing a return path for the high-frequency signal carried by each signal layer 475; a plurality of second dielectric layers 480, each dielectric layer 480 being disposed between and in contact with two of the power layers in the one or more second power layers 470, the ground layers in the one or more second ground layers 465 or the signal layers in the one or more second signal layers 475; and a solder resist layer 485, which is the lowest layer farthest from the substrate base or core layer 410 among the other layers in the second plurality of layers 460. According to some embodiments, the first plurality of layers 420 and the second plurality of layers 460 may each include, but are not limited to, any suitable or appropriate number of layers or pairs of layers in direct contact with adjacent layers, and / or the like, with any suitable or appropriate number of intervening layers (including, but not limited to, one or more dielectric layers, one or more power layers, one or more signal layers, or one or more other layers, and / or the like). Similarly, in some cases, the first plurality of layers 420 and the second plurality of layers 460 may each directly contact the substrate base or core layer 410, while in other cases, one or more intervening layers may be included between the substrate base or core layer 410 and each of the first plurality of layers 420 and the second plurality of layers 460.

[0063] In some embodiments, semiconductor package 405 further includes, but is not limited to, one or more anchors, solder balls, or anchoring balls 490, including at least one of one or more signal balls and one or more ground balls. Although described as signal / ground anchors or balls, these anchors may be embodied by any suitable shape of solder that has solidified over corresponding vias or the like, where its shape may be dictated by surrounding features or components of the area where the solder is applied until solidified. In some cases, at least one signal ball or anchor is disposed on or below the lowest layer 485 of the second plurality of layers 460, which is farthest from the substrate base or core layer 410, and at least one ground ball or anchor is disposed on or below the lowest layer 485 of the second plurality of layers 460. In some examples, at least one signal ball or anchor is near the edge of the substrate base or core layer 410 and is connected to one or more first signal layers 435 of the first plurality of layers 420 and one or more second signal layers 475 (or portions thereof) of the second plurality of layers 460 through the substrate base or core layer 410, thereby anchoring one or more signal layers 435 of the first plurality of layers 420 and one or more second signal layers 475 (or portions thereof) of the second plurality of layers 420 near the edge of the substrate base or core layer 410 to the substrate base or core layer 410. In some examples, at least one ground ball or anchor is near an edge of the substrate base or core layer 410 and is connected to one or more ground layers 425 of the first plurality of layers 420 and one or more second ground layers 465 of the second plurality of layers 460 (or portions thereof) through the substrate base or core layer 410, thereby anchoring the one or more ground layers 425 of the first plurality of layers 420 and the one or more second ground layers 465 of the second plurality of layers 460 (or portions thereof) near the edge of the substrate base or core layer 410 to the substrate base or core layer 410.

[0064] In some examples, at least one AC coupler 455 is coupled to two or more of at least one of the one or more first power layers 430, at least one of the one or more first ground layers 425, at least one of the one or more second power layers 470, or at least one of the one or more second ground layers 465, with any portion of any of the one or more first power layers 430 and the one or more second power layers 470 near an edge of the substrate base or core layer 410 not anchored to the substrate base or core layer 410. In some cases, the ground layer in the one or more first ground layers 425 is at least one of the topmost layer in the first plurality of layers 420 and the bottommost layer in the first plurality of layers 420 (excluding solder resist 445). Similarly, the ground layer in the one or more second ground layers 465 is at least one of the topmost layer in the second plurality of layers 460 and the bottommost layer in the second plurality of layers 460 (excluding solder resist 485).

[0065] These and other functions of system 400 (and its components) are described in more detail with respect to Figures 2, 3, and 5.

[0066] Figures 5A to 5E (collectively referred to as “ FIG. 5 ”) is a flow chart illustrating a method 500 for implementing a cantilevered power plane to provide a return current path for high-speed signals, according to various embodiments. Figure 5A The method 500 follows the circular markers labeled "A" or "C" to continue to Figure 5B and follow the circular sign marked "B" back to Figure 5A . Figure 5A Method 500 follows the circle marked "D" and continues to Figure 5C . Figure 5D Method 500 follows the circular marker labeled "E" and continues to Figure 5E .

[0067] Although the techniques and procedures are depicted and / or described in a particular order for illustrative purposes, it should be understood that certain procedures may be reordered and / or omitted within the scope of various embodiments. Figure 2A 、 2B , 3 and 4 are implemented (and in some cases described below with respect to) the respective systems, examples or embodiments 200, 200', 300 and 400 of FIG. , 3 and 4, such methods may also be implemented using any suitable hardware (or software) implementation. Similarly, although Figure 2A 、 2B Each of the respective systems, examples, or embodiments 200, 200', 300, and 400 of FIG. 3 and FIG. 4 (or components thereof) may operate according to the method 500 illustrated by FIG. 5 (e.g., by executing instructions embodied on a computer-readable medium), but Figure 2A 、 2B , 3 and 4, the systems, examples or embodiments 200, 200', 300 and 400 can each also operate according to other operating modes and / or perform other suitable procedures.

[0068] exist Figure 5A In a non-limiting embodiment, method 500 includes forming a first plurality of layers disposed on or above (a top surface of) a core layer of a semiconductor substrate at block 505. According to some embodiments, method 500 further includes forming a second plurality of layers disposed on or below (a bottom surface of) the core layer at optional block 510.

[0069] Method 500 continues to process at block 515 or by following the circle labeled "A" to Figure 5B The process at box 520 in .

[0070] At box 515, method 500 includes mounting at least one alternating current (“AC”) coupler on or over the first plurality of layers and coupling the at least one AC coupler to each of at least one of the one or more first power layers and at least one of the one or more first ground layers, with any portion of any of the one or more first power layers within a first distance from an edge of the core layer (e.g., near the edge of the core layer) not anchored to the core layer, the first distance being half the distance between the edge of the core layer and a nearest edge of a semiconductor chip or one of a mounting for the chip mounted on or over the semiconductor substrate.

[0071] In some embodiments, each of the at least one AC coupler is configured to reduce noise signals carried by each of the at least one power layer to which it is coupled. In some examples, each of the at least one AC coupler comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more dielectric materials, or one or more structures having a dielectric substructure, and / or the like. Alternatively or additionally, at least a portion of the at least one AC coupler is disposed within the first plurality of layers. In some cases, each of the at least one AC coupler comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more vias, one or more dielectric materials, or one or more structures having a dielectric substructure, and / or the like.

[0072] Method 500 continues to the circular marker marked with "C" Figure 5B The process at box 520 in .

[0073] In some embodiments, forming the first plurality of layers (at block 505) includes: forming a first ground layer of the one or more first ground layers on the core layer (block 505a); forming a first dielectric layer of the one or more first dielectric layers on the first ground layer (block 505b); forming a first power layer of the one or more first power layers on the first dielectric layer (block 505c); forming a second dielectric layer of the one or more first dielectric layers on the first power layer (block 505d); forming a first signal layer of the one or more first signal layers on the second dielectric layer (block 505e); forming a third dielectric layer of the one or more first dielectric layers on the first signal layer (block 505f); and forming a second ground layer of the one or more first ground layers on the third dielectric layer (block 505g). In some cases, the first power layer and the second ground layer each provide a return path for high-frequency signals (e.g., signals having a frequency of 1 kHz or greater) carried by the first signal layer.

[0074] According to some embodiments, at least one AC coupler is coupled to two or more of at least one of the one or more first power layers, at least one of the one or more first ground layers, at least one of the one or more second power layers, or at least one of the one or more second ground layers, and any portion of any of the one or more first power layers and the one or more second power layers near an edge of the core layer (e.g., within a first distance from the edge) is not anchored to the core layer.

[0075] Method 500 continues to the circular marker marked "D". Figure 5C The process at box 505h in.

[0076] exist Figure 5B At block 520 (following the circular markers labeled "A" or "C") in method 500, the method includes mounting a semiconductor chip on or above an uppermost layer of the first plurality of layers. The method 500 further includes mounting at block 525 at least one decoupling capacitor on or above an uppermost layer of the first plurality of layers proximate to the semiconductor chip, the at least one decoupling capacitor coupled to an uppermost power layer of the one or more first power layers and a ground layer of the one or more first ground layers, the at least one decoupling capacitor configured to reduce or prevent rapid power supply fluctuations, thereby maintaining power integrity of any power supplied to the semiconductor chip via the at least one power layer. If the at least one AC coupler has not been installed (at block 515), the method 500 returns to the method following the circular marker labeled "B." Figure 5A Otherwise, the method 500 continues to the process at block 530.

[0077] At block 530, method 500 includes forming one or more anchor vias for each of the signal and ground layers. In some cases, forming the one or more anchor vias for each of the signal and ground layers (at block 530) includes one of: forming a hole through all interposers in the first and second pluralities of layers and filling the hole with a conductive material (block 530a), wherein at least one signal anchor or at least one ground anchor, respectively, is formed in contact with the conductive material; or forming a hole through each interposer in the first and second pluralities of layers and filling the hole with a conductive material after each interposer is formed and before the next interposer is formed, and repeating the hole formation and hole filling until all at least one anchor vias are formed in all interposers (block 530b), wherein at least one signal anchor or at least one ground anchor, respectively, is formed in contact with the conductive material; and / or the like.

[0078] Method 500 further includes forming at least one first solder anchor as at least one signal anchor on or below the bottom surface of the core layer or one of the lowest layers of the second plurality of layers (or above when the semiconductor package is rotated with the bottom surface facing up) in box 535 and connecting the at least one signal anchor to the corresponding at least one signal anchor path, thereby mechanically (and electrically) connecting the at least one signal anchor to one or more signal layers of the first plurality of layers and one or more second signal layers of the second plurality of layers near the edge of the core layer and through the core layer (via the corresponding at least one signal anchor path), thereby anchoring the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer (for example, within a first distance from the edge) to the core layer.

[0079] At block 540, method 500 includes forming at least one second solder anchor as at least one ground anchor on or below a bottom surface of the core layer or one of the lowest layers in the second plurality of layers (or above when the semiconductor package is rotated with the bottom surface facing up) and connecting the at least one ground anchor to a corresponding at least one ground anchor via, thereby mechanically (and electrically) connecting the at least one ground anchor to one or more ground layers of the first plurality of layers and one or more second ground layers of the second plurality of layers near an edge of the core layer and through the core layer (via the corresponding at least one ground anchor via), thereby anchoring the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near an edge of the core layer (e.g., within a first distance from the edge) to the core layer.

[0080] exist Figure 5C At block 505h in (following the circular label marked “D”), method 500 may include: forming a fourth dielectric layer of the one or more first dielectric layers on the second ground layer; forming a second signal layer of the one or more first signal layers on the fourth dielectric layer (block 505i); forming a fifth dielectric layer of the one or more first dielectric layers on the second signal layer (block 505j); forming a second power layer of the one or more first power layers on the fifth dielectric layer (block 505k); forming a sixth dielectric layer of the one or more first dielectric layers on the second power layer (block 505l); forming a third signal layer of the one or more first signal layers on the sixth dielectric layer (block 505m); forming a seventh dielectric layer of the one or more first dielectric layers on the third signal layer (block 505n); and forming a third ground layer of the one or more first ground layers on the seventh dielectric layer (block 505o). In some examples, the second ground layer and the second power layer each provide a return path for high-frequency signals (e.g., signals having a frequency of 1 kHz or greater) carried by the second signal layer. In some cases, the second power layer and the third ground layer each provide a return path for high-frequency signals (e.g., signals having a frequency of 1 kHz or greater) carried by the third signal layer.

[0081] In some embodiments, forming the first plurality of layers (at block 505) further includes forming additional signal, power, ground, and / or dielectric layers (optional block 505p), wherein each additional signal layer is disposed between an additional power layer on one side and an additional ground layer on the other side, wherein each dielectric layer is disposed between each of two adjacent ones of the signal, power, or ground layers. The adjacent power and ground layers disposed on either side of a signal layer each provide a return path for high-frequency signals carried by the signal layer.

[0082] According to some embodiments, forming the first plurality of layers (at block 505 ) further includes forming a solder resist layer as an uppermost layer among other layers in the first plurality of layers (block 505 q ).

[0083] refer to Figure 5D Forming a second plurality of layers disposed above or below the core layer (at optional block 510) includes: rotating the semiconductor package so that the bottom surface of the core layer faces upward (block 510a); forming a first ground layer of the one or more second ground layers on the bottom surface of the core layer (block 510b); forming a first dielectric layer of the one or more second dielectric layers on the first ground layer (block 510c); forming a first power layer of the one or more second power layers on the first dielectric layer (block 510d); forming a second dielectric layer of the one or more second dielectric layers on the first power layer (block 510e); forming a first signal layer of the one or more second signal layers on the second dielectric layer (block 510f); forming a third dielectric layer of the one or more second dielectric layers on the first signal layer (block 510g); and forming a second ground layer of the one or more second ground layers on the third dielectric layer (block 510h). In some cases, the first power layer and the second ground layer each provide a return path for a high-frequency signal carried by the first signal layer.

[0084] Method 500 continues to the circular mark marked with "E" Figure 5E The process at box 510i in.

[0085] exist Figure 5EAt block 510i in the method 500 (following the circular label labeled "E"), the method 500 may include: forming a fourth dielectric layer of the one or more second dielectric layers on the second ground layer; forming a second signal layer of the one or more second signal layers on the fourth dielectric layer (block 510j); forming a fifth dielectric layer of the one or more second dielectric layers on the second signal layer (block 510k); forming a second power layer of the one or more second power layers on the fifth dielectric layer (block 510l); forming a sixth dielectric layer of the one or more second dielectric layers on the second power layer (block 510m); forming a third signal layer of the one or more second signal layers on the sixth dielectric layer (block 510n); forming a seventh dielectric layer of the one or more second dielectric layers on the third signal layer (block 510o); and forming a third ground layer of the one or more second ground layers on the seventh dielectric layer (block 510p). In some examples, the second ground layer and the second power layer each provide a return path for high-frequency signals carried by the second signal layer. In some cases, the second power layer and the third ground layer each provide a return path for the high frequency signal carried by the third signal layer.

[0086] In some embodiments, forming the first plurality of layers (at block 510) further includes forming additional signal, power, ground, and / or dielectric layers (optional block 510q), wherein each additional signal layer is disposed between an additional power layer on one side and an additional ground layer on the other side, wherein each dielectric layer is disposed between each of two adjacent ones of the signal, power, or ground layers. The adjacent power and ground layers disposed on either side of a signal layer each provide a return path for high-frequency signals carried by the signal layer.

[0087] According to some embodiments, forming the first plurality of layers (in box 510) further includes: when the semiconductor package is rotated so that the first plurality of layers are facing upward and the second plurality of layers are facing downward, forming a solder resist layer as the lowest layer farthest from the core layer among the other layers in the second plurality of layers (box 510r).

[0088] Although specific features and aspects have been described with respect to some embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, software components, and / or any combination thereof. Furthermore, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented on any suitable hardware, firmware, and / or software configuration. Similarly, although specific functionality is attributed to a specific system component, unless the context indicates otherwise, this functionality need not be limited thereto, but may be distributed among various other system components according to several embodiments.

[0089] Furthermore, although the procedures of the methods and processes described herein are described in a particular order for ease of description, unless the context indicates otherwise, various procedures may be reordered, added, and / or omitted according to various embodiments. Furthermore, procedures described with respect to one method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized in alternative structural architectures and / or incorporated into other described systems. Thus, although various embodiments are described with or without particular features for ease of description and to illustrate some aspects of the various embodiments, unless the context indicates otherwise, various components and / or features described herein with respect to a particular embodiment may be substituted, added, and / or subtracted from other described embodiments. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A semiconductor package comprising: A semiconductor substrate comprising: core layer; a first plurality of layers disposed on or over the core layer, the first plurality of layers comprising: One or more first power supply layers disposed on or above the core layer; one or more first ground layers disposed on or above the core layer; one or more first signal layers disposed on or over the core layer, each of the one or more first signal layers being disposed between a nearest power layer among the one or more first power layers and a nearest ground layer among the one or more first ground layers, the nearest power layer and the nearest ground layer each providing a return path for a high-frequency signal carried by each signal layer; and a plurality of first dielectric layers, each dielectric layer disposed between and in contact with two of the one or more first power layers, the one or more first ground layers, or the one or more first signal layers; and At least one alternating current (AC) coupler coupled to at least one of the one or more first power layers and each of at least one of the one or more first ground layers, any portion of any of the one or more first power layers being not anchored to the core layer within a first distance from an edge of the core layer, the first distance being half the distance between the edge of the core layer and a nearest edge of a semiconductor chip or one of a mounting for the chip mounted on or over the semiconductor substrate. 2 . The semiconductor package of claim 1 , wherein each of the at least one AC coupler is configured to reduce noise signals carried by each of the at least one first power plane to which it is coupled.

3. The semiconductor package of claim 1 , wherein the at least one AC coupler is disposed on or over the first plurality of layers, wherein the at least one AC coupler each comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more dielectric materials, or one or more structures having a dielectric substructure.

4. The semiconductor package of claim 1 , wherein at least a portion of the at least one AC coupler is disposed within the first plurality of layers, wherein the at least a portion of the at least one AC coupler each comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more vias, one or more dielectric materials, or one or more structures having a dielectric substructure. 5 . The semiconductor package of claim 1 , wherein the nearest power layer and the nearest ground layer to each signal layer each provide a return path for high frequency signals carried by the each signal layer based on magnetic induction.

6. The semiconductor package according to claim 1 , wherein the first plurality of layers further comprises a solder resist layer as an uppermost layer among the other layers in the first plurality of layers, wherein the semiconductor package further comprises: the semiconductor chip mounted on or above the uppermost layer of the first plurality of layers; and At least one decoupling capacitor is mounted on or above the uppermost layer of the first plurality of layers in proximity to the semiconductor chip, the at least one decoupling capacitor being coupled to an uppermost power layer of the one or more first power layers and a ground layer of the one or more first ground layers, the at least one decoupling capacitor being configured to reduce or prevent rapid power supply fluctuations.

7. The semiconductor package of claim 1 , wherein the core layer comprises a top surface and a bottom surface, wherein the first plurality of layers are disposed on or over the top surface of the core layer, wherein the semiconductor package further comprises: a second plurality of layers disposed on or below the bottom surface of the core layer, the second plurality of layers comprising: one or more second power supply layers disposed on or below the core layer; one or more second ground layers disposed on or below the core layer; one or more second signal layers disposed on or below the core layer, each of the one or more second signal layers being disposed between a nearest power layer among the one or more second power layers and a nearest ground layer among the one or more second ground layers, the nearest power layer and the nearest ground layer each providing a return path for a high-frequency signal carried by each signal layer; and a plurality of second dielectric layers, each dielectric layer disposed between and in contact with two of the one or more second power layers, the one or more second ground layers, or the one or more second signal layers; and at least one signal anchor disposed on or below a lowest layer of the second plurality of layers that is farthest from the core layer, the at least one signal anchor being connected to the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer and through the core layer, thereby anchoring the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer to the core layer; and and at least one ground anchor disposed on or below the lowest layer of the second plurality of layers, the at least one ground anchor connected to the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer and through the core layer, thereby anchoring the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer to the core layer.

8. The semiconductor package of claim 7 , wherein the at least one AC coupler is coupled to two or more of the at least one of the one or more first power layers, the at least one of the one or more first ground layers, the at least one of the one or more second power layers, or the at least one of the one or more second ground layers, and any portion of any of the one or more first power layers and the one or more second power layers near the edge of the core layer is not anchored to the core layer.

9. The semiconductor package according to claim 7 , wherein a ground layer in the one or more first ground layers is at least one of the uppermost layer in the first plurality of layers and the lowermost layer in the first plurality of layers, and wherein a ground layer in the one or more second ground layers is at least one of the uppermost layer in the second plurality of layers and the lowermost layer in the second plurality of layers.

10. The semiconductor package of claim 1, wherein the first plurality of layers comprises: a first ground layer of the one or more first ground layers, disposed on or above the core layer; a first dielectric layer of the one or more first dielectric layers, which is on the first ground layer; a first power layer of the one or more first power layers, disposed on the first dielectric layer; a second dielectric layer among the one or more first dielectric layers, which is on the first power layer; a first signal layer of the one or more first signal layers, disposed on the second dielectric layer; a third dielectric layer among the one or more first dielectric layers, which is on the first signal layer; a second ground layer of the one or more first ground layers, disposed on the third dielectric layer; a fourth dielectric layer among the one or more first dielectric layers, which is on the second ground layer; a second signal layer of the one or more first signal layers, disposed on the fourth dielectric layer; a fifth dielectric layer among the one or more first dielectric layers, which is on the second signal layer; a second power layer of the one or more first power layers, disposed on the fifth dielectric layer; a sixth dielectric layer among the one or more first dielectric layers, which is on the second power layer; a third signal layer of the one or more first signal layers, disposed on the sixth dielectric layer; a seventh dielectric layer among the one or more first dielectric layers, which is on the third signal layer; and a third ground layer of the one or more first ground layers, disposed on the seventh dielectric layer; The first power layer and the second ground layer each provide a return path for the high-frequency signal carried by the first signal layer, the second ground layer and the second power layer each provide a return path for the high-frequency signal carried by the second signal layer, and the second power layer and the third ground layer each provide a return path for the high-frequency signal carried by the third signal layer.

11. A method for forming a semiconductor device, comprising: forming a first plurality of layers disposed on or over a core layer of a semiconductor substrate, comprising: forming a first ground layer of one or more first ground layers on the core layer; forming a first dielectric layer of the one or more first dielectric layers on the first ground layer; forming a first power layer of the one or more first power layers on the first dielectric layer; forming a second dielectric layer of the one or more first dielectric layers on the first power layer; forming a first signal layer of the one or more first signal layers on the second dielectric layer; forming a third dielectric layer of the one or more first dielectric layers on the first signal layer; and forming a second ground layer of the one or more first ground layers on the third dielectric layer, wherein the first power layer and the second ground layer each provide a return path for a high frequency signal carried by the first signal layer; and At least one alternating current (AC) coupler is mounted on or over the first plurality of layers and coupled to each of at least one of the one or more first power layers and at least one of the one or more first ground layers, with no portion of any of the one or more first power layers being anchored to the core layer within a first distance from an edge of the core layer, the first distance being half the distance between the edge of the core layer and a nearest edge of a semiconductor chip or one of a mounting for the chip mounted on or over the semiconductor substrate.

12. The method of claim 11, wherein each of the at least one AC coupler is configured to reduce noise signals carried by each of the at least one power plane to which it is coupled.

13. The method of claim 11, wherein the at least one AC coupler each comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more dielectric materials, or one or more structures having a dielectric substructure.

14. The method of claim 11 , wherein at least a portion of the at least one AC coupler is disposed within the first plurality of layers, wherein the at least a portion of the at least one AC coupler each comprises one of one or more capacitors, one or more inductors, one or more metal traces, one or more small gaps, one or more vias, one or more dielectric materials, or one or more structures having a dielectric substructure.

15. The method of claim 11, further comprising: forming a solder resist layer as an uppermost layer among other layers in the first plurality of layers; mounting the semiconductor chip on or over the uppermost layer of the first plurality of layers; and At least one decoupling capacitor is mounted on or above the uppermost layer of the first plurality of layers proximate to the semiconductor chip, the at least one decoupling capacitor being coupled to an uppermost power layer of the one or more first power layers and a ground layer of the one or more first ground layers, the at least one decoupling capacitor being configured to reduce or prevent rapid power supply fluctuations.

16. The method of claim 11, wherein forming the first plurality of layers further comprises: forming a fourth dielectric layer among the one or more first dielectric layers on the second ground layer; forming a second signal layer among the one or more first signal layers on the fourth dielectric layer; forming a fifth dielectric layer of the one or more first dielectric layers on the second signal layer; forming a second power layer of the one or more first power layers on the fifth dielectric layer; forming a sixth dielectric layer of the one or more first dielectric layers on the second power supply layer; forming a third signal layer among the one or more first signal layers on the sixth dielectric layer; forming a seventh dielectric layer among the one or more first dielectric layers on the third signal layer; and forming a third ground layer among the one or more first ground layers on the seventh dielectric layer; The second ground layer and the second power layer each provide a return path for the high-frequency signal carried by the second signal layer, and the second power layer and the third ground layer each provide a return path for the high-frequency signal carried by the third signal layer.

17. The method of claim 11, wherein the core layer comprises a top surface and a bottom surface, wherein the first plurality of layers are disposed on or over the top surface of the core layer, wherein the method further comprises: forming a second plurality of layers disposed on or below the core layer, comprising: rotating the semiconductor package so that the bottom surface of the core layer faces upward; forming a first ground layer among one or more second ground layers on or above the bottom surface of the core layer; forming a first dielectric layer of the one or more second dielectric layers on the first ground layer; forming a first power layer of the one or more second power layers on the first dielectric layer; forming a second dielectric layer of the one or more second dielectric layers on the first power layer; forming a first signal layer of the one or more second signal layers on the second dielectric layer; forming a third dielectric layer of the one or more second dielectric layers on the first signal layer; and A second ground layer of the one or more second ground layers is formed on the third dielectric layer, wherein the first power layer and the second ground layer each provide a return path for a high frequency signal carried by the first signal layer.

18. A method according to claim 17, wherein the at least one AC coupler is coupled to two or more of the at least one power layer among the one or more first power layers, the at least one ground layer among the one or more first ground layers, at least one power layer among the one or more second power layers, or at least one ground layer among the one or more second ground layers, and any portion of any of the one or more first power layers and the one or more second power layers near the edge of the core layer is not anchored to the core layer.

19. The method of claim 17, further comprising: forming a solder resist layer as a lowermost layer farthest from the core layer among other layers in the second plurality of layers when the semiconductor package is rotated so that the first plurality of layers face upward and the second plurality of layers face downward; forming at least one first solder anchor as at least one signal anchor on or over the lowest layer of the second plurality of layers, the at least one signal anchor connected to the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer and through the core layer using a corresponding at least one anchor via, thereby anchoring the one or more signal layers of the first plurality of layers and the one or more second signal layers of the second plurality of layers near the edge of the core layer to the core layer; At least one second solder anchor is formed on or over the lowest layer of the second plurality of layers as at least one ground anchor, the at least one ground anchor being connected to the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer and through the core layer using a corresponding at least one anchor via, thereby anchoring the one or more ground layers of the first plurality of layers and the one or more second ground layers of the second plurality of layers near the edge of the core layer to the core layer.

20. The method of claim 19, wherein each of the at least one anchor passage is formed by a process comprising one of: forming holes through all interposers in the first and second pluralities of layers and filling the holes with a conductive material, wherein the at least one signal anchor or the at least one ground anchor, respectively, is formed in contact with the conductive material; or A hole is formed through each interposer in the first and second pluralities of layers and filled with a conductive material after each interposer is formed and before the next interposer is formed, and the hole formation and hole filling are repeated until all of the at least one anchor vias are formed in all of the interposers, wherein the at least one signal anchor or the at least one ground anchor, respectively, is formed in contact with the conductive material.

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