Surface treatment method of semiconductor structure

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a surface planarization method of a semiconductor structure, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a spin-on hard mask layer formed on the substrate; using a grinding liquid to perform primary grinding on a surface of the spin-on hard mask layer by using a first grinding pad; and performing secondary grinding on the surface of the spin-on hard mask layer by using a second grinding pad, wherein the hardness of the first grinding pad is greater than the hardness of the second grinding pad. The surface planarization method can reduce the probability of defects on the surface of the substrate and improve product yield.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a surface treatment method of semiconductor structure. BACKGROUND

[0002] In the process of semiconductor manufacturing, it is usually necessary to pattern a thin film to form a pattern required by a semiconductor device. In this process, a mask layer needs to be formed on the surface of a wafer to complete the pattern transfer. However, due to the limitation of the process, the surface of the spin-on mask layer is prone to have height difference, and in the subsequent etching process, the area with lower thickness in the mask layer is prone to be etched through completely, thereby damaging the wafer surface below and causing wafer defects, resulting in lower product yield.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a surface planarization method of semiconductor structure, which can reduce the probability of forming defects on the surface of the substrate and improve the product yield.

[0005] According to one aspect of the present disclosure, a surface planarization method of semiconductor structure is provided, comprising:

[0006] providing a semiconductor structure, the semiconductor structure comprising a substrate and a spin-on hard mask layer formed on the substrate;

[0007] using a polishing liquid to preliminarily polish the surface of the spin-on hard mask layer with a first polishing pad;

[0008] polishing the surface of the spin-on hard mask layer with a second polishing pad, the hardness of the first polishing pad being greater than the hardness of the second polishing pad.

[0009] In an exemplary embodiment of the present disclosure, the material of the spin-on hard mask layer is a material formed by polymerization of organic cyclic carbon compounds.

[0010] In an exemplary embodiment of the present disclosure, the polishing liquid is an acidic polishing liquid, and the pH value of the acidic polishing liquid is 4.5-6.2.

[0011] In an exemplary embodiment of the present disclosure, the polishing liquid is obtained by diluting a basic polishing liquid with deionized water, and the mass ratio of the basic polishing liquid to the deionized water is 1:6-1:20.

[0012] The base polishing liquid includes 1% to 12% of silicon dioxide and 87% to 98% of deionized water in terms of mass percentage.

[0013] In an exemplary embodiment of the present disclosure, the first polishing pad has a hardness of 55 to 100.

[0014] In an exemplary embodiment of the present disclosure, the second polishing pad has a hardness of 30 to 50.

[0015] In an exemplary embodiment of the present disclosure, the preliminary polishing has a polishing amount of 80 nm to 150 nm.

[0016] In an exemplary embodiment of the present disclosure, the secondary polishing has a polishing amount of 40 nm to 70 nm.

[0017] In an exemplary embodiment of the present disclosure, the surface of the spin-on hard mask layer is preliminarily polished by a first polishing pad using a polishing liquid, including:

[0018] A polishing machine table is provided, including a polishing head and a first polishing pad arranged oppositely;

[0019] The semiconductor structure is fixed to the side of the polishing head close to the first polishing pad;

[0020] The pressure between the first polishing pad and the semiconductor structure is adjusted;

[0021] The polishing liquid is dropped on the first polishing pad, and the polishing head is rotated at a first rotational speed, and the first polishing pad is rotated at a second rotational speed.

[0022] In an exemplary embodiment of the present disclosure, the first rotational speed is greater than the second rotational speed.

[0023] In an exemplary embodiment of the present disclosure, the first rotational speed is 20 r / min to 50 r / min, and the second rotational speed is 20 r / min to 40 r / min.

[0024] In an exemplary embodiment of the present disclosure, the surface of the spin-on hard mask layer is secondarily polished by a second polishing pad, including:

[0025] A polishing machine table is provided, including a polishing head and a second polishing pad arranged oppositely;

[0026] The semiconductor structure is fixed to the side of the polishing head close to the second polishing pad;

[0027] The pressure between the second polishing pad and the semiconductor structure is adjusted;

[0028] dropping the slurry on the second polishing pad and rotating the polishing head at a third rotation speed and rotating the second polishing pad at a fourth rotation speed.

[0029] In an example embodiment of the present disclosure, the third rotation speed is greater than the fourth rotation speed.

[0030] In an example embodiment of the present disclosure, the third rotation speed is 20r / min-50r / min and the fourth rotation speed is 20r / min-40r / min.

[0031] In an example embodiment of the present disclosure, the pressure is 0.3psi-1psi.

[0032] The surface planarization method of the semiconductor structure of the present disclosure can eliminate the height difference of the surface of the spin-on hard mask layer through the first polishing pad for preliminary polishing and the second polishing pad for secondary polishing, avoid the lower resistance and weaker blocking ability of the surface of the spin-on hard mask layer, and thus the surface of the substrate is easily etched through in the etching process, even etched to the surface of the substrate, and the probability of forming defects on the surface of the substrate is reduced, and the product yield is improved. Since the hardness of the first polishing pad is relatively large, the planarization effect of the preliminary polishing is good, and the polishing speed in the polishing process is large, which helps to reduce the polishing time and improve the polishing efficiency. At the same time, since the hardness of the second polishing pad is relatively small, the force of the second polishing pad acting on the surface of the spin-on hard mask layer can be reduced in the polishing process, the scratching of the substrate is reduced, the damage to the substrate in the polishing process is avoided, and the product yield is further improved.

[0033] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0034] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0035] Figure 1 is a schematic diagram of a core region in the related art;

[0036] Figure 2 is a schematic diagram of a peripheral region in the related art;

[0037] Figure 3 is a flowchart of the surface planarization method of the semiconductor structure in the embodiment of the present disclosure;

[0038] Figure 4 a schematic view of a polishing table in an embodiment of the present disclosure;

[0039] Figure 5 a flowchart of step S120 in an embodiment of the present disclosure;

[0040] Figure 6 a flowchart of step S130 in an embodiment of the present disclosure.

[0041] BRIEF DESCRIPTION OF DRAWINGS

[0042] 100, wafer; 200, hard mask layer; 1, semiconductor structure; 2, polishing table; 21, polishing head; 22, first polishing pad (second polishing pad); 23, polishing disc; 3, polishing liquid; 4, first mounting portion. DETAILED DESCRIPTION

[0043] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same or similar elements can be not be repeated. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0044] Although relative terms such as "upper", "lower", "horizontal", "vertical", "above", "below", "up", "down", "top" and "bottom" can be used herein to describe one element's relationship to another element as the device is oriented in a particular direction, such terms are used in the present description for convenience to describe the orientation of the device as shown in the figures. It is understood that the device can be turned in other orientations, and that terms such as "upper", "lower", "horizontal", "vertical", "above", "below", "up", "down", "top" and "bottom" can be interchanged with respect to the device.

[0045] The terms "one", "a", "an", "the", and "at least one" are used to mean that "one or more" of something is present; the terms "comprising", "having", "including", and "containing" are used to mean "including, and not limiting to, the listed items"; the term "first", "second", "third", and "fourth" are used to denote a number, not to limit the number of items to the number of times the term is used; and the term "plurality" is used to denote "more than one".

[0046] With the shrinking of the semiconductor critical dimension (CD) (15 nm, 16 nm, etc.), in the semiconductor process, it is necessary to realize the shrinking of the critical dimension by multiple exposure and etching processes, etc. In this process, a spin-on hard mask layer is often used, which can easily lead to the formation of height difference between different areas of the wafer surface, for example, as shown in Figure 1 and Figure 2 Generally, a hard mask layer 200 needs to be spin-coated on the surface of the wafer 100. Due to the difference in the spin-coated bottom pattern, the hard mask layer 200 has a non-flat topography after spin-coating. In the subsequent etching process, the area with lower thickness in the hard mask layer 200 is easily etched through, which can damage the surface of the wafer 100 below, causing defects in the wafer 100 and low product yield. If the conventional pattern optimization process is used to reduce the height difference and thus reduce the defects of the wafer 100, it will take a long time, the manufacturing cost will be high, and there will be certain limitations. In addition, there are few chemical mechanical polishing processes for processing the hard mask layer 200 in the prior art. The reason is that in the chemical mechanical polishing process, by-products are easily attached to the polishing pad under the action of chemical mechanical friction, causing scratches on the wafer 100. In the chemical mechanical polishing process, the film layer 200 on the surface of the wafer 100 is easily polished out, which can damage the film on the surface of the wafer 100, resulting in low device yield.

[0047] The surface planarization method provided by the embodiments of the present disclosure can include steps S110-S130, wherein: Figure 3

[0048] Step S110, providing a semiconductor structure, the semiconductor structure including a substrate and a spin-on hard mask layer formed on the substrate;

[0049] Step S120, using a polishing liquid to preliminarily polish the surface of the spin-on hard mask layer with a first polishing pad;

[0050] Step S130, second polishing the surface of the spin-on hard mask layer with a second polishing pad, the hardness of the first polishing pad being greater than the hardness of the second polishing pad.

[0051] ​The semiconductor structure surface planarization method disclosed herein involves preliminary grinding of the surface of a spin-coated hard mask layer using a first polishing pad, followed by a secondary polishing using a second polishing pad. This two-step polishing process eliminates unevenness on the surface of the spin-coated hard mask layer, preventing areas with lower surface resistance from being easily etched through during etching, potentially even reaching the substrate surface. This reduces the probability of substrate surface defects and improves product yield. In this process, the relatively high hardness of the first polishing pad results in better planarization during the initial polishing, allowing for a higher polishing speed and reducing polishing time, thus improving efficiency. Simultaneously, the relatively lower hardness of the second polishing pad reduces the force exerted on the spin-coated hard mask layer surface during polishing, minimizing scratches on the substrate and preventing damage, further improving product yield.

[0052] The following provides a detailed description of each step and its technical details in the surface planarization method for semiconductor structures according to the embodiments of this disclosure:

[0053] like Figure 3 As shown, in step S110, a semiconductor structure is provided, the semiconductor structure including a substrate and a spin-coated hard mask layer formed on the substrate.

[0054] In one exemplary embodiment of this disclosure, the semiconductor structure can be a structure prior to any patterning process or etching process in the semiconductor manufacturing process, or a structure between two patterning processes, without any particular limitation. For example, it can be a structure prior to the formation of a gate trench, a structure prior to the formation of a bit line trench, or a structure prior to the formation of a capacitor contact hole. Of course, it can also be other structures in the semiconductor manufacturing process, which will not be listed here one by one.

[0055] The semiconductor structure may include a substrate and a spin-coated hard mask layer. The substrate may include a base and a patterned film layer formed on the surface of the base. The patterned film layer may include at least one of word line structure, bit line structure, capacitor plug, storage capacitor, metal wiring or peripheral circuit. The spin-coated hard mask layer may be formed on the surface of the patterned film layer.

[0056] The substrate may include a core region and a peripheral region. The core region may be used to form word line structures, bit line structures, capacitor plugs, storage capacitors, or metal wiring for patterned film layers. The peripheral region may be used to form peripheral circuits. The peripheral circuits in the peripheral region may include word line driving circuits for driving word lines, bit line driving circuits for driving bit lines, capacitor lead-out circuits for leading out storage capacitors, and lead-out circuits for electrically leading out metal wiring layers. Of course, the peripheral circuits may also include other circuits, which will not be listed here.

[0057] In an exemplary embodiment of the present disclosure, the substrate can have a flat structure, which can be rectangular, circular, oval, polygonal or irregular, and the material thereof can be silicon or other semiconductor materials, and the shape and material of the substrate are not particularly limited herein.

[0058] The spin-on hard mask layer can be formed on the substrate, for example, it can be formed on the surface of the mask material layer and can fill the gaps between the mask patterns and adjacent mask patterns. The spin-on hard mask layer can be formed on the surface of the mask material layer away from the substrate by using a spin coating process. However, due to the limitations of the manufacturing process, there are height differences in the spin-on hard mask layer formed in different areas of the substrate during the formation of the spin-on hard mask layer.

[0059] In some embodiments, the thickness of the spin-on hard mask layer can be greater than the thickness of the mask material layer, so that the spin-on hard mask layer can fill the mask patterns in the mask material layer and the gaps between the mask patterns. For example, the thickness of the spin-on hard mask layer can be 250 nm to 500 nm, for example, the thickness thereof can be 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm, and of course, the thickness of the spin-on hard mask layer can also be other, which will not be listed one by one herein.

[0060] The material of the spin-on hard mask layer can be a spin-on hard mask material commonly used in the art, for example, it can be a material polymerized from an organic cyclic carbon compound (SOH, spin-on-hard mask). SOH is different from traditional chemical mechanical polishing inorganic oxide, metal and other materials, which can fill the gaps on the surface of the bottom film layer, increase the flatness, and also enhance the corrosion resistance, and can be used as a resist film in the subsequent etching process, which is helpful to realize the fine transfer of the pattern in the subsequent etching process.

[0061] As shown in Figure 3 In step S120, a polishing liquid is used to preliminarily polish the surface of the spin-on hard mask layer with a first polishing pad.

[0062] In some embodiments, as shown in Figure 4 A first polishing pad 22 with relatively high hardness can be used to preliminarily polish the spin-on hard mask layer, and in this process, due to the relatively high hardness of the first polishing pad 22, the polishing process can be accelerated, and the height difference on the surface of the spin-on hard mask layer can be quickly reduced.

[0063] In an exemplary embodiment of the present disclosure, a polishing liquid 3 is used to preliminarily polish the surface of the spin-on hard mask layer with a first polishing pad 22, that is, step S120 can include steps S1201-S1204, as shown in Figure 5

[0064] ​Step S1201, providing a grinding machine table, the grinding machine table comprising a grinding head and a first grinding pad arranged oppositely.

[0065] In an embodiment, the grinding machine can comprise a grinding head 21 and a grinding disc 23, wherein:

[0066] The grinding head 21 can be in the shape of a rod, and its cross section can be circular, elliptical, rectangular, or the like, which is not particularly limited herein. The grinding head 21 can be made of a material with relatively high rigidity, for example, a metal or an alloy, or the like. Of course, the grinding head 21 can also be made of other materials with relatively high rigidity, which is not particularly limited herein.

[0067] The grinding head 21 can have a first mounting portion 4, which can be arranged opposite to the grinding disc 23, and can be used to mount a structure to be ground. The first mounting portion 4 can be in the shape of a disc, and its cross section can be circular, elliptical, rectangular, or the like. The surface of the first mounting portion 4 close to the grinding disc 23 can be planar, and can be used to fix the structure to be ground on the planar surface of the first mounting portion 4.

[0068] For example, the structure to be ground can be fixed to the first mounting portion 4 by adhesion, clamping, or the like. Of course, the structure to be ground can also be fixed to the first mounting portion 4 by other means, as long as the surface of the structure to be ground is not damaged. The mounting manner of the structure to be ground is not particularly limited herein. It should be noted that the structure to be ground can be the semiconductor structure 1 in the present disclosure, or other structures to be ground, which are not listed herein.

[0069] The grinding disc 23 can be in the shape of a disc, and its cross section can be circular, elliptical, rectangular, or irregular, which is not particularly limited herein. The grinding disc 23 can comprise a planar surface, which can provide a flat reference for the grinding process.

[0070] In some embodiments, the grinding disc 23 can be made of a material with relatively high rigidity, for example, a metal or an alloy, or the like. Of course, the grinding disc 23 can also be made of other materials with relatively high rigidity, which is not particularly limited herein. The orthographic projection of the grinding head 21 on the grinding disc 23 can be located inside the grinding disc 23, that is, the area of the grinding head 21 can be smaller than the area of the grinding disc 23. The grinding pad can be fixed on the grinding disc 23, so that the grinding pad is arranged opposite to the grinding head 21. In the grinding process, the grinding pad needs to be fixed on the grinding disc 23. When the grinding pad needs to be replaced, the previously fixed grinding pad on the grinding disc 23 can be removed, and the required grinding pad can be mounted on the grinding disc 23. That is, the grinding pad and the grinding disc 23 are two different components.

[0071] For example, the polishing disc 23 can include a support portion and a second mounting portion. The second mounting portion can be disc-shaped, such as a circular disc, an elliptical disc, or a rectangular disc. The side of the second mounting portion close to the polishing head 21 can be a flat surface, and the polishing pad can be fixed to the flat surface of the second mounting portion. For example, the polishing pad can be fixed to the second mounting portion by adhesion, clamping, or other methods. Of course, the polishing pad can be fixed to the second mounting portion by other methods, and the mounting method of the polishing pad is not specifically limited herein.

[0072] In the preliminary polishing process, the first polishing pad 22 can be fixed to the polishing disc 23, and the first polishing pad 22 can rotate synchronously with the polishing disc 23.

[0073] In another embodiment, the polishing machine table 2 can include a plurality of polishing discs 23 of different types. The surface hardness of each polishing disc 23 is different. In the polishing process, if different hardness polishing discs 23 are required for polishing, the corresponding surface hardness polishing disc 23 can be directly replaced. That is, the polishing disc 23 is the polishing pad. In the preliminary polishing process, the polishing disc 23 with relatively large surface hardness can be used as the first polishing pad 22, so that the polishing speed in the preliminary polishing process is large, which helps to reduce the polishing time and improve the polishing efficiency.

[0074] In an exemplary embodiment of the present disclosure, the hardness of the first polishing pad 22 can be 55-100, such as 55, 60, 70, 80, 90, or 100. Of course, the hardness can also be other hardness, which is not listed one by one herein. It should be noted that the hardness in the present disclosure is Shore hardness. The polishing rate can be controlled according to the hardness of the first polishing pad 22, so that the polishing rate is maintained at 900 A / min-1600 A / min.

[0075] In step S1202, the semiconductor structure is fixed to the side of the polishing head close to the first polishing pad.

[0076] In an embodiment, the semiconductor structure 1 in the present disclosure can be used as a structure to be polished, and can be fixed to the side of the polishing head 21 close to the first polishing pad 22. For example, the semiconductor structure 1 can be fixedly connected to the first mounting portion 4, such as by adhesion, clamping, or other methods. It should be noted that the spin-on hard mask layer in the semiconductor structure 1 can be located on the side of the substrate close to the first polishing pad 22.

[0077] In step S1203, the pressure between the first polishing pad and the semiconductor structure is adjusted.

[0078] The pressure between the first polishing pad 22 and the semiconductor structure 1 can be adjusted to be 0.3 psi to 1 psi, for example, 0.3 psi, 0.5 psi, 0.7 psi, 0.9 psi or 1 psi, of course, other pressures can also be used, which are not listed one by one here.

[0079] In step S1204, the polishing liquid is dropped on the first polishing pad, and the polishing head is rotated at a first rotating speed, and the first polishing pad is rotated at a second rotating speed.

[0080] After adjusting the pressure between the first polishing pad 22 and the semiconductor structure 1, the polishing head 21 can be rotated at a first rotating speed, and the first polishing pad 22 can be rotated at a second rotating speed; during this process, chemical mechanical friction can be applied to the surface of the spin-on hard mask layer, and the height difference of the surface of the spin-on hard mask layer can be reduced by the action of the chemical mechanical friction.

[0081] In some embodiments, the first rotating speed can be 20 r / min to 50 r / min, for example, the first rotating speed can be 20 r / min, 30 r / min, 40 r / min or 50 r / min, of course, the first rotating speed can also be other rotating speeds, which are not listed one by one here.

[0082] In some embodiments, the second rotating speed can be 20 r / min to 40 r / min, for example, the second rotating speed can be 20 r / min, 25 r / min, 30 r / min, 35 r / min or 40 r / min, of course, the second rotating speed can also be other rotating speeds, which are not listed one by one here.

[0083] Preferably, the first rotating speed is greater than the second rotating speed, that is, the rotating speed of the polishing head 21 can be greater than the rotating speed of the first polishing pad 22, for example, the first rotating speed can be 30 r / min, and the second rotating speed can be 20 r / min; the first rotating speed can be 40 r / min, and the second rotating speed can be 30 r / min; the first rotating speed can be 50 r / min, and the second rotating speed can be 40 r / min; of course, the first rotating speed can also be other values, and the second rotating speed can also be other values, as long as the first rotating speed is greater than the second rotating speed, which are not listed one by one here.

[0084] During the rotation of the first polishing pad 22, polishing slurry 3 can be dripped onto the surface of the first polishing pad 22. The polishing slurry 3 can be an acidic solution or an alkaline solution. In one embodiment, in order to better eliminate the unevenness on the surface of the spin-coated hard mask layer, an acidic solution is preferred as the polishing slurry 3. This is because acidic polishing slurries are more stable and have a milder reaction when decomposing the spin-coated hard mask layer. For example, the pH value of the acidic polishing slurry 3 is 4.5 to 6.2. For example, its pH value can be 4.5, 4.8, 5.2, 5.5, 5.8 or 6.2. Of course, other pH values ​​are also possible. No special limitation is made to the pH value of the acidic polishing slurry 3 here.

[0085] In one exemplary embodiment of this disclosure, the polishing slurry 3 can be obtained by diluting a base polishing slurry 3 with deionized water, and the mass ratio of the base polishing slurry 3 to deionized water can be 1:6 to 1:20. Using a specific deionized water dilution ratio can reduce the formation of byproducts during the polishing process, reduce the probability of defects in the substrate, and improve product yield. For example, the mass ratio of the base polishing slurry 3 to deionized water can be 1:6, 1:10, 1:14, 1:18, or 1:20. Of course, other mass ratios of the base polishing slurry 3 to deionized water are also possible, and will not be listed here.

[0086] In some embodiments, the base polishing slurry 3 may include 1% to 12% silica and 87% to 98% deionized water by mass percentage. For example, the base polishing slurry 3 may include 1% silica and 98% deionized water by mass percentage; or, the base polishing slurry 3 may include 4% silica and 95% deionized water by mass percentage; or, the base polishing slurry 3 may include 10% silica and 88% deionized water by mass percentage. Of course, the base polishing slurry 3 may also include other component proportions, which will not be listed here.

[0087] In one exemplary embodiment of this disclosure, when the height difference of the spin-coated hard mask is greater than 150nm, the grinding amount of the initial grinding can be 80nm to 150nm. For example, the grinding amount can be 80nm, 100nm, 120nm, 140nm or 150nm. Of course, other grinding amounts are also possible, which will not be listed here.

[0088] like Figure 3 As shown, in step S130, the surface of the spin-coated hard mask layer is polished a second time using a second polishing pad, wherein the hardness of the first polishing pad is greater than that of the second polishing pad.

[0089] In some embodiments, a second polishing pad 22 with relatively low hardness can be used to polish the spin-on hard mask again, so that the damage to the substrate during polishing can be reduced, and the yield of products can be further improved.

[0090] In an exemplary embodiment of the present disclosure, the surface of the spin-on hard mask layer is polished again by the second polishing pad 22, i.e., step S130 can include steps S1301-S1304 as shown in Figure 6

[0091] In step S1301, a polishing machine table is provided, which includes a polishing head and a second polishing pad arranged oppositely.

[0092] In an embodiment, the polishing machine can include a polishing head 21 and a polishing disc 23, wherein:

[0093] During the second polishing, the second polishing pad 22 can be fixed on the polishing disc 23, and the second polishing pad 22 can rotate synchronously with the polishing disc 23.

[0094] In another embodiment, the polishing machine table 2 can include a plurality of polishing discs 23 of different types, each of which has a different surface hardness. If polishing discs 23 with different hardness are needed during polishing, the polishing disc 23 with the corresponding surface hardness can be directly replaced, i.e., the polishing disc 23 is the polishing pad. During the second polishing, the polishing disc 23 with relatively low surface hardness can be used as the second polishing pad 22, so that the damage to the substrate during polishing can be reduced, and the yield of products can be further improved.

[0095] In an exemplary embodiment of the present disclosure, the hardness of the second polishing pad 22 can be 30-50, for example, it can be 30, 35, 40, 45 or 50, of course, it can also be other hardness, which will not be listed one by one here. It should be noted that the polishing rate can be controlled according to the hardness of the second polishing pad 22, so that the polishing rate is maintained at 900 A / min-1600 A / min.

[0096] In step S1302, the semiconductor structure is fixed to the side of the polishing head close to the second polishing pad.

[0097] In an embodiment, the semiconductor structure 1 can be fixed to the side of the polishing head 21 close to the second polishing pad 22. For example, it can be fixedly connected with the second mounting portion, for example, the semiconductor structure 1 and the second mounting portion can be fixed together by bonding or clamping. It should be noted that the spin-on hard mask layer in the semiconductor structure 1 can be located on the side of the substrate close to the second polishing pad 22.​

[0098] In one embodiment, after the first polishing pad 22 is used to polish the semiconductor structure 1, the first polishing pad 22 can be removed, and the second polishing pad 22 can be installed on the polishing plate 23, and the surface of the semiconductor structure 1 can be further polished by the second polishing pad 22.

[0099] In step S1303, the pressure between the second polishing pad and the semiconductor structure is adjusted.

[0100] The pressure between the second polishing pad 22 and the semiconductor structure 1 can be adjusted by adjusting the distance between the second polishing pad 22 and the semiconductor structure 1. For example, the pressure between the second polishing pad 22 and the semiconductor structure 1 can be adjusted to 0.3 psi-1 psi, for example, it can be 0.3 psi, 0.5 psi, 0.7 psi, 0.9 psi or 1 psi, of course, it can also be other pressures, which are not listed one by one here.

[0101] In step S1304, the polishing liquid is dropped on the second polishing pad, and the polishing head is rotated at a third rotational speed, and the second polishing pad is rotated at a fourth rotational speed.

[0102] After adjusting the pressure between the second polishing pad 22 and the semiconductor structure 1, the polishing head 21 can be rotated at a third rotational speed, and the second polishing pad 22 can be rotated at a fourth rotational speed; in this process, the chemical mechanical friction force can be applied to the surface of the spin-on hard mask layer, and the height difference on the surface of the spin-on hard mask layer can be eliminated by the action of the chemical mechanical friction force.

[0103] In some embodiments, the third rotational speed can be 20 r / min-50 r / min, for example, the third rotational speed can be 20 r / min, 30 r / min, 40 r / min or 50 r / min, of course, the third rotational speed can also be other rotational speeds, which are not listed one by one here.

[0104] In some embodiments, the fourth rotational speed can be 20 r / min-40 r / min, for example, the fourth rotational speed can be 20 r / min, 25 r / min, 30 r / min, 35 r / min or 40 r / min, of course, the fourth rotational speed can also be other rotational speeds, which are not listed one by one here.

[0105] Preferably, the third rotation speed can be greater than the fourth rotation speed, i.e., the rotation speed of the polishing head 21 can be greater than the rotation speed of the second polishing pad 22, for example, the third rotation speed can be 30 r / min, and the fourth rotation speed can be 20 r / min; the third rotation speed can be 40 r / min, and the fourth rotation speed can be 30 r / min; the third rotation speed can be 50 r / min, and the fourth rotation speed can be 40 r / min; of course, the third rotation speed can also be other values, and the fourth rotation speed can also be other values, as long as the third rotation speed is greater than the fourth rotation speed, which will not be listed one by one here.

[0106] In the process of rotating the second polishing pad 22, the polishing liquid 3 can be dripped onto the surface of the second polishing pad 22, and the polishing liquid 3 can be an acidic solution or an alkaline solution. In an embodiment, in order to better eliminate the height difference on the surface of the spin-on hard mask layer, an acidic solution is preferably used as the polishing liquid 3. The reason is that the acidic polishing liquid is more stable and the reaction is more gentle when decomposing the spin-on hard mask layer. For example, the PH value of the acidic polishing liquid 3 is 4.5-6.2, for example, the PH value can be 4.5, 4.8, 5.2, 5.5, 5.8 or 6.2, of course, it can also be other PH values, and the PH value of the acidic polishing liquid 3 is not specially limited here.

[0107] In an exemplary embodiment of the present disclosure, the polishing liquid 3 for secondary polishing can be the same as the polishing liquid 3 for primary polishing, or can be different from the polishing liquid 3 for primary polishing, which is not specially limited here. For example, the polishing liquid 3 for secondary polishing can be obtained by diluting the base polishing liquid 3 with deionized water, and the mass ratio of the base polishing liquid 3 to the deionized water can be 1:6-1:20; for example, the mass ratio of the base polishing liquid 3 to the deionized water can be 1:6, 1:9, 1:12, 1:15, 1:18 or 1:20, of course, the mass ratio of the base polishing liquid 3 to the deionized water can also be other ratios, which will not be listed one by one here.

[0108] In some embodiments, the base polishing liquid 3 can include 1%-12% of silicon dioxide and 87%-98% of deionized water by mass percentage. For example, the base polishing liquid 3 can include 1% of silicon dioxide and 98% of deionized water by mass percentage; or the base polishing liquid 3 can include 4% of silicon dioxide and 95% of deionized water by mass percentage; or the base polishing liquid 3 can include 10% of silicon dioxide and 88% of deionized water by mass percentage, of course, the base polishing liquid 3 can also include other component ratios, which will not be listed one by one here.

[0109] In an exemplary embodiment of the present disclosure, the polishing amount during secondary polishing can be 40-70 nm, for example, the polishing amount can be 40 nm, 50 nm, 60 nm or 70 nm, of course, it can also be other polishing amounts, which will not be listed one by one here.

[0110] In some embodiments, the height difference of the core region of the substrate is reduced from 55nm to 5nm after the second grinding; in other embodiments, the height difference of the core region of the substrate is reduced from 60nm to 5nm after the second grinding; in other embodiments, the height difference of the peripheral region of the substrate is reduced from 80nm to 25nm after the second grinding. Thus, the height difference of the surface of the spin-on hard mask layer is greatly reduced by the two grinding processes. In the present disclosure, by adding a chemical mechanical treatment of the spin-on hard mask layer between the spin-on hard mask layer and the etching process, and combining with specific process steps, the process yield of the same batch of semiconductor structures is improved to 98%.

[0111] In some embodiments of the present disclosure, after the grinding is completed, the surface of the ground spin-on hard mask layer can be cleaned by the grinding machine 2 before the subsequent process, which can reduce the defect sources and further improve the product yield.

[0112] The working process of the surface planarization method of the semiconductor structure of the present disclosure is described below:

[0113] In the preliminary grinding process, the semiconductor structure 1 to be ground can be fixed on the first mounting portion 4 of the grinding head 21, and at the same time, the first grinding pad 22 with relatively high hardness is fixed on the second mounting portion of the grinding disc 23, so that the spin-on hard mask layer of the semiconductor structure 1 is arranged opposite to the first grinding pad 22. The pressure between the first grinding pad 22 and the semiconductor structure 1 is adjusted by adjusting the distance between the first grinding pad 22 and the semiconductor structure 1, so that the pressure is controlled within a suitable range, so that the grinding effect is ensured while avoiding excessive pressure, thereby avoiding damage to the substrate during grinding. After the preliminary grinding, the first grinding pad 22 can be removed, and the second grinding pad 22 with relatively low hardness is installed, and the surface of the spin-on hard mask layer is further ground by the second grinding pad 22 to eliminate the height difference of the surface of the spin-on hard mask layer. Avoiding the fact that the lower resistance of the surface of the spin-on hard mask layer in some areas is weaker, which is easy to be etched through in the etching process, and even etched to the surface of the substrate, which can reduce the probability of defects on the surface of the substrate and improve the product yield. In the above process, since the hardness of the first grinding pad 22 is relatively high, the planarization effect of the preliminary grinding is good, and the grinding speed during the grinding process is high, which helps to reduce the grinding time and improve the grinding efficiency; at the same time, since the hardness of the second grinding pad 22 is relatively low, the force acting on the surface of the spin-on hard mask layer during the grinding process can be reduced, the scratching of the substrate can be reduced, and the damage to the substrate during the grinding process can be avoided, which can further improve the product yield.

[0114] It is noted that while the various steps of the method of planarization of a surface of a semiconductor structure of the present disclosure are described in a particular order in the drawings, this is not required or implied as to the order in which the steps must be performed, or that all of the steps shown must be performed to achieve the desired result. Additionally or alternatively, certain steps can be omitted, multiple steps can be combined into a single step, a single step can be broken into multiple steps, etc.

[0115] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the present disclosure cover any and all variations of the present disclosure including those variations comprising any feature or combination of features taught by the disclosure and including those variations that would be obvious to one skilled in the art in light of the disclosure. The specification and examples given are intended as illustrative only and not limiting of the true scope and spirit of the present disclosure, which is to be given by the appended claims.

Claims

1. A method for planarizing a surface of a semiconductor structure, comprising: providing a semiconductor structure, the semiconductor structure comprising a substrate and a spin-on hard mask layer formed on the substrate; performing a first polishing on a surface of the spin-on hard mask layer using a polishing liquid and a first polishing pad; and performing a second polishing on the surface of the spin-on hard mask layer using a second polishing pad, wherein a hardness of the first polishing pad is greater than a hardness of the second polishing pad; wherein a height difference of the surface of the spin-on hard mask layer is reduced by the first polishing and the second polishing; wherein the spin-on hard mask layer is made of a material formed by polymerization of an organic cyclic carbon compound; wherein the hardness of the first polishing pad is 55-100; wherein the hardness of the second polishing pad is 30-50; wherein a polishing amount of the first polishing is 80-150 nm; and wherein a polishing amount of the second polishing is 40-70 nm. 2.The method of claim 1, wherein the polishing liquid is an acidic polishing liquid, and a pH value of the acidic polishing liquid is 4.5-6.

2. 3.The method of claim 1, wherein the polishing liquid is obtained by diluting a base polishing liquid with deionized water, and a mass ratio of the base polishing liquid to the deionized water is 1:6-1:20; wherein the base polishing liquid comprises 1-12% of silica and 87-98% of deionized water by mass percentage. 4.The method of claim 1, wherein the first polishing comprises: providing a polishing machine table comprising a polishing head and a first polishing pad arranged oppositely; fixing the semiconductor structure on a side of the polishing head close to the first polishing pad; adjusting a pressure between the first polishing pad and the semiconductor structure; dropping the polishing liquid on the first polishing pad, and rotating the polishing head at a first rotating speed and rotating the first polishing pad at a second rotating speed. 5.The method of claim 4, wherein the first rotating speed is greater than the second rotating speed. 6.The method of claim 4, wherein the first rotating speed is 20-50 r / min, and the second rotating speed is 20-40 r / min. 7.The method of claim 1, wherein the second polishing comprises: providing a polishing machine table comprising a polishing head and a second polishing pad arranged oppositely; fixing the semiconductor structure on a side of the polishing head close to the second polishing pad; adjusting a pressure between the second polishing pad and the semiconductor structure; dropping the polishing liquid on the second polishing pad, and rotating the polishing head at a third rotating speed and rotating the second polishing pad at a fourth rotating speed. 8.The method of claim 7, wherein the third rotating speed is greater than the fourth rotating speed. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 9. The surface planarization method of claim 7, wherein the third rotational speed is 20 r / min to 50 r / min, and the fourth rotational speed is 20 r / min to 40 r / min.

10. The surface planarization method of any one of claims 4 to 9, wherein the pressure is 0.3 psi to 1 psi. ​ ​

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