Multi-loop low-dropout linear regulator with fast transient response and no off-chip capacitance

Abstract

The application provides a multi-loop low-dropout linear voltage regulator with fast transient response and without off-chip capacitor, which comprises a main feedback loop, a fast feedback loop and an auxiliary fast feedback loop; the application adopts a multi-loop design, and improves the transient characteristics of the low-dropout linear voltage regulator without off-chip capacitor; compared with the traditional low-dropout linear voltage regulator, the voltage regulator of the application meets the on-chip system transient response, removes the off-chip capacitor required by the traditional linear voltage regulator, reduces the pin number, and meets the needs of the increasing single-chip integration and the development of digital-analog hybrid technology.

Description

Technical Field

[0001] This invention relates to low dropout linear regulators, and more particularly to multi-loop low dropout linear regulators with fast transient response and no external capacitors. Background Technology

[0002] Low-dropout linear regulators (LDL-LEF) serve as power supply modules for System-on-Chip (SoCs), directly converting the highly rippled output of front-end power supplies such as switching power supplies into a stable voltage for the SoC. With increasing chip integration and the development of low-voltage circuits, SoCs require various power supplies. Traditional LDL-LEF regulators require an external capacitor in the microsecond (µF) range. For the multiple power supply voltages of an SoC, each regulator would need an external capacitor, significantly increasing the number of chip interfaces. Therefore, using LDL-LEF regulators without external capacitors is a more suitable solution for powering various modules of the SoC. However, the absence of a large external capacitor at the output can cause severe overshoot and undershoot during load switching, especially in low-voltage circuits where the ratio of overshoot and undershoot to the required stable voltage is relatively large, potentially leading to system errors. Today, with increasing chip integration and the development of mixed-signal technology, the digital section, as the control part of the chip, has become an indispensable component for almost all chips. To reduce the power consumption of the digital section, the power supply voltage of the digital circuit is getting lower and lower. At the same time, the entire digital module is in constant level switching during operation, which causes the load current of the low dropout linear regulator to change constantly. This poses a great challenge to the transient response of the linear regulator applied to the system-on-a-chip.

[0003] Improving the transient response of low-dropout linear regulators typically involves two aspects: reducing overshoot and undershoot, and reducing recovery time. Methodologically, enhancing the transient response of a low-dropout linear regulator usually involves increasing bandwidth and slew rate. This invention addresses low-dropout linear regulators without external capacitors used in on-chip system power supply, proposing a multi-loop low-dropout linear regulator that increases both loop bandwidth and slew rate to meet the transient requirements of on-chip system power supply. Summary of the Invention

[0004] Objective of the Invention: To overcome the limitations and shortcomings of existing technologies, this invention proposes a multi-loop low-dropout linear regulator with fast transient response and no external capacitors. This linear regulator can suppress overshoot and undershoot during load switching and reduce the recovery time during load switching, thereby meeting the transient response requirements of an on-chip system power supply with no external capacitors, improving integration and reducing the number of chip pins.

[0005] Technical solution:

[0006] To achieve the above objectives, the present invention employs the following technical solution for specific application in low-dropout linear regulators:

[0007] This multi-loop low-dropout linear regulator, designed for on-chip system power supply, features fast transient response and no external capacitors. Its main components include a main feedback loop composed of a high-gain, high-slew-rate operational amplifier, a fast feedback loop composed of a bandpass filter, and an auxiliary fast feedback loop that enhances the slew rate. The regulating transistor is a P-type MOS transistor.

[0008] Main Feedback Loop: In this invention, the main feedback loop consists of an error amplifier and a buffer. The error amplifier is a high-gain, high-slew-rate Class AB amplifier, and the buffer is a high-slew-rate Class AB amplifier. Both operational amplifiers are high-slew-rate operational amplifiers. When the load changes, both amplifiers can provide a large current to the load capacitor of the next stage, rapidly changing the regulator's operating voltage and improving transient response characteristics. Simultaneously, the main feedback loop also provides a stable DC bias for the low-dropout linear regulator, providing loop gain at low frequencies to ensure a stable output voltage in steady state.

[0009] Fast Feedback Loop: This invention employs a fast feedback loop composed of a bandpass filter. The bandpass filter is directly connected to the output terminal and the gate of the regulating transistor, expanding the overall loop bandwidth of the low-dropout linear regulator and providing a fast feedback path from the output to the gate of the regulating transistor, thereby improving the overall transient response characteristics. The bandpass filter in this invention is a first-order active filter, forming two parallel paths with the main feedback loop, thus expanding the overall loop bandwidth.

[0010] Auxiliary Fast Feedback Loop: The auxiliary fast feedback loop consists of a voltage spike detection and elimination circuit. When a change in load current causes a change in output voltage, it detects the output voltage spike and increases the slew rate at the gate of the regulating transistor, thereby improving the transient response of the linear regulator and reducing overshoot and undershoot during load changes. Since the voltage across a capacitor cannot change abruptly, the capacitor can be used as a voltage sensing device. When a change in load current causes a change in output voltage, the capacitor changes the gate voltage of the transistor, and then the current mirror increases the current charging the gate of the regulating transistor, thus rapidly enhancing the slew rate and improving transient response characteristics.

[0011] A multi-loop low-dropout linear regulator with fast transient response and no external capacitors, including a main feedback loop, a fast feedback loop, and an auxiliary fast feedback loop;

[0012] The main feedback loop includes an error amplifier and a buffer;

[0013] The fast feedback loop includes a bandpass filter;

[0014] The auxiliary fast feedback loop includes a voltage spike detection and elimination circuit;

[0015] It also includes a regulating transistor, which is a PMOS transistor;

[0016] Specifically:

[0017] The reference voltage VREF is connected to the inverting input of the error amplifier, and the main feedback voltage VFB is connected to the non-inverting input of the error amplifier to form the main feedback loop.

[0018] The output of the error amplifier is connected to a buffer, the output of the buffer is connected to the gate of the regulating transistor, and the gate of the regulating transistor is connected to the feedback output interface of the bandpass filter to form a fast feedback loop.

[0019] The output interface of the gate voltage peak detection and elimination circuit of the regulating tube constitutes an auxiliary fast feedback loop;

[0020] The power supply V1N is connected to the power interface of the error amplifier and the source of the regulating transistor. The drain of the regulating transistor is connected to the drain resistor RF1, the input interface of the bandpass filter, the voltage peak detection and cancellation circuit, the load capacitor CL, and the resistor RL.

[0021] Preferably, the error amplifier includes transistor MP5, with power supply V1N connected to the sources of transistors MP5, MP10, MP11, MP12, and MP13; DC bias voltage Vp1 connected to the gate of transistor MP5; DC bias voltage Vp2 connected to the gates of transistors MP6, MP7, MP8, and MP9; and DC bias voltage VN connected to the gates of transistors MN1, MN2, MN3, and MN4. The bias voltage VN1 is connected to the gates of transistors MN5, MN6, MN7, and MN8. The drain of transistor MP5 is connected to the source of transistors MP1, MP2, MP3, and MP4. VFB is connected to the gates of transistors MP1 and MP2. The reference voltage is connected to the gates of transistors MP3 and MP4. The drain of transistor MP1 is connected to the source of transistor MN2 and the drain of transistor MN6. The drain of transistor MP2 is connected to the source of transistor MN1. The source of transistor MP3 is connected to the drain of transistor MN4, and the drain of transistor MN8 is connected to the source of transistor MN4, and the drain of transistor MN7 is connected to the source of transistor MN3, the drain of transistor MP6 is connected to the drain of transistor MP10, the drain of transistor MP6 is connected to the drain of transistor MN1, the source of transistor MP7 is connected to the drain of transistor MP11, and the drain of transistor MP7 is connected to the drain of transistor MN3 and the gates of transistors MP10 and MP11. The source of transistor MP8 is connected to the drain of transistor MP11. The drain of transistor MP8 is connected to the drain of transistor MN2 and the gates of transistors MP12 and MP13. The source of transistor MP9 is connected to the drain of transistor MP13. The drain of transistor MP9 is connected to the drain of transistor MN4 and the gates of transistors MN9 and MN10. At the same time, the drain of transistor MP9 is connected to capacitor C and transistor M. The sources of transistors MN5, MN6, MN7 and MN8 are all grounded.

[0022] Preferably, the buffer includes a transistor MP14, a DC bias voltage Vp1 connected to the gates of transistors MP14 and MP15, a power supply V1N connected to the sources of transistors MP14, MP15, MP18, MP19, and MP20, a power supply V1N connected to the drain of transistor MN12 to provide bias current, the drain of transistor MP14 connected to the drain of transistor MN9 and the gates of transistors MP19 and MP20, the drain of transistor MP15 connected to the drain of transistor MN10 and the gates of transistors MN14 and MN15, the gate of transistor MP16 connected to the gates of transistors MP17 and MP18, the source of transistor MP16 connected to the drain of transistor MP19, and transistor M... The drain of P16 is connected to the drain of transistor MN11. The source of transistor MP17 is connected to the drain of transistor MP18. The drain of transistor MP17 is grounded. The sources of transistors MN9, MN10, MN13, MN14, and MN15 are grounded. The gate of transistor MN11 is connected to the gates of transistors MN12 and MN13. The source of transistor MN11 is connected to the drain of transistor MN14. The drain of transistor MN115 is connected to the drain of transistor MP20 and outputs Vg to the gate of transistor MP. The source of transistor MP is connected to the power supply V1N. After the drain of transistor MP, resistors RF1 and RF2 are connected in sequence and then grounded. The drain of transistor MP is also connected to the load capacitor CL and resistor RL respectively, and outputs Vout at the drain.

[0023] Preferably, the fast feedback loop includes transistor MP23. The power supply V1N is connected to the source of transistors MP23, MP24, and MP25. The DC bias voltage Vp2 is connected to the gate of transistors MP21, MP22, and MP25. The DC bias voltage VN1 is connected to the gate of transistor MN20. The DC bias voltage VN2 is connected to the gate of transistor MN18. The DC bias voltage VN3 is connected to the gate of transistors MN16 and MN17. The drain of transistor MP21 is connected to the gate of transistors MP23 and MP24 and the drain of transistor MN16. The source of transistor MP21 is connected to the source of transistor MP23. The source of transistor MP22 is connected to the drain of transistor MP24. The drain of transistor MP22 is connected to the drain of transistor MN17, the gate of transistor MN19, and resistors R1 and R2. The source of transistor MN16 is connected to the drain of transistor MN18. The source of transistor MN17 is connected to the drain of transistor MN19. The sources of transistors MN18 and MN19 are connected to the drain of transistor MN20. The source of transistor MN20 is grounded. Resistor R1 is connected to the load capacitor C1. Resistor R2 is connected to the gate of transistor MN21. The drain of transistor MN21 is connected to the drain of transistor MP25 and outputs Vg. The source of transistor MN21 is connected to resistor R3 and grounded.

[0024] Preferably, the auxiliary fast feedback loop includes a transistor MP27. The power supply V1N is connected to the source of transistors MP27, MP28, MP29, and MP30. The gate of transistor MP27 is connected to the drain of transistor MP30. The source of transistor MP26 is connected to the drain of transistor MP27. The gate of transistor MP26 is connected to its drain and the drain of transistor MN22. The gate of transistor MP28 is connected to capacitor C3 and resistor R5. The gate of transistor MP29 is connected to the other end of resistor R5 and its drain. The drain of transistor MP30 is connected to... The drain of transistor MN26 outputs Vg. The gate of transistor MN22 is connected to capacitor C2 and outputs Vout. The gate of transistor MN22 is connected to resistor R4. The gate of transistor MN23 is connected to the other end of resistor R4 and the drain. The sources of transistors MN22 and MN23 are both grounded. The gate of transistor MN24 is connected to the drain of transistor MP28. The source of transistor MN24 is connected to the drain and gate of transistor MN25. The gate of transistor MN25 is connected to the gate of transistor MN26. The drains of transistors MN25 and MN26 are both grounded.

[0025] Beneficial effects:

[0026] This invention employs a multi-loop design to improve the transient characteristics of a low-dropout linear regulator without external capacitors. Compared to traditional low-dropout linear regulators, the regulator of this invention, while meeting the transient response requirements of on-chip systems, eliminates the external capacitors required by traditional linear regulators, reduces the number of pins, and meets the needs of continuously increasing monolithic integration and the ongoing development of mixed-signal technology. Attached Figure Description

[0027] Figure 1 This is a block diagram of the low-dropout linear regulator system of the present invention;

[0028] Figure 2 It is a high-gain, high-slew-rate Class AB error amplifier;

[0029] Figure 3 It is a high-gain, high-slew-rate Class AB buffer stage and output stage;

[0030] Figure 4 It is the fast feedback loop structure and circuit diagram;

[0031] Figure 5 It is a voltage detection and cancellation circuit;

[0032] Figure 6 This is a small-signal diagram of the low-dropout linear regulator of the present invention;

[0033] Figure 7 These are the simulation results of the loop Bode plot;

[0034] Figure 8 (a) is the simulated transient response waveform during load switching, with a change time of 20 ns;

[0035] Figure 8 (b) is the simulated waveform of the transient response during load switching, with a change time of 100ns. Detailed Implementation

[0036] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0037] Figure 1 This is a multi-loop low-dropout linear regulator with fast transient response and no external capacitors. The system block diagram shown in the figure includes three loops: a main feedback loop composed of a high-gain, high-slew-rate operational amplifier; a fast feedback loop composed of a bandpass filter; and an auxiliary fast feedback loop that enhances the slew rate. Figure 1The reference voltage VREF is connected to the inverting input of the error amplifier, and the main feedback voltage VFB is connected to the non-inverting input of the error amplifier to form the main feedback loop. The output of the error amplifier is connected to a buffer, the output of the buffer is connected to the gate of the transistor MP, the gate of the transistor MP is connected to the feedback output interface of the bandpass filter to form a fast feedback loop, and the gate of the transistor MP is connected to the output interface of the voltage peak detection and elimination circuit to form an auxiliary fast feedback loop. The power supply V1N is connected to the power interface of the error amplifier and the source of the transistor MP. The drain of the transistor MP is connected to the drain resistor RF1, the bandpass filter, the input interface of the voltage peak detection and elimination circuit, the load capacitor CL, and the resistor RL.

[0038] Figure 2This is a high-gain, high-slew-rate Class AB error amplifier. The first stage in the diagram consists of a folded cascode amplifier with cross-coupling. The cross-coupling increases the output slew rate, making this stage a Class AB operational amplifier. Simultaneously, the cross-coupling also increases the gain of the first stage, improving the overall DC gain at steady state and enhancing the accuracy of the output voltage. The second stage is a high-slew-rate rail-to-rail Class AB operational amplifier. The current ratios of each branch are shown in the diagram. In steady state, all transistors (MOSFETs) operate in the saturation region. During dynamic response, transistors MN11 or MP16 will operate in the linear region. Because the output transistors MP20 and MN15 of this stage are not fixed-biased, the buffer of the second stage has both high positive and negative slew rates, suppressing both overshoot and undershoot. In contrast, commonly used super-source followers or folded voltage followers, due to their fixed bias, typically have only one larger positive or negative slew rate. Meanwhile, since the output of the second stage, i.e., the gate of the regulating transistor, is connected to the drains of transistors MP20 and MN15, the second stage can achieve track-rail swing. Furthermore, although the gate voltage of the regulating transistor changes significantly under different load currents, because the output of the second stage is the drain of two MOSFETs, the different gate voltages under different load conditions have little impact on the static operating point of the first stage. This reduces the systematic offset voltage of the first-stage differential pair, ensures the accuracy of the output voltage under different load currents, and improves the load regulation of the low-dropout linear regulator. The lower left part of the figure shows the fast feedback loop and its impact on the amplitude-frequency curve. The fast feedback loop consists of a bandpass filter, which, along with the main feedback loop, forms two parallel paths. Its impact on the Bode plot is shown in the figure. As can be seen from the figure, low-frequency components pass through the main feedback loop, while high-frequency components pass through the fast feedback loop, expanding the system bandwidth. The lower right part of the figure is the voltage spike detection and elimination circuit. It uses the fact that the voltage across the capacitor cannot change abruptly as a voltage spike detection element. It changes the current of transistors MN22 and MP28 through the capacitor, and then feeds back to the gate of the regulating transistor through the current mirror. This establishes a fast feedback loop from the output to the gate of the regulating transistor.The power supply V1N is connected to the source of transistors MP5, MP10, MP11, MP12, and MP13. The DC bias voltage Vp1 is connected to the gate of transistor MP5. The DC bias voltage Vp2 is connected to the gate of transistors MP6, MP7, MP8, and MP9. The DC bias voltage VN is connected to the gate of transistors MN1, MN2, MN3, and MN4. The DC bias voltage VN1 is connected to transistor MN5. The gates of transistors MN6, MN7, and MN8 are connected to each other. The drain of transistor MP5 is connected to the source of transistors MP1, MP2, MP3, and MP4. VFB is connected to the gates of transistors MP1 and MP2. The reference voltage is connected to the gates of transistors MP3 and MP4. The drain of transistor MP1 is connected to the source of transistor MN2 and the drain of transistor MN6. The drain of transistor MP2 is connected to the source of transistor MN1 and the drain of transistor MN5. The drain of transistor MP3 is connected to the source of transistor MN4 and the drain of transistor MN8. The drain of transistor MP4 is connected to the source of transistor MN3 and the drain of transistor MN7. The source of transistor MP6 is connected to the drain of transistor MP10. The drain of transistor MP6 is connected to the drain of transistor MN1. The source of transistor MP7 is connected to the drain of transistor MP11. The drain of transistor MP7 is connected to the drain of transistor MN3 and the gates of transistors MP10 and MP11. Transistor M... The source of P8 is connected to the drain of MP11. The drain of MP8 is connected to the drain of MN2 and the gates of MP12 and MP13. The source of MP9 is connected to the drain of MP13. The drain of MP9 is connected to the drain of MN4 and the gates of MN9 and MN10. At the same time, the drain of MP9 is connected to capacitor C and transistor M. The sources of transistors MN5, MN6, MN7 and MN8 are all grounded.

[0039] Figure 3This is a high-gain, high-slew-rate Class AB buffer stage and output stage. The DC bias voltage Vp1 is connected to the gates of transistors MP14 and MP15. The power supply V1N is connected to the sources of transistors MP14, MP15, MP18, MP19, and MP20. The power supply V1N is also connected to the drain of transistor MN12 to provide bias current. The drain of transistor MP14 is connected to the drain of transistor MN9 and the gates of transistors MP19 and MP20. The drain of transistor MP15 is connected to the drain of transistor MN10 and the gates of transistors MN14 and MN15. The gate of transistor MP16 is connected to the gates of transistors MP17 and MP18. The source of transistor MP16 is connected to the drain of transistor MP19. The drain of transistor MP16 is connected to the source of transistor MP19. The drain of MN11 is connected to the drain of MP18, the source of MP17 is connected to the drain of MP18, the drain of MP17 is grounded, the sources of MN9, MN10, MN13, MN14, and MN15 are grounded, the gate of MN11 is connected to the gates of MN12 and MN13, the source of MN11 is connected to the drain of MN14, the drain of MN115 is connected to the drain of MP20 and outputs Vg to the gate of MP, the source of MP is connected to the power supply V1N, and the drain of MP is connected to resistors RF1 and RF2 in sequence and then grounded. The drain of MP is also connected to the load capacitor CL and resistor RL respectively and outputs Vout at the drain.

[0040] Figure 4This is the fast feedback loop structure and circuit diagram. The power supply V1N is connected to the source of transistors MP23, MP24, and MP25; the DC bias voltage Vp2 is connected to the gate of transistors MP21, MP22, and MP25; the DC bias voltage VN1 is connected to the gate of transistor MN20; the DC bias voltage VN2 is connected to the gate of transistor MN18; the DC bias voltage VN3 is connected to the gate of transistors MN16 and MN17; the drain of transistor MP21 is connected to the gate of transistors MP23 and MP24 and the drain of transistor MN16; the source of transistor MP21 is connected to the drain of transistor MP23; and the source of transistor MP22... The source of transistor MN16 is connected to the drain of transistor MN18, the source of transistor MN17 is connected to the drain of transistor MN19, the source of transistor MN18 and the source of transistor MN19 are connected to the drain of transistor MN20, the source of transistor MN20 is grounded, resistor R1 is connected to the load capacitor C1, resistor R2 is connected to the gate of transistor MN21, the drain of transistor MN21 is connected to the drain of transistor MP25 and outputs Vg, and the source of transistor MN21 is connected to resistor R3 and grounded.

[0041] Figure 5 This is a voltage detection and elimination circuit. The power supply V1N is connected to the source of transistors MP27, MP28, MP29, and MP30. The gate of transistor MP27 is connected to the drain of transistor MP30. The source of transistor MP26 is connected to the drain of transistor MP27. The gate of transistor MP26 is connected to its drain and the drain of transistor MN22. The gate of transistor MP28 is connected to capacitor C3 and resistor R5. The gate of transistor MP29 is connected to the other end of resistor R5 and its drain. The drain of transistor MP30 is connected to the drain of transistor MN26 and outputs power. The output Vg is connected to the gate of transistor MN22, which is connected to capacitor C2, and the output Vout is connected to the gate of transistor MN22. The gate of transistor MN22 is connected to resistor R4. The gate of transistor MN23 is connected to the other end of resistor R4 and the drain. The sources of transistors MN22 and MN23 are both grounded. The gate of transistor MN24 is connected to the drain of transistor MP28. The source of transistor MN24 is connected to the drain and gate of transistor MN25. The gate of transistor MN25 is connected to the gate of transistor MN26. The drains of transistors MN25 and MN26 are both grounded.

[0042] Figure 6This is the small-signal circuit diagram corresponding to the low-dropout linear regulator of the present invention. The non-inverting input of transistor Mn1 is grounded, and the inverting input is connected to Vfb. The output is connected to R01 and C01 and then grounded. The output is connected to the input of transistors Mn9 and Mn10, and capacitor C and transistor M. The output of transistor Mn9 is connected to R03, C03, and the input of transistor Mp19. The other ends of R03 and C03 are both grounded. The output of transistor Mn10 is connected to R04, C04, and the input of transistor Mn15. The other ends of R04 and C04 are both grounded. Transistor Mp10... The output terminals of p19 and -g transistor Mn15 are connected to the output terminal of -g transistor Mn21 and R02, C02, and the gate of g transistor Mp. The other ends of R02 and C02 are grounded. The input terminal of -g transistor Mn21 is connected to R2 and the output terminal of -g transistor Mn19. The inverting terminal of -g transistor Mn19 is connected to the other end of R2 and R1. The non-inverting terminal of -g transistor Mn19 is grounded. The other end of R1 is connected to C1. The power supply V1N is connected to the source of g transistor Mp and r0. The drain of g transistor Mp is connected to C1, the other ends of C transistor M and r0, and CL and RL. The other ends of CL and RL are grounded. The corresponding loop transfer function can be obtained according to the small-signal model. The low-frequency loop gain of the low-dropout linear regulator of the present invention is shown in formula (1):

[0043]

[0044] Where β is the feedback coefficient, K is the width-to-length ratio of transistor MP10 / MP11 and transistor MP13 / MP12, and g mn1 and g mn2 These are the equivalent transconductances of transistors MN1 and MN2, respectively, R O1 It is the output resistance of the first stage, g mn9 and g mp19 These are the equivalent transconductances of transistors MN9 and MP19, respectively. O3 and R O4 It is the equivalent output resistance of the intermediate stage of the buffer, g mn10 and g mn15 These are the equivalent transconductances of transistors MN10 and MP15, respectively. O2 It is the equivalent output resistance at the output terminal of the buffer, g mp It is the equivalent transconductance of the power transistor, R O It is the equivalent resistance of the linear regulator output, G. EA2 It is the equivalent transconductance of the buffer, and the transfer function of the main loop is shown in equation (2):

[0045]

[0046] Where CO1 and C O2 C represents the equivalent capacitance at the output of the first-stage error amplifier and the second-stage buffer stage, respectively. O3 and C O4 C represents the equivalent capacitance of the intermediate stage of the buffer, respectively. O This represents the capacitor at the output of the low-dropout linear regulator. Because the impedance of the intermediate node of a Class AB buffer is very small (R... O3 ,R O4 ≈1 / g m Therefore, the poles at the corresponding nodes are very high, having almost no effect on the loop. Thus, the main loop can be approximated as a three-pole system, where the dominant pole is located at the output of the first-stage op-amp, the secondary pole at the output of the second-stage buffer, and the third pole at the output of the linear regulator. The Miller compensation capacitor C... M The distances between the three poles were adjusted. The transmission of fast feedback is shown in equation (3):

[0047]

[0048] Where ω p4 Located at the output of the bandpass filter op-amp, since the bandwidth of the bandpass filter op-amp is greater than the bandwidth of the main feedback circuit, its impact on the stability of the low-dropout linear regulator is minimal. According to Mason's formula, the overall loop gain of the low-dropout linear regulator can be calculated as follows:

[0049]

[0050] The zero point is located at the point where the main loop gain equals the fast feedback loop gain, so the expression for the zero point is:

[0051]

[0052] Figure 7 These are simulation results of the overall loop stability of a low-dropout linear regulator. Under different load current conditions, the lowest DC gain of the loop is 105dB, and the bandwidth can reach 30 transistor MHz. Furthermore, the Bode plot shows that three poles and one zero mainly affect the loop stability, consistent with the small-signal analysis results. The loop maintains stability under various load current conditions.

[0053] Figure 5This is the transient response waveform of the low-dropout linear regulator of the present invention. The load current varies between 1-30mA (transistor mA), with load current change times of 20ns and 100ns, respectively. Simulation results show that when the load current change time is 20ns, the maximum undershoot is 236mA (transistor MV), the maximum overshoot is 84mA (transistor MV), and the slowest recovery time is 110ns. When the load current change time is 100ns, the maximum undershoot is 55mA (transistor MV), the maximum overshoot is 18mA (transistor MV), and the slowest recovery time is 210ns. Simulation results demonstrate that the transient response of the low-dropout linear regulator of the present invention is improved, meeting the requirements for providing a stable power supply voltage to on-chip systems without external capacitors.

[0054] The above description, in conjunction with the accompanying drawings, provides a further detailed explanation of the present invention. It should not be construed that the specific embodiments of the present invention are limited to these descriptions; the above descriptions are merely preferred embodiments of the present invention. For those skilled in the art, any modifications, equivalent substitutions, or improvements made without departing from the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-loop low-dropout linear regulator with fast transient response and no external capacitors, characterized in that, This includes the main feedback loop, the fast feedback loop, and the auxiliary fast feedback loop; The main feedback loop includes an error amplifier and a buffer; The fast feedback loop includes a bandpass filter; The auxiliary fast feedback loop includes a voltage spike detection and elimination circuit; It also includes a regulating transistor, which is a PMOS transistor; Specifically: Reference voltage V REF Connect the inverting input of the error amplifier, and the main feedback voltage V FB The non-inverting input of the error amplifier forms the main feedback loop; The output of the error amplifier is connected to a buffer, the output of the buffer is connected to the gate of the regulating transistor, and the gate of the regulating transistor is connected to the feedback output interface of the bandpass filter to form a fast feedback loop. The output interface of the gate voltage peak detection and elimination circuit of the regulating tube constitutes an auxiliary fast feedback loop; Power supply V IN Connect the power supply interface of the error amplifier and the source of the regulating transistor. Connect the drain of the regulating transistor to the drain resistor RF1, the input interface of the bandpass filter, the voltage peak detection and cancellation circuit, and the load capacitor C. L and resistance R L ; The error amplifier includes transistor MP5. The power supply VIN is connected to the source of transistors MP5, MP10, MP11, MP12, and MP13. The DC bias voltage V0 is... P1 Connect the gate of transistor MP5, DC bias voltage V P2 Connect the gates of transistors MP6, MP7, MP8, and MP9, with a DC bias voltage V. N2 Connect the gates of transistors MN1, MN2, MN3, and MN4, with a DC bias voltage V. N1 Connect the gates of transistors MN5, MN6, MN7, and MN8. Connect the drain of transistor MP5 to the source of transistors MP1, MP2, MP3, and MP4. V FB Connect the gates of transistors MP1 and MP2; connect the reference voltage to the gates of transistors MP3 and MP4; connect the drain of transistor MP1 to the source of transistor MN2 and the drain of transistor MN6; connect the drain of transistor MP2 to the source of transistor MN1 and the drain of transistor MN5; connect the drain of transistor MP3 to the source of transistor MN4 and the drain of transistor MN8; connect the drain of transistor MP4 to the source of transistor MN3 and the drain of transistor MN7; connect the source of transistor MP6 to the drain of transistor MP10; connect transistor MP... The drain of transistor 6 is connected to the drain of transistor MN1; the source of transistor MP7 is connected to the drain of transistor MP11; the drain of transistor MP7 is connected to the drain of transistor MN3 and the gates of transistors MP10 and MP11; the source of transistor MP8 is connected to the drain of transistor MP12; the drain of transistor MP8 is connected to the drain of transistor MN2 and the gates of transistors MP12 and MP13; the source of transistor MP9 is connected to the drain of transistor MP13; the drain of transistor MP9 is connected to the drain of transistor MN4, and serves as the output terminal V of the error amplifier. EA The sources of transistors MN5, MN6, MN7, and MN8 are all grounded to GND.

2. The multi-loop low-dropout linear regulator with fast transient response and no external capacitor as described in claim 1, characterized in that, The buffer includes a transistor MP14 and a DC bias voltage V. P Connect the gates of transistors MP14 and MP15, and the power supply V. IN Connect the sources of transistors MP14, MP15, MP18, MP19, and MP20, and the power supply V. IN The transistor MP14 is connected to the drain of transistor MN12 to provide bias current. The drain of transistor MP14 is connected to the drain of transistor MN9 and the gates of transistors MP19 and MP20. The drain of transistor MP15 is connected to the drain of transistor MN10 and the gates of transistors MN14 and MN15. The gate of transistor MP16 is connected to the gates of transistors MP17 and MP18. The source of transistor MP16 is connected to the drain of transistor MP19. The drain of transistor MP16 is connected to transistor MN12. The drain of transistor MN11 is connected to the drain of transistor MP18. The drain of transistor MP17 is grounded to GND. The sources of transistors MN9, MN10, MN13, MN14, and MN15 are grounded to GND. The gate of transistor MN11 is connected to the gates of transistors MN12 and MN13. The source of transistor MN11 is connected to the drain of transistor MN14. The drain of transistor MN115 is connected to the drain of transistor MP20 and outputs V. g The gate of transistor MP is connected to the power supply V. IN A resistor R is connected in sequence after the drain of transistor MP. F1 Resistance R F2 After grounding to GND, the drain of transistor MP is also connected to the load capacitor C. L and resistance R L And output V at the drain OUT Load capacitance C L and resistance R L The other end is grounded to GND; the gates of transistors MN9 and MN10 are connected to the output terminal V of the error amplifier. EA Capacitor C M The two ends are respectively connected to V EA and V OUT .

3. The multi-loop low-dropout linear regulator with fast transient response and no external capacitor as described in claim 1, characterized in that, The fast feedback loop includes a transistor MP23, and the power supply V IN Connect the sources of transistors MP23, MP24, and MP25, with a DC bias voltage V. P2 Connect the gates of transistors MP21, MP22, and MP25, with a DC bias voltage V. N1 Connected to the gate of transistor MN20, DC bias voltage V N2 Connected to the gate of transistor MN18, DC bias voltage V N3 Connect the gates of transistors MN16 and MN17. Connect the drain of transistor MP21 to the gates of transistors MP23 and MP24 and the drain of transistor MN16. Connect the source of transistor MP21 to the drain of transistor MP23. Connect the source of transistor MP22 to the drain of transistor MP24. Connect the drain of transistor MP22 to the drain of transistor MN17 and the gate of transistor MN19. Connect the source of transistor MN16 to the drain of transistor MN18. Connect the source of transistor MN17 to the drain of transistor MN19. Connect the sources of transistors MN18 and MN19 to the drain of transistor MN20. Connect the source of transistor MN20 to ground (GND). Connect the drain of transistor MN21 to the drain of transistor MP25 and output V. g The source of transistor MN21 is connected to resistor R3 and ground (GND). One end of resistor R1 is connected to the gate of M19, and the other end is connected to capacitor C1. The other end of capacitor C1 outputs V. OUT One end of resistor R2 is connected to the gate of M19, and the other end is connected to the gate of transistor MN21.

4. The multi-loop low-dropout linear regulator with fast transient response and no external capacitor as described in claim 1, characterized in that, The auxiliary fast feedback loop includes a transistor MP27 and a power supply V. IN Connect the sources of transistors MP27, MP28, MP29, and MP30. Connect the gate of transistor MP27 to its drain and the gate of transistor MP30. Connect the source of transistor MP26 to the drain of transistor MP27. Connect the gate of transistor MP26 to its drain and the drain of transistor MN22. Connect the gate of transistor MP28 to capacitor C3 and resistor R5. The other end of C3 outputs V. out The gate of transistor MP29 is connected to the other end of resistor R5 and the drain of transistor MP29. The drain of transistor MP29 is connected to ground GND through a bias current source. The drain of transistor MP30 is connected to the drain of transistor MN26 and outputs V. g The transistor MN22 outputs V after its gate is connected to capacitor C2. out The gate of transistor MN22 is connected to resistor R4, and the gate of transistor MN23 is connected to the other end of resistor R4 and the drain of MN23. The drain of transistor MN23 is connected to the power supply V through a bias current source. IN The sources of transistors MN22 and MN23 are both grounded. The gate of transistor MN24 is connected to the drain of transistor MP28. The source of transistor MN24 is connected to the drain and gate of transistor MN25. The gate of transistor MN25 is connected to the gate of transistor MN26. The sources of transistors MN25 and MN26 are both grounded to GND.

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