A hot plug IO port protection circuit

Abstract

The embodiment of the present application discloses a hot plug IO protection circuit, the circuit has two working states of normal work and hot plug, and the circuit comprises a host power supply end, a drive control port, a first MOS protection circuit, a second MOS protection circuit, a pulse control port and a PAD port. In the working state, the drive control circuit forms a first discharge channel and a second discharge channel by opening the first MOS protection circuit, and then controls the conduction and cutoff of the first discharge channel and the second discharge channel by the pulse control power supply. When hot plug, the second MOS protection circuit is used for shutting off the current channel between the host power supply end, the drive control port and the first MOS protection circuit, and between the PAD end and the first MOS protection circuit, so that the host will not generate leakage current when hot plug, and the host or peripheral equipment is prevented from being burned.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hot-swap I / O, in particular to a hot-swap I / O port protection circuit. BACKGROUND

[0002] Hot-swap, also known as "live insertion", refers to the ability to insert or remove peripheral devices supporting hot-swap without shutting down the system and cutting off the power supply, without causing the host or peripheral device to burn out. The traditional circuit uses a 5V input tolerance method to achieve hot-swap, as shown in Figure 1 When the external signal or voltage is higher than the internal IO voltage, the substrate voltage of the PMOS connected to the external input signal is equal to the external input voltage or signal; when the external voltage or signal is less than the internal IO voltage, the substrate voltage of the PMOS connected to the external input signal is equal to the internal voltage VDD, so that the external input signal can be ensured to have no current channel between the internal chip during the moment of insertion and removal.

[0003] Figure 2 The equivalent circuit schematic diagram of the parasitic diode of the PMOS tube in the current market IO port protection circuit is shown in Figure 2 and the above description is for easy understanding, only the IO drive circuit including PMOS transistor PM7 and NMOS transistor NM6 is described, but in fact the IO drive circuit can include a group of parallel PMOS tubes and a group of parallel NMOS tubes.

[0004] When the voltage power is powered on, regardless of whether the PAD port voltage PAD is high or low, the current direction in the IO sending end drive circuit is always from the source to the drain of PM7 and from the drain to the source of NM6. However, when the voltage VDD is not normally powered on, and the external device inserted into the PAD port already has a signal or voltage, that is, the source of PM7 is low and the drain of PM7 is high, the signal or voltage of the PAD port will be conducted to the power supply through the parasitic diode, that is, the PMOS tube can be regarded as a parasitic diode forward conduction, resulting in an unexpected leakage path, causing the host or peripheral device to burn out. SUMMARY

[0005] The purpose of the present application is to provide a hot-swap protection circuit to prevent the host or peripheral device from burning out when the chip needs to be hot-inserted or hot-pulled.

[0006] To solve the above problems, the embodiment of the present application discloses the following technical scheme:

[0007] A hot-swap IO port protection circuit has two working states: normal working and hot-swap, and the circuit includes:

[0008] The first discharge path is formed by the third PMOS tube (PM2), the second PMOS tube (PM1) to the PAD port connected to the peripheral device;

[0009] The second discharge path is formed by the third NMOS tube (NM2), the second NMOS (NM1) to the ground;

[0010] The first control path is formed by the driving control port to the second PMOS tube (PM1) and the driving control port to the fourth PMOS (PM3) tube, and the first control path outputs the first control signal and the fifth control signal;

[0011] The second control path is formed by the driving control port to the third NMOS tube (NM2), and the second control path outputs the second control signal;

[0012] The third control path is formed by the pulse control port to the second NMOS (NM1) and the pulse control port to the third PMOS tube (PM2), and the third control path outputs the third control signal and the fourth control signal;

[0013] In the normal working state, if the positive discharge occurs, the first control path outputs the first control signal, the second control path outputs the second control signal, and the third control path outputs the third control signal, and the first discharge path is turned on and the second discharge path is turned off; if the negative discharge occurs, the third control path outputs the fourth control signal, the second discharge path is turned on and the first discharge path is turned off;

[0014] In the hot plug state, the first control path outputs the fifth control signal, and PM3 protects the host and the peripheral device by turning off the current channel between the driving control port and the PAD port and between the host power supply end and the PAD port.

[0015] Preferably, the driving control port comprises an inverter access circuit composed of PM0 and NM0, the gate of PM0 and NM0 is connected to the hot plug enable foot, the drain output end is connected to the drain of PM1 and PM3, the substrate of PM0 is connected to the first discharge path, and the source of NM0 is connected to the substrate.

[0016] Preferably, the gate of PM1 is connected to the output end of the input circuit inverter, the substrate is connected to the substrate of PM3, the source is connected to the source of PM1, and the drain is connected to PAD to form the first discharge path; the gate of NM2 is connected to the output end of the input circuit inverter, the drain is connected to PM1 and PAD, and the substrate and the source are respectively connected to the substrate and the source of NM2 to form the second discharge path.

[0017] Preferably, the output end of the pulse control power supply is connected to the gate of NM1 and PM2.

[0018] Preferably, the gate of PM3 is connected with the output of the inverter, the drain and the substrate are connected with the substrate of PM1, and the source of PM3 is connected with the substrate and the source of PM0 and PM2 into the first discharge channel powered by the direct current power supply, so that PM3 can close the current channel between the PAD end of the cut-off parasitic diode between the substrates of PM0, PM1 and PM2 and the direct current power supply and the driving control circuit when the negative discharge occurs.

[0019] Further, the host power supply port comprises a direct current power supply for supplying power to the entire circuit and the PAD port; the PAD port is an interface for connecting peripheral device signals and voltages; the host power supply port and the driving control port are input ends in the normal working state, and the PAD port is an input end in the hot plug state.

[0020] Further, the driving control port outputs the first control signal as a high level in the normal working state, the first control signal is reversed by the inverter to output the second control signal as a low level, NM2 receives the first control signal to open NM2, and PM1 receives the second control signal to open PM1, thereby forming the first discharge channel and the second discharge channel.

[0021] Further, in the working state, the pulse control power supply outputs the third control signal as a low level to open PM2 and close NM1, thereby making the first discharge channel conductive and the second discharge channel cut off.

[0022] Further, in the working state, the pulse control power supply outputs the fourth control signal as a high level to close PM2 and open NM1, thereby making the first discharge channel cut off and the second discharge channel conductive.

[0023] Further, in the hot plug state, the hot plug enable foot is a high level to output the fifth control signal, PM1 and PM3 receive the fifth control signal to close the MOS tube, PM3 cuts off the current channel of the parasitic diode between the substrates of PM0, PM1 and PM2, and there is no leakage current between the PAD end and the driving control circuit and the direct current power supply.

[0024] The application realizes that the host will not generate leakage current to cause the host or peripheral device to be burned when the host is hot plugged by shutting down the circuit between the IN end and PM1 and the current channel between the PAD and the substrate of PM1. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to make the technical solutions and advantages in the embodiments of the present application clearer, the following further describes the exemplary embodiments of the present application with reference to the drawings. Obviously, the drawings in the following description are only a plurality of embodiments disclosed in the present specification, and other drawings can be obtained by those skilled in the art without any creative effort.

[0026] Figure 1 is the circuit design schematic diagram of the hot plug IO port currently adopted;

[0027] Figure 2 is the equivalent circuit schematic diagram of the PMOS parasitic diode in the current IO port design circuit;

[0028] Figure 3 is the circuit schematic diagram and the circuit unit structure schematic diagram of the hot plug IO protection circuit adopted in the present description;

[0029] Figure 4 is the circuit schematic diagram of the hot plug IO protection circuit adopted in the present description under normal working condition;

[0030] Figure 5 is the circuit schematic diagram of the hot plug IO protection circuit adopted in the present description under the plug-in state. DETAILED DESCRIPTION

[0031] The schemes provided by the embodiments of the present description are described below in combination with the drawings. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. The described embodiments are only part of the embodiments of the present description, not all the embodiments. Based on the embodiments in the present description, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0032] In order to avoid the generation of undesired leakage path between the PAD and the host when hot plugging, resulting in the burning of the host or the peripheral device, the present application provides a hot plug IO port protection circuit, the circuit schematic diagram and the circuit unit structure schematic diagram of the circuit are as shown in Figure 3 The circuit includes: a host power supply end 310, a drive control port 320, a first level MOS protection circuit 330, a second level MOS protection circuit 340, a pulse control port 350 and a PAD port 360.

[0033] The host power supply end 310 includes a DC power supply V1 connected to the host, which provides the required power for the entire circuit and the peripheral device when the peripheral device is inserted.

[0034] The drive control port 320 includes a control input port IN connected to the host control unit; two control output ports, one of which is connected to an inverter composed of a first PMOS tube (PM0) and a first NMOS tube (NM0), and in the normal working state, the gate of the inverter is connected as an input terminal to the hot plug enable pin of the host, and the drain output terminal of the inverter is connected to the gate of a second PMOS tube (PM1) and a fourth PMOS tube (PM3), forming a first control path, which outputs a first control signal and a fifth control signal; the other control port is connected to the gate of the second PMOS tube to form a second control path, which outputs a second control signal. The substrate and source of PM0 are connected to the source of PM3, and the source of NM0 is grounded; in the hot plug state, the output terminal of the inverter becomes an input terminal. The inverter controls the conduction or cutoff of the circuit by setting the working state of the MOS tube in each stage of the MOS protection circuit.

[0035] The first-stage MOS protection circuit 330 is composed of PM1, a third PMOS tube (PM2), a second NMOS tube (NM1), and a third NMOS tube (NM2). The gate of PM1 and the gate of NM2 are connected to the output terminal of the input circuit inverter. Among them, the substrate of PM1 is connected to the second-stage MOS protection circuit, the source and the drain of PM2 are connected, the drain is connected to PAD, and in the normal working state, the current channel between the host power supply end 310 and the PAD port 360 is ensured to be conductive to form a first discharge path; the drain of NM2 is connected to PM1 and PAD, the source is connected to the drain of NM1, the substrate is connected to the substrate of NM1 and is grounded, and a second discharge path is formed.

[0036] The second-stage MOS protection circuit 340 is composed of PM3, and the gate of PM3 is connected to the output of the inverter, which is the control terminal of the second-stage protection circuit. Among them, the drain and substrate of PM3 are connected to the substrate of PM1 of the first-stage protection circuit, and the source is connected to the source and drain of PM0 and PM1. When hot plug occurs, PM3 can shut off the current channel between the parasitic diode of the substrate of PM1, avoiding the generation of unexpected leakage current between the PAD port 360 and the host power supply end 310 and the drive control port 320.

[0037] The pulse control port 350 includes a pulse control power supply V2 that can output a pulse voltage, and the output terminal is connected to the gate of PM1 and the gate of NM2 to form a third control path, which outputs a third control signal and a fourth control signal to control the opening and closing of PM1 and NM2. The output of V2 shows high and low levels. When it is low, the first discharge path between the host power supply end 310 and the PAD port 360 is conductive, and the second discharge path from the PAD port 360 to the ground is cut off; when it is high, the first discharge path is cut off, and the second discharge path is conductive.

[0038] PAD port 360 is an interface for connecting peripheral device signals and voltage.

[0039] The whole circuit includes two working states of normal and hot plug. In normal working state, PAD is an input terminal, host power supply terminal is an output terminal, drive control terminal and pulse control terminal are control terminals. The current direction is from DC power supply V1 through PM1, PM2 to the peripheral device connected to PAD port through the first discharge path.

[0040] In hot plug working state, PAD is an output terminal, and the current is discharged to ground through the second discharge path from the peripheral device through NM1 and NM2.

[0041] In normal working state, the equivalent schematic diagram of the hot plug IO protection circuit is as shown in Figure 4

[0042] Firstly, the drive control circuit is equivalent to a DC power supply V3 outputting a first control signal as high level, the input terminal of the inverter is "1", and NM2 receives the first control signal MOS tube to open; the first control signal becomes a second control signal as low level "0" after passing through the inverter, and PM1 and PM3 are opened.

[0043] Then the pulse control power supply can output two kinds of control signals of high and low levels. When the output is "0" third control signal, the gate of PM2 is low, PM2 is opened, the first discharge path between the host power supply terminal 310 and the PAD port 360 is turned on, and the second discharge path from the PAD port 360 to the ground is cut off. The current is input to the PAD terminal from V1 through PM2 and PM1, the gate of NM1 is low, NM1 is closed, and the substrates of NM1 and NM2 are grounded, without leakage current.

[0044] If the pulse control power supply outputs "1" fourth control signal, the gate of PM2 is low, PM2 is closed; the gate of NM1 is high, and NM2 is opened. The first discharge path is cut off, the second discharge path is turned on, and the PAD terminal is high potential at this time, and the current is discharged to the ground through NM2 and NM1.

[0045] In the case of hot plug, the equivalent schematic diagram of the hot plug IO protection circuit is as shown in Figure 5

[0046] ​​First, the PAD port is high, the input end becomes the output end drive control circuit is closed, the hot plug host control unit through the hot plug enable foot through the first control path output fifth control signal is high, PM1, PM3 gate is high, PM1, PM3 is closed, from the host power supply end 310 to the first discharge path between PAD port 360 is closed, the second discharge path between PAD port 360 to the ground is turned on;And PM3 drain connected PM1 substrate without leakage current, current through NM1 ground discharge.

[0047] The present application through and PM2, NM1 in the working state control the first discharge path, the second discharge path and in the hot plug through PM3 shut off IN end and PM1 between the circuit, and the current channel between PAD and PM1 substrate realizes the circuit protection, the improvement is as follows Figure 1 The circuit in frame 1 is shown.1 part of the circuit is connected with 2, 3, 4 part of the circuit, which realizes that the PMOS tube in 1 part and the N tube in 4 part do not leak electricity when hot plug, the voltage passes through the internal circuit of 2 part, and then is output through the signal of 3 part with hysteresis effect of two buffers. No unexpected leakage current is generated, so as to cause the host or peripheral device to burn out.

[0048] The above specific embodiments further illustrate the purpose, technical scheme and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. based on the technical scheme of the present application should be included in the protection scope of the present application.

Claims

1. A hot plug IO protection circuit, having two working states: normal working state and hot plug state, the circuit comprising: a first discharge path formed by a host power supply end (310) connected to a host, through a third PMOS (PM2), a second PMOS (PM1) to a PAD port (360) connected to a peripheral device, wherein the host power supply end comprises a DC power supply, which supplies power to the entire circuit and the PAD port; the PAD port is an interface for connecting signals and voltage of the peripheral device; in the normal working state, the host power supply end and the drive control port are output ends, and the PAD port is an input end; in the hot plug state, the PAD port is an output end; a second discharge path formed by the PAD port (360) connected to the peripheral device, through a third NMOS (NM2), a second NMOS (NM1) to the ground; a first control path formed by the drive control port (320) to the second PMOS (PM1) and the drive control port (320) to the fourth PMOS (PM3), the first control path outputs a first control signal and a fifth control signal, the drive control port comprises an inverter access circuit composed of PM0 and NM0, the gate of PM0 and NM0 is connected to the hot plug enable pin, the drain output end is connected to the drain of PM1 and PM3, wherein the substrate and the source of PM0 are connected to the first discharge path, and the source and the substrate of NM0 are connected; a second control path formed by the drive control port (320) to the third NMOS (NM2), the second control path outputs a second control signal; a third control path formed by the pulse control port (350) to the second NMOS (NM1) and the pulse control port (350) to the third PMOS (PM2), the third control path outputs a third control signal and a fourth control signal; in the normal working state, if positive discharge occurs, the first control path outputs the first control signal, the second control path outputs the second control signal, and the third control path outputs the third control signal, the first discharge path is turned on, and the second discharge path is turned off; if negative discharge occurs, the third control path outputs the fourth control signal, the second discharge path is turned on, and the first discharge path is turned off; in the hot plug state, the first control path outputs the fifth control signal, PM1 and PM3 receive the fifth control signal to turn off the fourth PMOS, so that the fourth PMOS turns off the current path of the substrate parasitic diode of PM0, PM1 and PM2, and there is no leakage current between the PAD port and the drive control circuit and the DC power supply. The gate of PM1 is connected to the output end of the input circuit inverter, the substrate is connected to the substrate of PM3, the source is connected to the source of PM1, and the drain is connected to the PAD to form the first discharge path; the gate of NM2 is connected to the output end of the input circuit inverter, the drain is connected to PM1 and PAD, and the substrate and the source are connected to the substrate and the source of NM2 respectively to form the second discharge path. The pulse control port comprises: a pulse control power supply, the output end of the pulse control power supply is connected to the gate of NM1 and PM2. ​ ​ ​ ​ ​ 2. The protection circuit of claim 1, wherein: ​ 3. The protection circuit of claim 1, wherein, ​ ​ 4. The protection circuit of claim 3, wherein: The gate of the PM3 is connected with the output of the inverter, the drain and the substrate are connected with the substrate of the PM1, the source of the PM3 is connected with the substrate and the source of the PM0 and the PM2, and is connected into the first discharge channel supplied with the direct current power supply, so that when the negative discharge occurs, the PM3 can close the current channel between the PAD end of the cut-off parasitic diode between the substrates of the PM0, the PM1 and the PM2 and the direct current power supply and the driving control circuit.

5. The protection circuit of claim 1, wherein: In the normal working state, the driving control port outputs the first control signal as high level, the first control signal is reversed by the inverter and is output as the second control signal as low level, the NM2 receives the first control signal and opens the NM2, the PM1 receives the second control signal and opens the PM1, so as to form the first discharge channel and the second discharge channel.

6. The circuit according to any one of claims 3 and 5, characterized in that: In the working state, the pulse control power supply outputs the third control signal as low level, opens the PM2 and closes the NM1, so that the first discharge channel is conducted and the second discharge channel is cut off.

7. The circuit according to any one of claims 3 and 5, characterized in that: In the working state, the pulse control power supply outputs the fourth control signal as high level, closes the PM2 and opens the NM1, so that the first discharge channel is cut off and the second discharge channel is conducted.

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