Method and device for determining hardware parameter value, electronic equipment and storage medium

Abstract

The application relates to a hardware parameter value determination method and device, electronic equipment and a storage medium, and belongs to the technical field of neural networks. The method comprises the following steps: determining a plurality of target hardware parameters of a neural network chip; determining parameter value variation ranges of the plurality of target hardware parameters; determining a plurality of parameter optimization functions based on the parameter value variation ranges of the plurality of target hardware parameters, one parameter optimization function corresponding to the parameter value variation range of one hardware parameter, and the parameter optimization function being used for limiting the variation of the target hardware parameter within the parameter value variation range; and based on the plurality of parameter optimization functions, limiting the iterative training of an architecture simulation model within the parameter value variation ranges of the plurality of target hardware parameters to determine target parameter values of the plurality of target hardware parameters, the architecture simulation model being used for simulating the architecture of the neural network chip, and the target parameter values of the target hardware parameters being within the parameter value variation ranges of the hardware parameters. The application can improve the efficiency of determining hardware parameters.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of neural network, and particularly relate to a method and apparatus for determining hardware parameter values, an electronic device, and a storage medium. BACKGROUND

[0002] A neural network model needs to be dependent on a neural network chip, and the neural network chip generally includes multiple hardware parameters, and the parameter values of the multiple hardware parameters affect the performance of the neural network model. Therefore, before training the neural network model, the parameter values of the multiple hardware parameters of the neural network chip need to be determined, and the multiple hardware parameters can include memory space, supported transmission bandwidth, and the like.

[0003] In the related art, based on the multiple hardware parameters of the neural network chip, a plurality of parameter value combinations are determined, and the parameter value combinations include the parameter values of the multiple hardware parameters. Based on the plurality of parameter value combinations, a plurality of performances of the neural network model are determined through an architecture simulation model, and the architecture simulation model is used to simulate the neural network model. Based on the plurality of performances, a target parameter value combination of the neural network chip is determined, and the target parameter value combination includes target parameter values of the multiple hardware parameters, that is, the finally determined parameter values.

[0004] Since there are many types of hardware parameters and many parameter values of the hardware parameters, enumerating the parameter values of these hardware parameters will result in a large number of parameter value combinations, and thus determining the performances of the neural network model based on the large number of parameter value combinations will take a lot of time, and further result in low efficiency of determining the hardware parameter values. SUMMARY

[0005] Embodiments of the present application provide a method and apparatus for determining hardware parameter values, an electronic device, and a storage medium, which can improve the efficiency of determining the hardware parameter values. The technical solutions are as follows:

[0006] In one aspect, a method for determining hardware parameter values is provided, and the method includes:

[0007] determining a plurality of target hardware parameters of a neural network chip;

[0008] determining a parameter value variation range of the plurality of target hardware parameters;

[0009] based on the parameter value variation range of the plurality of target hardware parameters, determining a plurality of parameter optimization functions, one parameter optimization function corresponding to a parameter value variation range of one hardware parameter, and the parameter optimization function being used to limit the target hardware parameter to vary within the parameter value variation range;

[0010] determine target parameter values of the plurality of target hardware parameters based on the plurality of parameter optimization functions, the architecture simulation model being used to simulate an architecture of the neural network chip, the target parameter values of the target hardware parameters being within the parameter value variation ranges of the hardware parameters.

[0011] In another aspect, a device for determining hardware parameter values is provided, the device comprising:

[0012] a first determining module configured to determine a plurality of target hardware parameters of a neural network chip;

[0013] a second determining module configured to determine parameter value variation ranges of the plurality of target hardware parameters;

[0014] a third determining module configured to determine a plurality of parameter optimization functions based on the parameter value variation ranges of the plurality of target hardware parameters, one parameter optimization function corresponding to a parameter value variation range of one hardware parameter, and the parameter optimization function being used to limit the target hardware parameter to vary within the parameter value variation range;

[0015] a fourth determining module configured to determine target parameter values of the plurality of target hardware parameters based on the plurality of parameter optimization functions, the architecture simulation model being used to simulate an architecture of the neural network chip, the target parameter values of the target hardware parameters being within the parameter value variation ranges of the hardware parameters.

[0016] In another aspect, an electronic device is provided, the electronic device comprising a processor and a memory; the memory storing at least one program code for being executed by the processor to implement the method for determining hardware parameter values according to any of the above aspects.

[0017] In another aspect, a computer-readable storage medium is provided, the computer-readable storage medium storing at least one program code for being executed by a processor to implement the method for determining hardware parameter values according to any of the above aspects.

[0018] In another aspect, a computer program product is provided, the computer program product storing at least one program code for being executed by a processor to implement the method for determining hardware parameter values according to any of the above aspects.

[0019] In the embodiment of the present application, the parameter value variation range of the plurality of target hardware parameters is determined, and then a plurality of parameter optimization functions for limiting the plurality of target hardware parameters are determined, so that the plurality of parameter optimization functions are used to limit the plurality of target hardware parameters to search for an optimal solution (target parameter value) within the corresponding parameter value variation range, thereby reducing the search range of the optimal solution, improving the search efficiency, and improving the efficiency of determining the hardware parameter value. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A schematic diagram of an implementation environment of a hardware parameter value determination method according to an example embodiment of the present application is shown;

[0021] Figure 2 A flowchart of a hardware parameter value determination method according to an example embodiment of the present application is shown;

[0022] Figure 3 A flowchart of a hardware parameter value determination method according to an example embodiment of the present application is shown;

[0023] Figure 4 A flowchart of a hardware parameter value determination method according to an example embodiment of the present application is shown;

[0024] Figure 5 A flowchart of a hardware parameter value determination method according to an example embodiment of the present application is shown;

[0025] Figure 6 A structural block diagram of a hardware parameter value determination apparatus according to an example embodiment of the present application is shown;

[0026] Figure 7 A structural block diagram of a terminal according to an example embodiment of the present application is shown;

[0027] Figure 8 A structural block diagram of a server according to an example embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0029] In this document, "plurality" refers to two or more. The association relationship of "and / or" describing the associated objects means that there can be three relationships, for example, A and / or B can represent the three cases of A existing alone, A and B existing together, and B existing alone. The character " / " generally represents an "or" relationship between the front and rear associated objects. In addition, the related data involved in the present application can be data authorized by the user or fully authorized by all parties.

[0030] It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the hardware parameters, parameter value change range, performance requirement information and the like involved in the present application are obtained under full authorization.

[0031] Some technical terms involved in the present application are explained as follows.

[0032] Neural network chip: refers to a chip running a neural network model; for example, the neural network chip can be a neural network processing unit (NPU).

[0033] Hardware parameter: hardware parameter of a neural network chip; for example, system cache memory of a neural network chip, static random access memory (SRAM) memory included in a neural network chip, SRAM bandwidth included in a neural network chip, double data rate (DDR) bandwidth included in a neural network chip, and running frequency of a neural network chip, etc.

[0034] Neural network model: any type of neural network model, for example, the neural network model is a convolutional neural network (CNN) model, a deep neural network (DNN) model, or a recurrent neural network (RNN) model. Moreover, the neural network model can be a neural network model applied in various fields such as image recognition, speech signal processing, machine control, autonomous driving, etc., for performing tasks such as image classification, voice control, autonomous driving control, etc. For example, the neural network model is applied in the field of image recognition, and the neural network model can be an image recognition model, and the electronic device identifies objects in the image through the image recognition model. For another example, the neural network model is applied in the field of speech signal processing, and the neural network model can be a speech recognition model, and the electronic device identifies voice commands in the speech signal through the speech recognition model, and subsequently performs automatic control based on the voice commands. For another example, the neural network model is applied in the field of autonomous driving, and the neural network model can be a visual recognition model, and the electronic device identifies environmental information of the vehicle through the visual recognition model, and controls the vehicle to perform autonomous driving based on the environmental information.

[0035] Architecture simulation model: a model that simulates the functions of a neural network chip in a computer program language, commonly known as a c-model, used to simulate the architecture of a neural network chip.

[0036] Multi-objective optimization algorithm: an algorithm commonly used to optimize multiple objectives simultaneously; the general idea of the multi-objective optimization algorithm is to simultaneously optimize multiple target hardware parameters within a given parameter value range as best as possible; and the solution of multi-objective optimization is usually a set of equilibrium solutions, which include the optimal solution (or non-inferior optimal solution) of the parameter values of the multiple target hardware parameters.

[0037] Artificial intelligence benchmark (Ai-Benchmark): an artificial intelligence (AI) performance test list launched by the Swiss Federal Institute of Technology, which has a more professional evaluation method for the AI performance of a neural network chip, allowing consumers to more quantitatively experience AI performance.

[0038] Please refer to Figure 1 which shows a schematic diagram of an implementation environment of a hardware parameter value determination method according to an example embodiment of the present application; the implementation environment includes an electronic device, which determines the parameter values of multiple target hardware parameters of a neural network chip, so as to subsequently configure the neural network chip based on the determined parameter values of the multiple target hardware parameters, and run a neural network model on the neural network chip.

[0039] The electronic device can be provided as the terminal 101, can be provided as the server 102, or can be provided as both the terminal 101 and the server 102, and the terminal 101 and the server 102 can be connected through a wireless or wired network. In the embodiments of the present application, the electronic device is not specifically limited. If the electronic device is provided as both the terminal 101 and the server 102, refer to Figure 1 The server 102 determines the parameter values of the plurality of target hardware parameters of the neural network chip, so that the neural network chip is configured based on the determined parameter values of the plurality of target hardware parameters, and the neural network model is run on the neural network chip. For example, the neural network model is a speech recognition model, and when the terminal 101 needs to perform speech recognition, the server 102 is sent a voice signal to be recognized, the server 102 identifies a voice command in the voice signal through the speech recognition model, and sends the voice command to the terminal 101, and the terminal 101 performs automatic control based on the voice command.

[0040] The terminal 101 is at least one of a mobile phone, a tablet computer, and a PC (Personal Computer) device. The server 102 can be at least one of a server, a server cluster composed of multiple servers, a cloud server, a cloud computing platform, and a virtualization center.

[0041] Please refer to Figure 2 which shows a flowchart of a method for determining hardware parameter values according to an example embodiment of the present application. The method comprises the following steps:

[0042] Step S201: The electronic device determines a plurality of target hardware parameters of a neural network chip.

[0043] The neural network chip is a chip for a neural network model, and the plurality of target hardware parameters of the neural network chip includes a plurality of target hardware parameters including System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth, and Frequency.

[0044] Step S202: The electronic device determines the parameter value variation range of the plurality of target hardware parameters.

[0045] One hardware parameter corresponds to one parameter value variation range, and the parameter value variation range of the hardware parameter represents the range of the parameter value of the hardware parameter. For example, the plurality of target hardware parameters include System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth, and Frequency; and the parameter value variation range of the plurality of target hardware parameters is shown in Table 1 as follows:

[0046] Table 1

[0047]

[0048] Step 203: The electronic device determines a plurality of parameter optimization functions based on the parameter value variation range of the plurality of target hardware parameters, one parameter optimization function corresponding to the parameter value variation range of one target hardware parameter, and the parameter optimization function being used to limit the hardware parameter to vary within the parameter value variation range.

[0049] For example, the plurality of parameter optimization functions determined by the electronic device are respectively

[0050] s.t. System cache memory ∈ [0, 12], M+

[0051] s.t. SRAM memory ∈ [0, 4], N+

[0052] s.t. SRAM bandwidth ∈ [0, 64], P+

[0053] s.t. DDR bandwidth ∈ [0, 32], Q+

[0054] s.t. Frequency ∈ {600, 700, 800}

[0055] Wherein, “s.t. System cache memory ∈ [0, 12], M+” is the parameter optimization function corresponding to System cache memory, and [0, 12] is the parameter value variation range corresponding to System cache memory, M is the parameter value corresponding to System cache memory, and M is sequentially increased from 0 to 12 in the training iteration process.

[0056] “s.t. SRAM memory ∈ [0, 4], N+” is the parameter optimization function corresponding to SRAM memory, and [0, 4] is the parameter value variation range corresponding to SRAM memory, N is the parameter value corresponding to SRAM memory, and N is sequentially increased from 0 to 4 in the training iteration process.

[0057] “s.t. SRAM bandwidth ∈ [0, 64], P+” is the parameter optimization function corresponding to SRAM bandwidth, and [0, 64] is the parameter value variation range corresponding to bandwidth, P is the parameter value corresponding to SRAM bandwidth, and P is sequentially increased from 0 to 64 in the training iteration process.

[0058] "s.t.DDR bandwidth e [0, 32], Q+" is a parameter optimization function corresponding to the DDR bandwidth, [0, 32] is a parameter value variation range corresponding to the DDR bandwidth, Q is a parameter value corresponding to the DDR bandwidth, and Q is sequentially increased from 0 to 32 in the training iteration process.

[0059] "s.t.Frequency e {600, 700, 800}" is a parameter optimization function corresponding to the Frequency, and {600, 700, 800} is a parameter value variation range corresponding to the Frequency.

[0060] Step 204: The electronic device limits the iterative training of the architecture simulation model in the parameter value variation range of the plurality of target hardware parameters based on the plurality of parameter optimization functions, to determine the target parameter values of the plurality of target hardware parameters, and the architecture simulation model is used to simulate the architecture of the neural network chip, and the target parameter values of the target hardware parameters are in the parameter value variation range of the hardware parameters.

[0061] Wherein, the electronic device limits the iterative training of the architecture simulation model in the parameter range of the plurality of target hardware parameters based on the plurality of parameter optimization functions through the multi-objective optimization algorithm, to obtain a set of equilibrium solutions, the target parameter values of the plurality of target hardware parameters in the equilibrium solutions are simultaneously satisfied, that is, the target parameter values of the plurality of target hardware parameters are the optimal solution.

[0062] In the embodiments of the present application, the parameter value variation range of the plurality of target hardware parameters is determined, and then the plurality of parameter optimization functions for limiting the plurality of target hardware parameters are determined, so that the plurality of parameter optimization functions are used to limit the plurality of target hardware parameters to search for the optimal solution (target parameter value) in the corresponding parameter value variation range, thereby reducing the search range of the optimal solution and improving the search efficiency, that is, the efficiency of determining the hardware parameter value is improved.

[0063] Please refer to Figure 3 which shows a flowchart of a hardware parameter value determination method according to an example embodiment of the present application. The method comprises:

[0064] Step S301: The electronic device determines a plurality of target hardware parameters of a neural network chip.

[0065] The neural network chip is a chip for a neural network model, and the plurality of target hardware parameters of the neural network chip include a plurality of target hardware parameters including System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth, and Frequency.

[0066] In an implementation manner, the electronic device can determine the plurality of target hardware parameters of the neural network chip according to the design target of the technician; correspondingly, the step can be implemented through the following steps (1) to (3), including:

[0067] (1) The electronic device obtains performance requirement information, which is used to represent the performance requirement required to be met by the neural network chip.

[0068] The performance requirement information includes at least one performance indicator and a condition required to be met by the at least one performance indicator; for example, the at least one performance indicator includes Ai-Benchmark Scoring, chip area, and Power efficient when running the neural network model; correspondingly, the condition required to be met by the at least one performance indicator is that the Ai-Benchmark Scoring is greater than or equal to 1000k, the chip area is as small as possible, and the Power efficient when running the neural network model is as large as possible.

[0069] The performance requirement information is the design target; see Figure 4 , the electronic device determines the design target.

[0070] The performance requirement information is determined by the technician, thereby meeting the design requirement of the technician; correspondingly, the electronic device obtaining the performance requirement information can be implemented through the following steps (1-1) to (1-3), including:

[0071] (1-1) The electronic device displays a requirement setting interface.

[0072] The requirement setting interface includes a plurality of performance indicators, and the plurality of performance indicators are in a selectable state, so that the technician can select at least one performance indicator from the plurality of performance indicators.

[0073] (1-2) The electronic device obtains the selected at least one performance indicator.

[0074] (1-3) The electronic device obtains the condition required to be met by the at least one performance indicator.

[0075] In a possible implementation, the technician can set a condition that needs to be met by each performance indicator after selecting one performance indicator; for example, the electronic device displays a plurality of conditions that need to be met by the selected performance indicator, and the technician can select one condition from the plurality of conditions, and the electronic device acquires the selected condition.

[0076] In the embodiment of the present application, the electronic device displays a plurality of conditions that need to be met by each performance indicator after the technician selects one performance indicator, so that the technician can verify the plurality of conditions in time, and thus replace the performance indicator in time when there is no condition that the technician wants to set in the plurality of conditions.

[0077] In another possible implementation, after the technician selects at least one performance indicator, the electronic device jumps from the requirement setting interface to a condition configuration interface, the condition configuration interface includes the selected at least one performance indicator and a plurality of conditions that need to be met by the at least one performance indicator, and for any performance indicator, the technician can select one condition from the plurality of conditions that need to be met by the performance indicator, and the electronic device acquires the selected at least one performance, thereby acquiring the conditions that need to be met by the at least one performance indicator.

[0078] In the embodiment of the present application, after the technician selects at least one performance indicator, the electronic device jumps from the requirement setting interface to a condition configuration interface, so that the technician can configure the conditions that need to be met by the at least one performance indicator in the condition configuration interface at one time, which is more efficient.

[0079] (2) The electronic device determines a chip architecture of the neural network chip based on the performance requirement information, and the chip architecture meets the performance requirement.

[0080] For example, continuing to refer to Figure 4 , the electronic device determines a chip architecture of the neural network chip based on the performance requirement information (design target), that is, the design of the neural network chip architecture.

[0081] (3) The electronic device analyzes the chip architecture to obtain a plurality of target hardware parameters.

[0082] The electronic device determines a neural network model, which is a model to be run on the neural network chip; and analyzes the chip architecture based on the neural network model to obtain a plurality of target hardware parameters. Wherein, the electronic device analyzes the chip architecture based on the neural network model to obtain a plurality of target hardware parameters, including:

[0083] The electronic device determines a plurality of first hardware parameters required by the neural network model, parses the chip architecture to obtain a plurality of second hardware parameters included in the neural network chip, and determines a union of the plurality of first hardware parameters and the plurality of second hardware parameters to obtain a plurality of target hardware parameters.

[0084] For example, continuing to refer to Figure 4 , the electronic device analyzes the neural network model and determines the plurality of target hardware parameters based on the chip architecture.

[0085] Step S302: The electronic device determines a parameter value variation range of the plurality of target hardware parameters.

[0086] One hardware parameter corresponds to one parameter value variation range, and the parameter value variation range of the hardware parameter represents a range in which a parameter value of the hardware parameter is located. For example, continuing to refer to Figure 4 , the electronic device determines the parameter value variation range of the plurality of target hardware parameters.

[0087] In a possible implementation, a technical person configures the parameter value variation range of the plurality of target hardware parameters. Accordingly, the step can be implemented through the following steps (1) to (2), including:

[0088] (1) The electronic device displays a parameter configuration interface, and the parameter configuration interface includes a plurality of input boxes.

[0089] One input box corresponds to one hardware parameter, and the input box is used to input a parameter value variation range corresponding to the hardware parameter.

[0090] (2) The electronic device obtains, based on the parameter configuration interface, a plurality of target hardware parameter value variation ranges inputted.

[0091] In the embodiments of the present application, the technical person manually configures the parameter value variation range of the hardware parameter through the parameter configuration interface, which can realize individualized design and meet the needs of the technical person.

[0092] In another possible implementation, the neural network chip is used to run the neural network model, and therefore, the parameter value variation range of the plurality of target hardware parameters of the neural network chip can be determined based on the neural network model. Accordingly, the step in which the electronic device determines the parameter value variation range of the plurality of target hardware parameters includes:

[0093] The electronic device determines specification information of the neural network model to be run, and the specification information is used to represent a specification size of the neural network model, and obtains a parameter value variation range of a plurality of target hardware parameters matched with the specification information.

[0094] In the embodiment of the present application, based on the specification information of the neural network model, the parameter value variation range of the plurality of target hardware parameters is obtained, so that the neural network chip can better serve the neural network model, and the performance of the neural network model is improved.

[0095] Step 303: The electronic device determines a plurality of parameter optimization functions based on the parameter value variation range of the plurality of target hardware parameters, one parameter optimization function corresponding to the parameter value variation range of one hardware parameter, and the parameter optimization function being used to limit the hardware parameter to change within the parameter value variation range.

[0096] For example, the plurality of parameter optimization functions determined by the electronic device are respectively

[0097] s.t. System cache memory∈[0,12],M+

[0098] s.t. SRAM memory∈[0,4],N+

[0099] s.t. SRAM bandwidth∈[0,64],P+

[0100] s.t. DDR bandwidth∈[0,32],Q+

[0101] s.t. Frequency∈{600,700,800}

[0102] Wherein, "s.t. System cache memory∈[0,12],M+" is the parameter optimization function corresponding to System cache memory, and [0,12] is the parameter value variation range corresponding to System cache memory, M is the parameter value corresponding to System cache memory, and M is increased from 0 to 12 in the training iteration process.

[0103] "s.t. SRAM memory∈[0,4],N+" is the parameter optimization function corresponding to SRAM memory, and [0,4] is the parameter value variation range corresponding to SRAM memory, N is the parameter value corresponding to SRAM memory, and N is increased from 0 to 4 in the training iteration process.

[0104] "s.t. SRAM bandwidth∈[0,64],P+" is the parameter optimization function corresponding to SRAM bandwidth, and [0,64] is the parameter value variation range corresponding to bandwidth, P is the parameter value corresponding to SRAM bandwidth, and P is increased from 0 to 64 in the training iteration process.

[0105] "s.t. DDR bandwidth ∈ [0, 32], Q+" is a parameter optimization function corresponding to the DDR bandwidth, [0, 32] is a parameter value variation range corresponding to the DDR bandwidth, Q is a parameter value corresponding to the DDR bandwidth, and Q is sequentially increased from 0 to 32 in the training iteration process.

[0106] "s.t. Frequency ∈ {600, 700, 800}" is a parameter optimization function corresponding to the Frequency, and {600, 700, 800} is a parameter value variation range corresponding to the Frequency.

[0107] Step S304: The electronic device determines a first parameter value combination in the parameter value variation range of the plurality of target hardware parameters based on the plurality of parameter optimization functions, and the first parameter value combination includes first parameter values of the plurality of target hardware parameters.

[0108] For any hardware parameter, the electronic device determines a first parameter value in the parameter value variation range corresponding to the hardware parameter based on the parameter optimization function corresponding to the hardware parameter, thereby determining the first parameter values of the plurality of target hardware parameters, and the first parameter values of the plurality of target hardware parameters are the first parameter value combination.

[0109] In a possible implementation, the electronic device can randomly determine a first parameter value from the parameter value variation range corresponding to the hardware parameter, or the electronic device determines the first parameter value combination from the parameter value variation range of the plurality of target hardware parameters based on a multi-objective optimization algorithm.

[0110] In another possible implementation, the electronic device determines performance influence parameters of the plurality of target hardware parameters, the performance influence parameter of the hardware parameter is used to represent the influence degree and trend of the parameter value variation of the hardware parameter on the performance of the neural network chip, and determines the first parameter value combination in the parameter value variation range of the plurality of target hardware parameters based on the performance influence parameters of the plurality of target hardware parameters and the plurality of parameter optimization functions, and the first parameter value combination includes the parameter values of the plurality of target hardware parameters, so that the performance of the neural network chip meets the demand, and the parameter values of the plurality of target hardware parameters are in the parameter value variation range limited by the plurality of parameter optimization functions.

[0111] For example, the electronic device includes multiple target hardware parameters, respectively System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth and Frequency; and the performance influence parameters of System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth and Frequency are respectively +1, +1.5, +2, +3 and +2.5; wherein, +1 represents that the performance of the neural network chip increases by 1 when System cache memory increases by one unit value; +1.5 represents that the performance of the neural network chip increases by 1.5 when SRAM memory increases by one unit value; +2 represents that the performance of the neural network chip increases by 2 when SRAM bandwidth increases by one unit value; +3 represents that the performance of the neural network chip increases by 3 when DDR bandwidth increases by one unit value; +2.5 represents that the performance of the neural network chip increases by 2.5 when Frequency changes from 600 to 700 or from 700 to 800. For example, the parameter values of System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth and Frequency are respectively 1, 1, 1, 1 and 600, and the performance of the neural network chip is 10 at this time, and the required performance of the neural network chip is not less than 15, then at this time, it is necessary to increase the parameter values of these hardware parameters, so as to improve the performance of the neural network chip, and the parameter values of System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth and Frequency can be set to be respectively 6, 1, 1, 1 and 600 to obtain a first parameter value combination; or, the parameter values of System cache memory, SRAM memory, SRAM bandwidth, DDR bandwidth and Frequency can be set to be respectively 1, 1, 2, 2 and 600 to obtain a first parameter value combination.

[0112] In the embodiments of the present application, the parameter values of the multiple target hardware parameters are limited by the performance influence parameters and the parameter optimization function, so that the determined hardware parameters not only meet the performance requirements of the neural network chip, but also meet the multiple parameter optimization function limitations, that is, the accuracy of the determined hardware parameter values is improved.

[0113] Step S305: The electronic device iteratively trains the first parameter value combination based on the architecture simulation model.

[0114] The architecture simulation model is used to simulate the architecture of the neural network chip, and is used to determine the performance of the simulated neural network chip based on the parameter value combination, that is, the architecture simulation model is used to simulate the neural network chip, and then the performance of the simulated neural network chip is evaluated, for example, continue to refer to Figure 4 Correspondingly, this step can be: the electronic device inputs the first parameter value combination into the architecture simulation model, and outputs the performance of the neural network model.

[0115] After the electronic device determines the performance of the neural network model, it determines whether the first parameter value combination meets the iterative convergence condition; in the case that the first parameter value combination meets the iterative convergence condition, step S306 is performed; in the case that the first parameter value combination does not meet the iterative convergence condition, step S307 is performed.

[0116] The electronic device can determine whether the first parameter value combination meets the iterative convergence condition based on the number of iterations or the difference between the adjacent two performances; correspondingly, the step of the electronic device determining whether the first parameter value combination meets the iterative convergence condition comprises:

[0117] In the case that the current number of iterations reaches the target number of iterations or the difference between the adjacent two performances is less than the preset difference, the electronic device determines that the first parameter value combination meets the iterative convergence condition; in the case that the current number of iterations does not reach the target number of iterations, and the difference between the adjacent two performances is not less than the preset difference, the electronic device determines that the first parameter value combination does not meet the iterative convergence condition.

[0118] In the embodiments of the present application, the entire optimization process is integrated into the same environment through the iterative training method, which simplifies the search step and further improves the search efficiency, that is, further improves the efficiency of determining the hardware parameters.

[0119] Step S306: In the case that the first parameter value combination meets the iterative convergence condition, the electronic device takes the first parameter values of the plurality of target hardware parameters in the first parameter value combination as the target parameter values of the plurality of target hardware parameters.

[0120] In the case that the first parameter value meets the iterative convergence condition, the electronic device determines that the first parameter value combination is the optimal solution, and at this time the electronic device takes the first parameter values of the plurality of target hardware parameters in the first parameter value combination as the target parameter values of the plurality of target hardware parameters.

[0121] Step S307: In the case that the first parameter value combination does not meet the iterative convergence condition, the electronic device determines a second parameter value combination in the parameter value variation range of the plurality of target hardware parameters based on the plurality of parameter optimization functions, the second parameter value combination comprising second parameter values of the plurality of target hardware parameters.

[0122] In a case where the first parameter value combination does not satisfy the iterative convergence condition, the electronic device determines that the first parameter value combination is not an optimal solution, and in this case, the electronic device needs to determine a second parameter value combination.

[0123] In a possible implementation, the electronic device can determine the second parameter value combination based on a manner in which the first parameter value combination is determined. In another possible implementation, the electronic device can increase the parameter value of at least one target hardware parameter in the first parameter value combination to obtain the second parameter value combination, and ensure that the second parameter value of any target hardware parameter is within the parameter value variation range of the target hardware parameter. In another possible implementation, the electronic device automatically updates the parameter values of the plurality of target hardware parameters by using a multi-objective optimization algorithm to obtain the second parameter value combination, for example, continuing to refer to Figure 4 .

[0124] In the embodiments of the present application, the manner in which the electronic device determines the second parameter value combination is not limited in particular.

[0125] Step S308: The electronic device performs iterative training on the second parameter value combination based on the architecture simulation model until target parameter values of the plurality of target hardware parameters that satisfy the iterative convergence condition are obtained.

[0126] The electronic device inputs the second parameter value combination into the architecture simulation model, outputs the performance of the neural network model, and determines whether the second parameter value combination satisfies the iterative convergence condition. In a case where the second parameter value combination satisfies the iterative convergence condition, the electronic device takes the second parameter values of the plurality of target hardware parameters in the second parameter value combination as the target parameter values of the plurality of target hardware parameters. In a case where the second parameter value combination does not satisfy the iterative convergence condition, a third parameter value combination is determined, and iterative training is performed on the third parameter value combination based on the architecture simulation model until target parameter values of the plurality of target hardware parameters that satisfy the iterative convergence condition are obtained.

[0127] It should be noted that the target parameter values determined in the embodiments of the present application are optimal solutions, that is, the present application can find a parameter value combination that best meets the design target through continuous iteration, while the forward search in the related art can not find an optimal solution that meets the requirements due to the enumeration of parameter values. Moreover, the embodiments of the present application automatically search for an optimal solution that satisfies the design target by virtue of the feature of continuously searching for an optimal direction by using a multi-objective optimization algorithm, and the related art needs to be manually set and tried one by one, which is high in labor cost and low in efficiency. The automatic search in the embodiments of the present application greatly improves the search efficiency and simplifies the search steps.

[0128] It should be noted that the method provided in the embodiments of the present application has strong scalability, and can better adapt to the increase, decrease or change of target hardware parameters and quickly find the optimal solution, thereby improving the search speed and shortening the project cycle.

[0129] In a possible implementation, when a target hardware parameter is added, the electronic device determines a parameter value change range of the added target hardware parameter, determines a parameter optimization function corresponding to the added target hardware parameter based on the parameter value change range, and inputs the parameter optimization function corresponding to the added target hardware parameter into the simulation architecture model, so that the simulation architecture model automatically searches for the optimal solution based on the parameter optimization functions corresponding to the original target hardware parameters and the parameter optimization function corresponding to the added target hardware parameter through the multi-objective optimization algorithm, and finally obtains the target parameter values of the multiple target hardware parameters (the original target hardware parameters and the added target hardware parameter).

[0130] In another possible implementation, when a target hardware parameter is reduced, the electronic device deletes the parameter optimization function corresponding to the reduced target hardware parameter from the simulation architecture model, so that the simulation architecture model automatically searches for the optimal solution based on the parameter optimization functions corresponding to the remaining multiple target hardware parameters through the multi-objective optimization algorithm, and finally obtains the target parameter values of the remaining multiple target hardware parameters.

[0131] In another possible implementation, when a target hardware parameter is changed, the electronic device changes the parameter optimization function of the target hardware parameter in the simulation architecture model from a first optimization function to a second optimization function, the first optimization function is an optimization function before the target hardware parameter is changed, and the second optimization function is an optimization function after the target hardware parameter is changed, and then the electronic device automatically searches for the optimal solution based on the optimization function corresponding to the changed target hardware parameter through the multi-objective optimization algorithm, and finally obtains the target parameter values of the multiple target hardware parameters.

[0132] In the embodiments of the present application, the parameter value change ranges of the multiple target hardware parameters are determined, and then the multiple parameter optimization functions for limiting the multiple target hardware parameters are determined, so that the multiple target hardware parameters are limited in the corresponding parameter value change ranges through the multiple parameter optimization functions to search for the optimal solution (the target parameter values), the search range of the optimal solution is reduced, the search efficiency is improved, and the efficiency of determining the hardware parameter values is improved.

[0133] Please refer to Figure 5 which shows a flowchart of a method for determining hardware parameter values according to an example embodiment of the present application. The method comprises:

[0134] Step S501: The electronic device acquires performance requirement information, which is used to indicate the performance requirement that the neural network chip needs to meet.

[0135] The performance requirement information includes at least one performance indicator and a condition that needs to be met by the at least one performance indicator; for example, the at least one performance indicator includes Ai-Benchmark Scoring, chip area, and Power efficient when running a neural network model; and the condition that needs to be met by the at least one performance indicator is that the Ai-Benchmark Scoring is greater than or equal to 1000k, the chip area is as small as possible, and the Power efficient when running the neural network model is as large as possible.

[0136] Step S502: The electronic device determines a requirement optimization function of the neural network chip based on the performance requirement information.

[0137] For example, the performance requirement functions determined by the electronic device are as follows:

[0138] Max(Power efficient)

[0139] Min(chip area)

[0140] Ai-Benchmark Scoring>=1000k;

[0141] Wherein, Max(Power efficient) is the performance requirement function of Power efficient, which is used to limit Power efficient; Min(chip area) is the performance requirement function of chip area, which is used to limit chip area; and Ai-Benchmark Scoring>=1000k is the performance requirement function of Ai-Benchmark Scoring, which is used to limit Ai-Benchmark Scoring.

[0142] Step S503: The electronic device determines a plurality of target hardware parameters of the neural network chip.

[0143] Step S504: The electronic device determines a parameter value variation range of the plurality of target hardware parameters.

[0144] Step S505: The electronic device determines a plurality of parameter optimization functions based on the parameter value variation range of the plurality of target hardware parameters, one parameter optimization function corresponding to the parameter value variation range of one hardware parameter, and the parameter optimization function being used to limit the variation of the hardware parameter within the parameter value variation range.

[0145] It should be noted that steps S503-S505 are the same as steps S301-S303, and will not be described here.

[0146] Another point to be noted is that steps S501-S502 and steps S503-S505 do not have a strict time sequence, and steps S501-S502 can be executed first, followed by steps S503-S505, or steps S503-S505 can be executed first, followed by steps S501-S502. In the embodiments of the present application, the execution order of steps S501-S502 and steps S503-S505 is not specifically limited.

[0147] Step S506: The electronic device limits the architecture simulation model to meet the performance requirement represented by the performance requirement information based on the requirement optimization function and the plurality of parameter optimization functions, and iteratively trains within the parameter value variation range of the plurality of target hardware parameters to determine the target parameter values of the plurality of target hardware parameters.

[0148] The electronic device determines a first parameter value combination within the parameter value variation range of the plurality of target hardware parameters based on the requirement optimization function and the plurality of parameter optimization functions, the first parameter value combination including first parameter values of the plurality of target hardware parameters; iteratively trains the first parameter value combination based on the architecture simulation model; and in a case where the first parameter value combination meets an iterative convergence condition, takes the first parameter values of the plurality of target hardware parameters in the first parameter value combination as the target parameter values of the plurality of target hardware parameters. In a case where the first parameter value combination does not meet the iterative convergence condition, determines a second parameter value combination within the parameter value variation range of the plurality of target hardware parameters based on the requirement optimization function and the plurality of parameter optimization functions, the second parameter value combination including second parameter values of the plurality of target hardware parameters; iteratively trains the second parameter value combination based on the architecture simulation model until the target parameter values of the plurality of target hardware parameters meeting the iterative convergence condition are obtained.

[0149] The first parameter values of the plurality of target hardware parameters included in the determined first parameter value combination are within the parameter value variation range of the corresponding target hardware parameters, and the performance of the neural network chip determined based on the first parameter value combination meets the performance requirement represented by the requirement optimization function. Similarly, the second parameter values of the plurality of target hardware parameters included in the second parameter value combination are within the parameter value variation range of the corresponding target parameter values, and the performance of the neural network chip determined based on the second parameter value combination meets the performance requirement represented by the requirement optimization function.

[0150] In the embodiments of the present application, the parameter value variation ranges of the plurality of target hardware parameters and the performance requirement information are determined, and then a plurality of parameter optimization functions for limiting the plurality of target hardware parameters and a requirement optimization function for limiting the performance requirement are determined, so that the plurality of parameter optimization functions and the requirement optimization function are used to limit the plurality of target hardware parameters to search for an optimal solution (target parameter value) within the corresponding parameter value variation range, and ensure that the optimal solution can meet the performance requirement of the neural network chip, thereby not only narrowing the search range of the optimal solution and improving the search efficiency, but also improving the performance of the neural network chip.

[0151] Reference is made to Figure 6 which shows a structural block diagram of a hardware parameter value determination apparatus according to an example embodiment of the present application. The hardware parameter value determination apparatus can be realized by software, hardware or a combination of both to become all or part of a processor. The apparatus includes:

[0152] A first determination module 601 is configured to determine a plurality of target hardware parameters of a neural network chip.

[0153] A second determination module 602 is configured to determine parameter value variation ranges of the plurality of target hardware parameters.

[0154] A third determination module 603 is configured to determine a plurality of parameter optimization functions based on the parameter value variation ranges of the plurality of target hardware parameters, one parameter optimization function corresponding to the parameter value variation range of one hardware parameter, and the parameter optimization function being used to limit the target hardware parameter to vary within the parameter value variation range.

[0155] A fourth determination module 604 is configured to limit an architecture simulation model to iteratively train within the parameter value variation ranges of the plurality of target hardware parameters based on the plurality of parameter optimization functions, and determine target parameter values of the plurality of target hardware parameters, the architecture simulation model being used to simulate an architecture of the neural network chip, and the target parameter values of the target hardware parameters being within the parameter value variation ranges of the hardware parameters.

[0156] In a possible implementation, the fourth determination module 604 includes:

[0157] A first determination unit is configured to determine a first parameter value combination within the parameter value variation ranges of the plurality of target hardware parameters based on the plurality of parameter optimization functions, the first parameter value combination including first parameter values of the plurality of target hardware parameters.

[0158] A first iteration unit is configured to iteratively train the first parameter value combination based on the architecture simulation model.

[0159] As a unit, configured to, in a case where the first parameter value combination satisfies the iteration convergence condition, take the first parameter values of the plurality of target hardware parameters in the first parameter value combination as target parameter values of the plurality of target hardware parameters.

[0160] In another possible implementation, the first determining unit is further configured to, in a case where the first parameter value combination does not satisfy the iteration convergence condition, determine, based on the plurality of parameter optimization functions, a second parameter value combination within a parameter value variation range of the plurality of target hardware parameters, the second parameter value combination including second parameter values of the plurality of target hardware parameters;

[0161] The iteration unit is further configured to perform iterative training on the second parameter value combination based on the architecture simulation model until target parameter values of the plurality of target hardware parameters satisfying the iteration convergence condition are obtained.

[0162] In another possible implementation, the first determining unit is configured to determine performance influence parameters of the plurality of target hardware parameters, the performance influence parameter of a hardware parameter being used to represent an influence degree and a trend of a parameter value variation of the hardware parameter on performance of the neural network chip; and determine, based on the performance influence parameters of the plurality of target hardware parameters and the plurality of parameter optimization functions, the first parameter value combination within a parameter value variation range of the plurality of target hardware parameters, the first parameter value combination including parameter values of the plurality of target hardware parameters, which make the performance of the neural network chip satisfy a requirement and which are within the parameter value variation range limited by the plurality of parameter optimization functions.

[0163] In another possible implementation, the apparatus further includes:

[0164] The obtaining module is configured to obtain performance requirement information, the performance requirement information being used to represent a performance requirement required to be satisfied by the neural network chip.

[0165] The fifth determining module is configured to determine, based on the performance requirement information, a requirement optimization function of the neural network chip.

[0166] The fourth determining module 604 is configured to limit, based on the requirement optimization function and the plurality of parameter optimization functions, the architecture simulation model to satisfy the performance requirement represented by the performance requirement information and to perform iterative training within a parameter value variation range of the plurality of target hardware parameters, to determine target parameter values of the plurality of target hardware parameters.

[0167] In another possible implementation, the first determining module 601 is configured to determine, based on the performance requirement information, a chip architecture of the neural network chip, the performance requirement information being used to represent a performance requirement required to be satisfied by the neural network chip, and the chip architecture satisfying the performance requirement; and parse the chip architecture to obtain the plurality of target hardware parameters.

[0168] In another possible implementation, the second determining module 602 is configured to display a parameter configuration interface, the parameter configuration interface including a plurality of input boxes, one input box corresponding to one hardware parameter, and the input box being used for inputting a parameter value variation range corresponding to the hardware parameter; and obtain the parameter value variation ranges of the plurality of target hardware parameters based on the parameter configuration interface.

[0169] The second determining module 602 is configured to obtain specification information of the neural network model, the specification information being used to indicate a specification size of the neural network model, the neural network model being a model to be subsequently run on a neural network chip, and obtain the parameter value variation ranges of the plurality of target hardware parameters that match the specification information.

[0170] It should be noted that the above-described hardware parameter value determination method is only used as an example to divide the above functional modules, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the computer device is divided into different functional modules to complete all or part of the above-described functions. In addition, the hardware parameter value determination apparatus and the hardware parameter value determination method provided in the above embodiments belong to the same concept, and the specific implementation process is described in detail in the method embodiments, which will not be repeated here.

[0171] In the embodiments of the present application, the parameter value variation ranges of the plurality of target hardware parameters are determined, and then a plurality of parameter optimization functions for limiting the plurality of target hardware parameters are determined, so that the plurality of parameter optimization functions are used to limit the plurality of target hardware parameters to search for an optimal solution (target parameter value) within the corresponding parameter value variation range, thereby reducing the search range of the optimal solution and improving the search efficiency, that is, improving the efficiency of determining the hardware parameter value.

[0172] The electronic device can be provided as a terminal or a server; in the case of providing the electronic device as a terminal, refer to Figure 7 FIG. 7 shows a structural block diagram of a terminal according to an example embodiment of the present application. The terminal 700 can be a smart phone, a tablet computer, or the like, which has a function of controlling other devices. The terminal 700 in the present application can include one or more of the following components: a processor 701, a memory 702.

[0173] The processor 701 can include one or more processing cores. For example, the processor 701 includes a first processing chip and a second processing chip. The processor 701 connects various parts within the terminal 700 by various interfaces and lines, performs various functions of the terminal 700 and processes data by running or executing program codes, programs, code sets or program code sets stored in the memory 702, and calling data stored in the memory 702. Alternatively, the processor 701 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA). The processor 701 can integrate a combination of one or several of a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), and a modem. Among them, the CPU is mainly used to process operating systems, user interfaces, and application programs; the GPU is used to render and draw the content to be displayed on the display screen; the NPU is used to implement artificial intelligence (AI) functions; and the modem is used to process wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor 701, but be implemented by a separate chip.

[0174] The memory 702 can include a random access memory (RAM) and can also include a read-only memory (ROM). Alternatively, the memory 702 includes a non-transitory computer-readable storage medium. The memory 702 can be used to store program codes, programs, codes, code sets or program code sets. The memory 702 can include a program storage area and a data storage area, wherein the program storage area can store program codes for implementing an operating system, program codes for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), program codes for implementing various method embodiments described above, etc.; and the data storage area can store data (such as audio data, a phone book) created according to the use of the terminal 700, etc.

[0175] In addition, those skilled in the art can understand that the structure of the terminal 700 shown in the above-mentioned drawings does not constitute a limitation on the terminal 700, and the terminal 700 can include more or fewer components than those shown in the drawings, or combine certain components, or different component arrangements. For example, the terminal 700 also includes components such as a microphone, a speaker, a radio frequency circuit, an input unit, a sensor, an audio circuit, a Wireless Fidelity (Wi-Fi) module, a power supply, a Bluetooth module, and the like, which are not described here.

[0176] In the case of an electronic device provided as a server, refer to Figure 8 , Figure 8 is a structural block diagram of a server provided by an embodiment of the present application. The server 800 can have a large difference due to different configurations or performances, and can include a central processing unit (CPU) 801 and a memory 802, wherein the memory 802 stores at least one program code, and the at least one program code is loaded and executed by the processor 801 to implement the method provided by each method embodiment described above. Of course, the server 800 can also have a wired or wireless network interface, a keyboard, and an input and output interface, and the like, so as to perform input and output. The server 800 can also include other components for realizing the functions of the device, which are not described here.

[0177] In the case of an electronic device provided as a terminal and a server, refer to Figure 7 and Figure 8 .

[0178] The embodiment of the present application also provides a computer readable medium, which stores at least one program code, and the at least one program code is loaded and executed by the processor to implement the method for determining the hardware parameter value as shown in each of the above embodiments.

[0179] The embodiment of the present application also provides a computer program product, which stores at least one program code, and the at least one program code is loaded and executed by the processor to implement the method for determining the hardware parameter value as shown in each of the above embodiments.

[0180] In some embodiments, the computer program related to the embodiments of the present application can be deployed to execute on one computer device, or on multiple computer devices located in one place, or on multiple computer devices distributed in multiple places and interconnected through a communication network, which can constitute a blockchain system.

[0181] Those skilled in the art should be aware that, in the above one or more examples, the functions described in the embodiments of the present application can be implemented in hardware, software, firmware or any combination thereof. When implemented in software, the functions can be stored in a computer readable medium or transmitted as one or more instructions or code on the computer readable medium. The computer readable medium includes computer storage medium and communication medium, and the communication medium includes any medium that facilitates transfer of computer program from one place to another. The storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

[0182] The above merely provides the optional embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of determining a value of a hardware parameter, characterized by, The method comprises: determining a plurality of target hardware parameters of a neural network chip; determining a parameter value variation range of the plurality of target hardware parameters; determining a plurality of parameter optimization functions based on the parameter value variation range of the plurality of target hardware parameters, one parameter optimization function corresponding to a parameter value variation range of one hardware parameter, and the parameter optimization function being used to limit the target hardware parameter to vary within the parameter value variation range; based on the plurality of parameter optimization functions, limiting an architecture simulation model to iteratively train within the parameter value variation range of the plurality of target hardware parameters to determine target parameter values of the plurality of target hardware parameters, the architecture simulation model being used to simulate an architecture of the neural network chip, the target parameter values of the target hardware parameters being within the parameter value variation range of the hardware parameters; the method further comprises: based on the plurality of parameter optimization functions, determining a first parameter value combination within the parameter value variation range of the plurality of target hardware parameters, the first parameter value combination comprising first parameter values of the plurality of target hardware parameters; based on the architecture simulation model, iteratively training the first parameter value combination; in a case where the first parameter value combination satisfies an iterative convergence condition, taking the first parameter values of the plurality of target hardware parameters in the first parameter value combination as the target parameter values of the plurality of target hardware parameters.

2. The method of claim 1, wherein, The method further comprises: in a case where the first parameter value combination does not satisfy the iterative convergence condition, based on the plurality of parameter optimization functions, determining a second parameter value combination within the parameter value variation range of the plurality of target hardware parameters, the second parameter value combination comprising second parameter values of the plurality of target hardware parameters; based on the architecture simulation model, iteratively training the second parameter value combination until target parameter values of the plurality of target hardware parameters satisfying the iterative convergence condition are obtained.

3. The method of claim 1, wherein, The method further comprises: determining performance impact parameters of the plurality of target hardware parameters, the performance impact parameters of the hardware parameters being used to represent an influence degree and a trend of a parameter value variation of the hardware parameters on the performance of the neural network chip; based on the performance impact parameters of the plurality of target hardware parameters and the plurality of parameter optimization functions, determining a first parameter value combination within the parameter value variation range of the plurality of target hardware parameters, the first parameter value combination comprising parameter values of the plurality of target hardware parameters such that the performance of the neural network chip satisfies a demand, and the parameter values of the plurality of target hardware parameters being within the parameter value variation range limited by the plurality of parameter optimization functions.

4. The method of claim 1, wherein, The method further comprises: obtaining performance demand information, the performance demand information being used to represent a performance demand required to be satisfied by the neural network chip; based on the performance demand information, determining a demand optimization function of the neural network chip; The determining the target parameter values of the plurality of target hardware parameters based on the plurality of parameter optimization functions comprises: The determining the target parameter values of the plurality of target hardware parameters based on the plurality of parameter optimization functions comprises:

5. The method according to claim 1 or 4, characterized in that, The determining the plurality of target hardware parameters of the neural network chip comprises: The determining the plurality of target hardware parameters of the neural network chip comprises: The determining the plurality of target hardware parameters of the neural network chip comprises:

6. The method of claim 1, wherein, The determining the plurality of target hardware parameters of the neural network chip comprises: The determining the parameter value variation ranges of the plurality of target hardware parameters comprises: The determining the parameter value variation ranges of the plurality of target hardware parameters comprises:

7. An apparatus for determining a value of a hardware parameter, characterized by The determining the parameter value variation ranges of the plurality of target hardware parameters comprises: The apparatus comprises: The first determining module is configured to determine a plurality of target hardware parameters of a neural network chip. The second determining module is configured to determine parameter value variation ranges of the plurality of target hardware parameters. The third determining module is configured to determine a plurality of parameter optimization functions based on the parameter value variation ranges of the plurality of target hardware parameters, one parameter optimization function corresponding to a parameter value variation range of one hardware parameter, and the parameter optimization function being configured to limit the target hardware parameter to vary within the parameter value variation range. The fourth determining module is configured to determine target parameter values of the plurality of target hardware parameters by limiting an architecture simulation model to iteratively train within the parameter value variation ranges of the plurality of target hardware parameters based on the plurality of parameter optimization functions, the architecture simulation model being configured to simulate an architecture of the neural network chip, and the target parameter values of the target hardware parameters being within the parameter value variation ranges of the hardware parameters. The fourth determining module comprises: The first determining unit is configured to determine a first parameter value combination comprising first parameter values of the plurality of target hardware parameters within the parameter value variation ranges of the plurality of target hardware parameters based on the plurality of parameter optimization functions. The first iteration unit is configured to iteratively train the first parameter value combination based on the architecture simulation model. As a unit, for in the case where the first parameter value combination satisfies the iteration convergence condition, taking the first parameter value of a plurality of target hardware parameters in the first parameter value combination as a target parameter value of the plurality of target hardware parameters.

8. The apparatus of claim 7, wherein, The first determination unit is further configured to, in the case where the first parameter value combination does not satisfy the iteration convergence condition, determine a second parameter value combination within a parameter value variation range of the plurality of target hardware parameters based on the plurality of parameter optimization functions, the second parameter value combination comprising second parameter values of the plurality of target hardware parameters. The first iteration unit is further configured to perform iterative training on the second parameter value combination based on the architecture simulation model until target parameter values of the plurality of target hardware parameters satisfying the iteration convergence condition are obtained.

9. The apparatus of claim 7, wherein, The first determination unit is configured to determine performance influence parameters of the plurality of target hardware parameters, the performance influence parameters of the hardware parameters being used to represent the influence degree and trend of parameter value variation of the hardware parameters on the performance of the neural network chip. Based on the performance influence parameters of the plurality of target hardware parameters and the plurality of parameter optimization functions, a first parameter value combination is determined within a parameter value variation range of the plurality of target hardware parameters, the first parameter value combination comprising parameter values of the plurality of target hardware parameters such that the performance of the neural network chip satisfies the demand, and the parameter values of the plurality of target hardware parameters are within the parameter value variation range limited by the plurality of parameter optimization functions.

10. The apparatus of claim 7, wherein, The apparatus further comprises: An acquisition module configured to acquire performance demand information, the performance demand information being used to represent a performance demand required to be satisfied by the neural network chip; A fifth determination module configured to determine, based on the performance demand information, a demand optimization function of the neural network chip; The fourth determination module is configured to limit, based on the demand optimization function and the plurality of parameter optimization functions, the architecture simulation model to satisfy the performance demand represented by the performance demand information and to determine, within a parameter value variation range of the plurality of target hardware parameters, target parameter values of the plurality of target hardware parameters through iterative training.

11. The apparatus of claim 7 or 10, wherein, The first determination module is configured to determine, based on performance demand information, a chip architecture of the neural network chip, the performance demand information being used to represent a performance demand required to be satisfied by the neural network chip, and the chip architecture satisfying the performance demand; and parse the chip architecture to obtain the plurality of target hardware parameters.

12. The apparatus of claim 7, wherein, The second determination module is configured to display a parameter configuration interface, the parameter configuration interface comprising a plurality of input boxes, one input box corresponding to one hardware parameter, and the input box being used to input a parameter value variation range corresponding to the hardware parameter; and acquire, based on the parameter configuration interface, the parameter value variation range of the plurality of target hardware parameters that is input. The second determination module is configured to acquire specification information of a neural network model, the specification information being used to represent a specification size of the neural network model, the neural network model being a model to be subsequently run on the neural network chip, and acquire a parameter value variation range of a plurality of target hardware parameters matching the specification information.

13. An electronic device, comprising: The electronic device comprises a processor and a memory; the memory stores at least one program code, and the at least one program code is used for being executed by the processor to implement the hardware parameter value determination method in any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program code, and the at least one program code is used for being executed by the processor to implement the hardware parameter value determination method in any one of claims 1 to 6.

15. A computer program product, characterised in that, The computer program product stores at least one program code, and the at least one program code is loaded and executed by the processor to implement the hardware parameter value determination method in any one of claims 1 to 6.

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